MacroRat / MouseCode

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Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_mpu.h@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /*
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
sahilmgandhi 18:6a4db94011d3 3 * All rights reserved.
sahilmgandhi 18:6a4db94011d3 4 *
sahilmgandhi 18:6a4db94011d3 5 * Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi 18:6a4db94011d3 6 * are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * o Redistributions of source code must retain the above copyright notice, this list
sahilmgandhi 18:6a4db94011d3 9 * of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 10 *
sahilmgandhi 18:6a4db94011d3 11 * o Redistributions in binary form must reproduce the above copyright notice, this
sahilmgandhi 18:6a4db94011d3 12 * list of conditions and the following disclaimer in the documentation and/or
sahilmgandhi 18:6a4db94011d3 13 * other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 14 *
sahilmgandhi 18:6a4db94011d3 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
sahilmgandhi 18:6a4db94011d3 16 * contributors may be used to endorse or promote products derived from this
sahilmgandhi 18:6a4db94011d3 17 * software without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 18 *
sahilmgandhi 18:6a4db94011d3 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
sahilmgandhi 18:6a4db94011d3 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
sahilmgandhi 18:6a4db94011d3 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
sahilmgandhi 18:6a4db94011d3 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
sahilmgandhi 18:6a4db94011d3 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
sahilmgandhi 18:6a4db94011d3 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
sahilmgandhi 18:6a4db94011d3 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
sahilmgandhi 18:6a4db94011d3 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
sahilmgandhi 18:6a4db94011d3 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 29 */
sahilmgandhi 18:6a4db94011d3 30 #ifndef _FSL_MPU_H_
sahilmgandhi 18:6a4db94011d3 31 #define _FSL_MPU_H_
sahilmgandhi 18:6a4db94011d3 32
sahilmgandhi 18:6a4db94011d3 33 #include "fsl_common.h"
sahilmgandhi 18:6a4db94011d3 34
sahilmgandhi 18:6a4db94011d3 35 /*!
sahilmgandhi 18:6a4db94011d3 36 * @addtogroup mpu
sahilmgandhi 18:6a4db94011d3 37 * @{
sahilmgandhi 18:6a4db94011d3 38 */
sahilmgandhi 18:6a4db94011d3 39
sahilmgandhi 18:6a4db94011d3 40
sahilmgandhi 18:6a4db94011d3 41 /*******************************************************************************
sahilmgandhi 18:6a4db94011d3 42 * Definitions
sahilmgandhi 18:6a4db94011d3 43 ******************************************************************************/
sahilmgandhi 18:6a4db94011d3 44
sahilmgandhi 18:6a4db94011d3 45 /*! @name Driver version */
sahilmgandhi 18:6a4db94011d3 46 /*@{*/
sahilmgandhi 18:6a4db94011d3 47 /*! @brief MPU driver version 2.1.0. */
sahilmgandhi 18:6a4db94011d3 48 #define FSL_MPU_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
sahilmgandhi 18:6a4db94011d3 49 /*@}*/
sahilmgandhi 18:6a4db94011d3 50
sahilmgandhi 18:6a4db94011d3 51 /*! @brief MPU the bit shift for masters with privilege rights: read write and execute. */
sahilmgandhi 18:6a4db94011d3 52 #define MPU_REGION_RWXRIGHTS_MASTER_SHIFT(n) (n * 6)
sahilmgandhi 18:6a4db94011d3 53
sahilmgandhi 18:6a4db94011d3 54 /*! @brief MPU masters with read, write and execute rights bit mask. */
sahilmgandhi 18:6a4db94011d3 55 #define MPU_REGION_RWXRIGHTS_MASTER_MASK(n) (0x1Fu << MPU_REGION_RWXRIGHTS_MASTER_SHIFT(n))
sahilmgandhi 18:6a4db94011d3 56
sahilmgandhi 18:6a4db94011d3 57 /*! @brief MPU masters with read, write and execute rights bit width. */
sahilmgandhi 18:6a4db94011d3 58 #define MPU_REGION_RWXRIGHTS_MASTER_WIDTH 5
sahilmgandhi 18:6a4db94011d3 59
sahilmgandhi 18:6a4db94011d3 60 /*! @brief MPU masters with read, write and execute rights priority setting. */
sahilmgandhi 18:6a4db94011d3 61 #define MPU_REGION_RWXRIGHTS_MASTER(n, x) \
sahilmgandhi 18:6a4db94011d3 62 (((uint32_t)(((uint32_t)(x)) << MPU_REGION_RWXRIGHTS_MASTER_SHIFT(n))) & MPU_REGION_RWXRIGHTS_MASTER_MASK(n))
sahilmgandhi 18:6a4db94011d3 63
sahilmgandhi 18:6a4db94011d3 64 /*! @brief MPU masters with read, write and execute rights process enable bit shift. */
sahilmgandhi 18:6a4db94011d3 65 #define MPU_REGION_RWXRIGHTS_MASTER_PE_SHIFT(n) (n * 6 + MPU_REGION_RWXRIGHTS_MASTER_WIDTH)
sahilmgandhi 18:6a4db94011d3 66
sahilmgandhi 18:6a4db94011d3 67 /*! @brief MPU masters with read, write and execute rights process enable bit mask. */
sahilmgandhi 18:6a4db94011d3 68 #define MPU_REGION_RWXRIGHTS_MASTER_PE_MASK(n) (0x1u << MPU_REGION_RWXRIGHTS_MASTER_PE_SHIFT(n))
sahilmgandhi 18:6a4db94011d3 69
sahilmgandhi 18:6a4db94011d3 70 /*! @brief MPU masters with read, write and execute rights process enable setting. */
sahilmgandhi 18:6a4db94011d3 71 #define MPU_REGION_RWXRIGHTS_MASTER_PE(n, x) \
sahilmgandhi 18:6a4db94011d3 72 (((uint32_t)(((uint32_t)(x)) << MPU_REGION_RWXRIGHTS_MASTER_PE_SHIFT(n))) & MPU_REGION_RWXRIGHTS_MASTER_PE_MASK(n))
sahilmgandhi 18:6a4db94011d3 73
sahilmgandhi 18:6a4db94011d3 74 /*! @brief MPU masters with normal read write permission bit shift. */
sahilmgandhi 18:6a4db94011d3 75 #define MPU_REGION_RWRIGHTS_MASTER_SHIFT(n) ((n - FSL_FEATURE_MPU_PRIVILEGED_RIGHTS_MASTER_COUNT) * 2 + 24)
sahilmgandhi 18:6a4db94011d3 76
sahilmgandhi 18:6a4db94011d3 77 /*! @brief MPU masters with normal read write rights bit mask. */
sahilmgandhi 18:6a4db94011d3 78 #define MPU_REGION_RWRIGHTS_MASTER_MASK(n) (0x3u << MPU_REGION_RWRIGHTS_MASTER_SHIFT(n))
sahilmgandhi 18:6a4db94011d3 79
sahilmgandhi 18:6a4db94011d3 80 /*! @brief MPU masters with normal read write rights priority setting. */
sahilmgandhi 18:6a4db94011d3 81 #define MPU_REGION_RWRIGHTS_MASTER(n, x) \
sahilmgandhi 18:6a4db94011d3 82 (((uint32_t)(((uint32_t)(x)) << MPU_REGION_RWRIGHTS_MASTER_SHIFT(n))) & MPU_REGION_RWRIGHTS_MASTER_MASK(n))
sahilmgandhi 18:6a4db94011d3 83
sahilmgandhi 18:6a4db94011d3 84 /*! @brief the Slave port numbers. */
sahilmgandhi 18:6a4db94011d3 85 #define MPU_SLAVE_PORT_NUM (4u)
sahilmgandhi 18:6a4db94011d3 86 /*! @brief define the maximum index of master with privileged rights. */
sahilmgandhi 18:6a4db94011d3 87 #define MPU_PRIVILEGED_RIGHTS_MASTER_MAX_INDEX (3)
sahilmgandhi 18:6a4db94011d3 88
sahilmgandhi 18:6a4db94011d3 89 /*! @brief Describes the number of MPU regions. */
sahilmgandhi 18:6a4db94011d3 90 typedef enum _mpu_region_total_num
sahilmgandhi 18:6a4db94011d3 91 {
sahilmgandhi 18:6a4db94011d3 92 kMPU_8Regions = 0x0U, /*!< MPU supports 8 regions. */
sahilmgandhi 18:6a4db94011d3 93 kMPU_12Regions = 0x1U, /*!< MPU supports 12 regions. */
sahilmgandhi 18:6a4db94011d3 94 kMPU_16Regions = 0x2U /*!< MPU supports 16 regions. */
sahilmgandhi 18:6a4db94011d3 95 } mpu_region_total_num_t;
sahilmgandhi 18:6a4db94011d3 96
sahilmgandhi 18:6a4db94011d3 97 /*! @brief MPU slave port number. */
sahilmgandhi 18:6a4db94011d3 98 typedef enum _mpu_slave
sahilmgandhi 18:6a4db94011d3 99 {
sahilmgandhi 18:6a4db94011d3 100 kMPU_Slave0 = 0U, /*!< MPU slave port 0. */
sahilmgandhi 18:6a4db94011d3 101 kMPU_Slave1 = 1U, /*!< MPU slave port 1. */
sahilmgandhi 18:6a4db94011d3 102 kMPU_Slave2 = 2U, /*!< MPU slave port 2. */
sahilmgandhi 18:6a4db94011d3 103 kMPU_Slave3 = 3U, /*!< MPU slave port 3. */
sahilmgandhi 18:6a4db94011d3 104 kMPU_Slave4 = 4U /*!< MPU slave port 4. */
sahilmgandhi 18:6a4db94011d3 105 } mpu_slave_t;
sahilmgandhi 18:6a4db94011d3 106
sahilmgandhi 18:6a4db94011d3 107 /*! @brief MPU error access control detail. */
sahilmgandhi 18:6a4db94011d3 108 typedef enum _mpu_err_access_control
sahilmgandhi 18:6a4db94011d3 109 {
sahilmgandhi 18:6a4db94011d3 110 kMPU_NoRegionHit = 0U, /*!< No region hit error. */
sahilmgandhi 18:6a4db94011d3 111 kMPU_NoneOverlappRegion = 1U, /*!< Access single region error. */
sahilmgandhi 18:6a4db94011d3 112 kMPU_OverlappRegion = 2U /*!< Access overlapping region error. */
sahilmgandhi 18:6a4db94011d3 113 } mpu_err_access_control_t;
sahilmgandhi 18:6a4db94011d3 114
sahilmgandhi 18:6a4db94011d3 115 /*! @brief MPU error access type. */
sahilmgandhi 18:6a4db94011d3 116 typedef enum _mpu_err_access_type
sahilmgandhi 18:6a4db94011d3 117 {
sahilmgandhi 18:6a4db94011d3 118 kMPU_ErrTypeRead = 0U, /*!< MPU error access type --- read. */
sahilmgandhi 18:6a4db94011d3 119 kMPU_ErrTypeWrite = 1U /*!< MPU error access type --- write. */
sahilmgandhi 18:6a4db94011d3 120 } mpu_err_access_type_t;
sahilmgandhi 18:6a4db94011d3 121
sahilmgandhi 18:6a4db94011d3 122 /*! @brief MPU access error attributes.*/
sahilmgandhi 18:6a4db94011d3 123 typedef enum _mpu_err_attributes
sahilmgandhi 18:6a4db94011d3 124 {
sahilmgandhi 18:6a4db94011d3 125 kMPU_InstructionAccessInUserMode = 0U, /*!< Access instruction error in user mode. */
sahilmgandhi 18:6a4db94011d3 126 kMPU_DataAccessInUserMode = 1U, /*!< Access data error in user mode. */
sahilmgandhi 18:6a4db94011d3 127 kMPU_InstructionAccessInSupervisorMode = 2U, /*!< Access instruction error in supervisor mode. */
sahilmgandhi 18:6a4db94011d3 128 kMPU_DataAccessInSupervisorMode = 3U /*!< Access data error in supervisor mode. */
sahilmgandhi 18:6a4db94011d3 129 } mpu_err_attributes_t;
sahilmgandhi 18:6a4db94011d3 130
sahilmgandhi 18:6a4db94011d3 131 /*! @brief MPU access rights in supervisor mode for bus master 0 ~ 3. */
sahilmgandhi 18:6a4db94011d3 132 typedef enum _mpu_supervisor_access_rights
sahilmgandhi 18:6a4db94011d3 133 {
sahilmgandhi 18:6a4db94011d3 134 kMPU_SupervisorReadWriteExecute = 0U, /*!< Read write and execute operations are allowed in supervisor mode. */
sahilmgandhi 18:6a4db94011d3 135 kMPU_SupervisorReadExecute = 1U, /*!< Read and execute operations are allowed in supervisor mode. */
sahilmgandhi 18:6a4db94011d3 136 kMPU_SupervisorReadWrite = 2U, /*!< Read write operations are allowed in supervisor mode. */
sahilmgandhi 18:6a4db94011d3 137 kMPU_SupervisorEqualToUsermode = 3U /*!< Access permission equal to user mode. */
sahilmgandhi 18:6a4db94011d3 138 } mpu_supervisor_access_rights_t;
sahilmgandhi 18:6a4db94011d3 139
sahilmgandhi 18:6a4db94011d3 140 /*! @brief MPU access rights in user mode for bus master 0 ~ 3. */
sahilmgandhi 18:6a4db94011d3 141 typedef enum _mpu_user_access_rights
sahilmgandhi 18:6a4db94011d3 142 {
sahilmgandhi 18:6a4db94011d3 143 kMPU_UserNoAccessRights = 0U, /*!< No access allowed in user mode. */
sahilmgandhi 18:6a4db94011d3 144 kMPU_UserExecute = 1U, /*!< Execute operation is allowed in user mode. */
sahilmgandhi 18:6a4db94011d3 145 kMPU_UserWrite = 2U, /*!< Write operation is allowed in user mode. */
sahilmgandhi 18:6a4db94011d3 146 kMPU_UserWriteExecute = 3U, /*!< Write and execute operations are allowed in user mode. */
sahilmgandhi 18:6a4db94011d3 147 kMPU_UserRead = 4U, /*!< Read is allowed in user mode. */
sahilmgandhi 18:6a4db94011d3 148 kMPU_UserReadExecute = 5U, /*!< Read and execute operations are allowed in user mode. */
sahilmgandhi 18:6a4db94011d3 149 kMPU_UserReadWrite = 6U, /*!< Read and write operations are allowed in user mode. */
sahilmgandhi 18:6a4db94011d3 150 kMPU_UserReadWriteExecute = 7U /*!< Read write and execute operations are allowed in user mode. */
sahilmgandhi 18:6a4db94011d3 151 } mpu_user_access_rights_t;
sahilmgandhi 18:6a4db94011d3 152
sahilmgandhi 18:6a4db94011d3 153 /*! @brief MPU hardware basic information. */
sahilmgandhi 18:6a4db94011d3 154 typedef struct _mpu_hardware_info
sahilmgandhi 18:6a4db94011d3 155 {
sahilmgandhi 18:6a4db94011d3 156 uint8_t hardwareRevisionLevel; /*!< Specifies the MPU's hardware and definition reversion level. */
sahilmgandhi 18:6a4db94011d3 157 uint8_t slavePortsNumbers; /*!< Specifies the number of slave ports connected to MPU. */
sahilmgandhi 18:6a4db94011d3 158 mpu_region_total_num_t regionsNumbers; /*!< Indicates the number of region descriptors implemented. */
sahilmgandhi 18:6a4db94011d3 159 } mpu_hardware_info_t;
sahilmgandhi 18:6a4db94011d3 160
sahilmgandhi 18:6a4db94011d3 161 /*! @brief MPU detail error access information. */
sahilmgandhi 18:6a4db94011d3 162 typedef struct _mpu_access_err_info
sahilmgandhi 18:6a4db94011d3 163 {
sahilmgandhi 18:6a4db94011d3 164 uint32_t master; /*!< Access error master. */
sahilmgandhi 18:6a4db94011d3 165 mpu_err_attributes_t attributes; /*!< Access error attributes. */
sahilmgandhi 18:6a4db94011d3 166 mpu_err_access_type_t accessType; /*!< Access error type. */
sahilmgandhi 18:6a4db94011d3 167 mpu_err_access_control_t accessControl; /*!< Access error control. */
sahilmgandhi 18:6a4db94011d3 168 uint32_t address; /*!< Access error address. */
sahilmgandhi 18:6a4db94011d3 169 #if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
sahilmgandhi 18:6a4db94011d3 170 uint8_t processorIdentification; /*!< Access error processor identification. */
sahilmgandhi 18:6a4db94011d3 171 #endif /* FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER */
sahilmgandhi 18:6a4db94011d3 172 } mpu_access_err_info_t;
sahilmgandhi 18:6a4db94011d3 173
sahilmgandhi 18:6a4db94011d3 174 /*! @brief MPU read/write/execute rights control for bus master 0 ~ 3. */
sahilmgandhi 18:6a4db94011d3 175 typedef struct _mpu_rwxrights_master_access_control
sahilmgandhi 18:6a4db94011d3 176 {
sahilmgandhi 18:6a4db94011d3 177 mpu_supervisor_access_rights_t superAccessRights; /*!< Master access rights in supervisor mode. */
sahilmgandhi 18:6a4db94011d3 178 mpu_user_access_rights_t userAccessRights; /*!< Master access rights in user mode. */
sahilmgandhi 18:6a4db94011d3 179 #if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
sahilmgandhi 18:6a4db94011d3 180 bool processIdentifierEnable; /*!< Enables or disables process identifier. */
sahilmgandhi 18:6a4db94011d3 181 #endif /* FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER */
sahilmgandhi 18:6a4db94011d3 182 } mpu_rwxrights_master_access_control_t;
sahilmgandhi 18:6a4db94011d3 183
sahilmgandhi 18:6a4db94011d3 184 /*! @brief MPU read/write access control for bus master 4 ~ 7. */
sahilmgandhi 18:6a4db94011d3 185 typedef struct _mpu_rwrights_master_access_control
sahilmgandhi 18:6a4db94011d3 186 {
sahilmgandhi 18:6a4db94011d3 187 bool writeEnable; /*!< Enables or disables write permission. */
sahilmgandhi 18:6a4db94011d3 188 bool readEnable; /*!< Enables or disables read permission. */
sahilmgandhi 18:6a4db94011d3 189 } mpu_rwrights_master_access_control_t;
sahilmgandhi 18:6a4db94011d3 190
sahilmgandhi 18:6a4db94011d3 191 /*!
sahilmgandhi 18:6a4db94011d3 192 * @brief MPU region configuration structure.
sahilmgandhi 18:6a4db94011d3 193 *
sahilmgandhi 18:6a4db94011d3 194 * This structure is used to configure the regionNum region.
sahilmgandhi 18:6a4db94011d3 195 * The accessRights1[0] ~ accessRights1[3] are used to configure the bus master
sahilmgandhi 18:6a4db94011d3 196 * 0 ~ 3 with the privilege rights setting. The accessRights2[0] ~ accessRights2[3]
sahilmgandhi 18:6a4db94011d3 197 * are used to configure the high master 4 ~ 7 with the normal read write permission.
sahilmgandhi 18:6a4db94011d3 198 * The master port assignment is the chip configuration. Normally, the core is the
sahilmgandhi 18:6a4db94011d3 199 * master 0, debugger is the master 1.
sahilmgandhi 18:6a4db94011d3 200 * Note that the MPU assigns a priority scheme where the debugger is treated as the highest
sahilmgandhi 18:6a4db94011d3 201 * priority master followed by the core and then all the remaining masters.
sahilmgandhi 18:6a4db94011d3 202 * MPU protection does not allow writes from the core to affect the "regionNum 0" start
sahilmgandhi 18:6a4db94011d3 203 * and end address nor the permissions associated with the debugger. It can only write
sahilmgandhi 18:6a4db94011d3 204 * the permission fields associated with the other masters. This protection guarantees that
sahilmgandhi 18:6a4db94011d3 205 * the debugger always has access to the entire address space and those rights can't
sahilmgandhi 18:6a4db94011d3 206 * be changed by the core or any other bus master. Prepare
sahilmgandhi 18:6a4db94011d3 207 * the region configuration when regionNum is 0.
sahilmgandhi 18:6a4db94011d3 208 */
sahilmgandhi 18:6a4db94011d3 209 typedef struct _mpu_region_config
sahilmgandhi 18:6a4db94011d3 210 {
sahilmgandhi 18:6a4db94011d3 211 uint32_t regionNum; /*!< MPU region number, range form 0 ~ FSL_FEATURE_MPU_DESCRIPTOR_COUNT - 1. */
sahilmgandhi 18:6a4db94011d3 212 uint32_t startAddress; /*!< Memory region start address. Note: bit0 ~ bit4 always be marked as 0 by MPU. The actual
sahilmgandhi 18:6a4db94011d3 213 start address is 0-modulo-32 byte address. */
sahilmgandhi 18:6a4db94011d3 214 uint32_t endAddress; /*!< Memory region end address. Note: bit0 ~ bit4 always be marked as 1 by MPU. The actual end
sahilmgandhi 18:6a4db94011d3 215 address is 31-modulo-32 byte address. */
sahilmgandhi 18:6a4db94011d3 216 mpu_rwxrights_master_access_control_t accessRights1[4]; /*!< Masters with read, write and execute rights setting. */
sahilmgandhi 18:6a4db94011d3 217 mpu_rwrights_master_access_control_t accessRights2[4]; /*!< Masters with normal read write rights setting. */
sahilmgandhi 18:6a4db94011d3 218 #if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
sahilmgandhi 18:6a4db94011d3 219 uint8_t processIdentifier; /*!< Process identifier used when "processIdentifierEnable" set with true. */
sahilmgandhi 18:6a4db94011d3 220 uint8_t
sahilmgandhi 18:6a4db94011d3 221 processIdMask; /*!< Process identifier mask. The setting bit will ignore the same bit in process identifier. */
sahilmgandhi 18:6a4db94011d3 222 #endif /* FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER */
sahilmgandhi 18:6a4db94011d3 223 } mpu_region_config_t;
sahilmgandhi 18:6a4db94011d3 224
sahilmgandhi 18:6a4db94011d3 225 /*!
sahilmgandhi 18:6a4db94011d3 226 * @brief The configuration structure for the MPU initialization.
sahilmgandhi 18:6a4db94011d3 227 *
sahilmgandhi 18:6a4db94011d3 228 * This structure is used when calling the MPU_Init function.
sahilmgandhi 18:6a4db94011d3 229 */
sahilmgandhi 18:6a4db94011d3 230 typedef struct _mpu_config
sahilmgandhi 18:6a4db94011d3 231 {
sahilmgandhi 18:6a4db94011d3 232 mpu_region_config_t regionConfig; /*!< Region access permission. */
sahilmgandhi 18:6a4db94011d3 233 struct _mpu_config *next; /*!< Pointer to the next structure. */
sahilmgandhi 18:6a4db94011d3 234 } mpu_config_t;
sahilmgandhi 18:6a4db94011d3 235
sahilmgandhi 18:6a4db94011d3 236 /*******************************************************************************
sahilmgandhi 18:6a4db94011d3 237 * API
sahilmgandhi 18:6a4db94011d3 238 ******************************************************************************/
sahilmgandhi 18:6a4db94011d3 239
sahilmgandhi 18:6a4db94011d3 240 #if defined(__cplusplus)
sahilmgandhi 18:6a4db94011d3 241 extern "C" {
sahilmgandhi 18:6a4db94011d3 242 #endif /* _cplusplus */
sahilmgandhi 18:6a4db94011d3 243
sahilmgandhi 18:6a4db94011d3 244 /*!
sahilmgandhi 18:6a4db94011d3 245 * @name Initialization and deinitialization
sahilmgandhi 18:6a4db94011d3 246 * @{
sahilmgandhi 18:6a4db94011d3 247 */
sahilmgandhi 18:6a4db94011d3 248
sahilmgandhi 18:6a4db94011d3 249 /*!
sahilmgandhi 18:6a4db94011d3 250 * @brief Initializes the MPU with the user configuration structure.
sahilmgandhi 18:6a4db94011d3 251 *
sahilmgandhi 18:6a4db94011d3 252 * This function configures the MPU module with the user-defined configuration.
sahilmgandhi 18:6a4db94011d3 253 *
sahilmgandhi 18:6a4db94011d3 254 * @param base MPU peripheral base address.
sahilmgandhi 18:6a4db94011d3 255 * @param config The pointer to the configuration structure.
sahilmgandhi 18:6a4db94011d3 256 */
sahilmgandhi 18:6a4db94011d3 257 void MPU_Init(MPU_Type *base, const mpu_config_t *config);
sahilmgandhi 18:6a4db94011d3 258
sahilmgandhi 18:6a4db94011d3 259 /*!
sahilmgandhi 18:6a4db94011d3 260 * @brief Deinitializes the MPU regions.
sahilmgandhi 18:6a4db94011d3 261 *
sahilmgandhi 18:6a4db94011d3 262 * @param base MPU peripheral base address.
sahilmgandhi 18:6a4db94011d3 263 */
sahilmgandhi 18:6a4db94011d3 264 void MPU_Deinit(MPU_Type *base);
sahilmgandhi 18:6a4db94011d3 265
sahilmgandhi 18:6a4db94011d3 266 /* @}*/
sahilmgandhi 18:6a4db94011d3 267
sahilmgandhi 18:6a4db94011d3 268 /*!
sahilmgandhi 18:6a4db94011d3 269 * @name Basic Control Operations
sahilmgandhi 18:6a4db94011d3 270 * @{
sahilmgandhi 18:6a4db94011d3 271 */
sahilmgandhi 18:6a4db94011d3 272
sahilmgandhi 18:6a4db94011d3 273 /*!
sahilmgandhi 18:6a4db94011d3 274 * @brief Enables/disables the MPU globally.
sahilmgandhi 18:6a4db94011d3 275 *
sahilmgandhi 18:6a4db94011d3 276 * Call this API to enable or disable the MPU module.
sahilmgandhi 18:6a4db94011d3 277 *
sahilmgandhi 18:6a4db94011d3 278 * @param base MPU peripheral base address.
sahilmgandhi 18:6a4db94011d3 279 * @param enable True enable MPU, false disable MPU.
sahilmgandhi 18:6a4db94011d3 280 */
sahilmgandhi 18:6a4db94011d3 281 static inline void MPU_Enable(MPU_Type *base, bool enable)
sahilmgandhi 18:6a4db94011d3 282 {
sahilmgandhi 18:6a4db94011d3 283 if (enable)
sahilmgandhi 18:6a4db94011d3 284 {
sahilmgandhi 18:6a4db94011d3 285 /* Enable the MPU globally. */
sahilmgandhi 18:6a4db94011d3 286 base->CESR |= MPU_CESR_VLD_MASK;
sahilmgandhi 18:6a4db94011d3 287 }
sahilmgandhi 18:6a4db94011d3 288 else
sahilmgandhi 18:6a4db94011d3 289 { /* Disable the MPU globally. */
sahilmgandhi 18:6a4db94011d3 290 base->CESR &= ~MPU_CESR_VLD_MASK;
sahilmgandhi 18:6a4db94011d3 291 }
sahilmgandhi 18:6a4db94011d3 292 }
sahilmgandhi 18:6a4db94011d3 293
sahilmgandhi 18:6a4db94011d3 294 /*!
sahilmgandhi 18:6a4db94011d3 295 * @brief Enables/disables the MPU for a special region.
sahilmgandhi 18:6a4db94011d3 296 *
sahilmgandhi 18:6a4db94011d3 297 * When MPU is enabled, call this API to disable an unused region
sahilmgandhi 18:6a4db94011d3 298 * of an enabled MPU. Call this API to minimize the power dissipation.
sahilmgandhi 18:6a4db94011d3 299 *
sahilmgandhi 18:6a4db94011d3 300 * @param base MPU peripheral base address.
sahilmgandhi 18:6a4db94011d3 301 * @param number MPU region number.
sahilmgandhi 18:6a4db94011d3 302 * @param enable True enable the special region MPU, false disable the special region MPU.
sahilmgandhi 18:6a4db94011d3 303 */
sahilmgandhi 18:6a4db94011d3 304 static inline void MPU_RegionEnable(MPU_Type *base, uint32_t number, bool enable)
sahilmgandhi 18:6a4db94011d3 305 {
sahilmgandhi 18:6a4db94011d3 306 if (enable)
sahilmgandhi 18:6a4db94011d3 307 {
sahilmgandhi 18:6a4db94011d3 308 /* Enable the #number region MPU. */
sahilmgandhi 18:6a4db94011d3 309 base->WORD[number][3] |= MPU_WORD_VLD_MASK;
sahilmgandhi 18:6a4db94011d3 310 }
sahilmgandhi 18:6a4db94011d3 311 else
sahilmgandhi 18:6a4db94011d3 312 { /* Disable the #number region MPU. */
sahilmgandhi 18:6a4db94011d3 313 base->WORD[number][3] &= ~MPU_WORD_VLD_MASK;
sahilmgandhi 18:6a4db94011d3 314 }
sahilmgandhi 18:6a4db94011d3 315 }
sahilmgandhi 18:6a4db94011d3 316
sahilmgandhi 18:6a4db94011d3 317 /*!
sahilmgandhi 18:6a4db94011d3 318 * @brief Gets the MPU basic hardware information.
sahilmgandhi 18:6a4db94011d3 319 *
sahilmgandhi 18:6a4db94011d3 320 * @param base MPU peripheral base address.
sahilmgandhi 18:6a4db94011d3 321 * @param hardwareInform The pointer to the MPU hardware information structure. See "mpu_hardware_info_t".
sahilmgandhi 18:6a4db94011d3 322 */
sahilmgandhi 18:6a4db94011d3 323 void MPU_GetHardwareInfo(MPU_Type *base, mpu_hardware_info_t *hardwareInform);
sahilmgandhi 18:6a4db94011d3 324
sahilmgandhi 18:6a4db94011d3 325 /*!
sahilmgandhi 18:6a4db94011d3 326 * @brief Sets the MPU region.
sahilmgandhi 18:6a4db94011d3 327 *
sahilmgandhi 18:6a4db94011d3 328 * Note: Due to the MPU protection, the region number 0 does not allow writes from
sahilmgandhi 18:6a4db94011d3 329 * core to affect the start and end address nor the permissions associated with
sahilmgandhi 18:6a4db94011d3 330 * the debugger. It can only write the permission fields associated
sahilmgandhi 18:6a4db94011d3 331 * with the other masters.
sahilmgandhi 18:6a4db94011d3 332 *
sahilmgandhi 18:6a4db94011d3 333 * @param base MPU peripheral base address.
sahilmgandhi 18:6a4db94011d3 334 * @param regionConfig The pointer to the MPU user configuration structure. See "mpu_region_config_t".
sahilmgandhi 18:6a4db94011d3 335 */
sahilmgandhi 18:6a4db94011d3 336 void MPU_SetRegionConfig(MPU_Type *base, const mpu_region_config_t *regionConfig);
sahilmgandhi 18:6a4db94011d3 337
sahilmgandhi 18:6a4db94011d3 338 /*!
sahilmgandhi 18:6a4db94011d3 339 * @brief Sets the region start and end address.
sahilmgandhi 18:6a4db94011d3 340 *
sahilmgandhi 18:6a4db94011d3 341 * Memory region start address. Note: bit0 ~ bit4 is always marked as 0 by MPU.
sahilmgandhi 18:6a4db94011d3 342 * The actual start address by MPU is 0-modulo-32 byte address.
sahilmgandhi 18:6a4db94011d3 343 * Memory region end address. Note: bit0 ~ bit4 always be marked as 1 by MPU.
sahilmgandhi 18:6a4db94011d3 344 * The end address used by the MPU is 31-modulo-32 byte address.
sahilmgandhi 18:6a4db94011d3 345 * Note: Due to the MPU protection, the startAddr and endAddr can't be
sahilmgandhi 18:6a4db94011d3 346 * changed by the core when regionNum is 0.
sahilmgandhi 18:6a4db94011d3 347 *
sahilmgandhi 18:6a4db94011d3 348 * @param base MPU peripheral base address.
sahilmgandhi 18:6a4db94011d3 349 * @param regionNum MPU region number. The range is from 0 to
sahilmgandhi 18:6a4db94011d3 350 * FSL_FEATURE_MPU_DESCRIPTOR_COUNT - 1.
sahilmgandhi 18:6a4db94011d3 351 * @param startAddr Region start address.
sahilmgandhi 18:6a4db94011d3 352 * @param endAddr Region end address.
sahilmgandhi 18:6a4db94011d3 353 */
sahilmgandhi 18:6a4db94011d3 354 void MPU_SetRegionAddr(MPU_Type *base, uint32_t regionNum, uint32_t startAddr, uint32_t endAddr);
sahilmgandhi 18:6a4db94011d3 355
sahilmgandhi 18:6a4db94011d3 356 /*!
sahilmgandhi 18:6a4db94011d3 357 * @brief Sets the MPU region access rights for masters with read, write, and execute rights.
sahilmgandhi 18:6a4db94011d3 358 * The MPU access rights depend on two board classifications of bus masters.
sahilmgandhi 18:6a4db94011d3 359 * The privilege rights masters and the normal rights masters.
sahilmgandhi 18:6a4db94011d3 360 * The privilege rights masters have the read, write, and execute access rights.
sahilmgandhi 18:6a4db94011d3 361 * Except the normal read and write rights, the execute rights are also
sahilmgandhi 18:6a4db94011d3 362 * allowed for these masters. The privilege rights masters normally range from
sahilmgandhi 18:6a4db94011d3 363 * bus masters 0 - 3. However, the maximum master number is device-specific.
sahilmgandhi 18:6a4db94011d3 364 * See the "MPU_PRIVILEGED_RIGHTS_MASTER_MAX_INDEX".
sahilmgandhi 18:6a4db94011d3 365 * The normal rights masters access rights control see
sahilmgandhi 18:6a4db94011d3 366 * "MPU_SetRegionRwMasterAccessRights()".
sahilmgandhi 18:6a4db94011d3 367 *
sahilmgandhi 18:6a4db94011d3 368 * @param base MPU peripheral base address.
sahilmgandhi 18:6a4db94011d3 369 * @param regionNum MPU region number. Should range from 0 to
sahilmgandhi 18:6a4db94011d3 370 * FSL_FEATURE_MPU_DESCRIPTOR_COUNT - 1.
sahilmgandhi 18:6a4db94011d3 371 * @param masterNum MPU bus master number. Should range from 0 to
sahilmgandhi 18:6a4db94011d3 372 * MPU_PRIVILEGED_RIGHTS_MASTER_MAX_INDEX.
sahilmgandhi 18:6a4db94011d3 373 * @param accessRights The pointer to the MPU access rights configuration. See "mpu_rwxrights_master_access_control_t".
sahilmgandhi 18:6a4db94011d3 374 */
sahilmgandhi 18:6a4db94011d3 375 void MPU_SetRegionRwxMasterAccessRights(MPU_Type *base,
sahilmgandhi 18:6a4db94011d3 376 uint32_t regionNum,
sahilmgandhi 18:6a4db94011d3 377 uint32_t masterNum,
sahilmgandhi 18:6a4db94011d3 378 const mpu_rwxrights_master_access_control_t *accessRights);
sahilmgandhi 18:6a4db94011d3 379 #if FSL_FEATURE_MPU_HAS_MASTER_4_7
sahilmgandhi 18:6a4db94011d3 380 /*!
sahilmgandhi 18:6a4db94011d3 381 * @brief Sets the MPU region access rights for masters with read and write rights.
sahilmgandhi 18:6a4db94011d3 382 * The MPU access rights depend on two board classifications of bus masters.
sahilmgandhi 18:6a4db94011d3 383 * The privilege rights masters and the normal rights masters.
sahilmgandhi 18:6a4db94011d3 384 * The normal rights masters only have the read and write access permissions.
sahilmgandhi 18:6a4db94011d3 385 * The privilege rights access control see "MPU_SetRegionRwxMasterAccessRights".
sahilmgandhi 18:6a4db94011d3 386 *
sahilmgandhi 18:6a4db94011d3 387 * @param base MPU peripheral base address.
sahilmgandhi 18:6a4db94011d3 388 * @param regionNum MPU region number. The range is from 0 to
sahilmgandhi 18:6a4db94011d3 389 * FSL_FEATURE_MPU_DESCRIPTOR_COUNT - 1.
sahilmgandhi 18:6a4db94011d3 390 * @param masterNum MPU bus master number. Should range from FSL_FEATURE_MPU_PRIVILEGED_RIGHTS_MASTER_COUNT
sahilmgandhi 18:6a4db94011d3 391 * to ~ FSL_FEATURE_MPU_MASTER_MAX_INDEX.
sahilmgandhi 18:6a4db94011d3 392 * @param accessRights The pointer to the MPU access rights configuration. See "mpu_rwrights_master_access_control_t".
sahilmgandhi 18:6a4db94011d3 393 */
sahilmgandhi 18:6a4db94011d3 394 void MPU_SetRegionRwMasterAccessRights(MPU_Type *base,
sahilmgandhi 18:6a4db94011d3 395 uint32_t regionNum,
sahilmgandhi 18:6a4db94011d3 396 uint32_t masterNum,
sahilmgandhi 18:6a4db94011d3 397 const mpu_rwrights_master_access_control_t *accessRights);
sahilmgandhi 18:6a4db94011d3 398 #endif /* FSL_FEATURE_MPU_HAS_MASTER_4_7 */
sahilmgandhi 18:6a4db94011d3 399 /*!
sahilmgandhi 18:6a4db94011d3 400 * @brief Gets the numbers of slave ports where errors occur.
sahilmgandhi 18:6a4db94011d3 401 *
sahilmgandhi 18:6a4db94011d3 402 * @param base MPU peripheral base address.
sahilmgandhi 18:6a4db94011d3 403 * @param slaveNum MPU slave port number.
sahilmgandhi 18:6a4db94011d3 404 * @return The slave ports error status.
sahilmgandhi 18:6a4db94011d3 405 * true - error happens in this slave port.
sahilmgandhi 18:6a4db94011d3 406 * false - error didn't happen in this slave port.
sahilmgandhi 18:6a4db94011d3 407 */
sahilmgandhi 18:6a4db94011d3 408 bool MPU_GetSlavePortErrorStatus(MPU_Type *base, mpu_slave_t slaveNum);
sahilmgandhi 18:6a4db94011d3 409
sahilmgandhi 18:6a4db94011d3 410 /*!
sahilmgandhi 18:6a4db94011d3 411 * @brief Gets the MPU detailed error access information.
sahilmgandhi 18:6a4db94011d3 412 *
sahilmgandhi 18:6a4db94011d3 413 * @param base MPU peripheral base address.
sahilmgandhi 18:6a4db94011d3 414 * @param slaveNum MPU slave port number.
sahilmgandhi 18:6a4db94011d3 415 * @param errInform The pointer to the MPU access error information. See "mpu_access_err_info_t".
sahilmgandhi 18:6a4db94011d3 416 */
sahilmgandhi 18:6a4db94011d3 417 void MPU_GetDetailErrorAccessInfo(MPU_Type *base, mpu_slave_t slaveNum, mpu_access_err_info_t *errInform);
sahilmgandhi 18:6a4db94011d3 418
sahilmgandhi 18:6a4db94011d3 419 /* @} */
sahilmgandhi 18:6a4db94011d3 420
sahilmgandhi 18:6a4db94011d3 421 #if defined(__cplusplus)
sahilmgandhi 18:6a4db94011d3 422 }
sahilmgandhi 18:6a4db94011d3 423 #endif
sahilmgandhi 18:6a4db94011d3 424
sahilmgandhi 18:6a4db94011d3 425 /*! @}*/
sahilmgandhi 18:6a4db94011d3 426
sahilmgandhi 18:6a4db94011d3 427 #endif /* _FSL_MPU_H_ */