MacroRat / MouseCode

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/device/system_MK82F25615.c@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /*
sahilmgandhi 18:6a4db94011d3 2 ** ###################################################################
sahilmgandhi 18:6a4db94011d3 3 ** Processors: MK82FN256CAx15
sahilmgandhi 18:6a4db94011d3 4 ** MK82FN256VDC15
sahilmgandhi 18:6a4db94011d3 5 ** MK82FN256VLL15
sahilmgandhi 18:6a4db94011d3 6 ** MK82FN256VLQ15
sahilmgandhi 18:6a4db94011d3 7 **
sahilmgandhi 18:6a4db94011d3 8 ** Compilers: Keil ARM C/C++ Compiler
sahilmgandhi 18:6a4db94011d3 9 ** Freescale C/C++ for Embedded ARM
sahilmgandhi 18:6a4db94011d3 10 ** GNU C Compiler
sahilmgandhi 18:6a4db94011d3 11 ** IAR ANSI C/C++ Compiler for ARM
sahilmgandhi 18:6a4db94011d3 12 **
sahilmgandhi 18:6a4db94011d3 13 ** Reference manual: K82P121M150SF5RM, Rev. 0, May 2015
sahilmgandhi 18:6a4db94011d3 14 ** Version: rev. 1.2, 2015-07-29
sahilmgandhi 18:6a4db94011d3 15 ** Build: b151216
sahilmgandhi 18:6a4db94011d3 16 **
sahilmgandhi 18:6a4db94011d3 17 ** Abstract:
sahilmgandhi 18:6a4db94011d3 18 ** Provides a system configuration function and a global variable that
sahilmgandhi 18:6a4db94011d3 19 ** contains the system frequency. It configures the device and initializes
sahilmgandhi 18:6a4db94011d3 20 ** the oscillator (PLL) that is part of the microcontroller device.
sahilmgandhi 18:6a4db94011d3 21 **
sahilmgandhi 18:6a4db94011d3 22 ** Copyright (c) 2015 Freescale Semiconductor, Inc.
sahilmgandhi 18:6a4db94011d3 23 ** All rights reserved.
sahilmgandhi 18:6a4db94011d3 24 **
sahilmgandhi 18:6a4db94011d3 25 ** Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi 18:6a4db94011d3 26 ** are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 27 **
sahilmgandhi 18:6a4db94011d3 28 ** o Redistributions of source code must retain the above copyright notice, this list
sahilmgandhi 18:6a4db94011d3 29 ** of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 30 **
sahilmgandhi 18:6a4db94011d3 31 ** o Redistributions in binary form must reproduce the above copyright notice, this
sahilmgandhi 18:6a4db94011d3 32 ** list of conditions and the following disclaimer in the documentation and/or
sahilmgandhi 18:6a4db94011d3 33 ** other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 34 **
sahilmgandhi 18:6a4db94011d3 35 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
sahilmgandhi 18:6a4db94011d3 36 ** contributors may be used to endorse or promote products derived from this
sahilmgandhi 18:6a4db94011d3 37 ** software without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 38 **
sahilmgandhi 18:6a4db94011d3 39 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
sahilmgandhi 18:6a4db94011d3 40 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
sahilmgandhi 18:6a4db94011d3 41 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 42 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
sahilmgandhi 18:6a4db94011d3 43 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
sahilmgandhi 18:6a4db94011d3 44 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
sahilmgandhi 18:6a4db94011d3 45 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
sahilmgandhi 18:6a4db94011d3 46 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
sahilmgandhi 18:6a4db94011d3 47 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
sahilmgandhi 18:6a4db94011d3 48 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 49 **
sahilmgandhi 18:6a4db94011d3 50 ** http: www.freescale.com
sahilmgandhi 18:6a4db94011d3 51 ** mail: support@freescale.com
sahilmgandhi 18:6a4db94011d3 52 **
sahilmgandhi 18:6a4db94011d3 53 ** Revisions:
sahilmgandhi 18:6a4db94011d3 54 ** - rev. 1.0 (2015-04-09)
sahilmgandhi 18:6a4db94011d3 55 ** Initial version
sahilmgandhi 18:6a4db94011d3 56 ** - rev. 1.1 (2015-05-28)
sahilmgandhi 18:6a4db94011d3 57 ** Update according to the reference manual Rev. 0.
sahilmgandhi 18:6a4db94011d3 58 ** - rev. 1.2 (2015-07-29)
sahilmgandhi 18:6a4db94011d3 59 ** Correction of backward compatibility.
sahilmgandhi 18:6a4db94011d3 60 **
sahilmgandhi 18:6a4db94011d3 61 ** ###################################################################
sahilmgandhi 18:6a4db94011d3 62 */
sahilmgandhi 18:6a4db94011d3 63
sahilmgandhi 18:6a4db94011d3 64 /*!
sahilmgandhi 18:6a4db94011d3 65 * @file MK82F25615
sahilmgandhi 18:6a4db94011d3 66 * @version 1.2
sahilmgandhi 18:6a4db94011d3 67 * @date 2015-07-29
sahilmgandhi 18:6a4db94011d3 68 * @brief Device specific configuration file for MK82F25615 (implementation file)
sahilmgandhi 18:6a4db94011d3 69 *
sahilmgandhi 18:6a4db94011d3 70 * Provides a system configuration function and a global variable that contains
sahilmgandhi 18:6a4db94011d3 71 * the system frequency. It configures the device and initializes the oscillator
sahilmgandhi 18:6a4db94011d3 72 * (PLL) that is part of the microcontroller device.
sahilmgandhi 18:6a4db94011d3 73 */
sahilmgandhi 18:6a4db94011d3 74
sahilmgandhi 18:6a4db94011d3 75 #include <stdint.h>
sahilmgandhi 18:6a4db94011d3 76 #include "fsl_device_registers.h"
sahilmgandhi 18:6a4db94011d3 77
sahilmgandhi 18:6a4db94011d3 78
sahilmgandhi 18:6a4db94011d3 79
sahilmgandhi 18:6a4db94011d3 80 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 81 -- Core clock
sahilmgandhi 18:6a4db94011d3 82 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 83
sahilmgandhi 18:6a4db94011d3 84 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
sahilmgandhi 18:6a4db94011d3 85
sahilmgandhi 18:6a4db94011d3 86 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 87 -- SystemInit()
sahilmgandhi 18:6a4db94011d3 88 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 89
sahilmgandhi 18:6a4db94011d3 90 void SystemInit (void) {
sahilmgandhi 18:6a4db94011d3 91 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
sahilmgandhi 18:6a4db94011d3 92 SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
sahilmgandhi 18:6a4db94011d3 93 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
sahilmgandhi 18:6a4db94011d3 94
sahilmgandhi 18:6a4db94011d3 95 #if (DISABLE_WDOG)
sahilmgandhi 18:6a4db94011d3 96 /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
sahilmgandhi 18:6a4db94011d3 97 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
sahilmgandhi 18:6a4db94011d3 98 /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
sahilmgandhi 18:6a4db94011d3 99 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
sahilmgandhi 18:6a4db94011d3 100 /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
sahilmgandhi 18:6a4db94011d3 101 WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
sahilmgandhi 18:6a4db94011d3 102 WDOG_STCTRLH_WAITEN_MASK |
sahilmgandhi 18:6a4db94011d3 103 WDOG_STCTRLH_STOPEN_MASK |
sahilmgandhi 18:6a4db94011d3 104 WDOG_STCTRLH_ALLOWUPDATE_MASK |
sahilmgandhi 18:6a4db94011d3 105 WDOG_STCTRLH_CLKSRC_MASK |
sahilmgandhi 18:6a4db94011d3 106 0x0100U;
sahilmgandhi 18:6a4db94011d3 107 #endif /* (DISABLE_WDOG) */
sahilmgandhi 18:6a4db94011d3 108
sahilmgandhi 18:6a4db94011d3 109 }
sahilmgandhi 18:6a4db94011d3 110
sahilmgandhi 18:6a4db94011d3 111 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 112 -- SystemCoreClockUpdate()
sahilmgandhi 18:6a4db94011d3 113 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 114
sahilmgandhi 18:6a4db94011d3 115 void SystemCoreClockUpdate (void) {
sahilmgandhi 18:6a4db94011d3 116
sahilmgandhi 18:6a4db94011d3 117 uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
sahilmgandhi 18:6a4db94011d3 118 uint16_t Divider;
sahilmgandhi 18:6a4db94011d3 119
sahilmgandhi 18:6a4db94011d3 120 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
sahilmgandhi 18:6a4db94011d3 121 /* Output of FLL or PLL is selected */
sahilmgandhi 18:6a4db94011d3 122 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
sahilmgandhi 18:6a4db94011d3 123 /* FLL is selected */
sahilmgandhi 18:6a4db94011d3 124 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
sahilmgandhi 18:6a4db94011d3 125 /* External reference clock is selected */
sahilmgandhi 18:6a4db94011d3 126 switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
sahilmgandhi 18:6a4db94011d3 127 case 0x00U:
sahilmgandhi 18:6a4db94011d3 128 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
sahilmgandhi 18:6a4db94011d3 129 break;
sahilmgandhi 18:6a4db94011d3 130 case 0x01U:
sahilmgandhi 18:6a4db94011d3 131 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
sahilmgandhi 18:6a4db94011d3 132 break;
sahilmgandhi 18:6a4db94011d3 133 case 0x02U:
sahilmgandhi 18:6a4db94011d3 134 default:
sahilmgandhi 18:6a4db94011d3 135 MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
sahilmgandhi 18:6a4db94011d3 136 break;
sahilmgandhi 18:6a4db94011d3 137 }
sahilmgandhi 18:6a4db94011d3 138 if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
sahilmgandhi 18:6a4db94011d3 139 switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
sahilmgandhi 18:6a4db94011d3 140 case 0x38U:
sahilmgandhi 18:6a4db94011d3 141 Divider = 1536U;
sahilmgandhi 18:6a4db94011d3 142 break;
sahilmgandhi 18:6a4db94011d3 143 case 0x30U:
sahilmgandhi 18:6a4db94011d3 144 Divider = 1280U;
sahilmgandhi 18:6a4db94011d3 145 break;
sahilmgandhi 18:6a4db94011d3 146 default:
sahilmgandhi 18:6a4db94011d3 147 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
sahilmgandhi 18:6a4db94011d3 148 break;
sahilmgandhi 18:6a4db94011d3 149 }
sahilmgandhi 18:6a4db94011d3 150 } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
sahilmgandhi 18:6a4db94011d3 151 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
sahilmgandhi 18:6a4db94011d3 152 }
sahilmgandhi 18:6a4db94011d3 153 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
sahilmgandhi 18:6a4db94011d3 154 } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
sahilmgandhi 18:6a4db94011d3 155 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
sahilmgandhi 18:6a4db94011d3 156 } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
sahilmgandhi 18:6a4db94011d3 157 /* Select correct multiplier to calculate the MCG output clock */
sahilmgandhi 18:6a4db94011d3 158 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
sahilmgandhi 18:6a4db94011d3 159 case 0x00U:
sahilmgandhi 18:6a4db94011d3 160 MCGOUTClock *= 640U;
sahilmgandhi 18:6a4db94011d3 161 break;
sahilmgandhi 18:6a4db94011d3 162 case 0x20U:
sahilmgandhi 18:6a4db94011d3 163 MCGOUTClock *= 1280U;
sahilmgandhi 18:6a4db94011d3 164 break;
sahilmgandhi 18:6a4db94011d3 165 case 0x40U:
sahilmgandhi 18:6a4db94011d3 166 MCGOUTClock *= 1920U;
sahilmgandhi 18:6a4db94011d3 167 break;
sahilmgandhi 18:6a4db94011d3 168 case 0x60U:
sahilmgandhi 18:6a4db94011d3 169 MCGOUTClock *= 2560U;
sahilmgandhi 18:6a4db94011d3 170 break;
sahilmgandhi 18:6a4db94011d3 171 case 0x80U:
sahilmgandhi 18:6a4db94011d3 172 MCGOUTClock *= 732U;
sahilmgandhi 18:6a4db94011d3 173 break;
sahilmgandhi 18:6a4db94011d3 174 case 0xA0U:
sahilmgandhi 18:6a4db94011d3 175 MCGOUTClock *= 1464U;
sahilmgandhi 18:6a4db94011d3 176 break;
sahilmgandhi 18:6a4db94011d3 177 case 0xC0U:
sahilmgandhi 18:6a4db94011d3 178 MCGOUTClock *= 2197U;
sahilmgandhi 18:6a4db94011d3 179 break;
sahilmgandhi 18:6a4db94011d3 180 case 0xE0U:
sahilmgandhi 18:6a4db94011d3 181 MCGOUTClock *= 2929U;
sahilmgandhi 18:6a4db94011d3 182 break;
sahilmgandhi 18:6a4db94011d3 183 default:
sahilmgandhi 18:6a4db94011d3 184 break;
sahilmgandhi 18:6a4db94011d3 185 }
sahilmgandhi 18:6a4db94011d3 186 } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
sahilmgandhi 18:6a4db94011d3 187 /* PLL is selected */
sahilmgandhi 18:6a4db94011d3 188 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV_MASK) + 0x01U);
sahilmgandhi 18:6a4db94011d3 189 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
sahilmgandhi 18:6a4db94011d3 190 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV_MASK) + 16U);
sahilmgandhi 18:6a4db94011d3 191 MCGOUTClock *= Divider; /* Calculate the VCO output clock */
sahilmgandhi 18:6a4db94011d3 192 MCGOUTClock /= 2; /* Calculate the MCG output clock */
sahilmgandhi 18:6a4db94011d3 193 } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
sahilmgandhi 18:6a4db94011d3 194 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
sahilmgandhi 18:6a4db94011d3 195 /* Internal reference clock is selected */
sahilmgandhi 18:6a4db94011d3 196 if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
sahilmgandhi 18:6a4db94011d3 197 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
sahilmgandhi 18:6a4db94011d3 198 } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
sahilmgandhi 18:6a4db94011d3 199 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
sahilmgandhi 18:6a4db94011d3 200 MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
sahilmgandhi 18:6a4db94011d3 201 } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
sahilmgandhi 18:6a4db94011d3 202 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
sahilmgandhi 18:6a4db94011d3 203 /* External reference clock is selected */
sahilmgandhi 18:6a4db94011d3 204 switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
sahilmgandhi 18:6a4db94011d3 205 case 0x00U:
sahilmgandhi 18:6a4db94011d3 206 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
sahilmgandhi 18:6a4db94011d3 207 break;
sahilmgandhi 18:6a4db94011d3 208 case 0x01U:
sahilmgandhi 18:6a4db94011d3 209 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
sahilmgandhi 18:6a4db94011d3 210 break;
sahilmgandhi 18:6a4db94011d3 211 case 0x02U:
sahilmgandhi 18:6a4db94011d3 212 default:
sahilmgandhi 18:6a4db94011d3 213 MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
sahilmgandhi 18:6a4db94011d3 214 break;
sahilmgandhi 18:6a4db94011d3 215 }
sahilmgandhi 18:6a4db94011d3 216 } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
sahilmgandhi 18:6a4db94011d3 217 /* Reserved value */
sahilmgandhi 18:6a4db94011d3 218 return;
sahilmgandhi 18:6a4db94011d3 219 } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
sahilmgandhi 18:6a4db94011d3 220 SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
sahilmgandhi 18:6a4db94011d3 221 }