MacroRat / MouseCode

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Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_Freescale/TARGET_KLXX/rtc_api.c@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2006-2013 ARM Limited
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 */
sahilmgandhi 18:6a4db94011d3 16
sahilmgandhi 18:6a4db94011d3 17 #if DEVICE_RTC
sahilmgandhi 18:6a4db94011d3 18
sahilmgandhi 18:6a4db94011d3 19 #include "rtc_api.h"
sahilmgandhi 18:6a4db94011d3 20 #include "PeripheralPins.h"
sahilmgandhi 18:6a4db94011d3 21 #include "clk_freqs.h"
sahilmgandhi 18:6a4db94011d3 22
sahilmgandhi 18:6a4db94011d3 23 static void init(void) {
sahilmgandhi 18:6a4db94011d3 24 // enable RTC clock
sahilmgandhi 18:6a4db94011d3 25 SIM->SCGC6 |= SIM_SCGC6_RTC_MASK;
sahilmgandhi 18:6a4db94011d3 26
sahilmgandhi 18:6a4db94011d3 27 // select RTC clock source
sahilmgandhi 18:6a4db94011d3 28 SIM->SOPT1 &= ~SIM_SOPT1_OSC32KSEL_MASK;
sahilmgandhi 18:6a4db94011d3 29
sahilmgandhi 18:6a4db94011d3 30 // Enable external crystal source if clock source is 32KHz
sahilmgandhi 18:6a4db94011d3 31 if (extosc_frequency()==32768) {
sahilmgandhi 18:6a4db94011d3 32 SIM->SOPT1 |= SIM_SOPT1_OSC32KSEL(OSC32KCLK);
sahilmgandhi 18:6a4db94011d3 33 }
sahilmgandhi 18:6a4db94011d3 34 else{
sahilmgandhi 18:6a4db94011d3 35 // If main clock is NOT 32KHz crystal, use external 32KHz clock source defined in PeripheralPins.c
sahilmgandhi 18:6a4db94011d3 36 SIM->SOPT1 |= SIM_SOPT1_OSC32KSEL(PinMap_RTC[0].peripheral);
sahilmgandhi 18:6a4db94011d3 37 pinmap_pinout(PinMap_RTC[0].pin, PinMap_RTC); //Map RTC clk input (if not NC)
sahilmgandhi 18:6a4db94011d3 38 }
sahilmgandhi 18:6a4db94011d3 39 }
sahilmgandhi 18:6a4db94011d3 40
sahilmgandhi 18:6a4db94011d3 41 void rtc_init(void) {
sahilmgandhi 18:6a4db94011d3 42 init();
sahilmgandhi 18:6a4db94011d3 43
sahilmgandhi 18:6a4db94011d3 44 // Configure the TSR. default value: 1
sahilmgandhi 18:6a4db94011d3 45 RTC->TSR = 1;
sahilmgandhi 18:6a4db94011d3 46
sahilmgandhi 18:6a4db94011d3 47 // Configure Time Compensation Register to calibrate RTC accuracy
sahilmgandhi 18:6a4db94011d3 48
sahilmgandhi 18:6a4db94011d3 49 // dissable LRL lock
sahilmgandhi 18:6a4db94011d3 50 RTC->LR &= ~RTC_LR_LRL_MASK;
sahilmgandhi 18:6a4db94011d3 51 // RTC->TCR: RTC_TCR_CIR_MASK,RTC_TCR_CIR(x)=0,RTC_TCR_TCR(x)=0 Default no correction
sahilmgandhi 18:6a4db94011d3 52 RTC->TCR = RTC_TCR_CIR(0) | RTC_TCR_TCR(0);
sahilmgandhi 18:6a4db94011d3 53 /*
sahilmgandhi 18:6a4db94011d3 54 RTC_TCR_CIR(x) sets the compensation interval in seconds from 1 to 256.
sahilmgandhi 18:6a4db94011d3 55 0x05 will apply the compensation once every 4 seconds.
sahilmgandhi 18:6a4db94011d3 56
sahilmgandhi 18:6a4db94011d3 57 RTC_TCR_TCR(x) sets the Register Overflow
sahilmgandhi 18:6a4db94011d3 58 0x80 Time Prescaler Register overflows every 32896 clock cycles. (+128)
sahilmgandhi 18:6a4db94011d3 59 ... ... RTC runs slower
sahilmgandhi 18:6a4db94011d3 60 0xFF Time Prescaler Register overflows every 32769 clock cycles.
sahilmgandhi 18:6a4db94011d3 61 0x00 Time Prescaler Register overflows every 32768 clock cycles, Default.
sahilmgandhi 18:6a4db94011d3 62 0x01 Time Prescaler Register overflows every 32767 clock cycles.
sahilmgandhi 18:6a4db94011d3 63 ... ... RTC runs faster
sahilmgandhi 18:6a4db94011d3 64 0x7F Time Prescaler Register overflows every 32641 clock cycles. (-128)
sahilmgandhi 18:6a4db94011d3 65 */
sahilmgandhi 18:6a4db94011d3 66 // enable TCL lock
sahilmgandhi 18:6a4db94011d3 67 RTC->LR |= RTC_LR_TCL_MASK;
sahilmgandhi 18:6a4db94011d3 68 // enable LRL lock
sahilmgandhi 18:6a4db94011d3 69 RTC->LR |= RTC_LR_LRL_MASK;
sahilmgandhi 18:6a4db94011d3 70
sahilmgandhi 18:6a4db94011d3 71 // enable counter
sahilmgandhi 18:6a4db94011d3 72 RTC->SR |= RTC_SR_TCE_MASK;
sahilmgandhi 18:6a4db94011d3 73 }
sahilmgandhi 18:6a4db94011d3 74
sahilmgandhi 18:6a4db94011d3 75 void rtc_free(void) {
sahilmgandhi 18:6a4db94011d3 76 // [TODO]
sahilmgandhi 18:6a4db94011d3 77 }
sahilmgandhi 18:6a4db94011d3 78
sahilmgandhi 18:6a4db94011d3 79 /*
sahilmgandhi 18:6a4db94011d3 80 * Little check routine to see if the RTC has been enabled
sahilmgandhi 18:6a4db94011d3 81 * 0 = Disabled, 1 = Enabled
sahilmgandhi 18:6a4db94011d3 82 */
sahilmgandhi 18:6a4db94011d3 83 int rtc_isenabled(void) {
sahilmgandhi 18:6a4db94011d3 84 // even if the RTC module is enabled,
sahilmgandhi 18:6a4db94011d3 85 // as we use RTC_CLKIN and an external clock,
sahilmgandhi 18:6a4db94011d3 86 // we need to reconfigure the pins. That is why we
sahilmgandhi 18:6a4db94011d3 87 // call init() if the rtc is enabled
sahilmgandhi 18:6a4db94011d3 88
sahilmgandhi 18:6a4db94011d3 89 // if RTC not enabled return 0
sahilmgandhi 18:6a4db94011d3 90 SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK;
sahilmgandhi 18:6a4db94011d3 91 SIM->SCGC6 |= SIM_SCGC6_RTC_MASK;
sahilmgandhi 18:6a4db94011d3 92 if ((RTC->SR & RTC_SR_TCE_MASK) == 0)
sahilmgandhi 18:6a4db94011d3 93 return 0;
sahilmgandhi 18:6a4db94011d3 94
sahilmgandhi 18:6a4db94011d3 95 init();
sahilmgandhi 18:6a4db94011d3 96 return 1;
sahilmgandhi 18:6a4db94011d3 97 }
sahilmgandhi 18:6a4db94011d3 98
sahilmgandhi 18:6a4db94011d3 99 time_t rtc_read(void) {
sahilmgandhi 18:6a4db94011d3 100 return RTC->TSR;
sahilmgandhi 18:6a4db94011d3 101 }
sahilmgandhi 18:6a4db94011d3 102
sahilmgandhi 18:6a4db94011d3 103 void rtc_write(time_t t) {
sahilmgandhi 18:6a4db94011d3 104 // disable counter
sahilmgandhi 18:6a4db94011d3 105 RTC->SR &= ~RTC_SR_TCE_MASK;
sahilmgandhi 18:6a4db94011d3 106
sahilmgandhi 18:6a4db94011d3 107 // we do not write 0 into TSR
sahilmgandhi 18:6a4db94011d3 108 // to avoid invalid time
sahilmgandhi 18:6a4db94011d3 109 if (t == 0)
sahilmgandhi 18:6a4db94011d3 110 t = 1;
sahilmgandhi 18:6a4db94011d3 111
sahilmgandhi 18:6a4db94011d3 112 // write seconds
sahilmgandhi 18:6a4db94011d3 113 RTC->TSR = t;
sahilmgandhi 18:6a4db94011d3 114
sahilmgandhi 18:6a4db94011d3 115 // re-enable counter
sahilmgandhi 18:6a4db94011d3 116 RTC->SR |= RTC_SR_TCE_MASK;
sahilmgandhi 18:6a4db94011d3 117 }
sahilmgandhi 18:6a4db94011d3 118
sahilmgandhi 18:6a4db94011d3 119 #endif