MacroRat / MouseCode

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Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_Freescale/TARGET_KLXX/clk_freqs.h@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2006-2013 ARM Limited
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 */
sahilmgandhi 18:6a4db94011d3 16 #ifndef MBED_CLK_FREQS_H
sahilmgandhi 18:6a4db94011d3 17 #define MBED_CLK_FREQS_H
sahilmgandhi 18:6a4db94011d3 18
sahilmgandhi 18:6a4db94011d3 19 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 20 extern "C" {
sahilmgandhi 18:6a4db94011d3 21 #endif
sahilmgandhi 18:6a4db94011d3 22
sahilmgandhi 18:6a4db94011d3 23 #include "PeripheralPins.h"
sahilmgandhi 18:6a4db94011d3 24
sahilmgandhi 18:6a4db94011d3 25 //Get the peripheral bus clock frequency
sahilmgandhi 18:6a4db94011d3 26 static inline uint32_t bus_frequency(void) {
sahilmgandhi 18:6a4db94011d3 27 return (SystemCoreClock / (((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT) + 1));
sahilmgandhi 18:6a4db94011d3 28 }
sahilmgandhi 18:6a4db94011d3 29
sahilmgandhi 18:6a4db94011d3 30 #if defined(TARGET_KL43Z)
sahilmgandhi 18:6a4db94011d3 31
sahilmgandhi 18:6a4db94011d3 32 static inline uint32_t extosc_frequency(void) {
sahilmgandhi 18:6a4db94011d3 33 return CPU_XTAL_CLK_HZ;
sahilmgandhi 18:6a4db94011d3 34 }
sahilmgandhi 18:6a4db94011d3 35
sahilmgandhi 18:6a4db94011d3 36 static inline uint32_t fastirc_frequency(void) {
sahilmgandhi 18:6a4db94011d3 37 return CPU_INT_FAST_CLK_HZ;
sahilmgandhi 18:6a4db94011d3 38 }
sahilmgandhi 18:6a4db94011d3 39
sahilmgandhi 18:6a4db94011d3 40 static inline uint32_t mcgirc_frequency(void) {
sahilmgandhi 18:6a4db94011d3 41 uint32_t mcgirc_clock = 0;
sahilmgandhi 18:6a4db94011d3 42
sahilmgandhi 18:6a4db94011d3 43 if (MCG->C1 & MCG_C1_IREFSTEN_MASK) {
sahilmgandhi 18:6a4db94011d3 44 mcgirc_clock = (MCG->C2 & MCG_C2_IRCS_MASK) ? 8000000u : 2000000u;
sahilmgandhi 18:6a4db94011d3 45 mcgirc_clock /= 1u + ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT);
sahilmgandhi 18:6a4db94011d3 46 mcgirc_clock /= 1u + (MCG->MC & MCG_MC_LIRC_DIV2_MASK);
sahilmgandhi 18:6a4db94011d3 47 }
sahilmgandhi 18:6a4db94011d3 48
sahilmgandhi 18:6a4db94011d3 49 return mcgirc_clock;
sahilmgandhi 18:6a4db94011d3 50 }
sahilmgandhi 18:6a4db94011d3 51
sahilmgandhi 18:6a4db94011d3 52 #else
sahilmgandhi 18:6a4db94011d3 53
sahilmgandhi 18:6a4db94011d3 54 //Get external oscillator (crystal) frequency
sahilmgandhi 18:6a4db94011d3 55 static uint32_t extosc_frequency(void) {
sahilmgandhi 18:6a4db94011d3 56 uint32_t MCGClock = SystemCoreClock * (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT));
sahilmgandhi 18:6a4db94011d3 57
sahilmgandhi 18:6a4db94011d3 58 if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(2)) //MCG clock = external reference clock
sahilmgandhi 18:6a4db94011d3 59 return MCGClock;
sahilmgandhi 18:6a4db94011d3 60
sahilmgandhi 18:6a4db94011d3 61 uint32_t divider, multiplier;
sahilmgandhi 18:6a4db94011d3 62 #ifdef MCG_C5_PLLCLKEN0_MASK //PLL available
sahilmgandhi 18:6a4db94011d3 63 if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0)) { //PLL/FLL is selected
sahilmgandhi 18:6a4db94011d3 64 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { //FLL is selected
sahilmgandhi 18:6a4db94011d3 65 #endif
sahilmgandhi 18:6a4db94011d3 66 if ((MCG->S & MCG_S_IREFST_MASK) == 0x0u) { //FLL uses external reference
sahilmgandhi 18:6a4db94011d3 67 divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
sahilmgandhi 18:6a4db94011d3 68 if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u)
sahilmgandhi 18:6a4db94011d3 69 divider <<= 5u;
sahilmgandhi 18:6a4db94011d3 70 /* Select correct multiplier to calculate the MCG output clock */
sahilmgandhi 18:6a4db94011d3 71 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
sahilmgandhi 18:6a4db94011d3 72 case 0x0u:
sahilmgandhi 18:6a4db94011d3 73 multiplier = 640u;
sahilmgandhi 18:6a4db94011d3 74 break;
sahilmgandhi 18:6a4db94011d3 75 case 0x20u:
sahilmgandhi 18:6a4db94011d3 76 multiplier = 1280u;
sahilmgandhi 18:6a4db94011d3 77 break;
sahilmgandhi 18:6a4db94011d3 78 case 0x40u:
sahilmgandhi 18:6a4db94011d3 79 multiplier = 1920u;
sahilmgandhi 18:6a4db94011d3 80 break;
sahilmgandhi 18:6a4db94011d3 81 case 0x60u:
sahilmgandhi 18:6a4db94011d3 82 multiplier = 2560u;
sahilmgandhi 18:6a4db94011d3 83 break;
sahilmgandhi 18:6a4db94011d3 84 case 0x80u:
sahilmgandhi 18:6a4db94011d3 85 multiplier = 732u;
sahilmgandhi 18:6a4db94011d3 86 break;
sahilmgandhi 18:6a4db94011d3 87 case 0xA0u:
sahilmgandhi 18:6a4db94011d3 88 multiplier = 1464u;
sahilmgandhi 18:6a4db94011d3 89 break;
sahilmgandhi 18:6a4db94011d3 90 case 0xC0u:
sahilmgandhi 18:6a4db94011d3 91 multiplier = 2197u;
sahilmgandhi 18:6a4db94011d3 92 break;
sahilmgandhi 18:6a4db94011d3 93 case 0xE0u:
sahilmgandhi 18:6a4db94011d3 94 default:
sahilmgandhi 18:6a4db94011d3 95 multiplier = 2929u;
sahilmgandhi 18:6a4db94011d3 96 break;
sahilmgandhi 18:6a4db94011d3 97 }
sahilmgandhi 18:6a4db94011d3 98
sahilmgandhi 18:6a4db94011d3 99 return MCGClock * divider / multiplier;
sahilmgandhi 18:6a4db94011d3 100 }
sahilmgandhi 18:6a4db94011d3 101 #ifdef MCG_C5_PLLCLKEN0_MASK
sahilmgandhi 18:6a4db94011d3 102 } else { //PLL is selected
sahilmgandhi 18:6a4db94011d3 103 divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
sahilmgandhi 18:6a4db94011d3 104 multiplier = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
sahilmgandhi 18:6a4db94011d3 105 return MCGClock * divider / multiplier;
sahilmgandhi 18:6a4db94011d3 106 }
sahilmgandhi 18:6a4db94011d3 107 }
sahilmgandhi 18:6a4db94011d3 108 #endif
sahilmgandhi 18:6a4db94011d3 109
sahilmgandhi 18:6a4db94011d3 110 //In all other cases either there is no crystal or we cannot determine it
sahilmgandhi 18:6a4db94011d3 111 //For example when the FLL is running on the internal reference, and there is also an
sahilmgandhi 18:6a4db94011d3 112 //external crystal. However these are unlikely situations
sahilmgandhi 18:6a4db94011d3 113 return 0;
sahilmgandhi 18:6a4db94011d3 114 }
sahilmgandhi 18:6a4db94011d3 115
sahilmgandhi 18:6a4db94011d3 116 //Get MCG PLL/2 or FLL frequency, depending on which one is active, sets PLLFLLSEL bit
sahilmgandhi 18:6a4db94011d3 117 static uint32_t mcgpllfll_frequency(void) {
sahilmgandhi 18:6a4db94011d3 118 if ((MCG->C1 & MCG_C1_CLKS_MASK) != MCG_C1_CLKS(0)) //PLL/FLL is not selected
sahilmgandhi 18:6a4db94011d3 119 return 0;
sahilmgandhi 18:6a4db94011d3 120
sahilmgandhi 18:6a4db94011d3 121 uint32_t MCGClock = SystemCoreClock * (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT));
sahilmgandhi 18:6a4db94011d3 122 #ifdef MCG_C5_PLLCLKEN0_MASK
sahilmgandhi 18:6a4db94011d3 123 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { //FLL is selected
sahilmgandhi 18:6a4db94011d3 124 SIM->SOPT2 &= ~SIM_SOPT2_PLLFLLSEL_MASK; //MCG peripheral clock is FLL output
sahilmgandhi 18:6a4db94011d3 125 #endif
sahilmgandhi 18:6a4db94011d3 126 return MCGClock;
sahilmgandhi 18:6a4db94011d3 127 #ifdef MCG_C5_PLLCLKEN0_MASK
sahilmgandhi 18:6a4db94011d3 128 } else { //PLL is selected
sahilmgandhi 18:6a4db94011d3 129 SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; //MCG peripheral clock is PLL output
sahilmgandhi 18:6a4db94011d3 130 return (MCGClock >> 1);
sahilmgandhi 18:6a4db94011d3 131 }
sahilmgandhi 18:6a4db94011d3 132 #endif
sahilmgandhi 18:6a4db94011d3 133
sahilmgandhi 18:6a4db94011d3 134 //It is possible the SystemCoreClock isn't running on the PLL, and the PLL is still active
sahilmgandhi 18:6a4db94011d3 135 //for the peripherals, this is however an unlikely setup
sahilmgandhi 18:6a4db94011d3 136 }
sahilmgandhi 18:6a4db94011d3 137
sahilmgandhi 18:6a4db94011d3 138 #endif
sahilmgandhi 18:6a4db94011d3 139
sahilmgandhi 18:6a4db94011d3 140 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 141 }
sahilmgandhi 18:6a4db94011d3 142 #endif
sahilmgandhi 18:6a4db94011d3 143
sahilmgandhi 18:6a4db94011d3 144 #endif