MacroRat / MouseCode

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Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_Atmel/common/utils/interrupt/interrupt_sam_nvic.c@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 #include "interrupt_sam_nvic.h"
sahilmgandhi 18:6a4db94011d3 2
sahilmgandhi 18:6a4db94011d3 3 #if !defined(__DOXYGEN__)
sahilmgandhi 18:6a4db94011d3 4 /* Deprecated - global flag to determine the global interrupt state. Required by
sahilmgandhi 18:6a4db94011d3 5 * QTouch library, however new applications should use cpu_irq_is_enabled()
sahilmgandhi 18:6a4db94011d3 6 * which probes the true global interrupt state from the CPU special registers.
sahilmgandhi 18:6a4db94011d3 7 */
sahilmgandhi 18:6a4db94011d3 8 volatile bool g_interrupt_enabled = true;
sahilmgandhi 18:6a4db94011d3 9 #endif
sahilmgandhi 18:6a4db94011d3 10
sahilmgandhi 18:6a4db94011d3 11 void cpu_irq_enter_critical(void)
sahilmgandhi 18:6a4db94011d3 12 {
sahilmgandhi 18:6a4db94011d3 13 if (cpu_irq_critical_section_counter == 0) {
sahilmgandhi 18:6a4db94011d3 14 if (cpu_irq_is_enabled()) {
sahilmgandhi 18:6a4db94011d3 15 cpu_irq_disable();
sahilmgandhi 18:6a4db94011d3 16 cpu_irq_prev_interrupt_state = true;
sahilmgandhi 18:6a4db94011d3 17 } else {
sahilmgandhi 18:6a4db94011d3 18 /* Make sure the to save the prev state as false */
sahilmgandhi 18:6a4db94011d3 19 cpu_irq_prev_interrupt_state = false;
sahilmgandhi 18:6a4db94011d3 20 }
sahilmgandhi 18:6a4db94011d3 21
sahilmgandhi 18:6a4db94011d3 22 }
sahilmgandhi 18:6a4db94011d3 23
sahilmgandhi 18:6a4db94011d3 24 cpu_irq_critical_section_counter++;
sahilmgandhi 18:6a4db94011d3 25 }
sahilmgandhi 18:6a4db94011d3 26
sahilmgandhi 18:6a4db94011d3 27 void cpu_irq_leave_critical(void)
sahilmgandhi 18:6a4db94011d3 28 {
sahilmgandhi 18:6a4db94011d3 29 /* Check if the user is trying to leave a critical section when not in a critical section */
sahilmgandhi 18:6a4db94011d3 30 Assert(cpu_irq_critical_section_counter > 0);
sahilmgandhi 18:6a4db94011d3 31
sahilmgandhi 18:6a4db94011d3 32 cpu_irq_critical_section_counter--;
sahilmgandhi 18:6a4db94011d3 33
sahilmgandhi 18:6a4db94011d3 34 /* Only enable global interrupts when the counter reaches 0 and the state of the global interrupt flag
sahilmgandhi 18:6a4db94011d3 35 was enabled when entering critical state */
sahilmgandhi 18:6a4db94011d3 36 if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
sahilmgandhi 18:6a4db94011d3 37 cpu_irq_enable();
sahilmgandhi 18:6a4db94011d3 38 }
sahilmgandhi 18:6a4db94011d3 39 }
sahilmgandhi 18:6a4db94011d3 40