Mouse code for the MacroRat
mbed-dev/targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/device/system_MK20DX256.c@34:69342782fb68, 2017-05-26 (annotated)
- Committer:
- sahilmgandhi
- Date:
- Fri May 26 17:21:04 2017 +0000
- Revision:
- 34:69342782fb68
- Parent:
- 18:6a4db94011d3
Added small reverse turns before the break so that we can stop faster.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
sahilmgandhi | 18:6a4db94011d3 | 1 | /* |
sahilmgandhi | 18:6a4db94011d3 | 2 | ** ################################################################### |
sahilmgandhi | 18:6a4db94011d3 | 3 | ** Compilers: ARM Compiler |
sahilmgandhi | 18:6a4db94011d3 | 4 | ** Freescale C/C++ for Embedded ARM |
sahilmgandhi | 18:6a4db94011d3 | 5 | ** GNU C Compiler |
sahilmgandhi | 18:6a4db94011d3 | 6 | ** IAR ANSI C/C++ Compiler for ARM |
sahilmgandhi | 18:6a4db94011d3 | 7 | ** |
sahilmgandhi | 18:6a4db94011d3 | 8 | ** |
sahilmgandhi | 18:6a4db94011d3 | 9 | ** |
sahilmgandhi | 18:6a4db94011d3 | 10 | ** Version: rev. 1.0, 2011-12-15 |
sahilmgandhi | 18:6a4db94011d3 | 11 | ** |
sahilmgandhi | 18:6a4db94011d3 | 12 | ** Abstract: |
sahilmgandhi | 18:6a4db94011d3 | 13 | ** Provides a system configuration function and a global variable that |
sahilmgandhi | 18:6a4db94011d3 | 14 | ** contains the system frequency. It configures the device and initializes |
sahilmgandhi | 18:6a4db94011d3 | 15 | ** the oscillator (PLL) that is part of the microcontroller device. |
sahilmgandhi | 18:6a4db94011d3 | 16 | ** |
sahilmgandhi | 18:6a4db94011d3 | 17 | ** Copyright: 2015 Freescale Semiconductor, Inc. All Rights Reserved. |
sahilmgandhi | 18:6a4db94011d3 | 18 | ** |
sahilmgandhi | 18:6a4db94011d3 | 19 | ** http: www.freescale.com |
sahilmgandhi | 18:6a4db94011d3 | 20 | ** mail: support@freescale.com |
sahilmgandhi | 18:6a4db94011d3 | 21 | ** |
sahilmgandhi | 18:6a4db94011d3 | 22 | ** Revisions: |
sahilmgandhi | 18:6a4db94011d3 | 23 | ** - rev. 1.0 (2011-12-15) |
sahilmgandhi | 18:6a4db94011d3 | 24 | ** Initial version |
sahilmgandhi | 18:6a4db94011d3 | 25 | ** |
sahilmgandhi | 18:6a4db94011d3 | 26 | ** ################################################################### |
sahilmgandhi | 18:6a4db94011d3 | 27 | */ |
sahilmgandhi | 18:6a4db94011d3 | 28 | |
sahilmgandhi | 18:6a4db94011d3 | 29 | /** |
sahilmgandhi | 18:6a4db94011d3 | 30 | * @file MK20DX256 |
sahilmgandhi | 18:6a4db94011d3 | 31 | * @version 1.0 |
sahilmgandhi | 18:6a4db94011d3 | 32 | * @date 2011-12-15 |
sahilmgandhi | 18:6a4db94011d3 | 33 | * @brief Device specific configuration file for MK20DX256 (implementation file) |
sahilmgandhi | 18:6a4db94011d3 | 34 | * |
sahilmgandhi | 18:6a4db94011d3 | 35 | * Provides a system configuration function and a global variable that contains |
sahilmgandhi | 18:6a4db94011d3 | 36 | * the system frequency. It configures the device and initializes the oscillator |
sahilmgandhi | 18:6a4db94011d3 | 37 | * (PLL) that is part of the microcontroller device. |
sahilmgandhi | 18:6a4db94011d3 | 38 | */ |
sahilmgandhi | 18:6a4db94011d3 | 39 | |
sahilmgandhi | 18:6a4db94011d3 | 40 | #include <stdint.h> |
sahilmgandhi | 18:6a4db94011d3 | 41 | #include "MK20DX256.h" |
sahilmgandhi | 18:6a4db94011d3 | 42 | |
sahilmgandhi | 18:6a4db94011d3 | 43 | #define DISABLE_WDOG 1 |
sahilmgandhi | 18:6a4db94011d3 | 44 | |
sahilmgandhi | 18:6a4db94011d3 | 45 | #define CLOCK_SETUP 1 |
sahilmgandhi | 18:6a4db94011d3 | 46 | /* Predefined clock setups |
sahilmgandhi | 18:6a4db94011d3 | 47 | 0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode |
sahilmgandhi | 18:6a4db94011d3 | 48 | Reference clock source for MCG module is the slow internal clock source 32.768kHz |
sahilmgandhi | 18:6a4db94011d3 | 49 | Core clock = 41.94MHz, BusClock = 41.94MHz |
sahilmgandhi | 18:6a4db94011d3 | 50 | Works on Teensy3.1 but no USB support |
sahilmgandhi | 18:6a4db94011d3 | 51 | 1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode |
sahilmgandhi | 18:6a4db94011d3 | 52 | Reference clock source for MCG module is an external crystal 16MHz |
sahilmgandhi | 18:6a4db94011d3 | 53 | Core clock = 96MHz, BusClock = 48MHz |
sahilmgandhi | 18:6a4db94011d3 | 54 | Default high speed Teensy3.1 96Mhz set up |
sahilmgandhi | 18:6a4db94011d3 | 55 | 2 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode |
sahilmgandhi | 18:6a4db94011d3 | 56 | Reference clock source for MCG module is an external crystal 16MHz |
sahilmgandhi | 18:6a4db94011d3 | 57 | Core clock = 72MHz, BusClock = 36MHz |
sahilmgandhi | 18:6a4db94011d3 | 58 | Alternative standard 'slower' Teensy3.1 72Mhz set up |
sahilmgandhi | 18:6a4db94011d3 | 59 | */ |
sahilmgandhi | 18:6a4db94011d3 | 60 | |
sahilmgandhi | 18:6a4db94011d3 | 61 | /*---------------------------------------------------------------------------- |
sahilmgandhi | 18:6a4db94011d3 | 62 | Define clock source values |
sahilmgandhi | 18:6a4db94011d3 | 63 | *----------------------------------------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 64 | #if (CLOCK_SETUP == 0) |
sahilmgandhi | 18:6a4db94011d3 | 65 | #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */ |
sahilmgandhi | 18:6a4db94011d3 | 66 | #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ |
sahilmgandhi | 18:6a4db94011d3 | 67 | #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ |
sahilmgandhi | 18:6a4db94011d3 | 68 | #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ |
sahilmgandhi | 18:6a4db94011d3 | 69 | #define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */ |
sahilmgandhi | 18:6a4db94011d3 | 70 | #elif (CLOCK_SETUP == 1) |
sahilmgandhi | 18:6a4db94011d3 | 71 | #define CPU_XTAL_CLK_HZ 16000000u /* Value of the external crystal or oscillator clock frequency in Hz */ |
sahilmgandhi | 18:6a4db94011d3 | 72 | #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ |
sahilmgandhi | 18:6a4db94011d3 | 73 | #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ |
sahilmgandhi | 18:6a4db94011d3 | 74 | #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ |
sahilmgandhi | 18:6a4db94011d3 | 75 | #define DEFAULT_SYSTEM_CLOCK 96000000u /* Default System clock value */ |
sahilmgandhi | 18:6a4db94011d3 | 76 | #elif (CLOCK_SETUP == 2) |
sahilmgandhi | 18:6a4db94011d3 | 77 | #define CPU_XTAL_CLK_HZ 16000000u /* Value of the external crystal or oscillator clock frequency in Hz */ |
sahilmgandhi | 18:6a4db94011d3 | 78 | #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ |
sahilmgandhi | 18:6a4db94011d3 | 79 | #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ |
sahilmgandhi | 18:6a4db94011d3 | 80 | #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ |
sahilmgandhi | 18:6a4db94011d3 | 81 | #define DEFAULT_SYSTEM_CLOCK 72000000u /* Default System clock value */ |
sahilmgandhi | 18:6a4db94011d3 | 82 | #endif /* (CLOCK_SETUP == 2) */ |
sahilmgandhi | 18:6a4db94011d3 | 83 | |
sahilmgandhi | 18:6a4db94011d3 | 84 | |
sahilmgandhi | 18:6a4db94011d3 | 85 | /* ---------------------------------------------------------------------------- |
sahilmgandhi | 18:6a4db94011d3 | 86 | -- Core clock |
sahilmgandhi | 18:6a4db94011d3 | 87 | ---------------------------------------------------------------------------- */ |
sahilmgandhi | 18:6a4db94011d3 | 88 | |
sahilmgandhi | 18:6a4db94011d3 | 89 | uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; |
sahilmgandhi | 18:6a4db94011d3 | 90 | |
sahilmgandhi | 18:6a4db94011d3 | 91 | /* ---------------------------------------------------------------------------- |
sahilmgandhi | 18:6a4db94011d3 | 92 | -- SystemInit() |
sahilmgandhi | 18:6a4db94011d3 | 93 | ---------------------------------------------------------------------------- */ |
sahilmgandhi | 18:6a4db94011d3 | 94 | void SystemInit (void) { |
sahilmgandhi | 18:6a4db94011d3 | 95 | /* SystemInit MUST NOT use any variables from the .data section, as this section is not loaded yet! */ |
sahilmgandhi | 18:6a4db94011d3 | 96 | |
sahilmgandhi | 18:6a4db94011d3 | 97 | #if (DISABLE_WDOG) |
sahilmgandhi | 18:6a4db94011d3 | 98 | /* Disable the WDOG module */ |
sahilmgandhi | 18:6a4db94011d3 | 99 | /* WDOG_UNLOCK: WDOGUNLOCK=0xC520 */ |
sahilmgandhi | 18:6a4db94011d3 | 100 | WDOG->UNLOCK = (uint16_t)0xC520u; /* Key 1 */ |
sahilmgandhi | 18:6a4db94011d3 | 101 | /* WDOG_UNLOCK : WDOGUNLOCK=0xD928 */ |
sahilmgandhi | 18:6a4db94011d3 | 102 | WDOG->UNLOCK = (uint16_t)0xD928u; /* Key 2 */ |
sahilmgandhi | 18:6a4db94011d3 | 103 | /* WDOG_STCTRLH: DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,STNDBYEN=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */ |
sahilmgandhi | 18:6a4db94011d3 | 104 | WDOG->STCTRLH = (uint16_t)0x01D2u; |
sahilmgandhi | 18:6a4db94011d3 | 105 | #endif /* (DISABLE_WDOG) */ |
sahilmgandhi | 18:6a4db94011d3 | 106 | |
sahilmgandhi | 18:6a4db94011d3 | 107 | #if (CLOCK_SETUP == 0) |
sahilmgandhi | 18:6a4db94011d3 | 108 | /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=1 Set Prescalers 41.94MHz cpu, 41.94MHz system, 20.97MHz flash*/ |
sahilmgandhi | 18:6a4db94011d3 | 109 | SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV4(1); |
sahilmgandhi | 18:6a4db94011d3 | 110 | /* Switch to FEI Mode */ |
sahilmgandhi | 18:6a4db94011d3 | 111 | /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */ |
sahilmgandhi | 18:6a4db94011d3 | 112 | MCG->C1 = MCG_C1_IREFS_MASK | MCG_C1_IRCLKEN_MASK; |
sahilmgandhi | 18:6a4db94011d3 | 113 | /* MCG->C2: LOCKRE0=0,RANGE0=0,HGO=0,EREFS=0,LP=0,IRCS=0 */ |
sahilmgandhi | 18:6a4db94011d3 | 114 | MCG->C2 = (uint8_t)0x00u; |
sahilmgandhi | 18:6a4db94011d3 | 115 | /* MCG_C4: DMX32=0,DRST_DRS=1 */ |
sahilmgandhi | 18:6a4db94011d3 | 116 | MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0u) | (uint8_t)0x20u); |
sahilmgandhi | 18:6a4db94011d3 | 117 | /* MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */ |
sahilmgandhi | 18:6a4db94011d3 | 118 | MCG->C5 = (uint8_t)0x00u; |
sahilmgandhi | 18:6a4db94011d3 | 119 | /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */ |
sahilmgandhi | 18:6a4db94011d3 | 120 | MCG->C6 = (uint8_t)0x00u; |
sahilmgandhi | 18:6a4db94011d3 | 121 | while((MCG->S & MCG_S_IREFST_MASK) == 0u) { } /* Check that the source of the FLL reference clock is the internal reference clock. */ |
sahilmgandhi | 18:6a4db94011d3 | 122 | while((MCG->S & 0x0Cu) != 0x00u) { } /* Wait until output of the FLL is selected */ |
sahilmgandhi | 18:6a4db94011d3 | 123 | |
sahilmgandhi | 18:6a4db94011d3 | 124 | #elif (CLOCK_SETUP == 1) |
sahilmgandhi | 18:6a4db94011d3 | 125 | /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV4=3 Set Prescalers 96MHz cpu, 48MHz bus, 24MHz flash*/ |
sahilmgandhi | 18:6a4db94011d3 | 126 | SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(1) | SIM_CLKDIV1_OUTDIV4(3); |
sahilmgandhi | 18:6a4db94011d3 | 127 | /* SIM->CLKDIV2: USBDIV=2, Divide 96MHz system clock for USB 48MHz */ |
sahilmgandhi | 18:6a4db94011d3 | 128 | SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(1); |
sahilmgandhi | 18:6a4db94011d3 | 129 | /* OSC0->CR: ERCLKEN=0,EREFSTEN=0,SC2P=1,SC4P=0,SC8P=1,SC16P=0 10pF loading capacitors for 16MHz system oscillator*/ |
sahilmgandhi | 18:6a4db94011d3 | 130 | OSC0->CR = OSC_CR_SC8P_MASK | OSC_CR_SC2P_MASK; |
sahilmgandhi | 18:6a4db94011d3 | 131 | /* Switch to FBE Mode */ |
sahilmgandhi | 18:6a4db94011d3 | 132 | /* MCG->C7: OSCSEL=0 */ |
sahilmgandhi | 18:6a4db94011d3 | 133 | MCG->C7 = (uint8_t)0x00u; |
sahilmgandhi | 18:6a4db94011d3 | 134 | /* MCG->C2: LOCKRE0=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */ |
sahilmgandhi | 18:6a4db94011d3 | 135 | MCG->C2 = MCG_C2_RANGE0(2) | MCG_C2_EREFS0_MASK; |
sahilmgandhi | 18:6a4db94011d3 | 136 | //MCG->C2 = (uint8_t)0x24u; |
sahilmgandhi | 18:6a4db94011d3 | 137 | /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ |
sahilmgandhi | 18:6a4db94011d3 | 138 | MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3) | MCG_C1_IRCLKEN_MASK; |
sahilmgandhi | 18:6a4db94011d3 | 139 | /* MCG->C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */ |
sahilmgandhi | 18:6a4db94011d3 | 140 | MCG->C4 &= (uint8_t)~(uint8_t)0xE0u; |
sahilmgandhi | 18:6a4db94011d3 | 141 | /* MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=7 */ |
sahilmgandhi | 18:6a4db94011d3 | 142 | MCG->C5 = MCG_C5_PRDIV0(7); |
sahilmgandhi | 18:6a4db94011d3 | 143 | /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */ |
sahilmgandhi | 18:6a4db94011d3 | 144 | MCG->C6 = (uint8_t)0x00u; |
sahilmgandhi | 18:6a4db94011d3 | 145 | while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { } /* Check that the oscillator is running */ |
sahilmgandhi | 18:6a4db94011d3 | 146 | while((MCG->S & 0x0Cu) != 0x08u) { } /* Wait until external reference clock is selected as MCG output */ |
sahilmgandhi | 18:6a4db94011d3 | 147 | /* Switch to PBE Mode */ |
sahilmgandhi | 18:6a4db94011d3 | 148 | /* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=5 */ |
sahilmgandhi | 18:6a4db94011d3 | 149 | MCG->C5 = MCG_C5_PRDIV0(3); // config PLL input for 16 MHz Crystal / 4 = 4 MHz |
sahilmgandhi | 18:6a4db94011d3 | 150 | /* MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=3 */ |
sahilmgandhi | 18:6a4db94011d3 | 151 | MCG->C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV0(0);// config PLL for 96 MHz output |
sahilmgandhi | 18:6a4db94011d3 | 152 | while((MCG->S & MCG_S_PLLST_MASK) == 0u) { } /* Wait until the source of the PLLS clock has switched to the PLL */ |
sahilmgandhi | 18:6a4db94011d3 | 153 | while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } /* Wait until locked */ |
sahilmgandhi | 18:6a4db94011d3 | 154 | /* Switch to PEE Mode */ |
sahilmgandhi | 18:6a4db94011d3 | 155 | /* MCG->C1: CLKS=0,FRDIV=2,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ |
sahilmgandhi | 18:6a4db94011d3 | 156 | MCG->C1 = MCG_C1_FRDIV(2) | MCG_C1_IRCLKEN_MASK; |
sahilmgandhi | 18:6a4db94011d3 | 157 | while((MCG->S & 0x0Cu) != 0x0Cu) { } /* Wait until output of the PLL is selected */ |
sahilmgandhi | 18:6a4db94011d3 | 158 | while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } /* Wait until locked */ |
sahilmgandhi | 18:6a4db94011d3 | 159 | |
sahilmgandhi | 18:6a4db94011d3 | 160 | #elif (CLOCK_SETUP == 2) |
sahilmgandhi | 18:6a4db94011d3 | 161 | /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=1 Set Prescalers 72MHz cpu, 36MHz bus, 24MHz flash*/ |
sahilmgandhi | 18:6a4db94011d3 | 162 | SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV2(1) | SIM_CLKDIV1_OUTDIV4(2); |
sahilmgandhi | 18:6a4db94011d3 | 163 | /* SIM->CLKDIV2: USBDIV=2,USBFRAC=1 Divide 72MHz system clock for USB 48MHz */ |
sahilmgandhi | 18:6a4db94011d3 | 164 | SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC_MASK; |
sahilmgandhi | 18:6a4db94011d3 | 165 | /* OSC0->CR: ERCLKEN=0,EREFSTEN=0,SC2P=1,SC4P=0,SC8P=1,SC16P=0 10pF loading capacitors for 16MHz system oscillator*/ |
sahilmgandhi | 18:6a4db94011d3 | 166 | OSC0->CR = OSC_CR_SC8P_MASK | OSC_CR_SC2P_MASK; |
sahilmgandhi | 18:6a4db94011d3 | 167 | /* Switch to FBE Mode */ |
sahilmgandhi | 18:6a4db94011d3 | 168 | /* MCG->C7: OSCSEL=0 */ |
sahilmgandhi | 18:6a4db94011d3 | 169 | MCG->C7 = (uint8_t)0x00u; |
sahilmgandhi | 18:6a4db94011d3 | 170 | /* MCG->C2: LOCKRE0=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */ |
sahilmgandhi | 18:6a4db94011d3 | 171 | MCG->C2 = MCG_C2_RANGE0(2) | MCG_C2_EREFS0_MASK; |
sahilmgandhi | 18:6a4db94011d3 | 172 | //MCG->C2 = (uint8_t)0x24u; |
sahilmgandhi | 18:6a4db94011d3 | 173 | /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ |
sahilmgandhi | 18:6a4db94011d3 | 174 | MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3) | MCG_C1_IRCLKEN_MASK; |
sahilmgandhi | 18:6a4db94011d3 | 175 | /* MCG->C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */ |
sahilmgandhi | 18:6a4db94011d3 | 176 | MCG->C4 &= (uint8_t)~(uint8_t)0xE0u; |
sahilmgandhi | 18:6a4db94011d3 | 177 | /* MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=7 */ |
sahilmgandhi | 18:6a4db94011d3 | 178 | MCG->C5 = MCG_C5_PRDIV0(7); |
sahilmgandhi | 18:6a4db94011d3 | 179 | /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */ |
sahilmgandhi | 18:6a4db94011d3 | 180 | MCG->C6 = (uint8_t)0x00u; |
sahilmgandhi | 18:6a4db94011d3 | 181 | while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { } /* Check that the oscillator is running */ |
sahilmgandhi | 18:6a4db94011d3 | 182 | while((MCG->S & 0x0Cu) != 0x08u) { } /* Wait until external reference clock is selected as MCG output */ |
sahilmgandhi | 18:6a4db94011d3 | 183 | /* Switch to PBE Mode */ |
sahilmgandhi | 18:6a4db94011d3 | 184 | /* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=5 */ |
sahilmgandhi | 18:6a4db94011d3 | 185 | MCG->C5 = MCG_C5_PRDIV0(5); |
sahilmgandhi | 18:6a4db94011d3 | 186 | /* MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=3 */ |
sahilmgandhi | 18:6a4db94011d3 | 187 | MCG->C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV0(3); |
sahilmgandhi | 18:6a4db94011d3 | 188 | while((MCG->S & MCG_S_PLLST_MASK) == 0u) { } /* Wait until the source of the PLLS clock has switched to the PLL */ |
sahilmgandhi | 18:6a4db94011d3 | 189 | while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } /* Wait until locked */ |
sahilmgandhi | 18:6a4db94011d3 | 190 | /* Switch to PEE Mode */ |
sahilmgandhi | 18:6a4db94011d3 | 191 | /* MCG->C1: CLKS=0,FRDIV=2,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ |
sahilmgandhi | 18:6a4db94011d3 | 192 | MCG->C1 = MCG_C1_FRDIV(2) | MCG_C1_IRCLKEN_MASK; |
sahilmgandhi | 18:6a4db94011d3 | 193 | while((MCG->S & 0x0Cu) != 0x0Cu) { } /* Wait until output of the PLL is selected */ |
sahilmgandhi | 18:6a4db94011d3 | 194 | while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } /* Wait until locked */ |
sahilmgandhi | 18:6a4db94011d3 | 195 | #endif /* (CLOCK_SETUP) */ |
sahilmgandhi | 18:6a4db94011d3 | 196 | } |
sahilmgandhi | 18:6a4db94011d3 | 197 | |
sahilmgandhi | 18:6a4db94011d3 | 198 | /* ---------------------------------------------------------------------------- |
sahilmgandhi | 18:6a4db94011d3 | 199 | -- SystemCoreClockUpdate() |
sahilmgandhi | 18:6a4db94011d3 | 200 | ---------------------------------------------------------------------------- */ |
sahilmgandhi | 18:6a4db94011d3 | 201 | |
sahilmgandhi | 18:6a4db94011d3 | 202 | void SystemCoreClockUpdate (void) { |
sahilmgandhi | 18:6a4db94011d3 | 203 | uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */ |
sahilmgandhi | 18:6a4db94011d3 | 204 | uint8_t Divider; |
sahilmgandhi | 18:6a4db94011d3 | 205 | |
sahilmgandhi | 18:6a4db94011d3 | 206 | if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) { |
sahilmgandhi | 18:6a4db94011d3 | 207 | /* Output of FLL or PLL is selected */ |
sahilmgandhi | 18:6a4db94011d3 | 208 | if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { |
sahilmgandhi | 18:6a4db94011d3 | 209 | /* FLL is selected */ |
sahilmgandhi | 18:6a4db94011d3 | 210 | if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) { |
sahilmgandhi | 18:6a4db94011d3 | 211 | /* External reference clock is selected */ |
sahilmgandhi | 18:6a4db94011d3 | 212 | if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) { |
sahilmgandhi | 18:6a4db94011d3 | 213 | MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ |
sahilmgandhi | 18:6a4db94011d3 | 214 | } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */ |
sahilmgandhi | 18:6a4db94011d3 | 215 | MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */ |
sahilmgandhi | 18:6a4db94011d3 | 216 | } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */ |
sahilmgandhi | 18:6a4db94011d3 | 217 | Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); |
sahilmgandhi | 18:6a4db94011d3 | 218 | MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ |
sahilmgandhi | 18:6a4db94011d3 | 219 | if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) { |
sahilmgandhi | 18:6a4db94011d3 | 220 | MCGOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */ |
sahilmgandhi | 18:6a4db94011d3 | 221 | } /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */ |
sahilmgandhi | 18:6a4db94011d3 | 222 | } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */ |
sahilmgandhi | 18:6a4db94011d3 | 223 | MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */ |
sahilmgandhi | 18:6a4db94011d3 | 224 | } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */ |
sahilmgandhi | 18:6a4db94011d3 | 225 | /* Select correct multiplier to calculate the MCG output clock */ |
sahilmgandhi | 18:6a4db94011d3 | 226 | switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) { |
sahilmgandhi | 18:6a4db94011d3 | 227 | case 0x0u: |
sahilmgandhi | 18:6a4db94011d3 | 228 | MCGOUTClock *= 640u; |
sahilmgandhi | 18:6a4db94011d3 | 229 | break; |
sahilmgandhi | 18:6a4db94011d3 | 230 | case 0x20u: |
sahilmgandhi | 18:6a4db94011d3 | 231 | MCGOUTClock *= 1280u; |
sahilmgandhi | 18:6a4db94011d3 | 232 | break; |
sahilmgandhi | 18:6a4db94011d3 | 233 | case 0x40u: |
sahilmgandhi | 18:6a4db94011d3 | 234 | MCGOUTClock *= 1920u; |
sahilmgandhi | 18:6a4db94011d3 | 235 | break; |
sahilmgandhi | 18:6a4db94011d3 | 236 | case 0x60u: |
sahilmgandhi | 18:6a4db94011d3 | 237 | MCGOUTClock *= 2560u; |
sahilmgandhi | 18:6a4db94011d3 | 238 | break; |
sahilmgandhi | 18:6a4db94011d3 | 239 | case 0x80u: |
sahilmgandhi | 18:6a4db94011d3 | 240 | MCGOUTClock *= 732u; |
sahilmgandhi | 18:6a4db94011d3 | 241 | break; |
sahilmgandhi | 18:6a4db94011d3 | 242 | case 0xA0u: |
sahilmgandhi | 18:6a4db94011d3 | 243 | MCGOUTClock *= 1464u; |
sahilmgandhi | 18:6a4db94011d3 | 244 | break; |
sahilmgandhi | 18:6a4db94011d3 | 245 | case 0xC0u: |
sahilmgandhi | 18:6a4db94011d3 | 246 | MCGOUTClock *= 2197u; |
sahilmgandhi | 18:6a4db94011d3 | 247 | break; |
sahilmgandhi | 18:6a4db94011d3 | 248 | case 0xE0u: |
sahilmgandhi | 18:6a4db94011d3 | 249 | MCGOUTClock *= 2929u; |
sahilmgandhi | 18:6a4db94011d3 | 250 | break; |
sahilmgandhi | 18:6a4db94011d3 | 251 | default: |
sahilmgandhi | 18:6a4db94011d3 | 252 | break; |
sahilmgandhi | 18:6a4db94011d3 | 253 | } |
sahilmgandhi | 18:6a4db94011d3 | 254 | } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */ |
sahilmgandhi | 18:6a4db94011d3 | 255 | /* PLL is selected */ |
sahilmgandhi | 18:6a4db94011d3 | 256 | Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK)); |
sahilmgandhi | 18:6a4db94011d3 | 257 | MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */ |
sahilmgandhi | 18:6a4db94011d3 | 258 | Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u); |
sahilmgandhi | 18:6a4db94011d3 | 259 | MCGOUTClock *= Divider; /* Calculate the MCG output clock */ |
sahilmgandhi | 18:6a4db94011d3 | 260 | } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */ |
sahilmgandhi | 18:6a4db94011d3 | 261 | } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) { |
sahilmgandhi | 18:6a4db94011d3 | 262 | /* Internal reference clock is selected */ |
sahilmgandhi | 18:6a4db94011d3 | 263 | if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) { |
sahilmgandhi | 18:6a4db94011d3 | 264 | MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */ |
sahilmgandhi | 18:6a4db94011d3 | 265 | } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */ |
sahilmgandhi | 18:6a4db94011d3 | 266 | MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */ |
sahilmgandhi | 18:6a4db94011d3 | 267 | } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */ |
sahilmgandhi | 18:6a4db94011d3 | 268 | } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) { |
sahilmgandhi | 18:6a4db94011d3 | 269 | /* External reference clock is selected */ |
sahilmgandhi | 18:6a4db94011d3 | 270 | if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) { |
sahilmgandhi | 18:6a4db94011d3 | 271 | MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ |
sahilmgandhi | 18:6a4db94011d3 | 272 | } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */ |
sahilmgandhi | 18:6a4db94011d3 | 273 | MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */ |
sahilmgandhi | 18:6a4db94011d3 | 274 | } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */ |
sahilmgandhi | 18:6a4db94011d3 | 275 | } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */ |
sahilmgandhi | 18:6a4db94011d3 | 276 | /* Reserved value */ |
sahilmgandhi | 18:6a4db94011d3 | 277 | return; |
sahilmgandhi | 18:6a4db94011d3 | 278 | } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */ |
sahilmgandhi | 18:6a4db94011d3 | 279 | SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT))); |
sahilmgandhi | 18:6a4db94011d3 | 280 | } |