MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/cmsis/core_sc000.h@29:ec2c5a69acd6, 2017-05-24 (annotated)

Committer:
sahilmgandhi
Date:
Wed May 24 01:57:01 2017 +0000
Revision:
29:ec2c5a69acd6
Parent:
18:6a4db94011d3 
Need to change ir2-ir3 to now be ir1 - ir4

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 2 * @file core_sc000.h
sahilmgandhi 18:6a4db94011d3 3 * @brief CMSIS SC000 Core Peripheral Access Layer Header File
sahilmgandhi 18:6a4db94011d3 4 * @version V4.10
sahilmgandhi 18:6a4db94011d3 5 * @date 18. March 2015
sahilmgandhi 18:6a4db94011d3 6 *
sahilmgandhi 18:6a4db94011d3 7 * @note
sahilmgandhi 18:6a4db94011d3 8 *
sahilmgandhi 18:6a4db94011d3 9 ******************************************************************************/
sahilmgandhi 18:6a4db94011d3 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
sahilmgandhi 18:6a4db94011d3 11
sahilmgandhi 18:6a4db94011d3 12 All rights reserved.
sahilmgandhi 18:6a4db94011d3 13 Redistribution and use in source and binary forms, with or without
sahilmgandhi 18:6a4db94011d3 14 modification, are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 15 - Redistributions of source code must retain the above copyright
sahilmgandhi 18:6a4db94011d3 16 notice, this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 17 - Redistributions in binary form must reproduce the above copyright
sahilmgandhi 18:6a4db94011d3 18 notice, this list of conditions and the following disclaimer in the
sahilmgandhi 18:6a4db94011d3 19 documentation and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 20 - Neither the name of ARM nor the names of its contributors may be used
sahilmgandhi 18:6a4db94011d3 21 to endorse or promote products derived from this software without
sahilmgandhi 18:6a4db94011d3 22 specific prior written permission.
sahilmgandhi 18:6a4db94011d3 23 *
sahilmgandhi 18:6a4db94011d3 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
sahilmgandhi 18:6a4db94011d3 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
sahilmgandhi 18:6a4db94011d3 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
sahilmgandhi 18:6a4db94011d3 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
sahilmgandhi 18:6a4db94011d3 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
sahilmgandhi 18:6a4db94011d3 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
sahilmgandhi 18:6a4db94011d3 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
sahilmgandhi 18:6a4db94011d3 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
sahilmgandhi 18:6a4db94011d3 34 POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 35 ---------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 36
sahilmgandhi 18:6a4db94011d3 37
sahilmgandhi 18:6a4db94011d3 38 #if defined ( __ICCARM__ )
sahilmgandhi 18:6a4db94011d3 39 #pragma system_include /* treat file as system include file for MISRA check */
sahilmgandhi 18:6a4db94011d3 40 #endif
sahilmgandhi 18:6a4db94011d3 41
sahilmgandhi 18:6a4db94011d3 42 #ifndef __CORE_SC000_H_GENERIC
sahilmgandhi 18:6a4db94011d3 43 #define __CORE_SC000_H_GENERIC
sahilmgandhi 18:6a4db94011d3 44
sahilmgandhi 18:6a4db94011d3 45 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 46 extern "C" {
sahilmgandhi 18:6a4db94011d3 47 #endif
sahilmgandhi 18:6a4db94011d3 48
sahilmgandhi 18:6a4db94011d3 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
sahilmgandhi 18:6a4db94011d3 50 CMSIS violates the following MISRA-C:2004 rules:
sahilmgandhi 18:6a4db94011d3 51
sahilmgandhi 18:6a4db94011d3 52 \li Required Rule 8.5, object/function definition in header file.<br>
sahilmgandhi 18:6a4db94011d3 53 Function definitions in header files are used to allow 'inlining'.
sahilmgandhi 18:6a4db94011d3 54
sahilmgandhi 18:6a4db94011d3 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
sahilmgandhi 18:6a4db94011d3 56 Unions are used for effective representation of core registers.
sahilmgandhi 18:6a4db94011d3 57
sahilmgandhi 18:6a4db94011d3 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
sahilmgandhi 18:6a4db94011d3 59 Function-like macros are used to allow more efficient code.
sahilmgandhi 18:6a4db94011d3 60 */
sahilmgandhi 18:6a4db94011d3 61
sahilmgandhi 18:6a4db94011d3 62
sahilmgandhi 18:6a4db94011d3 63 /*******************************************************************************
sahilmgandhi 18:6a4db94011d3 64 * CMSIS definitions
sahilmgandhi 18:6a4db94011d3 65 ******************************************************************************/
sahilmgandhi 18:6a4db94011d3 66 /** \ingroup SC000
sahilmgandhi 18:6a4db94011d3 67 @{
sahilmgandhi 18:6a4db94011d3 68 */
sahilmgandhi 18:6a4db94011d3 69
sahilmgandhi 18:6a4db94011d3 70 /* CMSIS SC000 definitions */
sahilmgandhi 18:6a4db94011d3 71 #define __SC000_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
sahilmgandhi 18:6a4db94011d3 72 #define __SC000_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
sahilmgandhi 18:6a4db94011d3 73 #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \
sahilmgandhi 18:6a4db94011d3 74 __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
sahilmgandhi 18:6a4db94011d3 75
sahilmgandhi 18:6a4db94011d3 76 #define __CORTEX_SC (000) /*!< Cortex secure core */
sahilmgandhi 18:6a4db94011d3 77
sahilmgandhi 18:6a4db94011d3 78
sahilmgandhi 18:6a4db94011d3 79 #if defined ( __CC_ARM )
sahilmgandhi 18:6a4db94011d3 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
sahilmgandhi 18:6a4db94011d3 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
sahilmgandhi 18:6a4db94011d3 82 #define __STATIC_INLINE static __inline
sahilmgandhi 18:6a4db94011d3 83
sahilmgandhi 18:6a4db94011d3 84 #elif defined ( __GNUC__ )
sahilmgandhi 18:6a4db94011d3 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
sahilmgandhi 18:6a4db94011d3 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
sahilmgandhi 18:6a4db94011d3 87 #define __STATIC_INLINE static inline
sahilmgandhi 18:6a4db94011d3 88
sahilmgandhi 18:6a4db94011d3 89 #elif defined ( __ICCARM__ )
sahilmgandhi 18:6a4db94011d3 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
sahilmgandhi 18:6a4db94011d3 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
sahilmgandhi 18:6a4db94011d3 92 #define __STATIC_INLINE static inline
sahilmgandhi 18:6a4db94011d3 93
sahilmgandhi 18:6a4db94011d3 94 #elif defined ( __TMS470__ )
sahilmgandhi 18:6a4db94011d3 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
sahilmgandhi 18:6a4db94011d3 96 #define __STATIC_INLINE static inline
sahilmgandhi 18:6a4db94011d3 97
sahilmgandhi 18:6a4db94011d3 98 #elif defined ( __TASKING__ )
sahilmgandhi 18:6a4db94011d3 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
sahilmgandhi 18:6a4db94011d3 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
sahilmgandhi 18:6a4db94011d3 101 #define __STATIC_INLINE static inline
sahilmgandhi 18:6a4db94011d3 102
sahilmgandhi 18:6a4db94011d3 103 #elif defined ( __CSMC__ )
sahilmgandhi 18:6a4db94011d3 104 #define __packed
sahilmgandhi 18:6a4db94011d3 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
sahilmgandhi 18:6a4db94011d3 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
sahilmgandhi 18:6a4db94011d3 107 #define __STATIC_INLINE static inline
sahilmgandhi 18:6a4db94011d3 108
sahilmgandhi 18:6a4db94011d3 109 #endif
sahilmgandhi 18:6a4db94011d3 110
sahilmgandhi 18:6a4db94011d3 111 /** __FPU_USED indicates whether an FPU is used or not.
sahilmgandhi 18:6a4db94011d3 112 This core does not support an FPU at all
sahilmgandhi 18:6a4db94011d3 113 */
sahilmgandhi 18:6a4db94011d3 114 #define __FPU_USED 0
sahilmgandhi 18:6a4db94011d3 115
sahilmgandhi 18:6a4db94011d3 116 #if defined ( __CC_ARM )
sahilmgandhi 18:6a4db94011d3 117 #if defined __TARGET_FPU_VFP
sahilmgandhi 18:6a4db94011d3 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
sahilmgandhi 18:6a4db94011d3 119 #endif
sahilmgandhi 18:6a4db94011d3 120
sahilmgandhi 18:6a4db94011d3 121 #elif defined ( __GNUC__ )
sahilmgandhi 18:6a4db94011d3 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
sahilmgandhi 18:6a4db94011d3 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
sahilmgandhi 18:6a4db94011d3 124 #endif
sahilmgandhi 18:6a4db94011d3 125
sahilmgandhi 18:6a4db94011d3 126 #elif defined ( __ICCARM__ )
sahilmgandhi 18:6a4db94011d3 127 #if defined __ARMVFP__
sahilmgandhi 18:6a4db94011d3 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
sahilmgandhi 18:6a4db94011d3 129 #endif
sahilmgandhi 18:6a4db94011d3 130
sahilmgandhi 18:6a4db94011d3 131 #elif defined ( __TMS470__ )
sahilmgandhi 18:6a4db94011d3 132 #if defined __TI__VFP_SUPPORT____
sahilmgandhi 18:6a4db94011d3 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
sahilmgandhi 18:6a4db94011d3 134 #endif
sahilmgandhi 18:6a4db94011d3 135
sahilmgandhi 18:6a4db94011d3 136 #elif defined ( __TASKING__ )
sahilmgandhi 18:6a4db94011d3 137 #if defined __FPU_VFP__
sahilmgandhi 18:6a4db94011d3 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
sahilmgandhi 18:6a4db94011d3 139 #endif
sahilmgandhi 18:6a4db94011d3 140
sahilmgandhi 18:6a4db94011d3 141 #elif defined ( __CSMC__ ) /* Cosmic */
sahilmgandhi 18:6a4db94011d3 142 #if ( __CSMC__ & 0x400) // FPU present for parser
sahilmgandhi 18:6a4db94011d3 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
sahilmgandhi 18:6a4db94011d3 144 #endif
sahilmgandhi 18:6a4db94011d3 145 #endif
sahilmgandhi 18:6a4db94011d3 146
sahilmgandhi 18:6a4db94011d3 147 #include <stdint.h> /* standard types definitions */
sahilmgandhi 18:6a4db94011d3 148 #include <core_cmInstr.h> /* Core Instruction Access */
sahilmgandhi 18:6a4db94011d3 149 #include <core_cmFunc.h> /* Core Function Access */
sahilmgandhi 18:6a4db94011d3 150
sahilmgandhi 18:6a4db94011d3 151 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 152 }
sahilmgandhi 18:6a4db94011d3 153 #endif
sahilmgandhi 18:6a4db94011d3 154
sahilmgandhi 18:6a4db94011d3 155 #endif /* __CORE_SC000_H_GENERIC */
sahilmgandhi 18:6a4db94011d3 156
sahilmgandhi 18:6a4db94011d3 157 #ifndef __CMSIS_GENERIC
sahilmgandhi 18:6a4db94011d3 158
sahilmgandhi 18:6a4db94011d3 159 #ifndef __CORE_SC000_H_DEPENDANT
sahilmgandhi 18:6a4db94011d3 160 #define __CORE_SC000_H_DEPENDANT
sahilmgandhi 18:6a4db94011d3 161
sahilmgandhi 18:6a4db94011d3 162 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 163 extern "C" {
sahilmgandhi 18:6a4db94011d3 164 #endif
sahilmgandhi 18:6a4db94011d3 165
sahilmgandhi 18:6a4db94011d3 166 /* check device defines and use defaults */
sahilmgandhi 18:6a4db94011d3 167 #if defined __CHECK_DEVICE_DEFINES
sahilmgandhi 18:6a4db94011d3 168 #ifndef __SC000_REV
sahilmgandhi 18:6a4db94011d3 169 #define __SC000_REV 0x0000
sahilmgandhi 18:6a4db94011d3 170 #warning "__SC000_REV not defined in device header file; using default!"
sahilmgandhi 18:6a4db94011d3 171 #endif
sahilmgandhi 18:6a4db94011d3 172
sahilmgandhi 18:6a4db94011d3 173 #ifndef __MPU_PRESENT
sahilmgandhi 18:6a4db94011d3 174 #define __MPU_PRESENT 0
sahilmgandhi 18:6a4db94011d3 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
sahilmgandhi 18:6a4db94011d3 176 #endif
sahilmgandhi 18:6a4db94011d3 177
sahilmgandhi 18:6a4db94011d3 178 #ifndef __NVIC_PRIO_BITS
sahilmgandhi 18:6a4db94011d3 179 #define __NVIC_PRIO_BITS 2
sahilmgandhi 18:6a4db94011d3 180 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
sahilmgandhi 18:6a4db94011d3 181 #endif
sahilmgandhi 18:6a4db94011d3 182
sahilmgandhi 18:6a4db94011d3 183 #ifndef __Vendor_SysTickConfig
sahilmgandhi 18:6a4db94011d3 184 #define __Vendor_SysTickConfig 0
sahilmgandhi 18:6a4db94011d3 185 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
sahilmgandhi 18:6a4db94011d3 186 #endif
sahilmgandhi 18:6a4db94011d3 187 #endif
sahilmgandhi 18:6a4db94011d3 188
sahilmgandhi 18:6a4db94011d3 189 /* IO definitions (access restrictions to peripheral registers) */
sahilmgandhi 18:6a4db94011d3 190 /**
sahilmgandhi 18:6a4db94011d3 191 \defgroup CMSIS_glob_defs CMSIS Global Defines
sahilmgandhi 18:6a4db94011d3 192
sahilmgandhi 18:6a4db94011d3 193 <strong>IO Type Qualifiers</strong> are used
sahilmgandhi 18:6a4db94011d3 194 \li to specify the access to peripheral variables.
sahilmgandhi 18:6a4db94011d3 195 \li for automatic generation of peripheral register debug information.
sahilmgandhi 18:6a4db94011d3 196 */
sahilmgandhi 18:6a4db94011d3 197 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 198 #define __I volatile /*!< Defines 'read only' permissions */
sahilmgandhi 18:6a4db94011d3 199 #else
sahilmgandhi 18:6a4db94011d3 200 #define __I volatile const /*!< Defines 'read only' permissions */
sahilmgandhi 18:6a4db94011d3 201 #endif
sahilmgandhi 18:6a4db94011d3 202 #define __O volatile /*!< Defines 'write only' permissions */
sahilmgandhi 18:6a4db94011d3 203 #define __IO volatile /*!< Defines 'read / write' permissions */
sahilmgandhi 18:6a4db94011d3 204
sahilmgandhi 18:6a4db94011d3 205 /*@} end of group SC000 */
sahilmgandhi 18:6a4db94011d3 206
sahilmgandhi 18:6a4db94011d3 207
sahilmgandhi 18:6a4db94011d3 208
sahilmgandhi 18:6a4db94011d3 209 /*******************************************************************************
sahilmgandhi 18:6a4db94011d3 210 * Register Abstraction
sahilmgandhi 18:6a4db94011d3 211 Core Register contain:
sahilmgandhi 18:6a4db94011d3 212 - Core Register
sahilmgandhi 18:6a4db94011d3 213 - Core NVIC Register
sahilmgandhi 18:6a4db94011d3 214 - Core SCB Register
sahilmgandhi 18:6a4db94011d3 215 - Core SysTick Register
sahilmgandhi 18:6a4db94011d3 216 - Core MPU Register
sahilmgandhi 18:6a4db94011d3 217 ******************************************************************************/
sahilmgandhi 18:6a4db94011d3 218 /** \defgroup CMSIS_core_register Defines and Type Definitions
sahilmgandhi 18:6a4db94011d3 219 \brief Type definitions and defines for Cortex-M processor based devices.
sahilmgandhi 18:6a4db94011d3 220 */
sahilmgandhi 18:6a4db94011d3 221
sahilmgandhi 18:6a4db94011d3 222 /** \ingroup CMSIS_core_register
sahilmgandhi 18:6a4db94011d3 223 \defgroup CMSIS_CORE Status and Control Registers
sahilmgandhi 18:6a4db94011d3 224 \brief Core Register type definitions.
sahilmgandhi 18:6a4db94011d3 225 @{
sahilmgandhi 18:6a4db94011d3 226 */
sahilmgandhi 18:6a4db94011d3 227
sahilmgandhi 18:6a4db94011d3 228 /** \brief Union type to access the Application Program Status Register (APSR).
sahilmgandhi 18:6a4db94011d3 229 */
sahilmgandhi 18:6a4db94011d3 230 typedef union
sahilmgandhi 18:6a4db94011d3 231 {
sahilmgandhi 18:6a4db94011d3 232 struct
sahilmgandhi 18:6a4db94011d3 233 {
sahilmgandhi 18:6a4db94011d3 234 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
sahilmgandhi 18:6a4db94011d3 235 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
sahilmgandhi 18:6a4db94011d3 236 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
sahilmgandhi 18:6a4db94011d3 237 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
sahilmgandhi 18:6a4db94011d3 238 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
sahilmgandhi 18:6a4db94011d3 239 } b; /*!< Structure used for bit access */
sahilmgandhi 18:6a4db94011d3 240 uint32_t w; /*!< Type used for word access */
sahilmgandhi 18:6a4db94011d3 241 } APSR_Type;
sahilmgandhi 18:6a4db94011d3 242
sahilmgandhi 18:6a4db94011d3 243 /* APSR Register Definitions */
sahilmgandhi 18:6a4db94011d3 244 #define APSR_N_Pos 31 /*!< APSR: N Position */
sahilmgandhi 18:6a4db94011d3 245 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
sahilmgandhi 18:6a4db94011d3 246
sahilmgandhi 18:6a4db94011d3 247 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
sahilmgandhi 18:6a4db94011d3 248 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
sahilmgandhi 18:6a4db94011d3 249
sahilmgandhi 18:6a4db94011d3 250 #define APSR_C_Pos 29 /*!< APSR: C Position */
sahilmgandhi 18:6a4db94011d3 251 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
sahilmgandhi 18:6a4db94011d3 252
sahilmgandhi 18:6a4db94011d3 253 #define APSR_V_Pos 28 /*!< APSR: V Position */
sahilmgandhi 18:6a4db94011d3 254 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
sahilmgandhi 18:6a4db94011d3 255
sahilmgandhi 18:6a4db94011d3 256
sahilmgandhi 18:6a4db94011d3 257 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
sahilmgandhi 18:6a4db94011d3 258 */
sahilmgandhi 18:6a4db94011d3 259 typedef union
sahilmgandhi 18:6a4db94011d3 260 {
sahilmgandhi 18:6a4db94011d3 261 struct
sahilmgandhi 18:6a4db94011d3 262 {
sahilmgandhi 18:6a4db94011d3 263 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
sahilmgandhi 18:6a4db94011d3 264 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
sahilmgandhi 18:6a4db94011d3 265 } b; /*!< Structure used for bit access */
sahilmgandhi 18:6a4db94011d3 266 uint32_t w; /*!< Type used for word access */
sahilmgandhi 18:6a4db94011d3 267 } IPSR_Type;
sahilmgandhi 18:6a4db94011d3 268
sahilmgandhi 18:6a4db94011d3 269 /* IPSR Register Definitions */
sahilmgandhi 18:6a4db94011d3 270 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
sahilmgandhi 18:6a4db94011d3 271 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
sahilmgandhi 18:6a4db94011d3 272
sahilmgandhi 18:6a4db94011d3 273
sahilmgandhi 18:6a4db94011d3 274 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
sahilmgandhi 18:6a4db94011d3 275 */
sahilmgandhi 18:6a4db94011d3 276 typedef union
sahilmgandhi 18:6a4db94011d3 277 {
sahilmgandhi 18:6a4db94011d3 278 struct
sahilmgandhi 18:6a4db94011d3 279 {
sahilmgandhi 18:6a4db94011d3 280 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
sahilmgandhi 18:6a4db94011d3 281 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
sahilmgandhi 18:6a4db94011d3 282 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
sahilmgandhi 18:6a4db94011d3 283 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
sahilmgandhi 18:6a4db94011d3 284 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
sahilmgandhi 18:6a4db94011d3 285 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
sahilmgandhi 18:6a4db94011d3 286 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
sahilmgandhi 18:6a4db94011d3 287 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
sahilmgandhi 18:6a4db94011d3 288 } b; /*!< Structure used for bit access */
sahilmgandhi 18:6a4db94011d3 289 uint32_t w; /*!< Type used for word access */
sahilmgandhi 18:6a4db94011d3 290 } xPSR_Type;
sahilmgandhi 18:6a4db94011d3 291
sahilmgandhi 18:6a4db94011d3 292 /* xPSR Register Definitions */
sahilmgandhi 18:6a4db94011d3 293 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
sahilmgandhi 18:6a4db94011d3 294 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
sahilmgandhi 18:6a4db94011d3 295
sahilmgandhi 18:6a4db94011d3 296 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
sahilmgandhi 18:6a4db94011d3 297 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
sahilmgandhi 18:6a4db94011d3 298
sahilmgandhi 18:6a4db94011d3 299 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
sahilmgandhi 18:6a4db94011d3 300 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
sahilmgandhi 18:6a4db94011d3 301
sahilmgandhi 18:6a4db94011d3 302 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
sahilmgandhi 18:6a4db94011d3 303 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
sahilmgandhi 18:6a4db94011d3 304
sahilmgandhi 18:6a4db94011d3 305 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
sahilmgandhi 18:6a4db94011d3 306 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
sahilmgandhi 18:6a4db94011d3 307
sahilmgandhi 18:6a4db94011d3 308 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
sahilmgandhi 18:6a4db94011d3 309 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
sahilmgandhi 18:6a4db94011d3 310
sahilmgandhi 18:6a4db94011d3 311
sahilmgandhi 18:6a4db94011d3 312 /** \brief Union type to access the Control Registers (CONTROL).
sahilmgandhi 18:6a4db94011d3 313 */
sahilmgandhi 18:6a4db94011d3 314 typedef union
sahilmgandhi 18:6a4db94011d3 315 {
sahilmgandhi 18:6a4db94011d3 316 struct
sahilmgandhi 18:6a4db94011d3 317 {
sahilmgandhi 18:6a4db94011d3 318 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
sahilmgandhi 18:6a4db94011d3 319 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
sahilmgandhi 18:6a4db94011d3 320 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
sahilmgandhi 18:6a4db94011d3 321 } b; /*!< Structure used for bit access */
sahilmgandhi 18:6a4db94011d3 322 uint32_t w; /*!< Type used for word access */
sahilmgandhi 18:6a4db94011d3 323 } CONTROL_Type;
sahilmgandhi 18:6a4db94011d3 324
sahilmgandhi 18:6a4db94011d3 325 /* CONTROL Register Definitions */
sahilmgandhi 18:6a4db94011d3 326 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
sahilmgandhi 18:6a4db94011d3 327 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
sahilmgandhi 18:6a4db94011d3 328
sahilmgandhi 18:6a4db94011d3 329 /*@} end of group CMSIS_CORE */
sahilmgandhi 18:6a4db94011d3 330
sahilmgandhi 18:6a4db94011d3 331
sahilmgandhi 18:6a4db94011d3 332 /** \ingroup CMSIS_core_register
sahilmgandhi 18:6a4db94011d3 333 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
sahilmgandhi 18:6a4db94011d3 334 \brief Type definitions for the NVIC Registers
sahilmgandhi 18:6a4db94011d3 335 @{
sahilmgandhi 18:6a4db94011d3 336 */
sahilmgandhi 18:6a4db94011d3 337
sahilmgandhi 18:6a4db94011d3 338 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
sahilmgandhi 18:6a4db94011d3 339 */
sahilmgandhi 18:6a4db94011d3 340 typedef struct
sahilmgandhi 18:6a4db94011d3 341 {
sahilmgandhi 18:6a4db94011d3 342 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
sahilmgandhi 18:6a4db94011d3 343 uint32_t RESERVED0[31];
sahilmgandhi 18:6a4db94011d3 344 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
sahilmgandhi 18:6a4db94011d3 345 uint32_t RSERVED1[31];
sahilmgandhi 18:6a4db94011d3 346 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
sahilmgandhi 18:6a4db94011d3 347 uint32_t RESERVED2[31];
sahilmgandhi 18:6a4db94011d3 348 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
sahilmgandhi 18:6a4db94011d3 349 uint32_t RESERVED3[31];
sahilmgandhi 18:6a4db94011d3 350 uint32_t RESERVED4[64];
sahilmgandhi 18:6a4db94011d3 351 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
sahilmgandhi 18:6a4db94011d3 352 } NVIC_Type;
sahilmgandhi 18:6a4db94011d3 353
sahilmgandhi 18:6a4db94011d3 354 /*@} end of group CMSIS_NVIC */
sahilmgandhi 18:6a4db94011d3 355
sahilmgandhi 18:6a4db94011d3 356
sahilmgandhi 18:6a4db94011d3 357 /** \ingroup CMSIS_core_register
sahilmgandhi 18:6a4db94011d3 358 \defgroup CMSIS_SCB System Control Block (SCB)
sahilmgandhi 18:6a4db94011d3 359 \brief Type definitions for the System Control Block Registers
sahilmgandhi 18:6a4db94011d3 360 @{
sahilmgandhi 18:6a4db94011d3 361 */
sahilmgandhi 18:6a4db94011d3 362
sahilmgandhi 18:6a4db94011d3 363 /** \brief Structure type to access the System Control Block (SCB).
sahilmgandhi 18:6a4db94011d3 364 */
sahilmgandhi 18:6a4db94011d3 365 typedef struct
sahilmgandhi 18:6a4db94011d3 366 {
sahilmgandhi 18:6a4db94011d3 367 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
sahilmgandhi 18:6a4db94011d3 368 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
sahilmgandhi 18:6a4db94011d3 369 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
sahilmgandhi 18:6a4db94011d3 370 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
sahilmgandhi 18:6a4db94011d3 371 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
sahilmgandhi 18:6a4db94011d3 372 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
sahilmgandhi 18:6a4db94011d3 373 uint32_t RESERVED0[1];
sahilmgandhi 18:6a4db94011d3 374 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
sahilmgandhi 18:6a4db94011d3 375 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
sahilmgandhi 18:6a4db94011d3 376 uint32_t RESERVED1[154];
sahilmgandhi 18:6a4db94011d3 377 __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
sahilmgandhi 18:6a4db94011d3 378 } SCB_Type;
sahilmgandhi 18:6a4db94011d3 379
sahilmgandhi 18:6a4db94011d3 380 /* SCB CPUID Register Definitions */
sahilmgandhi 18:6a4db94011d3 381 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
sahilmgandhi 18:6a4db94011d3 382 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
sahilmgandhi 18:6a4db94011d3 383
sahilmgandhi 18:6a4db94011d3 384 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
sahilmgandhi 18:6a4db94011d3 385 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
sahilmgandhi 18:6a4db94011d3 386
sahilmgandhi 18:6a4db94011d3 387 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
sahilmgandhi 18:6a4db94011d3 388 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
sahilmgandhi 18:6a4db94011d3 389
sahilmgandhi 18:6a4db94011d3 390 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
sahilmgandhi 18:6a4db94011d3 391 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
sahilmgandhi 18:6a4db94011d3 392
sahilmgandhi 18:6a4db94011d3 393 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
sahilmgandhi 18:6a4db94011d3 394 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
sahilmgandhi 18:6a4db94011d3 395
sahilmgandhi 18:6a4db94011d3 396 /* SCB Interrupt Control State Register Definitions */
sahilmgandhi 18:6a4db94011d3 397 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
sahilmgandhi 18:6a4db94011d3 398 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
sahilmgandhi 18:6a4db94011d3 399
sahilmgandhi 18:6a4db94011d3 400 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
sahilmgandhi 18:6a4db94011d3 401 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
sahilmgandhi 18:6a4db94011d3 402
sahilmgandhi 18:6a4db94011d3 403 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
sahilmgandhi 18:6a4db94011d3 404 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
sahilmgandhi 18:6a4db94011d3 405
sahilmgandhi 18:6a4db94011d3 406 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
sahilmgandhi 18:6a4db94011d3 407 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
sahilmgandhi 18:6a4db94011d3 408
sahilmgandhi 18:6a4db94011d3 409 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
sahilmgandhi 18:6a4db94011d3 410 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
sahilmgandhi 18:6a4db94011d3 411
sahilmgandhi 18:6a4db94011d3 412 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
sahilmgandhi 18:6a4db94011d3 413 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
sahilmgandhi 18:6a4db94011d3 414
sahilmgandhi 18:6a4db94011d3 415 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
sahilmgandhi 18:6a4db94011d3 416 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
sahilmgandhi 18:6a4db94011d3 417
sahilmgandhi 18:6a4db94011d3 418 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
sahilmgandhi 18:6a4db94011d3 419 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
sahilmgandhi 18:6a4db94011d3 420
sahilmgandhi 18:6a4db94011d3 421 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
sahilmgandhi 18:6a4db94011d3 422 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
sahilmgandhi 18:6a4db94011d3 423
sahilmgandhi 18:6a4db94011d3 424 /* SCB Interrupt Control State Register Definitions */
sahilmgandhi 18:6a4db94011d3 425 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
sahilmgandhi 18:6a4db94011d3 426 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
sahilmgandhi 18:6a4db94011d3 427
sahilmgandhi 18:6a4db94011d3 428 /* SCB Application Interrupt and Reset Control Register Definitions */
sahilmgandhi 18:6a4db94011d3 429 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
sahilmgandhi 18:6a4db94011d3 430 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
sahilmgandhi 18:6a4db94011d3 431
sahilmgandhi 18:6a4db94011d3 432 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
sahilmgandhi 18:6a4db94011d3 433 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
sahilmgandhi 18:6a4db94011d3 434
sahilmgandhi 18:6a4db94011d3 435 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
sahilmgandhi 18:6a4db94011d3 436 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
sahilmgandhi 18:6a4db94011d3 437
sahilmgandhi 18:6a4db94011d3 438 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
sahilmgandhi 18:6a4db94011d3 439 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
sahilmgandhi 18:6a4db94011d3 440
sahilmgandhi 18:6a4db94011d3 441 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
sahilmgandhi 18:6a4db94011d3 442 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
sahilmgandhi 18:6a4db94011d3 443
sahilmgandhi 18:6a4db94011d3 444 /* SCB System Control Register Definitions */
sahilmgandhi 18:6a4db94011d3 445 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
sahilmgandhi 18:6a4db94011d3 446 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
sahilmgandhi 18:6a4db94011d3 447
sahilmgandhi 18:6a4db94011d3 448 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
sahilmgandhi 18:6a4db94011d3 449 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
sahilmgandhi 18:6a4db94011d3 450
sahilmgandhi 18:6a4db94011d3 451 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
sahilmgandhi 18:6a4db94011d3 452 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
sahilmgandhi 18:6a4db94011d3 453
sahilmgandhi 18:6a4db94011d3 454 /* SCB Configuration Control Register Definitions */
sahilmgandhi 18:6a4db94011d3 455 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
sahilmgandhi 18:6a4db94011d3 456 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
sahilmgandhi 18:6a4db94011d3 457
sahilmgandhi 18:6a4db94011d3 458 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
sahilmgandhi 18:6a4db94011d3 459 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
sahilmgandhi 18:6a4db94011d3 460
sahilmgandhi 18:6a4db94011d3 461 /* SCB System Handler Control and State Register Definitions */
sahilmgandhi 18:6a4db94011d3 462 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
sahilmgandhi 18:6a4db94011d3 463 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
sahilmgandhi 18:6a4db94011d3 464
sahilmgandhi 18:6a4db94011d3 465 /*@} end of group CMSIS_SCB */
sahilmgandhi 18:6a4db94011d3 466
sahilmgandhi 18:6a4db94011d3 467
sahilmgandhi 18:6a4db94011d3 468 /** \ingroup CMSIS_core_register
sahilmgandhi 18:6a4db94011d3 469 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
sahilmgandhi 18:6a4db94011d3 470 \brief Type definitions for the System Control and ID Register not in the SCB
sahilmgandhi 18:6a4db94011d3 471 @{
sahilmgandhi 18:6a4db94011d3 472 */
sahilmgandhi 18:6a4db94011d3 473
sahilmgandhi 18:6a4db94011d3 474 /** \brief Structure type to access the System Control and ID Register not in the SCB.
sahilmgandhi 18:6a4db94011d3 475 */
sahilmgandhi 18:6a4db94011d3 476 typedef struct
sahilmgandhi 18:6a4db94011d3 477 {
sahilmgandhi 18:6a4db94011d3 478 uint32_t RESERVED0[2];
sahilmgandhi 18:6a4db94011d3 479 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
sahilmgandhi 18:6a4db94011d3 480 } SCnSCB_Type;
sahilmgandhi 18:6a4db94011d3 481
sahilmgandhi 18:6a4db94011d3 482 /* Auxiliary Control Register Definitions */
sahilmgandhi 18:6a4db94011d3 483 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
sahilmgandhi 18:6a4db94011d3 484 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
sahilmgandhi 18:6a4db94011d3 485
sahilmgandhi 18:6a4db94011d3 486 /*@} end of group CMSIS_SCnotSCB */
sahilmgandhi 18:6a4db94011d3 487
sahilmgandhi 18:6a4db94011d3 488
sahilmgandhi 18:6a4db94011d3 489 /** \ingroup CMSIS_core_register
sahilmgandhi 18:6a4db94011d3 490 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
sahilmgandhi 18:6a4db94011d3 491 \brief Type definitions for the System Timer Registers.
sahilmgandhi 18:6a4db94011d3 492 @{
sahilmgandhi 18:6a4db94011d3 493 */
sahilmgandhi 18:6a4db94011d3 494
sahilmgandhi 18:6a4db94011d3 495 /** \brief Structure type to access the System Timer (SysTick).
sahilmgandhi 18:6a4db94011d3 496 */
sahilmgandhi 18:6a4db94011d3 497 typedef struct
sahilmgandhi 18:6a4db94011d3 498 {
sahilmgandhi 18:6a4db94011d3 499 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
sahilmgandhi 18:6a4db94011d3 500 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
sahilmgandhi 18:6a4db94011d3 501 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
sahilmgandhi 18:6a4db94011d3 502 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
sahilmgandhi 18:6a4db94011d3 503 } SysTick_Type;
sahilmgandhi 18:6a4db94011d3 504
sahilmgandhi 18:6a4db94011d3 505 /* SysTick Control / Status Register Definitions */
sahilmgandhi 18:6a4db94011d3 506 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
sahilmgandhi 18:6a4db94011d3 507 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
sahilmgandhi 18:6a4db94011d3 508
sahilmgandhi 18:6a4db94011d3 509 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
sahilmgandhi 18:6a4db94011d3 510 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
sahilmgandhi 18:6a4db94011d3 511
sahilmgandhi 18:6a4db94011d3 512 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
sahilmgandhi 18:6a4db94011d3 513 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
sahilmgandhi 18:6a4db94011d3 514
sahilmgandhi 18:6a4db94011d3 515 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
sahilmgandhi 18:6a4db94011d3 516 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
sahilmgandhi 18:6a4db94011d3 517
sahilmgandhi 18:6a4db94011d3 518 /* SysTick Reload Register Definitions */
sahilmgandhi 18:6a4db94011d3 519 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
sahilmgandhi 18:6a4db94011d3 520 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
sahilmgandhi 18:6a4db94011d3 521
sahilmgandhi 18:6a4db94011d3 522 /* SysTick Current Register Definitions */
sahilmgandhi 18:6a4db94011d3 523 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
sahilmgandhi 18:6a4db94011d3 524 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
sahilmgandhi 18:6a4db94011d3 525
sahilmgandhi 18:6a4db94011d3 526 /* SysTick Calibration Register Definitions */
sahilmgandhi 18:6a4db94011d3 527 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
sahilmgandhi 18:6a4db94011d3 528 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
sahilmgandhi 18:6a4db94011d3 529
sahilmgandhi 18:6a4db94011d3 530 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
sahilmgandhi 18:6a4db94011d3 531 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
sahilmgandhi 18:6a4db94011d3 532
sahilmgandhi 18:6a4db94011d3 533 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
sahilmgandhi 18:6a4db94011d3 534 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
sahilmgandhi 18:6a4db94011d3 535
sahilmgandhi 18:6a4db94011d3 536 /*@} end of group CMSIS_SysTick */
sahilmgandhi 18:6a4db94011d3 537
sahilmgandhi 18:6a4db94011d3 538 #if (__MPU_PRESENT == 1)
sahilmgandhi 18:6a4db94011d3 539 /** \ingroup CMSIS_core_register
sahilmgandhi 18:6a4db94011d3 540 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
sahilmgandhi 18:6a4db94011d3 541 \brief Type definitions for the Memory Protection Unit (MPU)
sahilmgandhi 18:6a4db94011d3 542 @{
sahilmgandhi 18:6a4db94011d3 543 */
sahilmgandhi 18:6a4db94011d3 544
sahilmgandhi 18:6a4db94011d3 545 /** \brief Structure type to access the Memory Protection Unit (MPU).
sahilmgandhi 18:6a4db94011d3 546 */
sahilmgandhi 18:6a4db94011d3 547 typedef struct
sahilmgandhi 18:6a4db94011d3 548 {
sahilmgandhi 18:6a4db94011d3 549 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
sahilmgandhi 18:6a4db94011d3 550 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
sahilmgandhi 18:6a4db94011d3 551 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
sahilmgandhi 18:6a4db94011d3 552 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
sahilmgandhi 18:6a4db94011d3 553 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
sahilmgandhi 18:6a4db94011d3 554 } MPU_Type;
sahilmgandhi 18:6a4db94011d3 555
sahilmgandhi 18:6a4db94011d3 556 /* MPU Type Register */
sahilmgandhi 18:6a4db94011d3 557 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
sahilmgandhi 18:6a4db94011d3 558 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
sahilmgandhi 18:6a4db94011d3 559
sahilmgandhi 18:6a4db94011d3 560 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
sahilmgandhi 18:6a4db94011d3 561 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
sahilmgandhi 18:6a4db94011d3 562
sahilmgandhi 18:6a4db94011d3 563 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
sahilmgandhi 18:6a4db94011d3 564 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
sahilmgandhi 18:6a4db94011d3 565
sahilmgandhi 18:6a4db94011d3 566 /* MPU Control Register */
sahilmgandhi 18:6a4db94011d3 567 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
sahilmgandhi 18:6a4db94011d3 568 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
sahilmgandhi 18:6a4db94011d3 569
sahilmgandhi 18:6a4db94011d3 570 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
sahilmgandhi 18:6a4db94011d3 571 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
sahilmgandhi 18:6a4db94011d3 572
sahilmgandhi 18:6a4db94011d3 573 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
sahilmgandhi 18:6a4db94011d3 574 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
sahilmgandhi 18:6a4db94011d3 575
sahilmgandhi 18:6a4db94011d3 576 /* MPU Region Number Register */
sahilmgandhi 18:6a4db94011d3 577 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
sahilmgandhi 18:6a4db94011d3 578 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
sahilmgandhi 18:6a4db94011d3 579
sahilmgandhi 18:6a4db94011d3 580 /* MPU Region Base Address Register */
sahilmgandhi 18:6a4db94011d3 581 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
sahilmgandhi 18:6a4db94011d3 582 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
sahilmgandhi 18:6a4db94011d3 583
sahilmgandhi 18:6a4db94011d3 584 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
sahilmgandhi 18:6a4db94011d3 585 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
sahilmgandhi 18:6a4db94011d3 586
sahilmgandhi 18:6a4db94011d3 587 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
sahilmgandhi 18:6a4db94011d3 588 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
sahilmgandhi 18:6a4db94011d3 589
sahilmgandhi 18:6a4db94011d3 590 /* MPU Region Attribute and Size Register */
sahilmgandhi 18:6a4db94011d3 591 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
sahilmgandhi 18:6a4db94011d3 592 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
sahilmgandhi 18:6a4db94011d3 593
sahilmgandhi 18:6a4db94011d3 594 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
sahilmgandhi 18:6a4db94011d3 595 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
sahilmgandhi 18:6a4db94011d3 596
sahilmgandhi 18:6a4db94011d3 597 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
sahilmgandhi 18:6a4db94011d3 598 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
sahilmgandhi 18:6a4db94011d3 599
sahilmgandhi 18:6a4db94011d3 600 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
sahilmgandhi 18:6a4db94011d3 601 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
sahilmgandhi 18:6a4db94011d3 602
sahilmgandhi 18:6a4db94011d3 603 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
sahilmgandhi 18:6a4db94011d3 604 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
sahilmgandhi 18:6a4db94011d3 605
sahilmgandhi 18:6a4db94011d3 606 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
sahilmgandhi 18:6a4db94011d3 607 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
sahilmgandhi 18:6a4db94011d3 608
sahilmgandhi 18:6a4db94011d3 609 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
sahilmgandhi 18:6a4db94011d3 610 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
sahilmgandhi 18:6a4db94011d3 611
sahilmgandhi 18:6a4db94011d3 612 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
sahilmgandhi 18:6a4db94011d3 613 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
sahilmgandhi 18:6a4db94011d3 614
sahilmgandhi 18:6a4db94011d3 615 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
sahilmgandhi 18:6a4db94011d3 616 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
sahilmgandhi 18:6a4db94011d3 617
sahilmgandhi 18:6a4db94011d3 618 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
sahilmgandhi 18:6a4db94011d3 619 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
sahilmgandhi 18:6a4db94011d3 620
sahilmgandhi 18:6a4db94011d3 621 /*@} end of group CMSIS_MPU */
sahilmgandhi 18:6a4db94011d3 622 #endif
sahilmgandhi 18:6a4db94011d3 623
sahilmgandhi 18:6a4db94011d3 624
sahilmgandhi 18:6a4db94011d3 625 /** \ingroup CMSIS_core_register
sahilmgandhi 18:6a4db94011d3 626 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
sahilmgandhi 18:6a4db94011d3 627 \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR)
sahilmgandhi 18:6a4db94011d3 628 are only accessible over DAP and not via processor. Therefore
sahilmgandhi 18:6a4db94011d3 629 they are not covered by the Cortex-M0 header file.
sahilmgandhi 18:6a4db94011d3 630 @{
sahilmgandhi 18:6a4db94011d3 631 */
sahilmgandhi 18:6a4db94011d3 632 /*@} end of group CMSIS_CoreDebug */
sahilmgandhi 18:6a4db94011d3 633
sahilmgandhi 18:6a4db94011d3 634
sahilmgandhi 18:6a4db94011d3 635 /** \ingroup CMSIS_core_register
sahilmgandhi 18:6a4db94011d3 636 \defgroup CMSIS_core_base Core Definitions
sahilmgandhi 18:6a4db94011d3 637 \brief Definitions for base addresses, unions, and structures.
sahilmgandhi 18:6a4db94011d3 638 @{
sahilmgandhi 18:6a4db94011d3 639 */
sahilmgandhi 18:6a4db94011d3 640
sahilmgandhi 18:6a4db94011d3 641 /* Memory mapping of SC000 Hardware */
sahilmgandhi 18:6a4db94011d3 642 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
sahilmgandhi 18:6a4db94011d3 643 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
sahilmgandhi 18:6a4db94011d3 644 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
sahilmgandhi 18:6a4db94011d3 645 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
sahilmgandhi 18:6a4db94011d3 646
sahilmgandhi 18:6a4db94011d3 647 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
sahilmgandhi 18:6a4db94011d3 648 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
sahilmgandhi 18:6a4db94011d3 649 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
sahilmgandhi 18:6a4db94011d3 650 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
sahilmgandhi 18:6a4db94011d3 651
sahilmgandhi 18:6a4db94011d3 652 #if (__MPU_PRESENT == 1)
sahilmgandhi 18:6a4db94011d3 653 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
sahilmgandhi 18:6a4db94011d3 654 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
sahilmgandhi 18:6a4db94011d3 655 #endif
sahilmgandhi 18:6a4db94011d3 656
sahilmgandhi 18:6a4db94011d3 657 /*@} */
sahilmgandhi 18:6a4db94011d3 658
sahilmgandhi 18:6a4db94011d3 659
sahilmgandhi 18:6a4db94011d3 660
sahilmgandhi 18:6a4db94011d3 661 /*******************************************************************************
sahilmgandhi 18:6a4db94011d3 662 * Hardware Abstraction Layer
sahilmgandhi 18:6a4db94011d3 663 Core Function Interface contains:
sahilmgandhi 18:6a4db94011d3 664 - Core NVIC Functions
sahilmgandhi 18:6a4db94011d3 665 - Core SysTick Functions
sahilmgandhi 18:6a4db94011d3 666 - Core Register Access Functions
sahilmgandhi 18:6a4db94011d3 667 ******************************************************************************/
sahilmgandhi 18:6a4db94011d3 668 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
sahilmgandhi 18:6a4db94011d3 669 */
sahilmgandhi 18:6a4db94011d3 670
sahilmgandhi 18:6a4db94011d3 671
sahilmgandhi 18:6a4db94011d3 672
sahilmgandhi 18:6a4db94011d3 673 /* ########################## NVIC functions #################################### */
sahilmgandhi 18:6a4db94011d3 674 /** \ingroup CMSIS_Core_FunctionInterface
sahilmgandhi 18:6a4db94011d3 675 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
sahilmgandhi 18:6a4db94011d3 676 \brief Functions that manage interrupts and exceptions via the NVIC.
sahilmgandhi 18:6a4db94011d3 677 @{
sahilmgandhi 18:6a4db94011d3 678 */
sahilmgandhi 18:6a4db94011d3 679
sahilmgandhi 18:6a4db94011d3 680 /* Interrupt Priorities are WORD accessible only under ARMv6M */
sahilmgandhi 18:6a4db94011d3 681 /* The following MACROS handle generation of the register offset and byte masks */
sahilmgandhi 18:6a4db94011d3 682 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
sahilmgandhi 18:6a4db94011d3 683 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
sahilmgandhi 18:6a4db94011d3 684 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
sahilmgandhi 18:6a4db94011d3 685
sahilmgandhi 18:6a4db94011d3 686
sahilmgandhi 18:6a4db94011d3 687 /** \brief Enable External Interrupt
sahilmgandhi 18:6a4db94011d3 688
sahilmgandhi 18:6a4db94011d3 689 The function enables a device-specific interrupt in the NVIC interrupt controller.
sahilmgandhi 18:6a4db94011d3 690
sahilmgandhi 18:6a4db94011d3 691 \param [in] IRQn External interrupt number. Value cannot be negative.
sahilmgandhi 18:6a4db94011d3 692 */
sahilmgandhi 18:6a4db94011d3 693 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
sahilmgandhi 18:6a4db94011d3 694 {
sahilmgandhi 18:6a4db94011d3 695 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
sahilmgandhi 18:6a4db94011d3 696 }
sahilmgandhi 18:6a4db94011d3 697
sahilmgandhi 18:6a4db94011d3 698
sahilmgandhi 18:6a4db94011d3 699 /** \brief Disable External Interrupt
sahilmgandhi 18:6a4db94011d3 700
sahilmgandhi 18:6a4db94011d3 701 The function disables a device-specific interrupt in the NVIC interrupt controller.
sahilmgandhi 18:6a4db94011d3 702
sahilmgandhi 18:6a4db94011d3 703 \param [in] IRQn External interrupt number. Value cannot be negative.
sahilmgandhi 18:6a4db94011d3 704 */
sahilmgandhi 18:6a4db94011d3 705 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
sahilmgandhi 18:6a4db94011d3 706 {
sahilmgandhi 18:6a4db94011d3 707 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
sahilmgandhi 18:6a4db94011d3 708 __DSB();
sahilmgandhi 18:6a4db94011d3 709 __ISB();
sahilmgandhi 18:6a4db94011d3 710 }
sahilmgandhi 18:6a4db94011d3 711
sahilmgandhi 18:6a4db94011d3 712
sahilmgandhi 18:6a4db94011d3 713 /** \brief Get Pending Interrupt
sahilmgandhi 18:6a4db94011d3 714
sahilmgandhi 18:6a4db94011d3 715 The function reads the pending register in the NVIC and returns the pending bit
sahilmgandhi 18:6a4db94011d3 716 for the specified interrupt.
sahilmgandhi 18:6a4db94011d3 717
sahilmgandhi 18:6a4db94011d3 718 \param [in] IRQn Interrupt number.
sahilmgandhi 18:6a4db94011d3 719
sahilmgandhi 18:6a4db94011d3 720 \return 0 Interrupt status is not pending.
sahilmgandhi 18:6a4db94011d3 721 \return 1 Interrupt status is pending.
sahilmgandhi 18:6a4db94011d3 722 */
sahilmgandhi 18:6a4db94011d3 723 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
sahilmgandhi 18:6a4db94011d3 724 {
sahilmgandhi 18:6a4db94011d3 725 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
sahilmgandhi 18:6a4db94011d3 726 }
sahilmgandhi 18:6a4db94011d3 727
sahilmgandhi 18:6a4db94011d3 728
sahilmgandhi 18:6a4db94011d3 729 /** \brief Set Pending Interrupt
sahilmgandhi 18:6a4db94011d3 730
sahilmgandhi 18:6a4db94011d3 731 The function sets the pending bit of an external interrupt.
sahilmgandhi 18:6a4db94011d3 732
sahilmgandhi 18:6a4db94011d3 733 \param [in] IRQn Interrupt number. Value cannot be negative.
sahilmgandhi 18:6a4db94011d3 734 */
sahilmgandhi 18:6a4db94011d3 735 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
sahilmgandhi 18:6a4db94011d3 736 {
sahilmgandhi 18:6a4db94011d3 737 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
sahilmgandhi 18:6a4db94011d3 738 }
sahilmgandhi 18:6a4db94011d3 739
sahilmgandhi 18:6a4db94011d3 740
sahilmgandhi 18:6a4db94011d3 741 /** \brief Clear Pending Interrupt
sahilmgandhi 18:6a4db94011d3 742
sahilmgandhi 18:6a4db94011d3 743 The function clears the pending bit of an external interrupt.
sahilmgandhi 18:6a4db94011d3 744
sahilmgandhi 18:6a4db94011d3 745 \param [in] IRQn External interrupt number. Value cannot be negative.
sahilmgandhi 18:6a4db94011d3 746 */
sahilmgandhi 18:6a4db94011d3 747 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
sahilmgandhi 18:6a4db94011d3 748 {
sahilmgandhi 18:6a4db94011d3 749 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
sahilmgandhi 18:6a4db94011d3 750 }
sahilmgandhi 18:6a4db94011d3 751
sahilmgandhi 18:6a4db94011d3 752
sahilmgandhi 18:6a4db94011d3 753 /** \brief Set Interrupt Priority
sahilmgandhi 18:6a4db94011d3 754
sahilmgandhi 18:6a4db94011d3 755 The function sets the priority of an interrupt.
sahilmgandhi 18:6a4db94011d3 756
sahilmgandhi 18:6a4db94011d3 757 \note The priority cannot be set for every core interrupt.
sahilmgandhi 18:6a4db94011d3 758
sahilmgandhi 18:6a4db94011d3 759 \param [in] IRQn Interrupt number.
sahilmgandhi 18:6a4db94011d3 760 \param [in] priority Priority to set.
sahilmgandhi 18:6a4db94011d3 761 */
sahilmgandhi 18:6a4db94011d3 762 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
sahilmgandhi 18:6a4db94011d3 763 {
sahilmgandhi 18:6a4db94011d3 764 if((int32_t)(IRQn) < 0) {
sahilmgandhi 18:6a4db94011d3 765 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
sahilmgandhi 18:6a4db94011d3 766 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
sahilmgandhi 18:6a4db94011d3 767 }
sahilmgandhi 18:6a4db94011d3 768 else {
sahilmgandhi 18:6a4db94011d3 769 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
sahilmgandhi 18:6a4db94011d3 770 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
sahilmgandhi 18:6a4db94011d3 771 }
sahilmgandhi 18:6a4db94011d3 772 }
sahilmgandhi 18:6a4db94011d3 773
sahilmgandhi 18:6a4db94011d3 774
sahilmgandhi 18:6a4db94011d3 775 /** \brief Get Interrupt Priority
sahilmgandhi 18:6a4db94011d3 776
sahilmgandhi 18:6a4db94011d3 777 The function reads the priority of an interrupt. The interrupt
sahilmgandhi 18:6a4db94011d3 778 number can be positive to specify an external (device specific)
sahilmgandhi 18:6a4db94011d3 779 interrupt, or negative to specify an internal (core) interrupt.
sahilmgandhi 18:6a4db94011d3 780
sahilmgandhi 18:6a4db94011d3 781
sahilmgandhi 18:6a4db94011d3 782 \param [in] IRQn Interrupt number.
sahilmgandhi 18:6a4db94011d3 783 \return Interrupt Priority. Value is aligned automatically to the implemented
sahilmgandhi 18:6a4db94011d3 784 priority bits of the microcontroller.
sahilmgandhi 18:6a4db94011d3 785 */
sahilmgandhi 18:6a4db94011d3 786 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
sahilmgandhi 18:6a4db94011d3 787 {
sahilmgandhi 18:6a4db94011d3 788
sahilmgandhi 18:6a4db94011d3 789 if((int32_t)(IRQn) < 0) {
sahilmgandhi 18:6a4db94011d3 790 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
sahilmgandhi 18:6a4db94011d3 791 }
sahilmgandhi 18:6a4db94011d3 792 else {
sahilmgandhi 18:6a4db94011d3 793 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
sahilmgandhi 18:6a4db94011d3 794 }
sahilmgandhi 18:6a4db94011d3 795 }
sahilmgandhi 18:6a4db94011d3 796
sahilmgandhi 18:6a4db94011d3 797
sahilmgandhi 18:6a4db94011d3 798 /** \brief System Reset
sahilmgandhi 18:6a4db94011d3 799
sahilmgandhi 18:6a4db94011d3 800 The function initiates a system reset request to reset the MCU.
sahilmgandhi 18:6a4db94011d3 801 */
sahilmgandhi 18:6a4db94011d3 802 __STATIC_INLINE void NVIC_SystemReset(void)
sahilmgandhi 18:6a4db94011d3 803 {
sahilmgandhi 18:6a4db94011d3 804 __DSB(); /* Ensure all outstanding memory accesses included
sahilmgandhi 18:6a4db94011d3 805 buffered write are completed before reset */
sahilmgandhi 18:6a4db94011d3 806 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
sahilmgandhi 18:6a4db94011d3 807 SCB_AIRCR_SYSRESETREQ_Msk);
sahilmgandhi 18:6a4db94011d3 808 __DSB(); /* Ensure completion of memory access */
sahilmgandhi 18:6a4db94011d3 809 while(1) { __NOP(); } /* wait until reset */
sahilmgandhi 18:6a4db94011d3 810 }
sahilmgandhi 18:6a4db94011d3 811
sahilmgandhi 18:6a4db94011d3 812 /*@} end of CMSIS_Core_NVICFunctions */
sahilmgandhi 18:6a4db94011d3 813
sahilmgandhi 18:6a4db94011d3 814
sahilmgandhi 18:6a4db94011d3 815
sahilmgandhi 18:6a4db94011d3 816 /* ################################## SysTick function ############################################ */
sahilmgandhi 18:6a4db94011d3 817 /** \ingroup CMSIS_Core_FunctionInterface
sahilmgandhi 18:6a4db94011d3 818 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
sahilmgandhi 18:6a4db94011d3 819 \brief Functions that configure the System.
sahilmgandhi 18:6a4db94011d3 820 @{
sahilmgandhi 18:6a4db94011d3 821 */
sahilmgandhi 18:6a4db94011d3 822
sahilmgandhi 18:6a4db94011d3 823 #if (__Vendor_SysTickConfig == 0)
sahilmgandhi 18:6a4db94011d3 824
sahilmgandhi 18:6a4db94011d3 825 /** \brief System Tick Configuration
sahilmgandhi 18:6a4db94011d3 826
sahilmgandhi 18:6a4db94011d3 827 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
sahilmgandhi 18:6a4db94011d3 828 Counter is in free running mode to generate periodic interrupts.
sahilmgandhi 18:6a4db94011d3 829
sahilmgandhi 18:6a4db94011d3 830 \param [in] ticks Number of ticks between two interrupts.
sahilmgandhi 18:6a4db94011d3 831
sahilmgandhi 18:6a4db94011d3 832 \return 0 Function succeeded.
sahilmgandhi 18:6a4db94011d3 833 \return 1 Function failed.
sahilmgandhi 18:6a4db94011d3 834
sahilmgandhi 18:6a4db94011d3 835 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
sahilmgandhi 18:6a4db94011d3 836 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
sahilmgandhi 18:6a4db94011d3 837 must contain a vendor-specific implementation of this function.
sahilmgandhi 18:6a4db94011d3 838
sahilmgandhi 18:6a4db94011d3 839 */
sahilmgandhi 18:6a4db94011d3 840 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
sahilmgandhi 18:6a4db94011d3 841 {
sahilmgandhi 18:6a4db94011d3 842 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */
sahilmgandhi 18:6a4db94011d3 843
sahilmgandhi 18:6a4db94011d3 844 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
sahilmgandhi 18:6a4db94011d3 845 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
sahilmgandhi 18:6a4db94011d3 846 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
sahilmgandhi 18:6a4db94011d3 847 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
sahilmgandhi 18:6a4db94011d3 848 SysTick_CTRL_TICKINT_Msk |
sahilmgandhi 18:6a4db94011d3 849 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
sahilmgandhi 18:6a4db94011d3 850 return (0UL); /* Function successful */
sahilmgandhi 18:6a4db94011d3 851 }
sahilmgandhi 18:6a4db94011d3 852
sahilmgandhi 18:6a4db94011d3 853 #endif
sahilmgandhi 18:6a4db94011d3 854
sahilmgandhi 18:6a4db94011d3 855 /*@} end of CMSIS_Core_SysTickFunctions */
sahilmgandhi 18:6a4db94011d3 856
sahilmgandhi 18:6a4db94011d3 857
sahilmgandhi 18:6a4db94011d3 858
sahilmgandhi 18:6a4db94011d3 859
sahilmgandhi 18:6a4db94011d3 860 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 861 }
sahilmgandhi 18:6a4db94011d3 862 #endif
sahilmgandhi 18:6a4db94011d3 863
sahilmgandhi 18:6a4db94011d3 864 #endif /* __CORE_SC000_H_DEPENDANT */
sahilmgandhi 18:6a4db94011d3 865
sahilmgandhi 18:6a4db94011d3 866 #endif /* __CMSIS_GENERIC */