MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/cmsis/core_cm4_simd.h@29:ec2c5a69acd6, 2017-05-24 (annotated)

Committer:
sahilmgandhi
Date:
Wed May 24 01:57:01 2017 +0000
Revision:
29:ec2c5a69acd6
Parent:
18:6a4db94011d3 
Need to change ir2-ir3 to now be ir1 - ir4

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 2 * @file core_cm4_simd.h
sahilmgandhi 18:6a4db94011d3 3 * @brief CMSIS Cortex-M4 SIMD Header File
sahilmgandhi 18:6a4db94011d3 4 * @version V3.20
sahilmgandhi 18:6a4db94011d3 5 * @date 25. February 2013
sahilmgandhi 18:6a4db94011d3 6 *
sahilmgandhi 18:6a4db94011d3 7 * @note
sahilmgandhi 18:6a4db94011d3 8 *
sahilmgandhi 18:6a4db94011d3 9 ******************************************************************************/
sahilmgandhi 18:6a4db94011d3 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
sahilmgandhi 18:6a4db94011d3 11
sahilmgandhi 18:6a4db94011d3 12 All rights reserved.
sahilmgandhi 18:6a4db94011d3 13 Redistribution and use in source and binary forms, with or without
sahilmgandhi 18:6a4db94011d3 14 modification, are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 15 - Redistributions of source code must retain the above copyright
sahilmgandhi 18:6a4db94011d3 16 notice, this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 17 - Redistributions in binary form must reproduce the above copyright
sahilmgandhi 18:6a4db94011d3 18 notice, this list of conditions and the following disclaimer in the
sahilmgandhi 18:6a4db94011d3 19 documentation and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 20 - Neither the name of ARM nor the names of its contributors may be used
sahilmgandhi 18:6a4db94011d3 21 to endorse or promote products derived from this software without
sahilmgandhi 18:6a4db94011d3 22 specific prior written permission.
sahilmgandhi 18:6a4db94011d3 23 *
sahilmgandhi 18:6a4db94011d3 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
sahilmgandhi 18:6a4db94011d3 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
sahilmgandhi 18:6a4db94011d3 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
sahilmgandhi 18:6a4db94011d3 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
sahilmgandhi 18:6a4db94011d3 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
sahilmgandhi 18:6a4db94011d3 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
sahilmgandhi 18:6a4db94011d3 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
sahilmgandhi 18:6a4db94011d3 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
sahilmgandhi 18:6a4db94011d3 34 POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 35 ---------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 36
sahilmgandhi 18:6a4db94011d3 37
sahilmgandhi 18:6a4db94011d3 38 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 39 extern "C" {
sahilmgandhi 18:6a4db94011d3 40 #endif
sahilmgandhi 18:6a4db94011d3 41
sahilmgandhi 18:6a4db94011d3 42 #ifndef __CORE_CM4_SIMD_H
sahilmgandhi 18:6a4db94011d3 43 #define __CORE_CM4_SIMD_H
sahilmgandhi 18:6a4db94011d3 44
sahilmgandhi 18:6a4db94011d3 45
sahilmgandhi 18:6a4db94011d3 46 /*******************************************************************************
sahilmgandhi 18:6a4db94011d3 47 * Hardware Abstraction Layer
sahilmgandhi 18:6a4db94011d3 48 ******************************************************************************/
sahilmgandhi 18:6a4db94011d3 49
sahilmgandhi 18:6a4db94011d3 50
sahilmgandhi 18:6a4db94011d3 51 /* ################### Compiler specific Intrinsics ########################### */
sahilmgandhi 18:6a4db94011d3 52 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
sahilmgandhi 18:6a4db94011d3 53 Access to dedicated SIMD instructions
sahilmgandhi 18:6a4db94011d3 54 @{
sahilmgandhi 18:6a4db94011d3 55 */
sahilmgandhi 18:6a4db94011d3 56
sahilmgandhi 18:6a4db94011d3 57 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
sahilmgandhi 18:6a4db94011d3 58 /* ARM armcc specific functions */
sahilmgandhi 18:6a4db94011d3 59
sahilmgandhi 18:6a4db94011d3 60 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 61 #define __SADD8 __sadd8
sahilmgandhi 18:6a4db94011d3 62 #define __QADD8 __qadd8
sahilmgandhi 18:6a4db94011d3 63 #define __SHADD8 __shadd8
sahilmgandhi 18:6a4db94011d3 64 #define __UADD8 __uadd8
sahilmgandhi 18:6a4db94011d3 65 #define __UQADD8 __uqadd8
sahilmgandhi 18:6a4db94011d3 66 #define __UHADD8 __uhadd8
sahilmgandhi 18:6a4db94011d3 67 #define __SSUB8 __ssub8
sahilmgandhi 18:6a4db94011d3 68 #define __QSUB8 __qsub8
sahilmgandhi 18:6a4db94011d3 69 #define __SHSUB8 __shsub8
sahilmgandhi 18:6a4db94011d3 70 #define __USUB8 __usub8
sahilmgandhi 18:6a4db94011d3 71 #define __UQSUB8 __uqsub8
sahilmgandhi 18:6a4db94011d3 72 #define __UHSUB8 __uhsub8
sahilmgandhi 18:6a4db94011d3 73 #define __SADD16 __sadd16
sahilmgandhi 18:6a4db94011d3 74 #define __QADD16 __qadd16
sahilmgandhi 18:6a4db94011d3 75 #define __SHADD16 __shadd16
sahilmgandhi 18:6a4db94011d3 76 #define __UADD16 __uadd16
sahilmgandhi 18:6a4db94011d3 77 #define __UQADD16 __uqadd16
sahilmgandhi 18:6a4db94011d3 78 #define __UHADD16 __uhadd16
sahilmgandhi 18:6a4db94011d3 79 #define __SSUB16 __ssub16
sahilmgandhi 18:6a4db94011d3 80 #define __QSUB16 __qsub16
sahilmgandhi 18:6a4db94011d3 81 #define __SHSUB16 __shsub16
sahilmgandhi 18:6a4db94011d3 82 #define __USUB16 __usub16
sahilmgandhi 18:6a4db94011d3 83 #define __UQSUB16 __uqsub16
sahilmgandhi 18:6a4db94011d3 84 #define __UHSUB16 __uhsub16
sahilmgandhi 18:6a4db94011d3 85 #define __SASX __sasx
sahilmgandhi 18:6a4db94011d3 86 #define __QASX __qasx
sahilmgandhi 18:6a4db94011d3 87 #define __SHASX __shasx
sahilmgandhi 18:6a4db94011d3 88 #define __UASX __uasx
sahilmgandhi 18:6a4db94011d3 89 #define __UQASX __uqasx
sahilmgandhi 18:6a4db94011d3 90 #define __UHASX __uhasx
sahilmgandhi 18:6a4db94011d3 91 #define __SSAX __ssax
sahilmgandhi 18:6a4db94011d3 92 #define __QSAX __qsax
sahilmgandhi 18:6a4db94011d3 93 #define __SHSAX __shsax
sahilmgandhi 18:6a4db94011d3 94 #define __USAX __usax
sahilmgandhi 18:6a4db94011d3 95 #define __UQSAX __uqsax
sahilmgandhi 18:6a4db94011d3 96 #define __UHSAX __uhsax
sahilmgandhi 18:6a4db94011d3 97 #define __USAD8 __usad8
sahilmgandhi 18:6a4db94011d3 98 #define __USADA8 __usada8
sahilmgandhi 18:6a4db94011d3 99 #define __SSAT16 __ssat16
sahilmgandhi 18:6a4db94011d3 100 #define __USAT16 __usat16
sahilmgandhi 18:6a4db94011d3 101 #define __UXTB16 __uxtb16
sahilmgandhi 18:6a4db94011d3 102 #define __UXTAB16 __uxtab16
sahilmgandhi 18:6a4db94011d3 103 #define __SXTB16 __sxtb16
sahilmgandhi 18:6a4db94011d3 104 #define __SXTAB16 __sxtab16
sahilmgandhi 18:6a4db94011d3 105 #define __SMUAD __smuad
sahilmgandhi 18:6a4db94011d3 106 #define __SMUADX __smuadx
sahilmgandhi 18:6a4db94011d3 107 #define __SMLAD __smlad
sahilmgandhi 18:6a4db94011d3 108 #define __SMLADX __smladx
sahilmgandhi 18:6a4db94011d3 109 #define __SMLALD __smlald
sahilmgandhi 18:6a4db94011d3 110 #define __SMLALDX __smlaldx
sahilmgandhi 18:6a4db94011d3 111 #define __SMUSD __smusd
sahilmgandhi 18:6a4db94011d3 112 #define __SMUSDX __smusdx
sahilmgandhi 18:6a4db94011d3 113 #define __SMLSD __smlsd
sahilmgandhi 18:6a4db94011d3 114 #define __SMLSDX __smlsdx
sahilmgandhi 18:6a4db94011d3 115 #define __SMLSLD __smlsld
sahilmgandhi 18:6a4db94011d3 116 #define __SMLSLDX __smlsldx
sahilmgandhi 18:6a4db94011d3 117 #define __SEL __sel
sahilmgandhi 18:6a4db94011d3 118 #define __QADD __qadd
sahilmgandhi 18:6a4db94011d3 119 #define __QSUB __qsub
sahilmgandhi 18:6a4db94011d3 120
sahilmgandhi 18:6a4db94011d3 121 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
sahilmgandhi 18:6a4db94011d3 122 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
sahilmgandhi 18:6a4db94011d3 123
sahilmgandhi 18:6a4db94011d3 124 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
sahilmgandhi 18:6a4db94011d3 125 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
sahilmgandhi 18:6a4db94011d3 126
sahilmgandhi 18:6a4db94011d3 127 #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
sahilmgandhi 18:6a4db94011d3 128 ((int64_t)(ARG3) << 32) ) >> 32))
sahilmgandhi 18:6a4db94011d3 129
sahilmgandhi 18:6a4db94011d3 130 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 131
sahilmgandhi 18:6a4db94011d3 132
sahilmgandhi 18:6a4db94011d3 133
sahilmgandhi 18:6a4db94011d3 134 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
sahilmgandhi 18:6a4db94011d3 135 /* IAR iccarm specific functions */
sahilmgandhi 18:6a4db94011d3 136
sahilmgandhi 18:6a4db94011d3 137 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 138 #include <cmsis_iar.h>
sahilmgandhi 18:6a4db94011d3 139
sahilmgandhi 18:6a4db94011d3 140 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 141
sahilmgandhi 18:6a4db94011d3 142
sahilmgandhi 18:6a4db94011d3 143
sahilmgandhi 18:6a4db94011d3 144 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
sahilmgandhi 18:6a4db94011d3 145 /* TI CCS specific functions */
sahilmgandhi 18:6a4db94011d3 146
sahilmgandhi 18:6a4db94011d3 147 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 148 #include <cmsis_ccs.h>
sahilmgandhi 18:6a4db94011d3 149
sahilmgandhi 18:6a4db94011d3 150 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 151
sahilmgandhi 18:6a4db94011d3 152
sahilmgandhi 18:6a4db94011d3 153
sahilmgandhi 18:6a4db94011d3 154 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
sahilmgandhi 18:6a4db94011d3 155 /* GNU gcc specific functions */
sahilmgandhi 18:6a4db94011d3 156
sahilmgandhi 18:6a4db94011d3 157 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 158 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
sahilmgandhi 18:6a4db94011d3 159 {
sahilmgandhi 18:6a4db94011d3 160 uint32_t result;
sahilmgandhi 18:6a4db94011d3 161
sahilmgandhi 18:6a4db94011d3 162 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sahilmgandhi 18:6a4db94011d3 163 return(result);
sahilmgandhi 18:6a4db94011d3 164 }
sahilmgandhi 18:6a4db94011d3 165
sahilmgandhi 18:6a4db94011d3 166 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
sahilmgandhi 18:6a4db94011d3 167 {
sahilmgandhi 18:6a4db94011d3 168 uint32_t result;
sahilmgandhi 18:6a4db94011d3 169
sahilmgandhi 18:6a4db94011d3 170 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sahilmgandhi 18:6a4db94011d3 171 return(result);
sahilmgandhi 18:6a4db94011d3 172 }
sahilmgandhi 18:6a4db94011d3 173
sahilmgandhi 18:6a4db94011d3 174 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
sahilmgandhi 18:6a4db94011d3 175 {
sahilmgandhi 18:6a4db94011d3 176 uint32_t result;
sahilmgandhi 18:6a4db94011d3 177
sahilmgandhi 18:6a4db94011d3 178 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sahilmgandhi 18:6a4db94011d3 179 return(result);
sahilmgandhi 18:6a4db94011d3 180 }
sahilmgandhi 18:6a4db94011d3 181
sahilmgandhi 18:6a4db94011d3 182 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
sahilmgandhi 18:6a4db94011d3 183 {
sahilmgandhi 18:6a4db94011d3 184 uint32_t result;
sahilmgandhi 18:6a4db94011d3 185
sahilmgandhi 18:6a4db94011d3 186 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sahilmgandhi 18:6a4db94011d3 187 return(result);
sahilmgandhi 18:6a4db94011d3 188 }
sahilmgandhi 18:6a4db94011d3 189
sahilmgandhi 18:6a4db94011d3 190 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
sahilmgandhi 18:6a4db94011d3 191 {
sahilmgandhi 18:6a4db94011d3 192 uint32_t result;
sahilmgandhi 18:6a4db94011d3 193
sahilmgandhi 18:6a4db94011d3 194 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sahilmgandhi 18:6a4db94011d3 195 return(result);
sahilmgandhi 18:6a4db94011d3 196 }
sahilmgandhi 18:6a4db94011d3 197
sahilmgandhi 18:6a4db94011d3 198 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
sahilmgandhi 18:6a4db94011d3 199 {
sahilmgandhi 18:6a4db94011d3 200 uint32_t result;
sahilmgandhi 18:6a4db94011d3 201
sahilmgandhi 18:6a4db94011d3 202 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sahilmgandhi 18:6a4db94011d3 203 return(result);
sahilmgandhi 18:6a4db94011d3 204 }
sahilmgandhi 18:6a4db94011d3 205
sahilmgandhi 18:6a4db94011d3 206
sahilmgandhi 18:6a4db94011d3 207 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
sahilmgandhi 18:6a4db94011d3 208 {
sahilmgandhi 18:6a4db94011d3 209 uint32_t result;
sahilmgandhi 18:6a4db94011d3 210
sahilmgandhi 18:6a4db94011d3 211 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sahilmgandhi 18:6a4db94011d3 212 return(result);
sahilmgandhi 18:6a4db94011d3 213 }
sahilmgandhi 18:6a4db94011d3 214
sahilmgandhi 18:6a4db94011d3 215 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
sahilmgandhi 18:6a4db94011d3 216 {
sahilmgandhi 18:6a4db94011d3 217 uint32_t result;
sahilmgandhi 18:6a4db94011d3 218
sahilmgandhi 18:6a4db94011d3 219 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sahilmgandhi 18:6a4db94011d3 220 return(result);
sahilmgandhi 18:6a4db94011d3 221 }
sahilmgandhi 18:6a4db94011d3 222
sahilmgandhi 18:6a4db94011d3 223 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
sahilmgandhi 18:6a4db94011d3 224 {
sahilmgandhi 18:6a4db94011d3 225 uint32_t result;
sahilmgandhi 18:6a4db94011d3 226
sahilmgandhi 18:6a4db94011d3 227 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sahilmgandhi 18:6a4db94011d3 228 return(result);
sahilmgandhi 18:6a4db94011d3 229 }
sahilmgandhi 18:6a4db94011d3 230
sahilmgandhi 18:6a4db94011d3 231 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
sahilmgandhi 18:6a4db94011d3 232 {
sahilmgandhi 18:6a4db94011d3 233 uint32_t result;
sahilmgandhi 18:6a4db94011d3 234
sahilmgandhi 18:6a4db94011d3 235 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sahilmgandhi 18:6a4db94011d3 236 return(result);
sahilmgandhi 18:6a4db94011d3 237 }
sahilmgandhi 18:6a4db94011d3 238
sahilmgandhi 18:6a4db94011d3 239 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
sahilmgandhi 18:6a4db94011d3 240 {
sahilmgandhi 18:6a4db94011d3 241 uint32_t result;
sahilmgandhi 18:6a4db94011d3 242
sahilmgandhi 18:6a4db94011d3 243 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sahilmgandhi 18:6a4db94011d3 244 return(result);
sahilmgandhi 18:6a4db94011d3 245 }
sahilmgandhi 18:6a4db94011d3 246
sahilmgandhi 18:6a4db94011d3 247 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
sahilmgandhi 18:6a4db94011d3 248 {
sahilmgandhi 18:6a4db94011d3 249 uint32_t result;
sahilmgandhi 18:6a4db94011d3 250
sahilmgandhi 18:6a4db94011d3 251 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sahilmgandhi 18:6a4db94011d3 252 return(result);
sahilmgandhi 18:6a4db94011d3 253 }
sahilmgandhi 18:6a4db94011d3 254
sahilmgandhi 18:6a4db94011d3 255
sahilmgandhi 18:6a4db94011d3 256 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
sahilmgandhi 18:6a4db94011d3 257 {
sahilmgandhi 18:6a4db94011d3 258 uint32_t result;
sahilmgandhi 18:6a4db94011d3 259
sahilmgandhi 18:6a4db94011d3 260 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sahilmgandhi 18:6a4db94011d3 261 return(result);
sahilmgandhi 18:6a4db94011d3 262 }
sahilmgandhi 18:6a4db94011d3 263
sahilmgandhi 18:6a4db94011d3 264 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
sahilmgandhi 18:6a4db94011d3 265 {
sahilmgandhi 18:6a4db94011d3 266 uint32_t result;
sahilmgandhi 18:6a4db94011d3 267
sahilmgandhi 18:6a4db94011d3 268 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sahilmgandhi 18:6a4db94011d3 269 return(result);
sahilmgandhi 18:6a4db94011d3 270 }
sahilmgandhi 18:6a4db94011d3 271
sahilmgandhi 18:6a4db94011d3 272 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
sahilmgandhi 18:6a4db94011d3 273 {
sahilmgandhi 18:6a4db94011d3 274 uint32_t result;
sahilmgandhi 18:6a4db94011d3 275
sahilmgandhi 18:6a4db94011d3 276 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sahilmgandhi 18:6a4db94011d3 277 return(result);
sahilmgandhi 18:6a4db94011d3 278 }
sahilmgandhi 18:6a4db94011d3 279
sahilmgandhi 18:6a4db94011d3 280 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
sahilmgandhi 18:6a4db94011d3 281 {
sahilmgandhi 18:6a4db94011d3 282 uint32_t result;
sahilmgandhi 18:6a4db94011d3 283
sahilmgandhi 18:6a4db94011d3 284 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sahilmgandhi 18:6a4db94011d3 285 return(result);
sahilmgandhi 18:6a4db94011d3 286 }
sahilmgandhi 18:6a4db94011d3 287
sahilmgandhi 18:6a4db94011d3 288 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
sahilmgandhi 18:6a4db94011d3 289 {
sahilmgandhi 18:6a4db94011d3 290 uint32_t result;
sahilmgandhi 18:6a4db94011d3 291
sahilmgandhi 18:6a4db94011d3 292 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sahilmgandhi 18:6a4db94011d3 293 return(result);
sahilmgandhi 18:6a4db94011d3 294 }
sahilmgandhi 18:6a4db94011d3 295
sahilmgandhi 18:6a4db94011d3 296 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
sahilmgandhi 18:6a4db94011d3 297 {
sahilmgandhi 18:6a4db94011d3 298 uint32_t result;
sahilmgandhi 18:6a4db94011d3 299
sahilmgandhi 18:6a4db94011d3 300 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sahilmgandhi 18:6a4db94011d3 301 return(result);
sahilmgandhi 18:6a4db94011d3 302 }
sahilmgandhi 18:6a4db94011d3 303
sahilmgandhi 18:6a4db94011d3 304 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
sahilmgandhi 18:6a4db94011d3 305 {
sahilmgandhi 18:6a4db94011d3 306 uint32_t result;
sahilmgandhi 18:6a4db94011d3 307
sahilmgandhi 18:6a4db94011d3 308 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sahilmgandhi 18:6a4db94011d3 309 return(result);
sahilmgandhi 18:6a4db94011d3 310 }
sahilmgandhi 18:6a4db94011d3 311
sahilmgandhi 18:6a4db94011d3 312 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
sahilmgandhi 18:6a4db94011d3 313 {
sahilmgandhi 18:6a4db94011d3 314 uint32_t result;
sahilmgandhi 18:6a4db94011d3 315
sahilmgandhi 18:6a4db94011d3 316 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sahilmgandhi 18:6a4db94011d3 317 return(result);
sahilmgandhi 18:6a4db94011d3 318 }
sahilmgandhi 18:6a4db94011d3 319
sahilmgandhi 18:6a4db94011d3 320 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
sahilmgandhi 18:6a4db94011d3 321 {
sahilmgandhi 18:6a4db94011d3 322 uint32_t result;
sahilmgandhi 18:6a4db94011d3 323
sahilmgandhi 18:6a4db94011d3 324 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sahilmgandhi 18:6a4db94011d3 325 return(result);
sahilmgandhi 18:6a4db94011d3 326 }
sahilmgandhi 18:6a4db94011d3 327
sahilmgandhi 18:6a4db94011d3 328 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
sahilmgandhi 18:6a4db94011d3 329 {
sahilmgandhi 18:6a4db94011d3 330 uint32_t result;
sahilmgandhi 18:6a4db94011d3 331
sahilmgandhi 18:6a4db94011d3 332 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sahilmgandhi 18:6a4db94011d3 333 return(result);
sahilmgandhi 18:6a4db94011d3 334 }
sahilmgandhi 18:6a4db94011d3 335
sahilmgandhi 18:6a4db94011d3 336 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
sahilmgandhi 18:6a4db94011d3 337 {
sahilmgandhi 18:6a4db94011d3 338 uint32_t result;
sahilmgandhi 18:6a4db94011d3 339
sahilmgandhi 18:6a4db94011d3 340 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sahilmgandhi 18:6a4db94011d3 341 return(result);
sahilmgandhi 18:6a4db94011d3 342 }
sahilmgandhi 18:6a4db94011d3 343
sahilmgandhi 18:6a4db94011d3 344 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
sahilmgandhi 18:6a4db94011d3 345 {
sahilmgandhi 18:6a4db94011d3 346 uint32_t result;
sahilmgandhi 18:6a4db94011d3 347
sahilmgandhi 18:6a4db94011d3 348 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sahilmgandhi 18:6a4db94011d3 349 return(result);
sahilmgandhi 18:6a4db94011d3 350 }
sahilmgandhi 18:6a4db94011d3 351
sahilmgandhi 18:6a4db94011d3 352 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
sahilmgandhi 18:6a4db94011d3 353 {
sahilmgandhi 18:6a4db94011d3 354 uint32_t result;
sahilmgandhi 18:6a4db94011d3 355
sahilmgandhi 18:6a4db94011d3 356 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sahilmgandhi 18:6a4db94011d3 357 return(result);
sahilmgandhi 18:6a4db94011d3 358 }
sahilmgandhi 18:6a4db94011d3 359
sahilmgandhi 18:6a4db94011d3 360 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
sahilmgandhi 18:6a4db94011d3 361 {
sahilmgandhi 18:6a4db94011d3 362 uint32_t result;
sahilmgandhi 18:6a4db94011d3 363
sahilmgandhi 18:6a4db94011d3 364 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sahilmgandhi 18:6a4db94011d3 365 return(result);
sahilmgandhi 18:6a4db94011d3 366 }
sahilmgandhi 18:6a4db94011d3 367
sahilmgandhi 18:6a4db94011d3 368 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
sahilmgandhi 18:6a4db94011d3 369 {
sahilmgandhi 18:6a4db94011d3 370 uint32_t result;
sahilmgandhi 18:6a4db94011d3 371
sahilmgandhi 18:6a4db94011d3 372 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sahilmgandhi 18:6a4db94011d3 373 return(result);
sahilmgandhi 18:6a4db94011d3 374 }
sahilmgandhi 18:6a4db94011d3 375
sahilmgandhi 18:6a4db94011d3 376 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
sahilmgandhi 18:6a4db94011d3 377 {
sahilmgandhi 18:6a4db94011d3 378 uint32_t result;
sahilmgandhi 18:6a4db94011d3 379
sahilmgandhi 18:6a4db94011d3 380 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sahilmgandhi 18:6a4db94011d3 381 return(result);
sahilmgandhi 18:6a4db94011d3 382 }
sahilmgandhi 18:6a4db94011d3 383
sahilmgandhi 18:6a4db94011d3 384 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
sahilmgandhi 18:6a4db94011d3 385 {
sahilmgandhi 18:6a4db94011d3 386 uint32_t result;
sahilmgandhi 18:6a4db94011d3 387
sahilmgandhi 18:6a4db94011d3 388 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sahilmgandhi 18:6a4db94011d3 389 return(result);
sahilmgandhi 18:6a4db94011d3 390 }
sahilmgandhi 18:6a4db94011d3 391
sahilmgandhi 18:6a4db94011d3 392 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
sahilmgandhi 18:6a4db94011d3 393 {
sahilmgandhi 18:6a4db94011d3 394 uint32_t result;
sahilmgandhi 18:6a4db94011d3 395
sahilmgandhi 18:6a4db94011d3 396 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sahilmgandhi 18:6a4db94011d3 397 return(result);
sahilmgandhi 18:6a4db94011d3 398 }
sahilmgandhi 18:6a4db94011d3 399
sahilmgandhi 18:6a4db94011d3 400 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
sahilmgandhi 18:6a4db94011d3 401 {
sahilmgandhi 18:6a4db94011d3 402 uint32_t result;
sahilmgandhi 18:6a4db94011d3 403
sahilmgandhi 18:6a4db94011d3 404 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sahilmgandhi 18:6a4db94011d3 405 return(result);
sahilmgandhi 18:6a4db94011d3 406 }
sahilmgandhi 18:6a4db94011d3 407
sahilmgandhi 18:6a4db94011d3 408 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
sahilmgandhi 18:6a4db94011d3 409 {
sahilmgandhi 18:6a4db94011d3 410 uint32_t result;
sahilmgandhi 18:6a4db94011d3 411
sahilmgandhi 18:6a4db94011d3 412 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sahilmgandhi 18:6a4db94011d3 413 return(result);
sahilmgandhi 18:6a4db94011d3 414 }
sahilmgandhi 18:6a4db94011d3 415
sahilmgandhi 18:6a4db94011d3 416 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
sahilmgandhi 18:6a4db94011d3 417 {
sahilmgandhi 18:6a4db94011d3 418 uint32_t result;
sahilmgandhi 18:6a4db94011d3 419
sahilmgandhi 18:6a4db94011d3 420 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sahilmgandhi 18:6a4db94011d3 421 return(result);
sahilmgandhi 18:6a4db94011d3 422 }
sahilmgandhi 18:6a4db94011d3 423
sahilmgandhi 18:6a4db94011d3 424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
sahilmgandhi 18:6a4db94011d3 425 {
sahilmgandhi 18:6a4db94011d3 426 uint32_t result;
sahilmgandhi 18:6a4db94011d3 427
sahilmgandhi 18:6a4db94011d3 428 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sahilmgandhi 18:6a4db94011d3 429 return(result);
sahilmgandhi 18:6a4db94011d3 430 }
sahilmgandhi 18:6a4db94011d3 431
sahilmgandhi 18:6a4db94011d3 432 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
sahilmgandhi 18:6a4db94011d3 433 {
sahilmgandhi 18:6a4db94011d3 434 uint32_t result;
sahilmgandhi 18:6a4db94011d3 435
sahilmgandhi 18:6a4db94011d3 436 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sahilmgandhi 18:6a4db94011d3 437 return(result);
sahilmgandhi 18:6a4db94011d3 438 }
sahilmgandhi 18:6a4db94011d3 439
sahilmgandhi 18:6a4db94011d3 440 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
sahilmgandhi 18:6a4db94011d3 441 {
sahilmgandhi 18:6a4db94011d3 442 uint32_t result;
sahilmgandhi 18:6a4db94011d3 443
sahilmgandhi 18:6a4db94011d3 444 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sahilmgandhi 18:6a4db94011d3 445 return(result);
sahilmgandhi 18:6a4db94011d3 446 }
sahilmgandhi 18:6a4db94011d3 447
sahilmgandhi 18:6a4db94011d3 448 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
sahilmgandhi 18:6a4db94011d3 449 {
sahilmgandhi 18:6a4db94011d3 450 uint32_t result;
sahilmgandhi 18:6a4db94011d3 451
sahilmgandhi 18:6a4db94011d3 452 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sahilmgandhi 18:6a4db94011d3 453 return(result);
sahilmgandhi 18:6a4db94011d3 454 }
sahilmgandhi 18:6a4db94011d3 455
sahilmgandhi 18:6a4db94011d3 456 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
sahilmgandhi 18:6a4db94011d3 457 {
sahilmgandhi 18:6a4db94011d3 458 uint32_t result;
sahilmgandhi 18:6a4db94011d3 459
sahilmgandhi 18:6a4db94011d3 460 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
sahilmgandhi 18:6a4db94011d3 461 return(result);
sahilmgandhi 18:6a4db94011d3 462 }
sahilmgandhi 18:6a4db94011d3 463
sahilmgandhi 18:6a4db94011d3 464 #define __SSAT16(ARG1,ARG2) \
sahilmgandhi 18:6a4db94011d3 465 ({ \
sahilmgandhi 18:6a4db94011d3 466 uint32_t __RES, __ARG1 = (ARG1); \
sahilmgandhi 18:6a4db94011d3 467 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
sahilmgandhi 18:6a4db94011d3 468 __RES; \
sahilmgandhi 18:6a4db94011d3 469 })
sahilmgandhi 18:6a4db94011d3 470
sahilmgandhi 18:6a4db94011d3 471 #define __USAT16(ARG1,ARG2) \
sahilmgandhi 18:6a4db94011d3 472 ({ \
sahilmgandhi 18:6a4db94011d3 473 uint32_t __RES, __ARG1 = (ARG1); \
sahilmgandhi 18:6a4db94011d3 474 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
sahilmgandhi 18:6a4db94011d3 475 __RES; \
sahilmgandhi 18:6a4db94011d3 476 })
sahilmgandhi 18:6a4db94011d3 477
sahilmgandhi 18:6a4db94011d3 478 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
sahilmgandhi 18:6a4db94011d3 479 {
sahilmgandhi 18:6a4db94011d3 480 uint32_t result;
sahilmgandhi 18:6a4db94011d3 481
sahilmgandhi 18:6a4db94011d3 482 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
sahilmgandhi 18:6a4db94011d3 483 return(result);
sahilmgandhi 18:6a4db94011d3 484 }
sahilmgandhi 18:6a4db94011d3 485
sahilmgandhi 18:6a4db94011d3 486 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
sahilmgandhi 18:6a4db94011d3 487 {
sahilmgandhi 18:6a4db94011d3 488 uint32_t result;
sahilmgandhi 18:6a4db94011d3 489
sahilmgandhi 18:6a4db94011d3 490 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sahilmgandhi 18:6a4db94011d3 491 return(result);
sahilmgandhi 18:6a4db94011d3 492 }
sahilmgandhi 18:6a4db94011d3 493
sahilmgandhi 18:6a4db94011d3 494 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
sahilmgandhi 18:6a4db94011d3 495 {
sahilmgandhi 18:6a4db94011d3 496 uint32_t result;
sahilmgandhi 18:6a4db94011d3 497
sahilmgandhi 18:6a4db94011d3 498 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
sahilmgandhi 18:6a4db94011d3 499 return(result);
sahilmgandhi 18:6a4db94011d3 500 }
sahilmgandhi 18:6a4db94011d3 501
sahilmgandhi 18:6a4db94011d3 502 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
sahilmgandhi 18:6a4db94011d3 503 {
sahilmgandhi 18:6a4db94011d3 504 uint32_t result;
sahilmgandhi 18:6a4db94011d3 505
sahilmgandhi 18:6a4db94011d3 506 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sahilmgandhi 18:6a4db94011d3 507 return(result);
sahilmgandhi 18:6a4db94011d3 508 }
sahilmgandhi 18:6a4db94011d3 509
sahilmgandhi 18:6a4db94011d3 510 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
sahilmgandhi 18:6a4db94011d3 511 {
sahilmgandhi 18:6a4db94011d3 512 uint32_t result;
sahilmgandhi 18:6a4db94011d3 513
sahilmgandhi 18:6a4db94011d3 514 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sahilmgandhi 18:6a4db94011d3 515 return(result);
sahilmgandhi 18:6a4db94011d3 516 }
sahilmgandhi 18:6a4db94011d3 517
sahilmgandhi 18:6a4db94011d3 518 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
sahilmgandhi 18:6a4db94011d3 519 {
sahilmgandhi 18:6a4db94011d3 520 uint32_t result;
sahilmgandhi 18:6a4db94011d3 521
sahilmgandhi 18:6a4db94011d3 522 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sahilmgandhi 18:6a4db94011d3 523 return(result);
sahilmgandhi 18:6a4db94011d3 524 }
sahilmgandhi 18:6a4db94011d3 525
sahilmgandhi 18:6a4db94011d3 526 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
sahilmgandhi 18:6a4db94011d3 527 {
sahilmgandhi 18:6a4db94011d3 528 uint32_t result;
sahilmgandhi 18:6a4db94011d3 529
sahilmgandhi 18:6a4db94011d3 530 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
sahilmgandhi 18:6a4db94011d3 531 return(result);
sahilmgandhi 18:6a4db94011d3 532 }
sahilmgandhi 18:6a4db94011d3 533
sahilmgandhi 18:6a4db94011d3 534 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
sahilmgandhi 18:6a4db94011d3 535 {
sahilmgandhi 18:6a4db94011d3 536 uint32_t result;
sahilmgandhi 18:6a4db94011d3 537
sahilmgandhi 18:6a4db94011d3 538 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
sahilmgandhi 18:6a4db94011d3 539 return(result);
sahilmgandhi 18:6a4db94011d3 540 }
sahilmgandhi 18:6a4db94011d3 541
sahilmgandhi 18:6a4db94011d3 542 #define __SMLALD(ARG1,ARG2,ARG3) \
sahilmgandhi 18:6a4db94011d3 543 ({ \
sahilmgandhi 18:6a4db94011d3 544 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
sahilmgandhi 18:6a4db94011d3 545 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
sahilmgandhi 18:6a4db94011d3 546 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
sahilmgandhi 18:6a4db94011d3 547 })
sahilmgandhi 18:6a4db94011d3 548
sahilmgandhi 18:6a4db94011d3 549 #define __SMLALDX(ARG1,ARG2,ARG3) \
sahilmgandhi 18:6a4db94011d3 550 ({ \
sahilmgandhi 18:6a4db94011d3 551 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
sahilmgandhi 18:6a4db94011d3 552 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
sahilmgandhi 18:6a4db94011d3 553 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
sahilmgandhi 18:6a4db94011d3 554 })
sahilmgandhi 18:6a4db94011d3 555
sahilmgandhi 18:6a4db94011d3 556 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
sahilmgandhi 18:6a4db94011d3 557 {
sahilmgandhi 18:6a4db94011d3 558 uint32_t result;
sahilmgandhi 18:6a4db94011d3 559
sahilmgandhi 18:6a4db94011d3 560 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sahilmgandhi 18:6a4db94011d3 561 return(result);
sahilmgandhi 18:6a4db94011d3 562 }
sahilmgandhi 18:6a4db94011d3 563
sahilmgandhi 18:6a4db94011d3 564 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
sahilmgandhi 18:6a4db94011d3 565 {
sahilmgandhi 18:6a4db94011d3 566 uint32_t result;
sahilmgandhi 18:6a4db94011d3 567
sahilmgandhi 18:6a4db94011d3 568 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sahilmgandhi 18:6a4db94011d3 569 return(result);
sahilmgandhi 18:6a4db94011d3 570 }
sahilmgandhi 18:6a4db94011d3 571
sahilmgandhi 18:6a4db94011d3 572 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
sahilmgandhi 18:6a4db94011d3 573 {
sahilmgandhi 18:6a4db94011d3 574 uint32_t result;
sahilmgandhi 18:6a4db94011d3 575
sahilmgandhi 18:6a4db94011d3 576 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
sahilmgandhi 18:6a4db94011d3 577 return(result);
sahilmgandhi 18:6a4db94011d3 578 }
sahilmgandhi 18:6a4db94011d3 579
sahilmgandhi 18:6a4db94011d3 580 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
sahilmgandhi 18:6a4db94011d3 581 {
sahilmgandhi 18:6a4db94011d3 582 uint32_t result;
sahilmgandhi 18:6a4db94011d3 583
sahilmgandhi 18:6a4db94011d3 584 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
sahilmgandhi 18:6a4db94011d3 585 return(result);
sahilmgandhi 18:6a4db94011d3 586 }
sahilmgandhi 18:6a4db94011d3 587
sahilmgandhi 18:6a4db94011d3 588 #define __SMLSLD(ARG1,ARG2,ARG3) \
sahilmgandhi 18:6a4db94011d3 589 ({ \
sahilmgandhi 18:6a4db94011d3 590 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
sahilmgandhi 18:6a4db94011d3 591 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
sahilmgandhi 18:6a4db94011d3 592 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
sahilmgandhi 18:6a4db94011d3 593 })
sahilmgandhi 18:6a4db94011d3 594
sahilmgandhi 18:6a4db94011d3 595 #define __SMLSLDX(ARG1,ARG2,ARG3) \
sahilmgandhi 18:6a4db94011d3 596 ({ \
sahilmgandhi 18:6a4db94011d3 597 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
sahilmgandhi 18:6a4db94011d3 598 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
sahilmgandhi 18:6a4db94011d3 599 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
sahilmgandhi 18:6a4db94011d3 600 })
sahilmgandhi 18:6a4db94011d3 601
sahilmgandhi 18:6a4db94011d3 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
sahilmgandhi 18:6a4db94011d3 603 {
sahilmgandhi 18:6a4db94011d3 604 uint32_t result;
sahilmgandhi 18:6a4db94011d3 605
sahilmgandhi 18:6a4db94011d3 606 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sahilmgandhi 18:6a4db94011d3 607 return(result);
sahilmgandhi 18:6a4db94011d3 608 }
sahilmgandhi 18:6a4db94011d3 609
sahilmgandhi 18:6a4db94011d3 610 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
sahilmgandhi 18:6a4db94011d3 611 {
sahilmgandhi 18:6a4db94011d3 612 uint32_t result;
sahilmgandhi 18:6a4db94011d3 613
sahilmgandhi 18:6a4db94011d3 614 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sahilmgandhi 18:6a4db94011d3 615 return(result);
sahilmgandhi 18:6a4db94011d3 616 }
sahilmgandhi 18:6a4db94011d3 617
sahilmgandhi 18:6a4db94011d3 618 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
sahilmgandhi 18:6a4db94011d3 619 {
sahilmgandhi 18:6a4db94011d3 620 uint32_t result;
sahilmgandhi 18:6a4db94011d3 621
sahilmgandhi 18:6a4db94011d3 622 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
sahilmgandhi 18:6a4db94011d3 623 return(result);
sahilmgandhi 18:6a4db94011d3 624 }
sahilmgandhi 18:6a4db94011d3 625
sahilmgandhi 18:6a4db94011d3 626 #define __PKHBT(ARG1,ARG2,ARG3) \
sahilmgandhi 18:6a4db94011d3 627 ({ \
sahilmgandhi 18:6a4db94011d3 628 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
sahilmgandhi 18:6a4db94011d3 629 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
sahilmgandhi 18:6a4db94011d3 630 __RES; \
sahilmgandhi 18:6a4db94011d3 631 })
sahilmgandhi 18:6a4db94011d3 632
sahilmgandhi 18:6a4db94011d3 633 #define __PKHTB(ARG1,ARG2,ARG3) \
sahilmgandhi 18:6a4db94011d3 634 ({ \
sahilmgandhi 18:6a4db94011d3 635 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
sahilmgandhi 18:6a4db94011d3 636 if (ARG3 == 0) \
sahilmgandhi 18:6a4db94011d3 637 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
sahilmgandhi 18:6a4db94011d3 638 else \
sahilmgandhi 18:6a4db94011d3 639 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
sahilmgandhi 18:6a4db94011d3 640 __RES; \
sahilmgandhi 18:6a4db94011d3 641 })
sahilmgandhi 18:6a4db94011d3 642
sahilmgandhi 18:6a4db94011d3 643 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
sahilmgandhi 18:6a4db94011d3 644 {
sahilmgandhi 18:6a4db94011d3 645 int32_t result;
sahilmgandhi 18:6a4db94011d3 646
sahilmgandhi 18:6a4db94011d3 647 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
sahilmgandhi 18:6a4db94011d3 648 return(result);
sahilmgandhi 18:6a4db94011d3 649 }
sahilmgandhi 18:6a4db94011d3 650
sahilmgandhi 18:6a4db94011d3 651 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 652
sahilmgandhi 18:6a4db94011d3 653
sahilmgandhi 18:6a4db94011d3 654
sahilmgandhi 18:6a4db94011d3 655 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
sahilmgandhi 18:6a4db94011d3 656 /* TASKING carm specific functions */
sahilmgandhi 18:6a4db94011d3 657
sahilmgandhi 18:6a4db94011d3 658
sahilmgandhi 18:6a4db94011d3 659 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 660 /* not yet supported */
sahilmgandhi 18:6a4db94011d3 661 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 662
sahilmgandhi 18:6a4db94011d3 663
sahilmgandhi 18:6a4db94011d3 664 #endif
sahilmgandhi 18:6a4db94011d3 665
sahilmgandhi 18:6a4db94011d3 666 /*@} end of group CMSIS_SIMD_intrinsics */
sahilmgandhi 18:6a4db94011d3 667
sahilmgandhi 18:6a4db94011d3 668
sahilmgandhi 18:6a4db94011d3 669 #endif /* __CORE_CM4_SIMD_H */
sahilmgandhi 18:6a4db94011d3 670
sahilmgandhi 18:6a4db94011d3 671 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 672 }
sahilmgandhi 18:6a4db94011d3 673 #endif