MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NXP/TARGET_LPC81X/spi_api.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2006-2013 ARM Limited
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 */
sahilmgandhi 18:6a4db94011d3 16 #include "mbed_assert.h"
sahilmgandhi 18:6a4db94011d3 17 #include <math.h>
sahilmgandhi 18:6a4db94011d3 18
sahilmgandhi 18:6a4db94011d3 19 #include "spi_api.h"
sahilmgandhi 18:6a4db94011d3 20 #include "cmsis.h"
sahilmgandhi 18:6a4db94011d3 21 #include "pinmap.h"
sahilmgandhi 18:6a4db94011d3 22 #include "mbed_error.h"
sahilmgandhi 18:6a4db94011d3 23
sahilmgandhi 18:6a4db94011d3 24 static const SWM_Map SWM_SPI_SSEL[] = {
sahilmgandhi 18:6a4db94011d3 25 {4, 16},
sahilmgandhi 18:6a4db94011d3 26 {5, 16},
sahilmgandhi 18:6a4db94011d3 27 };
sahilmgandhi 18:6a4db94011d3 28
sahilmgandhi 18:6a4db94011d3 29 static const SWM_Map SWM_SPI_SCLK[] = {
sahilmgandhi 18:6a4db94011d3 30 {3, 24},
sahilmgandhi 18:6a4db94011d3 31 {4, 24},
sahilmgandhi 18:6a4db94011d3 32 };
sahilmgandhi 18:6a4db94011d3 33
sahilmgandhi 18:6a4db94011d3 34 static const SWM_Map SWM_SPI_MOSI[] = {
sahilmgandhi 18:6a4db94011d3 35 {4, 0},
sahilmgandhi 18:6a4db94011d3 36 {5, 0},
sahilmgandhi 18:6a4db94011d3 37 };
sahilmgandhi 18:6a4db94011d3 38
sahilmgandhi 18:6a4db94011d3 39 static const SWM_Map SWM_SPI_MISO[] = {
sahilmgandhi 18:6a4db94011d3 40 {4, 8},
sahilmgandhi 18:6a4db94011d3 41 {5, 16},
sahilmgandhi 18:6a4db94011d3 42 };
sahilmgandhi 18:6a4db94011d3 43
sahilmgandhi 18:6a4db94011d3 44 // bit flags for used SPIs
sahilmgandhi 18:6a4db94011d3 45 static unsigned char spi_used = 0;
sahilmgandhi 18:6a4db94011d3 46 static int get_available_spi(void) {
sahilmgandhi 18:6a4db94011d3 47 int i;
sahilmgandhi 18:6a4db94011d3 48 for (i=0; i<2; i++) {
sahilmgandhi 18:6a4db94011d3 49 if ((spi_used & (1 << i)) == 0)
sahilmgandhi 18:6a4db94011d3 50 return i;
sahilmgandhi 18:6a4db94011d3 51 }
sahilmgandhi 18:6a4db94011d3 52 return -1;
sahilmgandhi 18:6a4db94011d3 53 }
sahilmgandhi 18:6a4db94011d3 54
sahilmgandhi 18:6a4db94011d3 55 static inline int ssp_disable(spi_t *obj);
sahilmgandhi 18:6a4db94011d3 56 static inline int ssp_enable(spi_t *obj);
sahilmgandhi 18:6a4db94011d3 57
sahilmgandhi 18:6a4db94011d3 58 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
sahilmgandhi 18:6a4db94011d3 59 int spi_n = get_available_spi();
sahilmgandhi 18:6a4db94011d3 60 if (spi_n == -1) {
sahilmgandhi 18:6a4db94011d3 61 error("No available SPI");
sahilmgandhi 18:6a4db94011d3 62 }
sahilmgandhi 18:6a4db94011d3 63 obj->spi_n = spi_n;
sahilmgandhi 18:6a4db94011d3 64 spi_used |= (1 << spi_n);
sahilmgandhi 18:6a4db94011d3 65
sahilmgandhi 18:6a4db94011d3 66 obj->spi = (spi_n) ? (LPC_SPI_TypeDef *)(LPC_SPI1_BASE) : (LPC_SPI_TypeDef *)(LPC_SPI0_BASE);
sahilmgandhi 18:6a4db94011d3 67
sahilmgandhi 18:6a4db94011d3 68 const SWM_Map *swm;
sahilmgandhi 18:6a4db94011d3 69 uint32_t regVal;
sahilmgandhi 18:6a4db94011d3 70
sahilmgandhi 18:6a4db94011d3 71 swm = &SWM_SPI_SCLK[obj->spi_n];
sahilmgandhi 18:6a4db94011d3 72 regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
sahilmgandhi 18:6a4db94011d3 73 LPC_SWM->PINASSIGN[swm->n] = regVal | (sclk << swm->offset);
sahilmgandhi 18:6a4db94011d3 74
sahilmgandhi 18:6a4db94011d3 75 swm = &SWM_SPI_MOSI[obj->spi_n];
sahilmgandhi 18:6a4db94011d3 76 regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
sahilmgandhi 18:6a4db94011d3 77 LPC_SWM->PINASSIGN[swm->n] = regVal | (mosi << swm->offset);
sahilmgandhi 18:6a4db94011d3 78
sahilmgandhi 18:6a4db94011d3 79 swm = &SWM_SPI_MISO[obj->spi_n];
sahilmgandhi 18:6a4db94011d3 80 regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
sahilmgandhi 18:6a4db94011d3 81 LPC_SWM->PINASSIGN[swm->n] = regVal | (miso << swm->offset);
sahilmgandhi 18:6a4db94011d3 82
sahilmgandhi 18:6a4db94011d3 83 swm = &SWM_SPI_SSEL[obj->spi_n];
sahilmgandhi 18:6a4db94011d3 84 regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
sahilmgandhi 18:6a4db94011d3 85 LPC_SWM->PINASSIGN[swm->n] = regVal | (ssel << swm->offset);
sahilmgandhi 18:6a4db94011d3 86
sahilmgandhi 18:6a4db94011d3 87 // clear interrupts
sahilmgandhi 18:6a4db94011d3 88 obj->spi->INTENCLR = 0x3f;
sahilmgandhi 18:6a4db94011d3 89
sahilmgandhi 18:6a4db94011d3 90 // enable power and clocking
sahilmgandhi 18:6a4db94011d3 91 switch (obj->spi_n) {
sahilmgandhi 18:6a4db94011d3 92 case 0:
sahilmgandhi 18:6a4db94011d3 93 LPC_SYSCON->SYSAHBCLKCTRL |= (1<<11);
sahilmgandhi 18:6a4db94011d3 94 LPC_SYSCON->PRESETCTRL &= ~(0x1<<0);
sahilmgandhi 18:6a4db94011d3 95 LPC_SYSCON->PRESETCTRL |= (0x1<<0);
sahilmgandhi 18:6a4db94011d3 96 break;
sahilmgandhi 18:6a4db94011d3 97 case 1:
sahilmgandhi 18:6a4db94011d3 98 LPC_SYSCON->SYSAHBCLKCTRL |= (1<<12);
sahilmgandhi 18:6a4db94011d3 99 LPC_SYSCON->PRESETCTRL &= ~(0x1<<1);
sahilmgandhi 18:6a4db94011d3 100 LPC_SYSCON->PRESETCTRL |= (0x1<<1);
sahilmgandhi 18:6a4db94011d3 101 break;
sahilmgandhi 18:6a4db94011d3 102 }
sahilmgandhi 18:6a4db94011d3 103 }
sahilmgandhi 18:6a4db94011d3 104
sahilmgandhi 18:6a4db94011d3 105 void spi_free(spi_t *obj) {}
sahilmgandhi 18:6a4db94011d3 106
sahilmgandhi 18:6a4db94011d3 107 void spi_format(spi_t *obj, int bits, int mode, int slave) {
sahilmgandhi 18:6a4db94011d3 108 MBED_ASSERT(((bits >= 1) && (bits <= 16)) && ((mode >= 0) && (mode <= 3)));
sahilmgandhi 18:6a4db94011d3 109 ssp_disable(obj);
sahilmgandhi 18:6a4db94011d3 110
sahilmgandhi 18:6a4db94011d3 111 int polarity = (mode & 0x2) ? 1 : 0;
sahilmgandhi 18:6a4db94011d3 112 int phase = (mode & 0x1) ? 1 : 0;
sahilmgandhi 18:6a4db94011d3 113
sahilmgandhi 18:6a4db94011d3 114 // set it up
sahilmgandhi 18:6a4db94011d3 115 int DSS = bits - 1; // DSS (data select size)
sahilmgandhi 18:6a4db94011d3 116 int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity
sahilmgandhi 18:6a4db94011d3 117 int SPH = (phase) ? 1 : 0; // SPH - clock out phase
sahilmgandhi 18:6a4db94011d3 118
sahilmgandhi 18:6a4db94011d3 119 uint32_t tmp = obj->spi->CFG;
sahilmgandhi 18:6a4db94011d3 120 tmp &= ~((1 << 2) | (1 << 4) | (1 << 5));
sahilmgandhi 18:6a4db94011d3 121 tmp |= (SPH << 4) | (SPO << 5) | ((slave ? 0 : 1) << 2);
sahilmgandhi 18:6a4db94011d3 122 obj->spi->CFG = tmp;
sahilmgandhi 18:6a4db94011d3 123
sahilmgandhi 18:6a4db94011d3 124 // select frame length
sahilmgandhi 18:6a4db94011d3 125 tmp = obj->spi->TXDATCTL;
sahilmgandhi 18:6a4db94011d3 126 tmp &= ~(0xf << 24);
sahilmgandhi 18:6a4db94011d3 127 tmp |= (DSS << 24);
sahilmgandhi 18:6a4db94011d3 128 obj->spi->TXDATCTL = tmp;
sahilmgandhi 18:6a4db94011d3 129
sahilmgandhi 18:6a4db94011d3 130 ssp_enable(obj);
sahilmgandhi 18:6a4db94011d3 131 }
sahilmgandhi 18:6a4db94011d3 132
sahilmgandhi 18:6a4db94011d3 133 void spi_frequency(spi_t *obj, int hz) {
sahilmgandhi 18:6a4db94011d3 134 ssp_disable(obj);
sahilmgandhi 18:6a4db94011d3 135
sahilmgandhi 18:6a4db94011d3 136 uint32_t PCLK = SystemCoreClock;
sahilmgandhi 18:6a4db94011d3 137
sahilmgandhi 18:6a4db94011d3 138 obj->spi->DIV = PCLK/hz - 1;
sahilmgandhi 18:6a4db94011d3 139 obj->spi->DLY = 0;
sahilmgandhi 18:6a4db94011d3 140 ssp_enable(obj);
sahilmgandhi 18:6a4db94011d3 141 }
sahilmgandhi 18:6a4db94011d3 142
sahilmgandhi 18:6a4db94011d3 143 static inline int ssp_disable(spi_t *obj) {
sahilmgandhi 18:6a4db94011d3 144 return obj->spi->CFG &= ~(1 << 0);
sahilmgandhi 18:6a4db94011d3 145 }
sahilmgandhi 18:6a4db94011d3 146
sahilmgandhi 18:6a4db94011d3 147 static inline int ssp_enable(spi_t *obj) {
sahilmgandhi 18:6a4db94011d3 148 return obj->spi->CFG |= (1 << 0);
sahilmgandhi 18:6a4db94011d3 149 }
sahilmgandhi 18:6a4db94011d3 150
sahilmgandhi 18:6a4db94011d3 151 static inline int ssp_readable(spi_t *obj) {
sahilmgandhi 18:6a4db94011d3 152 return obj->spi->STAT & (1 << 0);
sahilmgandhi 18:6a4db94011d3 153 }
sahilmgandhi 18:6a4db94011d3 154
sahilmgandhi 18:6a4db94011d3 155 static inline int ssp_writeable(spi_t *obj) {
sahilmgandhi 18:6a4db94011d3 156 return obj->spi->STAT & (1 << 1);
sahilmgandhi 18:6a4db94011d3 157 }
sahilmgandhi 18:6a4db94011d3 158
sahilmgandhi 18:6a4db94011d3 159 static inline void ssp_write(spi_t *obj, int value) {
sahilmgandhi 18:6a4db94011d3 160 while (!ssp_writeable(obj));
sahilmgandhi 18:6a4db94011d3 161 // end of transfer
sahilmgandhi 18:6a4db94011d3 162 obj->spi->TXDATCTL |= (1 << 20);
sahilmgandhi 18:6a4db94011d3 163 obj->spi->TXDAT = value;
sahilmgandhi 18:6a4db94011d3 164 }
sahilmgandhi 18:6a4db94011d3 165
sahilmgandhi 18:6a4db94011d3 166 static inline int ssp_read(spi_t *obj) {
sahilmgandhi 18:6a4db94011d3 167 while (!ssp_readable(obj));
sahilmgandhi 18:6a4db94011d3 168 return obj->spi->RXDAT;
sahilmgandhi 18:6a4db94011d3 169 }
sahilmgandhi 18:6a4db94011d3 170
sahilmgandhi 18:6a4db94011d3 171 static inline int ssp_busy(spi_t *obj) {
sahilmgandhi 18:6a4db94011d3 172 // checking RXOV(Receiver Overrun interrupt flag)
sahilmgandhi 18:6a4db94011d3 173 return obj->spi->STAT & (1 << 2);
sahilmgandhi 18:6a4db94011d3 174 }
sahilmgandhi 18:6a4db94011d3 175
sahilmgandhi 18:6a4db94011d3 176 int spi_master_write(spi_t *obj, int value) {
sahilmgandhi 18:6a4db94011d3 177 ssp_write(obj, value);
sahilmgandhi 18:6a4db94011d3 178 return ssp_read(obj);
sahilmgandhi 18:6a4db94011d3 179 }
sahilmgandhi 18:6a4db94011d3 180
sahilmgandhi 18:6a4db94011d3 181 int spi_slave_receive(spi_t *obj) {
sahilmgandhi 18:6a4db94011d3 182 return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
sahilmgandhi 18:6a4db94011d3 183 }
sahilmgandhi 18:6a4db94011d3 184
sahilmgandhi 18:6a4db94011d3 185 int spi_slave_read(spi_t *obj) {
sahilmgandhi 18:6a4db94011d3 186 return obj->spi->RXDAT;
sahilmgandhi 18:6a4db94011d3 187 }
sahilmgandhi 18:6a4db94011d3 188
sahilmgandhi 18:6a4db94011d3 189 void spi_slave_write(spi_t *obj, int value) {
sahilmgandhi 18:6a4db94011d3 190 while (ssp_writeable(obj) == 0) ;
sahilmgandhi 18:6a4db94011d3 191 obj->spi->TXDAT = value;
sahilmgandhi 18:6a4db94011d3 192 }
sahilmgandhi 18:6a4db94011d3 193
sahilmgandhi 18:6a4db94011d3 194 int spi_busy(spi_t *obj) {
sahilmgandhi 18:6a4db94011d3 195 return ssp_busy(obj);
sahilmgandhi 18:6a4db94011d3 196 }