MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NXP/TARGET_LPC43XX/port_api.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2006-2013 ARM Limited
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 *
sahilmgandhi 18:6a4db94011d3 16 * Ported to NXP LPC43XX by Micromint USA <support@micromint.com>
sahilmgandhi 18:6a4db94011d3 17 */
sahilmgandhi 18:6a4db94011d3 18 #include "mbed_assert.h"
sahilmgandhi 18:6a4db94011d3 19 #include "port_api.h"
sahilmgandhi 18:6a4db94011d3 20 #include "pinmap.h"
sahilmgandhi 18:6a4db94011d3 21 #include "gpio_api.h"
sahilmgandhi 18:6a4db94011d3 22
sahilmgandhi 18:6a4db94011d3 23 // Lookup table to determine SCU offset for GPIO [port][pin]
sahilmgandhi 18:6a4db94011d3 24 // Supports eight 16-bit ports to limit table size
sahilmgandhi 18:6a4db94011d3 25 #define _SO(MBED_PIN) (MBED_PIN >> 18)
sahilmgandhi 18:6a4db94011d3 26
sahilmgandhi 18:6a4db94011d3 27 static const uint8_t _scu_off[][16] =
sahilmgandhi 18:6a4db94011d3 28 { // GPIO0 to GPIO3
sahilmgandhi 18:6a4db94011d3 29 { _SO(GPIO0_0), _SO(GPIO0_1), _SO(GPIO0_2), _SO(GPIO0_3),
sahilmgandhi 18:6a4db94011d3 30 _SO(GPIO0_4), _SO(GPIO0_5), _SO(GPIO0_6), _SO(GPIO0_7),
sahilmgandhi 18:6a4db94011d3 31 _SO(GPIO0_8), _SO(GPIO0_9), _SO(GPIO0_10), _SO(GPIO0_11),
sahilmgandhi 18:6a4db94011d3 32 _SO(GPIO0_12), _SO(GPIO0_13), _SO(GPIO0_14), _SO(GPIO0_15)
sahilmgandhi 18:6a4db94011d3 33 },
sahilmgandhi 18:6a4db94011d3 34 { _SO(GPIO1_0), _SO(GPIO1_1), _SO(GPIO1_2), _SO(GPIO1_3),
sahilmgandhi 18:6a4db94011d3 35 _SO(GPIO1_4), _SO(GPIO1_5), _SO(GPIO1_6), _SO(GPIO1_7),
sahilmgandhi 18:6a4db94011d3 36 _SO(GPIO1_8), _SO(GPIO1_9), _SO(GPIO1_10), _SO(GPIO1_11),
sahilmgandhi 18:6a4db94011d3 37 _SO(GPIO1_12), _SO(GPIO1_13), _SO(GPIO1_14), _SO(GPIO1_15)
sahilmgandhi 18:6a4db94011d3 38 },
sahilmgandhi 18:6a4db94011d3 39 { _SO(GPIO2_0), _SO(GPIO2_1), _SO(GPIO2_2), _SO(GPIO2_3),
sahilmgandhi 18:6a4db94011d3 40 _SO(GPIO2_4), _SO(GPIO2_5), _SO(GPIO2_6), _SO(GPIO2_7),
sahilmgandhi 18:6a4db94011d3 41 _SO(GPIO2_8), _SO(GPIO2_9), _SO(GPIO2_10), _SO(GPIO2_11),
sahilmgandhi 18:6a4db94011d3 42 _SO(GPIO2_12), _SO(GPIO2_13), _SO(GPIO2_14), _SO(GPIO2_15)
sahilmgandhi 18:6a4db94011d3 43 },
sahilmgandhi 18:6a4db94011d3 44 { _SO(GPIO3_0), _SO(GPIO3_1), _SO(GPIO3_2), _SO(GPIO3_3),
sahilmgandhi 18:6a4db94011d3 45 _SO(GPIO3_4), _SO(GPIO3_5), _SO(GPIO3_6), _SO(GPIO3_7),
sahilmgandhi 18:6a4db94011d3 46 _SO(GPIO3_8), _SO(GPIO3_9), _SO(GPIO3_10), _SO(GPIO3_11),
sahilmgandhi 18:6a4db94011d3 47 _SO(GPIO3_12), _SO(GPIO3_13), _SO(GPIO3_14), _SO(GPIO3_15)
sahilmgandhi 18:6a4db94011d3 48 },
sahilmgandhi 18:6a4db94011d3 49 };
sahilmgandhi 18:6a4db94011d3 50
sahilmgandhi 18:6a4db94011d3 51 // Use alternate encoding for ports 4 to 7 so lookup stays within uint8
sahilmgandhi 18:6a4db94011d3 52 #define _S2(MBED_PIN) (((MBED_PIN >> 19) & 0xf0) | ((MBED_PIN >> 18) & 0x0f))
sahilmgandhi 18:6a4db94011d3 53
sahilmgandhi 18:6a4db94011d3 54 static const uint8_t _scu_off2[][16] =
sahilmgandhi 18:6a4db94011d3 55 { // GPIO4 to GPIO7
sahilmgandhi 18:6a4db94011d3 56 { _S2(GPIO4_0), _S2(GPIO4_1), _S2(GPIO4_2), _S2(GPIO4_3),
sahilmgandhi 18:6a4db94011d3 57 _S2(GPIO4_4), _S2(GPIO4_5), _S2(GPIO4_6), _S2(GPIO4_7),
sahilmgandhi 18:6a4db94011d3 58 _S2(GPIO4_8), _S2(GPIO4_9), _S2(GPIO4_10), _S2(GPIO4_11),
sahilmgandhi 18:6a4db94011d3 59 _S2(GPIO4_12), _S2(GPIO4_13), _S2(GPIO4_14), _S2(GPIO4_15)
sahilmgandhi 18:6a4db94011d3 60 },
sahilmgandhi 18:6a4db94011d3 61 { _S2(GPIO5_0), _S2(GPIO5_1), _S2(GPIO5_2), _S2(GPIO5_3),
sahilmgandhi 18:6a4db94011d3 62 _S2(GPIO5_4), _S2(GPIO5_5), _S2(GPIO5_6), _S2(GPIO5_7),
sahilmgandhi 18:6a4db94011d3 63 _S2(GPIO5_8), _S2(GPIO5_9), _S2(GPIO5_10), _S2(GPIO5_11),
sahilmgandhi 18:6a4db94011d3 64 _S2(GPIO5_12), _S2(GPIO5_13), _S2(GPIO5_14), _S2(GPIO5_15)
sahilmgandhi 18:6a4db94011d3 65 },
sahilmgandhi 18:6a4db94011d3 66 { _S2(GPIO6_0), _S2(GPIO6_1), _S2(GPIO6_2), _S2(GPIO6_3),
sahilmgandhi 18:6a4db94011d3 67 _S2(GPIO6_4), _S2(GPIO6_5), _S2(GPIO6_6), _S2(GPIO6_7),
sahilmgandhi 18:6a4db94011d3 68 _S2(GPIO6_8), _S2(GPIO6_9), _S2(GPIO6_10), _S2(GPIO6_11),
sahilmgandhi 18:6a4db94011d3 69 _S2(GPIO6_12), _S2(GPIO6_13), _S2(GPIO6_14), _S2(GPIO6_15)
sahilmgandhi 18:6a4db94011d3 70 },
sahilmgandhi 18:6a4db94011d3 71 { _S2(GPIO7_0), _S2(GPIO7_1), _S2(GPIO7_2), _S2(GPIO7_3),
sahilmgandhi 18:6a4db94011d3 72 _S2(GPIO7_4), _S2(GPIO7_5), _S2(GPIO7_6), _S2(GPIO7_7),
sahilmgandhi 18:6a4db94011d3 73 _S2(GPIO7_8), _S2(GPIO7_9), _S2(GPIO7_10), _S2(GPIO7_11),
sahilmgandhi 18:6a4db94011d3 74 _S2(GPIO7_12), _S2(GPIO7_13), _S2(GPIO7_14), _S2(GPIO7_15)
sahilmgandhi 18:6a4db94011d3 75 },
sahilmgandhi 18:6a4db94011d3 76 };
sahilmgandhi 18:6a4db94011d3 77
sahilmgandhi 18:6a4db94011d3 78 PinName port_pin(PortName port, int pin_n) {
sahilmgandhi 18:6a4db94011d3 79 MBED_ASSERT((port <= Port7) && (pin_n < 32));
sahilmgandhi 18:6a4db94011d3 80 int offset = 0;
sahilmgandhi 18:6a4db94011d3 81
sahilmgandhi 18:6a4db94011d3 82 // Lookup table only maps pins 0 to 15
sahilmgandhi 18:6a4db94011d3 83 if (pin_n > 15) {
sahilmgandhi 18:6a4db94011d3 84 return NC;
sahilmgandhi 18:6a4db94011d3 85 }
sahilmgandhi 18:6a4db94011d3 86
sahilmgandhi 18:6a4db94011d3 87 // Lookup SCU offset
sahilmgandhi 18:6a4db94011d3 88 if (port < Port4) {
sahilmgandhi 18:6a4db94011d3 89 offset = _scu_off[port][pin_n];
sahilmgandhi 18:6a4db94011d3 90 } else {
sahilmgandhi 18:6a4db94011d3 91 offset = _scu_off2[port - Port4][pin_n];
sahilmgandhi 18:6a4db94011d3 92 offset = ((offset & 0xf0) << 1) | (offset & 0x0f);
sahilmgandhi 18:6a4db94011d3 93 }
sahilmgandhi 18:6a4db94011d3 94
sahilmgandhi 18:6a4db94011d3 95 // Return pin name
sahilmgandhi 18:6a4db94011d3 96 return (PinName)((offset << 18) | GPIO_OFF(port, pin_n));
sahilmgandhi 18:6a4db94011d3 97 }
sahilmgandhi 18:6a4db94011d3 98
sahilmgandhi 18:6a4db94011d3 99 void port_init(port_t *obj, PortName port, int mask, PinDirection dir) {
sahilmgandhi 18:6a4db94011d3 100 obj->port = port;
sahilmgandhi 18:6a4db94011d3 101 obj->mask = mask;
sahilmgandhi 18:6a4db94011d3 102
sahilmgandhi 18:6a4db94011d3 103 LPC_GPIO_T *port_reg = (LPC_GPIO_T *)(LPC_GPIO_PORT_BASE);
sahilmgandhi 18:6a4db94011d3 104
sahilmgandhi 18:6a4db94011d3 105 // Do not use masking, because it prevents the use of the unmasked pins
sahilmgandhi 18:6a4db94011d3 106 // port_reg->MASK[port] = ~mask;
sahilmgandhi 18:6a4db94011d3 107
sahilmgandhi 18:6a4db94011d3 108 obj->reg_out = &port_reg->PIN[port];
sahilmgandhi 18:6a4db94011d3 109 obj->reg_in = &port_reg->PIN[port];
sahilmgandhi 18:6a4db94011d3 110 obj->reg_dir = &port_reg->DIR[port];
sahilmgandhi 18:6a4db94011d3 111
sahilmgandhi 18:6a4db94011d3 112 uint32_t i;
sahilmgandhi 18:6a4db94011d3 113 // The function is set per pin: reuse gpio logic
sahilmgandhi 18:6a4db94011d3 114 for (i=0; i<32; i++) {
sahilmgandhi 18:6a4db94011d3 115 if (obj->mask & (1<<i)) {
sahilmgandhi 18:6a4db94011d3 116 gpio_set(port_pin(obj->port, i));
sahilmgandhi 18:6a4db94011d3 117 }
sahilmgandhi 18:6a4db94011d3 118 }
sahilmgandhi 18:6a4db94011d3 119
sahilmgandhi 18:6a4db94011d3 120 port_dir(obj, dir);
sahilmgandhi 18:6a4db94011d3 121 }
sahilmgandhi 18:6a4db94011d3 122
sahilmgandhi 18:6a4db94011d3 123 void port_mode(port_t *obj, PinMode mode) {
sahilmgandhi 18:6a4db94011d3 124 uint32_t i;
sahilmgandhi 18:6a4db94011d3 125 // The mode is set per pin: reuse pinmap logic
sahilmgandhi 18:6a4db94011d3 126 for (i=0; i<32; i++) {
sahilmgandhi 18:6a4db94011d3 127 if (obj->mask & (1<<i)) {
sahilmgandhi 18:6a4db94011d3 128 pin_mode(port_pin(obj->port, i), mode);
sahilmgandhi 18:6a4db94011d3 129 }
sahilmgandhi 18:6a4db94011d3 130 }
sahilmgandhi 18:6a4db94011d3 131 }
sahilmgandhi 18:6a4db94011d3 132
sahilmgandhi 18:6a4db94011d3 133 void port_dir(port_t *obj, PinDirection dir) {
sahilmgandhi 18:6a4db94011d3 134 switch (dir) {
sahilmgandhi 18:6a4db94011d3 135 case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break;
sahilmgandhi 18:6a4db94011d3 136 case PIN_OUTPUT: *obj->reg_dir |= obj->mask; break;
sahilmgandhi 18:6a4db94011d3 137 }
sahilmgandhi 18:6a4db94011d3 138 }
sahilmgandhi 18:6a4db94011d3 139
sahilmgandhi 18:6a4db94011d3 140 void port_write(port_t *obj, int value) {
sahilmgandhi 18:6a4db94011d3 141 *obj->reg_out = (*obj->reg_in & ~obj->mask) | (value & obj->mask);
sahilmgandhi 18:6a4db94011d3 142 }
sahilmgandhi 18:6a4db94011d3 143
sahilmgandhi 18:6a4db94011d3 144 int port_read(port_t *obj) {
sahilmgandhi 18:6a4db94011d3 145 return (*obj->reg_in & obj->mask);
sahilmgandhi 18:6a4db94011d3 146 }