MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NXP/TARGET_LPC43XX/gpio_irq_api.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2006-2013 ARM Limited
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 *
sahilmgandhi 18:6a4db94011d3 16 * Ported to NXP LPC43XX by Micromint USA <support@micromint.com>
sahilmgandhi 18:6a4db94011d3 17 */
sahilmgandhi 18:6a4db94011d3 18 #include <stddef.h>
sahilmgandhi 18:6a4db94011d3 19 #include "gpio_irq_api.h"
sahilmgandhi 18:6a4db94011d3 20 #include "mbed_error.h"
sahilmgandhi 18:6a4db94011d3 21 #include "cmsis.h"
sahilmgandhi 18:6a4db94011d3 22
sahilmgandhi 18:6a4db94011d3 23 /* The LPC43xx implements GPIO pin and group interrupts. Any pin in the
sahilmgandhi 18:6a4db94011d3 24 * 8 32-bit GPIO ports can interrupt. On group interrupts a pin can
sahilmgandhi 18:6a4db94011d3 25 * only interrupt on the rising or falling edge, not both as required
sahilmgandhi 18:6a4db94011d3 26 * by mbed. Also, group interrupts can't be cleared individually.
sahilmgandhi 18:6a4db94011d3 27 * This implementation uses pin interrupts (8 on M4/M3, 1 on M0).
sahilmgandhi 18:6a4db94011d3 28 * A future implementation may provide group interrupt support.
sahilmgandhi 18:6a4db94011d3 29 */
sahilmgandhi 18:6a4db94011d3 30 #if !defined(CORE_M0)
sahilmgandhi 18:6a4db94011d3 31 #define CHANNEL_MAX 8
sahilmgandhi 18:6a4db94011d3 32 #else
sahilmgandhi 18:6a4db94011d3 33 #define CHANNEL_MAX 1
sahilmgandhi 18:6a4db94011d3 34 #endif
sahilmgandhi 18:6a4db94011d3 35
sahilmgandhi 18:6a4db94011d3 36 static uint32_t channel_ids[CHANNEL_MAX] = {0};
sahilmgandhi 18:6a4db94011d3 37 static uint8_t channel = 0;
sahilmgandhi 18:6a4db94011d3 38 static gpio_irq_handler irq_handler;
sahilmgandhi 18:6a4db94011d3 39
sahilmgandhi 18:6a4db94011d3 40 static void handle_interrupt_in(void) {
sahilmgandhi 18:6a4db94011d3 41 uint32_t rise = LPC_GPIO_PIN_INT->RISE;
sahilmgandhi 18:6a4db94011d3 42 uint32_t fall = LPC_GPIO_PIN_INT->FALL;
sahilmgandhi 18:6a4db94011d3 43 uint32_t pmask;
sahilmgandhi 18:6a4db94011d3 44 int i;
sahilmgandhi 18:6a4db94011d3 45
sahilmgandhi 18:6a4db94011d3 46 for (i = 0; i < CHANNEL_MAX; i++) {
sahilmgandhi 18:6a4db94011d3 47 pmask = (1 << i);
sahilmgandhi 18:6a4db94011d3 48 if (rise & pmask) {
sahilmgandhi 18:6a4db94011d3 49 /* Rising edge interrupts */
sahilmgandhi 18:6a4db94011d3 50 if (channel_ids[i] != 0) {
sahilmgandhi 18:6a4db94011d3 51 irq_handler(channel_ids[i], IRQ_RISE);
sahilmgandhi 18:6a4db94011d3 52 }
sahilmgandhi 18:6a4db94011d3 53 /* Clear rising edge detected */
sahilmgandhi 18:6a4db94011d3 54 LPC_GPIO_PIN_INT->RISE = pmask;
sahilmgandhi 18:6a4db94011d3 55 }
sahilmgandhi 18:6a4db94011d3 56 if (fall & pmask) {
sahilmgandhi 18:6a4db94011d3 57 /* Falling edge interrupts */
sahilmgandhi 18:6a4db94011d3 58 if (channel_ids[i] != 0) {
sahilmgandhi 18:6a4db94011d3 59 irq_handler(channel_ids[i], IRQ_FALL);
sahilmgandhi 18:6a4db94011d3 60 }
sahilmgandhi 18:6a4db94011d3 61 /* Clear falling edge detected */
sahilmgandhi 18:6a4db94011d3 62 LPC_GPIO_PIN_INT->FALL = pmask;
sahilmgandhi 18:6a4db94011d3 63 }
sahilmgandhi 18:6a4db94011d3 64 }
sahilmgandhi 18:6a4db94011d3 65 }
sahilmgandhi 18:6a4db94011d3 66
sahilmgandhi 18:6a4db94011d3 67 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
sahilmgandhi 18:6a4db94011d3 68 uint32_t portnum, pinnum; //, pmask;
sahilmgandhi 18:6a4db94011d3 69
sahilmgandhi 18:6a4db94011d3 70 if (pin == NC) return -1;
sahilmgandhi 18:6a4db94011d3 71
sahilmgandhi 18:6a4db94011d3 72 irq_handler = handler;
sahilmgandhi 18:6a4db94011d3 73
sahilmgandhi 18:6a4db94011d3 74 /* Set port and pin numbers */
sahilmgandhi 18:6a4db94011d3 75 obj->port = portnum = MBED_GPIO_PORT(pin);
sahilmgandhi 18:6a4db94011d3 76 obj->pin = pinnum = MBED_GPIO_PIN(pin);
sahilmgandhi 18:6a4db94011d3 77
sahilmgandhi 18:6a4db94011d3 78 /* Add to channel table */
sahilmgandhi 18:6a4db94011d3 79 channel_ids[channel] = id;
sahilmgandhi 18:6a4db94011d3 80 obj->ch = channel;
sahilmgandhi 18:6a4db94011d3 81
sahilmgandhi 18:6a4db94011d3 82 /* Clear rising and falling edge detection */
sahilmgandhi 18:6a4db94011d3 83 //pmask = (1 << channel);
sahilmgandhi 18:6a4db94011d3 84 //LPC_GPIO_PIN_INT->IST = pmask;
sahilmgandhi 18:6a4db94011d3 85
sahilmgandhi 18:6a4db94011d3 86 /* Set SCU */
sahilmgandhi 18:6a4db94011d3 87 if (channel < 4) {
sahilmgandhi 18:6a4db94011d3 88 LPC_SCU->PINTSEL0 &= ~(0xFF << (portnum << 3));
sahilmgandhi 18:6a4db94011d3 89 LPC_SCU->PINTSEL0 |= (((portnum << 5) | pinnum) << (channel << 3));
sahilmgandhi 18:6a4db94011d3 90 } else {
sahilmgandhi 18:6a4db94011d3 91 LPC_SCU->PINTSEL1 &= ~(0xFF << ((portnum - 4) << 3));
sahilmgandhi 18:6a4db94011d3 92 LPC_SCU->PINTSEL1 |= (((portnum << 5) | pinnum) << ((channel - 4) << 3));
sahilmgandhi 18:6a4db94011d3 93 }
sahilmgandhi 18:6a4db94011d3 94
sahilmgandhi 18:6a4db94011d3 95 #if !defined(CORE_M0)
sahilmgandhi 18:6a4db94011d3 96 NVIC_SetVector((IRQn_Type)(PIN_INT0_IRQn + channel), (uint32_t)handle_interrupt_in);
sahilmgandhi 18:6a4db94011d3 97 NVIC_EnableIRQ((IRQn_Type)(PIN_INT0_IRQn + channel));
sahilmgandhi 18:6a4db94011d3 98 #else
sahilmgandhi 18:6a4db94011d3 99 NVIC_SetVector((IRQn_Type)PIN_INT4_IRQn, (uint32_t)handle_interrupt_in);
sahilmgandhi 18:6a4db94011d3 100 NVIC_EnableIRQ((IRQn_Type)PIN_INT4_IRQn);
sahilmgandhi 18:6a4db94011d3 101 #endif
sahilmgandhi 18:6a4db94011d3 102
sahilmgandhi 18:6a4db94011d3 103 // Increment channel number
sahilmgandhi 18:6a4db94011d3 104 channel++;
sahilmgandhi 18:6a4db94011d3 105 channel %= CHANNEL_MAX;
sahilmgandhi 18:6a4db94011d3 106
sahilmgandhi 18:6a4db94011d3 107 return 0;
sahilmgandhi 18:6a4db94011d3 108 }
sahilmgandhi 18:6a4db94011d3 109
sahilmgandhi 18:6a4db94011d3 110 void gpio_irq_free(gpio_irq_t *obj) {
sahilmgandhi 18:6a4db94011d3 111 channel_ids[obj->ch] = 0;
sahilmgandhi 18:6a4db94011d3 112 }
sahilmgandhi 18:6a4db94011d3 113
sahilmgandhi 18:6a4db94011d3 114 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
sahilmgandhi 18:6a4db94011d3 115 uint32_t pmask;
sahilmgandhi 18:6a4db94011d3 116
sahilmgandhi 18:6a4db94011d3 117 /* Clear pending interrupts */
sahilmgandhi 18:6a4db94011d3 118 pmask = (1 << obj->ch);
sahilmgandhi 18:6a4db94011d3 119 LPC_GPIO_PIN_INT->IST = pmask;
sahilmgandhi 18:6a4db94011d3 120
sahilmgandhi 18:6a4db94011d3 121 /* Configure pin interrupt */
sahilmgandhi 18:6a4db94011d3 122 LPC_GPIO_PIN_INT->ISEL &= ~pmask;
sahilmgandhi 18:6a4db94011d3 123 if (event == IRQ_RISE) {
sahilmgandhi 18:6a4db94011d3 124 /* Rising edge interrupts */
sahilmgandhi 18:6a4db94011d3 125 if (enable) {
sahilmgandhi 18:6a4db94011d3 126 LPC_GPIO_PIN_INT->SIENR |= pmask;
sahilmgandhi 18:6a4db94011d3 127 } else {
sahilmgandhi 18:6a4db94011d3 128 LPC_GPIO_PIN_INT->CIENR |= pmask;
sahilmgandhi 18:6a4db94011d3 129 }
sahilmgandhi 18:6a4db94011d3 130 } else {
sahilmgandhi 18:6a4db94011d3 131 /* Falling edge interrupts */
sahilmgandhi 18:6a4db94011d3 132 if (enable) {
sahilmgandhi 18:6a4db94011d3 133 LPC_GPIO_PIN_INT->SIENF |= pmask;
sahilmgandhi 18:6a4db94011d3 134 } else {
sahilmgandhi 18:6a4db94011d3 135 LPC_GPIO_PIN_INT->CIENF |= pmask;
sahilmgandhi 18:6a4db94011d3 136 }
sahilmgandhi 18:6a4db94011d3 137 }
sahilmgandhi 18:6a4db94011d3 138 }
sahilmgandhi 18:6a4db94011d3 139
sahilmgandhi 18:6a4db94011d3 140 void gpio_irq_enable(gpio_irq_t *obj) {
sahilmgandhi 18:6a4db94011d3 141 #if !defined(CORE_M0)
sahilmgandhi 18:6a4db94011d3 142 NVIC_EnableIRQ((IRQn_Type)(PIN_INT0_IRQn + obj->ch));
sahilmgandhi 18:6a4db94011d3 143 #else
sahilmgandhi 18:6a4db94011d3 144 NVIC_EnableIRQ((IRQn_Type)(PIN_INT4_IRQn + obj->ch));
sahilmgandhi 18:6a4db94011d3 145 #endif
sahilmgandhi 18:6a4db94011d3 146 }
sahilmgandhi 18:6a4db94011d3 147
sahilmgandhi 18:6a4db94011d3 148 void gpio_irq_disable(gpio_irq_t *obj) {
sahilmgandhi 18:6a4db94011d3 149 #if !defined(CORE_M0)
sahilmgandhi 18:6a4db94011d3 150 NVIC_DisableIRQ((IRQn_Type)(PIN_INT0_IRQn + obj->ch));
sahilmgandhi 18:6a4db94011d3 151 #else
sahilmgandhi 18:6a4db94011d3 152 NVIC_DisableIRQ((IRQn_Type)(PIN_INT4_IRQn + obj->ch));
sahilmgandhi 18:6a4db94011d3 153 #endif
sahilmgandhi 18:6a4db94011d3 154 }