MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NXP/TARGET_LPC43XX/ethernet_api.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2006-2015 ARM Limited
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 *
sahilmgandhi 18:6a4db94011d3 16 * Contribution by Nitin Bhaskar(nitin.bhaskar.27.09@gmail.com)
sahilmgandhi 18:6a4db94011d3 17 */
sahilmgandhi 18:6a4db94011d3 18 #include "ethernet_api.h"
sahilmgandhi 18:6a4db94011d3 19
sahilmgandhi 18:6a4db94011d3 20 #include <string.h>
sahilmgandhi 18:6a4db94011d3 21 #include "cmsis.h"
sahilmgandhi 18:6a4db94011d3 22 #include "mbed_interface.h"
sahilmgandhi 18:6a4db94011d3 23 #include "mbed_toolchain.h"
sahilmgandhi 18:6a4db94011d3 24 #include "mbed_error.h"
sahilmgandhi 18:6a4db94011d3 25 #include "pinmap.h"
sahilmgandhi 18:6a4db94011d3 26
sahilmgandhi 18:6a4db94011d3 27 #define NEW_LOGIC 0
sahilmgandhi 18:6a4db94011d3 28 #define NEW_ETH_BUFFER 0
sahilmgandhi 18:6a4db94011d3 29
sahilmgandhi 18:6a4db94011d3 30 #if NEW_ETH_BUFFER
sahilmgandhi 18:6a4db94011d3 31
sahilmgandhi 18:6a4db94011d3 32 #define NUM_RX_FRAG 4 // Number of Rx Fragments (== packets)
sahilmgandhi 18:6a4db94011d3 33 #define NUM_TX_FRAG 3 // Number of Tx Fragments (== packets)
sahilmgandhi 18:6a4db94011d3 34
sahilmgandhi 18:6a4db94011d3 35 #define ETH_MAX_FLEN 1536 // Maximum Ethernet Frame Size
sahilmgandhi 18:6a4db94011d3 36 #define ETH_FRAG_SIZE ETH_MAX_FLEN // Packet Fragment size (same as packet length)
sahilmgandhi 18:6a4db94011d3 37
sahilmgandhi 18:6a4db94011d3 38 #else
sahilmgandhi 18:6a4db94011d3 39
sahilmgandhi 18:6a4db94011d3 40 // Memfree calculation:
sahilmgandhi 18:6a4db94011d3 41 // (16 * 1024) - ((2 * 4 * NUM_RX) + (2 * 4 * NUM_RX) + (0x300 * NUM_RX) +
sahilmgandhi 18:6a4db94011d3 42 // (2 * 4 * NUM_TX) + (1 * 4 * NUM_TX) + (0x300 * NUM_TX)) = 8556
sahilmgandhi 18:6a4db94011d3 43 /* EMAC Memory Buffer configuration for 16K Ethernet RAM. */
sahilmgandhi 18:6a4db94011d3 44 #define NUM_RX_FRAG 4 /* Num.of RX Fragments 4*1536= 6.0kB */
sahilmgandhi 18:6a4db94011d3 45 #define NUM_TX_FRAG 3 /* Num.of TX Fragments 3*1536= 4.6kB */
sahilmgandhi 18:6a4db94011d3 46 //#define ETH_FRAG_SIZE 1536 /* Packet Fragment size 1536 Bytes */
sahilmgandhi 18:6a4db94011d3 47
sahilmgandhi 18:6a4db94011d3 48 //#define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */
sahilmgandhi 18:6a4db94011d3 49 #define ETH_FRAG_SIZE 0x300 /* Packet Fragment size 1536/2 Bytes */
sahilmgandhi 18:6a4db94011d3 50 #define ETH_MAX_FLEN 0x300 /* Max. Ethernet Frame Size */
sahilmgandhi 18:6a4db94011d3 51
sahilmgandhi 18:6a4db94011d3 52 const int ethernet_MTU_SIZE = 0x300;
sahilmgandhi 18:6a4db94011d3 53
sahilmgandhi 18:6a4db94011d3 54 #endif
sahilmgandhi 18:6a4db94011d3 55
sahilmgandhi 18:6a4db94011d3 56 #define ETHERNET_ADDR_SIZE 6
sahilmgandhi 18:6a4db94011d3 57
sahilmgandhi 18:6a4db94011d3 58 /* Descriptors Fields bits */
sahilmgandhi 18:6a4db94011d3 59 #define TRDES_OWN_BIT (1U<<31) /* Own bit in RDES0 & TDES0 */
sahilmgandhi 18:6a4db94011d3 60 #define RX_END_RING (1<<15) /* Receive End of Ring bit in RDES1 */
sahilmgandhi 18:6a4db94011d3 61 #define RX_NXTDESC_FLAG (1<<14) /* Second Address Chained bit in RDES1 */
sahilmgandhi 18:6a4db94011d3 62 #define TX_LAST_SEGM (1<<29) /* Last Segment bit in TDES0 */
sahilmgandhi 18:6a4db94011d3 63 #define TX_FIRST_SEGM (1<<28) /* First Segment bit in TDES0 */
sahilmgandhi 18:6a4db94011d3 64 #define TX_END_RING (1<<21) /* Transmit End of Ring bit in TDES0 */
sahilmgandhi 18:6a4db94011d3 65 #define TX_NXTDESC_FLAG (1<<20) /* Second Address Chained bit in TDES0 */
sahilmgandhi 18:6a4db94011d3 66
sahilmgandhi 18:6a4db94011d3 67 PACKED struct RX_DESC_TypeDef { /* RX Descriptor struct */
sahilmgandhi 18:6a4db94011d3 68 unsigned int Status;
sahilmgandhi 18:6a4db94011d3 69 unsigned int Ctrl;
sahilmgandhi 18:6a4db94011d3 70 unsigned int BufAddr1;
sahilmgandhi 18:6a4db94011d3 71 unsigned int NextDescAddr;
sahilmgandhi 18:6a4db94011d3 72 };
sahilmgandhi 18:6a4db94011d3 73 typedef struct RX_DESC_TypeDef RX_DESC_TypeDef;
sahilmgandhi 18:6a4db94011d3 74
sahilmgandhi 18:6a4db94011d3 75 PACKED struct TX_DESC_TypeDef { /* TX Descriptor struct */
sahilmgandhi 18:6a4db94011d3 76 unsigned int Status;
sahilmgandhi 18:6a4db94011d3 77 unsigned int Ctrl;
sahilmgandhi 18:6a4db94011d3 78 unsigned int BufAddr1;
sahilmgandhi 18:6a4db94011d3 79 unsigned int NextDescAddr;
sahilmgandhi 18:6a4db94011d3 80 };
sahilmgandhi 18:6a4db94011d3 81 typedef struct TX_DESC_TypeDef TX_DESC_TypeDef;
sahilmgandhi 18:6a4db94011d3 82
sahilmgandhi 18:6a4db94011d3 83 /* ETHMODE RMII SELECT */
sahilmgandhi 18:6a4db94011d3 84 #define RMII_SELECT 0x04
sahilmgandhi 18:6a4db94011d3 85 /* define to tell PHY about write operation */
sahilmgandhi 18:6a4db94011d3 86 #define MII_WRITE (1 << 1)
sahilmgandhi 18:6a4db94011d3 87 /* define to tell PHY about read operation */
sahilmgandhi 18:6a4db94011d3 88 #define MII_READ (0 << 1)
sahilmgandhi 18:6a4db94011d3 89 /* define to enable duplex mode */
sahilmgandhi 18:6a4db94011d3 90 #define MAC_DUPLEX_MODE (1 << 11)
sahilmgandhi 18:6a4db94011d3 91
sahilmgandhi 18:6a4db94011d3 92 /* MAC_FRAME_FILTER register bit defines */
sahilmgandhi 18:6a4db94011d3 93 #define MAC_FRAME_FILTER_PR (1 << 0) /* Promiscuous Mode */
sahilmgandhi 18:6a4db94011d3 94 #define MAC_FRAME_FILTER_RA (1UL << 31) /* Receive all */
sahilmgandhi 18:6a4db94011d3 95
sahilmgandhi 18:6a4db94011d3 96 /* MAC_CONFIG register bit defines */
sahilmgandhi 18:6a4db94011d3 97 #define MAC_CONFIG_RE (1 << 2) /* Receiver enable */
sahilmgandhi 18:6a4db94011d3 98 #define MAC_CONFIG_TE (1 << 3) /* Transmitter Enable */
sahilmgandhi 18:6a4db94011d3 99
sahilmgandhi 18:6a4db94011d3 100 /* DMA_OP_MODE register bit defines */
sahilmgandhi 18:6a4db94011d3 101 #define DMA_OP_MODE_SSR (1 << 1) /* Start/stop receive */
sahilmgandhi 18:6a4db94011d3 102 #define DMA_OP_MODE_SST (1 << 13) /* Start/Stop Transmission Command */
sahilmgandhi 18:6a4db94011d3 103
sahilmgandhi 18:6a4db94011d3 104 /* DMA_INT_EN register bit defines */
sahilmgandhi 18:6a4db94011d3 105 #define DMA_INT_EN_TIE (1 << 0) /* Transmit interrupt enable */
sahilmgandhi 18:6a4db94011d3 106 #define DMA_INT_EN_TSE (1 << 1) /* Transmit stopped enable */
sahilmgandhi 18:6a4db94011d3 107 #define DMA_INT_EN_TUE (1 << 2) /* Transmit buffer unavailable enable */
sahilmgandhi 18:6a4db94011d3 108 #define DMA_INT_EN_TJE (1 << 3) /* Transmit jabber timeout enable */
sahilmgandhi 18:6a4db94011d3 109 #define DMA_INT_EN_OVE (1 << 4) /* Overflow interrupt enable */
sahilmgandhi 18:6a4db94011d3 110 #define DMA_INT_EN_UNE (1 << 5) /* Underflow interrupt enable */
sahilmgandhi 18:6a4db94011d3 111 #define DMA_INT_EN_RIE (1 << 6) /* Receive interrupt enable */
sahilmgandhi 18:6a4db94011d3 112 #define DMA_INT_EN_RUE (1 << 7) /* Receive buffer unavailable enable */
sahilmgandhi 18:6a4db94011d3 113 #define DMA_INT_EN_RSE (1 << 8) /* Received stopped enable */
sahilmgandhi 18:6a4db94011d3 114 #define DMA_INT_EN_RWE (1 << 9) /* Receive watchdog timeout enable */
sahilmgandhi 18:6a4db94011d3 115 #define DMA_INT_EN_ETE (1 << 10) /* Early transmit interrupt enable */
sahilmgandhi 18:6a4db94011d3 116 #define DMA_INT_EN_FBE (1 << 13) /* Fatal bus error enable */
sahilmgandhi 18:6a4db94011d3 117 #define DMA_INT_EN_ERE (1 << 14) /* Early receive interrupt enable */
sahilmgandhi 18:6a4db94011d3 118 #define DMA_INT_EN_AIE (1 << 15) /* Abnormal interrupt summary enable */
sahilmgandhi 18:6a4db94011d3 119 #define DMA_INT_EN_NIE (1 << 16) /* Normal interrupt summary enable */
sahilmgandhi 18:6a4db94011d3 120
sahilmgandhi 18:6a4db94011d3 121
sahilmgandhi 18:6a4db94011d3 122
sahilmgandhi 18:6a4db94011d3 123 /* PHY Support Register */
sahilmgandhi 18:6a4db94011d3 124 #define SUPP_SPEED 0x00004000 /* Reduced MII Logic Current Speed */
sahilmgandhi 18:6a4db94011d3 125 //#define SUPP_RES_RMII 0x00000800 /* Reset Reduced MII Logic */
sahilmgandhi 18:6a4db94011d3 126 #define SUPP_RES_RMII 0x00000000 /* Reset Reduced MII Logic */
sahilmgandhi 18:6a4db94011d3 127
sahilmgandhi 18:6a4db94011d3 128 /* MII Management Command Register */
sahilmgandhi 18:6a4db94011d3 129 #define MCMD_READ 0x00000001 /* MII Read */
sahilmgandhi 18:6a4db94011d3 130 #define MCMD_SCAN 0x00000002 /* MII Scan continuously */
sahilmgandhi 18:6a4db94011d3 131
sahilmgandhi 18:6a4db94011d3 132 #define MII_WR_TOUT 0x00050000 /* MII Write timeout count */
sahilmgandhi 18:6a4db94011d3 133 #define MII_RD_TOUT 0x00050000 /* MII Read timeout count */
sahilmgandhi 18:6a4db94011d3 134
sahilmgandhi 18:6a4db94011d3 135 /* MII Management Address Register */
sahilmgandhi 18:6a4db94011d3 136 #define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */
sahilmgandhi 18:6a4db94011d3 137 #define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */
sahilmgandhi 18:6a4db94011d3 138
sahilmgandhi 18:6a4db94011d3 139 /* MII Management Indicators Register */
sahilmgandhi 18:6a4db94011d3 140 #define MIND_BUSY 0x00000001 /* MII is Busy */
sahilmgandhi 18:6a4db94011d3 141 #define MIND_SCAN 0x00000002 /* MII Scanning in Progress */
sahilmgandhi 18:6a4db94011d3 142 #define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */
sahilmgandhi 18:6a4db94011d3 143 #define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */
sahilmgandhi 18:6a4db94011d3 144
sahilmgandhi 18:6a4db94011d3 145 /* DP83848C PHY Registers */
sahilmgandhi 18:6a4db94011d3 146 #define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */
sahilmgandhi 18:6a4db94011d3 147 #define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */
sahilmgandhi 18:6a4db94011d3 148 #define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */
sahilmgandhi 18:6a4db94011d3 149 #define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */
sahilmgandhi 18:6a4db94011d3 150 #define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */
sahilmgandhi 18:6a4db94011d3 151 #define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */
sahilmgandhi 18:6a4db94011d3 152 #define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */
sahilmgandhi 18:6a4db94011d3 153 #define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */
sahilmgandhi 18:6a4db94011d3 154
sahilmgandhi 18:6a4db94011d3 155 /* PHY Extended Registers */
sahilmgandhi 18:6a4db94011d3 156 #define PHY_REG_STS 0x10 /* Status Register */
sahilmgandhi 18:6a4db94011d3 157 #define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */
sahilmgandhi 18:6a4db94011d3 158 #define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */
sahilmgandhi 18:6a4db94011d3 159 #define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */
sahilmgandhi 18:6a4db94011d3 160 #define PHY_REG_RECR 0x15 /* Receive Error Counter */
sahilmgandhi 18:6a4db94011d3 161 #define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */
sahilmgandhi 18:6a4db94011d3 162 #define PHY_REG_RBR 0x17 /* RMII and Bypass Register */
sahilmgandhi 18:6a4db94011d3 163 #define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */
sahilmgandhi 18:6a4db94011d3 164 #define PHY_REG_PHYCR 0x19 /* PHY Control Register */
sahilmgandhi 18:6a4db94011d3 165 #define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */
sahilmgandhi 18:6a4db94011d3 166 #define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */
sahilmgandhi 18:6a4db94011d3 167 #define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */
sahilmgandhi 18:6a4db94011d3 168
sahilmgandhi 18:6a4db94011d3 169 #define PHY_REG_SCSR 0x1F /* PHY Special Control/Status Register */
sahilmgandhi 18:6a4db94011d3 170
sahilmgandhi 18:6a4db94011d3 171 #define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */
sahilmgandhi 18:6a4db94011d3 172 #define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */
sahilmgandhi 18:6a4db94011d3 173 #define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */
sahilmgandhi 18:6a4db94011d3 174 #define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */
sahilmgandhi 18:6a4db94011d3 175 #define PHY_AUTO_NEG 0x1000 /* Select Auto Negotiation */
sahilmgandhi 18:6a4db94011d3 176
sahilmgandhi 18:6a4db94011d3 177 #define DP83848C_DEF_ADR 0x01 /* Default PHY device address */
sahilmgandhi 18:6a4db94011d3 178 #define DP83848C_ID 0x20005C90 /* PHY Identifier - DP83848C */
sahilmgandhi 18:6a4db94011d3 179
sahilmgandhi 18:6a4db94011d3 180 #define LAN8720_ID 0x0007C0F0 /* PHY Identifier - LAN8720 */
sahilmgandhi 18:6a4db94011d3 181
sahilmgandhi 18:6a4db94011d3 182 #define PHY_STS_LINK 0x0001 /* PHY Status Link Mask */
sahilmgandhi 18:6a4db94011d3 183 #define PHY_STS_SPEED 0x0002 /* PHY Status Speed Mask */
sahilmgandhi 18:6a4db94011d3 184 #define PHY_STS_DUPLEX 0x0004 /* PHY Status Duplex Mask */
sahilmgandhi 18:6a4db94011d3 185
sahilmgandhi 18:6a4db94011d3 186 #define PHY_BMCR_RESET 0x8000 /* PHY Reset */
sahilmgandhi 18:6a4db94011d3 187
sahilmgandhi 18:6a4db94011d3 188 #define PHY_BMSR_LINK 0x0004 /* PHY BMSR Link valid */
sahilmgandhi 18:6a4db94011d3 189
sahilmgandhi 18:6a4db94011d3 190 #define PHY_SCSR_100MBIT 0x0008 /* Speed: 1=100 MBit, 0=10Mbit */
sahilmgandhi 18:6a4db94011d3 191 #define PHY_SCSR_DUPLEX 0x0010 /* PHY Duplex Mask */
sahilmgandhi 18:6a4db94011d3 192
sahilmgandhi 18:6a4db94011d3 193 static int phy_read(unsigned int PhyReg);
sahilmgandhi 18:6a4db94011d3 194 static int phy_write(unsigned int PhyReg, unsigned short Data);
sahilmgandhi 18:6a4db94011d3 195
sahilmgandhi 18:6a4db94011d3 196 static void txdscr_init(void);
sahilmgandhi 18:6a4db94011d3 197 static void rxdscr_init(void);
sahilmgandhi 18:6a4db94011d3 198
sahilmgandhi 18:6a4db94011d3 199 #if defined (__ICCARM__)
sahilmgandhi 18:6a4db94011d3 200 # define AHBSRAM1
sahilmgandhi 18:6a4db94011d3 201 #elif defined(TOOLCHAIN_GCC_CR)
sahilmgandhi 18:6a4db94011d3 202 # define AHBSRAM1 __attribute__((section(".data.$RamPeriph32")))
sahilmgandhi 18:6a4db94011d3 203 #else
sahilmgandhi 18:6a4db94011d3 204 # define AHBSRAM1 __attribute__((section("AHBSRAM1"),aligned))
sahilmgandhi 18:6a4db94011d3 205 #endif
sahilmgandhi 18:6a4db94011d3 206
sahilmgandhi 18:6a4db94011d3 207 AHBSRAM1 volatile uint8_t rxbuf[NUM_RX_FRAG][ETH_FRAG_SIZE];
sahilmgandhi 18:6a4db94011d3 208 AHBSRAM1 volatile uint8_t txbuf[NUM_TX_FRAG][ETH_FRAG_SIZE];
sahilmgandhi 18:6a4db94011d3 209 AHBSRAM1 volatile RX_DESC_TypeDef rxdesc[NUM_RX_FRAG];
sahilmgandhi 18:6a4db94011d3 210 AHBSRAM1 volatile TX_DESC_TypeDef txdesc[NUM_TX_FRAG];
sahilmgandhi 18:6a4db94011d3 211
sahilmgandhi 18:6a4db94011d3 212 #ifndef min
sahilmgandhi 18:6a4db94011d3 213 #define min(x, y) (((x)<(y))?(x):(y))
sahilmgandhi 18:6a4db94011d3 214 #endif
sahilmgandhi 18:6a4db94011d3 215
sahilmgandhi 18:6a4db94011d3 216 static uint32_t phy_id = 0;
sahilmgandhi 18:6a4db94011d3 217 static uint32_t TxDescIndex = 0;
sahilmgandhi 18:6a4db94011d3 218 static uint32_t RxDescIndex = 0;
sahilmgandhi 18:6a4db94011d3 219 static uint32_t RxOffset = 0;
sahilmgandhi 18:6a4db94011d3 220
sahilmgandhi 18:6a4db94011d3 221 /*----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 222 Ethernet Device initialize
sahilmgandhi 18:6a4db94011d3 223 *----------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 224 int ethernet_init()
sahilmgandhi 18:6a4db94011d3 225 {
sahilmgandhi 18:6a4db94011d3 226 int regv, tout;
sahilmgandhi 18:6a4db94011d3 227 char mac[ETHERNET_ADDR_SIZE];
sahilmgandhi 18:6a4db94011d3 228
sahilmgandhi 18:6a4db94011d3 229 pin_function(PC_0, (SCU_MODE_INACT | FUNC3)); /* Enable ENET RX CLK */
sahilmgandhi 18:6a4db94011d3 230 pin_function(P1_19, (SCU_MODE_INACT | FUNC0)); /* Enable ENET TX CLK */
sahilmgandhi 18:6a4db94011d3 231
sahilmgandhi 18:6a4db94011d3 232 /* Ethernet pinmuxing */
sahilmgandhi 18:6a4db94011d3 233 pin_function(P2_0, SCU_PINIO_FAST | FUNC7); /* ENET_MDC */
sahilmgandhi 18:6a4db94011d3 234 pin_function(P1_17, SCU_PINIO_FAST | FUNC3); /* ENET_MDIO */
sahilmgandhi 18:6a4db94011d3 235 pin_function(P1_18, SCU_PINIO_FAST | FUNC3); /* ENET_TXD0 */
sahilmgandhi 18:6a4db94011d3 236 pin_function(P1_20, SCU_PINIO_FAST | FUNC3); /* ENET_TXD1 */
sahilmgandhi 18:6a4db94011d3 237 pin_function(P1_19, SCU_PINIO_FAST | FUNC0); /* ENET_REF */
sahilmgandhi 18:6a4db94011d3 238 pin_function(P0_1, SCU_PINIO_FAST | FUNC6); /* ENET_TX_EN */
sahilmgandhi 18:6a4db94011d3 239 pin_function(P1_15, SCU_PINIO_FAST | FUNC3); /* ENET_RXD0 */
sahilmgandhi 18:6a4db94011d3 240 pin_function(P0_0, SCU_PINIO_FAST | FUNC2); /* ENET_RXD1 */
sahilmgandhi 18:6a4db94011d3 241 pin_function(P1_16, SCU_PINIO_FAST | FUNC3); /* ENET_CRS */
sahilmgandhi 18:6a4db94011d3 242 pin_function(PC_9, SCU_PINIO_FAST | FUNC3); /* ENET_RX_ER */
sahilmgandhi 18:6a4db94011d3 243 pin_function(P1_16, SCU_PINIO_FAST | FUNC7); /* ENET_RXDV */
sahilmgandhi 18:6a4db94011d3 244
sahilmgandhi 18:6a4db94011d3 245 LPC_CREG->CREG6 |= RMII_SELECT;
sahilmgandhi 18:6a4db94011d3 246
sahilmgandhi 18:6a4db94011d3 247 /* perform RGU soft reset */
sahilmgandhi 18:6a4db94011d3 248 LPC_RGU->RESET_CTRL0 = 1 << 22;
sahilmgandhi 18:6a4db94011d3 249 LPC_RGU->RESET_CTRL0 = 0;
sahilmgandhi 18:6a4db94011d3 250
sahilmgandhi 18:6a4db94011d3 251 /* Wait until reset is performed */
sahilmgandhi 18:6a4db94011d3 252 while(1) {
sahilmgandhi 18:6a4db94011d3 253 if (LPC_RGU->RESET_ACTIVE_STATUS0 & (1 << 22))
sahilmgandhi 18:6a4db94011d3 254 break;
sahilmgandhi 18:6a4db94011d3 255 }
sahilmgandhi 18:6a4db94011d3 256
sahilmgandhi 18:6a4db94011d3 257 /* Reset MAC DMA Controller */
sahilmgandhi 18:6a4db94011d3 258 LPC_ETHERNET->DMA_BUS_MODE |= 0x01;
sahilmgandhi 18:6a4db94011d3 259 while(LPC_ETHERNET->DMA_BUS_MODE & 0x01);
sahilmgandhi 18:6a4db94011d3 260
sahilmgandhi 18:6a4db94011d3 261 phy_write(PHY_REG_BMCR, PHY_BMCR_RESET); /* perform PHY reset */
sahilmgandhi 18:6a4db94011d3 262
sahilmgandhi 18:6a4db94011d3 263 for(tout = 0x20000; ; tout--) { /* Wait for hardware reset to end. */
sahilmgandhi 18:6a4db94011d3 264 regv = phy_read(PHY_REG_BMCR);
sahilmgandhi 18:6a4db94011d3 265 if(regv < 0 || tout == 0) {
sahilmgandhi 18:6a4db94011d3 266 return -1; /* Error */
sahilmgandhi 18:6a4db94011d3 267 }
sahilmgandhi 18:6a4db94011d3 268 if(!(regv & PHY_BMCR_RESET)) {
sahilmgandhi 18:6a4db94011d3 269 break; /* Reset complete. */
sahilmgandhi 18:6a4db94011d3 270 }
sahilmgandhi 18:6a4db94011d3 271 }
sahilmgandhi 18:6a4db94011d3 272
sahilmgandhi 18:6a4db94011d3 273 phy_id = (phy_read(PHY_REG_IDR1) << 16);
sahilmgandhi 18:6a4db94011d3 274 phy_id |= (phy_read(PHY_REG_IDR2) & 0XFFF0);
sahilmgandhi 18:6a4db94011d3 275
sahilmgandhi 18:6a4db94011d3 276 if (phy_id != DP83848C_ID && phy_id != LAN8720_ID) {
sahilmgandhi 18:6a4db94011d3 277 error("Unknown Ethernet PHY (%x)", (unsigned int)phy_id);
sahilmgandhi 18:6a4db94011d3 278 }
sahilmgandhi 18:6a4db94011d3 279
sahilmgandhi 18:6a4db94011d3 280 ethernet_set_link(-1, 0);
sahilmgandhi 18:6a4db94011d3 281
sahilmgandhi 18:6a4db94011d3 282 /* Set the Ethernet MAC Address registers */
sahilmgandhi 18:6a4db94011d3 283 ethernet_address(mac);
sahilmgandhi 18:6a4db94011d3 284 LPC_ETHERNET->MAC_ADDR0_HIGH = (mac[5] << 8) | mac[4];
sahilmgandhi 18:6a4db94011d3 285 LPC_ETHERNET->MAC_ADDR0_LOW = (mac[3] << 24) | (mac[2] << 16) | (mac[1] << 8) | mac[0];
sahilmgandhi 18:6a4db94011d3 286
sahilmgandhi 18:6a4db94011d3 287 txdscr_init(); /* initialize DMA TX Descriptor */
sahilmgandhi 18:6a4db94011d3 288 rxdscr_init(); /* initialize DMA RX Descriptor */
sahilmgandhi 18:6a4db94011d3 289
sahilmgandhi 18:6a4db94011d3 290 /* Configure Filter */
sahilmgandhi 18:6a4db94011d3 291 LPC_ETHERNET->MAC_FRAME_FILTER = MAC_FRAME_FILTER_PR | MAC_FRAME_FILTER_RA;
sahilmgandhi 18:6a4db94011d3 292
sahilmgandhi 18:6a4db94011d3 293 /* Enable Receiver and Transmitter */
sahilmgandhi 18:6a4db94011d3 294 LPC_ETHERNET->MAC_CONFIG |= (MAC_CONFIG_RE | MAC_CONFIG_TE);
sahilmgandhi 18:6a4db94011d3 295
sahilmgandhi 18:6a4db94011d3 296 //LPC_ETHERNET->DMA_INT_EN = DMA_INT_EN_NIE | DMA_INT_EN_RIE | DMA_INT_EN_TJE; /* Enable EMAC interrupts. */
sahilmgandhi 18:6a4db94011d3 297
sahilmgandhi 18:6a4db94011d3 298 /* Start Transmission & Receive processes */
sahilmgandhi 18:6a4db94011d3 299 LPC_ETHERNET->DMA_OP_MODE |= (DMA_OP_MODE_SST | DMA_OP_MODE_SSR);
sahilmgandhi 18:6a4db94011d3 300
sahilmgandhi 18:6a4db94011d3 301 return 0;
sahilmgandhi 18:6a4db94011d3 302 }
sahilmgandhi 18:6a4db94011d3 303
sahilmgandhi 18:6a4db94011d3 304 /*----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 305 Ethernet Device Uninitialize
sahilmgandhi 18:6a4db94011d3 306 *----------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 307 void ethernet_free()
sahilmgandhi 18:6a4db94011d3 308 {
sahilmgandhi 18:6a4db94011d3 309 }
sahilmgandhi 18:6a4db94011d3 310
sahilmgandhi 18:6a4db94011d3 311 /*----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 312 Ethernet write
sahilmgandhi 18:6a4db94011d3 313 *----------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 314 int ethernet_write(const char *data, int slen)
sahilmgandhi 18:6a4db94011d3 315 {
sahilmgandhi 18:6a4db94011d3 316 if (slen > ETH_FRAG_SIZE)
sahilmgandhi 18:6a4db94011d3 317 return -1;
sahilmgandhi 18:6a4db94011d3 318
sahilmgandhi 18:6a4db94011d3 319 txdesc[TxDescIndex].Ctrl = slen;
sahilmgandhi 18:6a4db94011d3 320 memcpy((void *)txdesc[TxDescIndex].BufAddr1, data, slen);
sahilmgandhi 18:6a4db94011d3 321 return slen;
sahilmgandhi 18:6a4db94011d3 322 }
sahilmgandhi 18:6a4db94011d3 323
sahilmgandhi 18:6a4db94011d3 324 /*----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 325 Ethernet Send
sahilmgandhi 18:6a4db94011d3 326 *----------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 327 int ethernet_send()
sahilmgandhi 18:6a4db94011d3 328 {
sahilmgandhi 18:6a4db94011d3 329 int s = txdesc[TxDescIndex].Ctrl;
sahilmgandhi 18:6a4db94011d3 330 txdesc[TxDescIndex].Status |= TRDES_OWN_BIT;
sahilmgandhi 18:6a4db94011d3 331 LPC_ETHERNET->DMA_TRANS_POLL_DEMAND = 1; // Wake Up the DMA if it's in Suspended Mode
sahilmgandhi 18:6a4db94011d3 332 TxDescIndex++;
sahilmgandhi 18:6a4db94011d3 333 if (TxDescIndex == NUM_TX_FRAG)
sahilmgandhi 18:6a4db94011d3 334 TxDescIndex = 0;
sahilmgandhi 18:6a4db94011d3 335
sahilmgandhi 18:6a4db94011d3 336 return s;
sahilmgandhi 18:6a4db94011d3 337 }
sahilmgandhi 18:6a4db94011d3 338
sahilmgandhi 18:6a4db94011d3 339 /*----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 340 Ethernet receive
sahilmgandhi 18:6a4db94011d3 341 *----------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 342 int ethernet_receive()
sahilmgandhi 18:6a4db94011d3 343 {
sahilmgandhi 18:6a4db94011d3 344 int i, slen = 0;
sahilmgandhi 18:6a4db94011d3 345 for (i = RxDescIndex;; i++) {
sahilmgandhi 18:6a4db94011d3 346 if (rxdesc[i].Status & TRDES_OWN_BIT)
sahilmgandhi 18:6a4db94011d3 347 return (slen - RxOffset);
sahilmgandhi 18:6a4db94011d3 348 else
sahilmgandhi 18:6a4db94011d3 349 slen += (rxdesc[i].Status >> 16) & 0x03FFF;
sahilmgandhi 18:6a4db94011d3 350 }
sahilmgandhi 18:6a4db94011d3 351 return 0;
sahilmgandhi 18:6a4db94011d3 352 }
sahilmgandhi 18:6a4db94011d3 353
sahilmgandhi 18:6a4db94011d3 354
sahilmgandhi 18:6a4db94011d3 355 /*----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 356 Ethernet read
sahilmgandhi 18:6a4db94011d3 357 *----------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 358 int ethernet_read(char *data, int dlen)
sahilmgandhi 18:6a4db94011d3 359 {
sahilmgandhi 18:6a4db94011d3 360 int copylen;
sahilmgandhi 18:6a4db94011d3 361 uint32_t *pSrc = (uint32_t *)rxdesc[RxDescIndex].BufAddr1;
sahilmgandhi 18:6a4db94011d3 362 copylen = (rxdesc[RxDescIndex].Status >> 16) & 0x03FFF;
sahilmgandhi 18:6a4db94011d3 363 if (rxdesc[RxDescIndex].Status & TRDES_OWN_BIT || (dlen + RxOffset) > copylen)
sahilmgandhi 18:6a4db94011d3 364 return -1;
sahilmgandhi 18:6a4db94011d3 365
sahilmgandhi 18:6a4db94011d3 366 if ((dlen + RxOffset) == copylen) {
sahilmgandhi 18:6a4db94011d3 367 memcpy(&pSrc[RxOffset], data, copylen);
sahilmgandhi 18:6a4db94011d3 368 rxdesc[RxDescIndex].Status = TRDES_OWN_BIT;
sahilmgandhi 18:6a4db94011d3 369 RxDescIndex++;
sahilmgandhi 18:6a4db94011d3 370 RxOffset = 0;
sahilmgandhi 18:6a4db94011d3 371 if (RxDescIndex == NUM_RX_FRAG)
sahilmgandhi 18:6a4db94011d3 372 RxDescIndex = 0;
sahilmgandhi 18:6a4db94011d3 373 } else if ((dlen + RxOffset) < copylen) {
sahilmgandhi 18:6a4db94011d3 374 copylen = dlen;
sahilmgandhi 18:6a4db94011d3 375 memcpy(&pSrc[RxOffset], data, copylen);
sahilmgandhi 18:6a4db94011d3 376 RxOffset += dlen;
sahilmgandhi 18:6a4db94011d3 377 }
sahilmgandhi 18:6a4db94011d3 378 return copylen;
sahilmgandhi 18:6a4db94011d3 379 }
sahilmgandhi 18:6a4db94011d3 380
sahilmgandhi 18:6a4db94011d3 381 int ethernet_link(void)
sahilmgandhi 18:6a4db94011d3 382 {
sahilmgandhi 18:6a4db94011d3 383
sahilmgandhi 18:6a4db94011d3 384 if (phy_id == DP83848C_ID) {
sahilmgandhi 18:6a4db94011d3 385 return (phy_read(PHY_REG_STS) & PHY_STS_LINK);
sahilmgandhi 18:6a4db94011d3 386 } else { // LAN8720_ID
sahilmgandhi 18:6a4db94011d3 387 return (phy_read(PHY_REG_BMSR) & PHY_BMSR_LINK);
sahilmgandhi 18:6a4db94011d3 388 }
sahilmgandhi 18:6a4db94011d3 389 }
sahilmgandhi 18:6a4db94011d3 390
sahilmgandhi 18:6a4db94011d3 391 static int phy_write(unsigned int PhyReg, unsigned short Data)
sahilmgandhi 18:6a4db94011d3 392 {
sahilmgandhi 18:6a4db94011d3 393 unsigned int timeOut;
sahilmgandhi 18:6a4db94011d3 394
sahilmgandhi 18:6a4db94011d3 395 while(LPC_ETHERNET->MAC_MII_ADDR & MIND_BUSY);
sahilmgandhi 18:6a4db94011d3 396 LPC_ETHERNET->MAC_MII_ADDR = (DP83848C_DEF_ADR<<11) | (PhyReg<<6) | MII_WRITE;
sahilmgandhi 18:6a4db94011d3 397 LPC_ETHERNET->MAC_MII_DATA = Data;
sahilmgandhi 18:6a4db94011d3 398 LPC_ETHERNET->MAC_MII_ADDR |= MIND_BUSY; // Start PHY Write Cycle
sahilmgandhi 18:6a4db94011d3 399
sahilmgandhi 18:6a4db94011d3 400 /* Wait utill operation completed */
sahilmgandhi 18:6a4db94011d3 401 for (timeOut = 0; timeOut < MII_WR_TOUT; timeOut++) {
sahilmgandhi 18:6a4db94011d3 402 if ((LPC_ETHERNET->MAC_MII_ADDR & MIND_BUSY) == 0) {
sahilmgandhi 18:6a4db94011d3 403 break;
sahilmgandhi 18:6a4db94011d3 404 }
sahilmgandhi 18:6a4db94011d3 405 }
sahilmgandhi 18:6a4db94011d3 406
sahilmgandhi 18:6a4db94011d3 407 return -1;
sahilmgandhi 18:6a4db94011d3 408 }
sahilmgandhi 18:6a4db94011d3 409
sahilmgandhi 18:6a4db94011d3 410 static int phy_read(unsigned int PhyReg)
sahilmgandhi 18:6a4db94011d3 411 {
sahilmgandhi 18:6a4db94011d3 412 unsigned int timeOut;
sahilmgandhi 18:6a4db94011d3 413
sahilmgandhi 18:6a4db94011d3 414 while(LPC_ETHERNET->MAC_MII_ADDR & MIND_BUSY);
sahilmgandhi 18:6a4db94011d3 415 LPC_ETHERNET->MAC_MII_ADDR = (DP83848C_DEF_ADR<<11) | (PhyReg<<6) | MII_READ;
sahilmgandhi 18:6a4db94011d3 416 LPC_ETHERNET->MAC_MII_ADDR |= MIND_BUSY;
sahilmgandhi 18:6a4db94011d3 417
sahilmgandhi 18:6a4db94011d3 418 for(timeOut = 0; timeOut < MII_RD_TOUT; timeOut++) { /* Wait until operation completed */
sahilmgandhi 18:6a4db94011d3 419 if((LPC_ETHERNET->MAC_MII_ADDR & MIND_BUSY) == 0) {
sahilmgandhi 18:6a4db94011d3 420 return LPC_ETHERNET->MAC_MII_DATA; /* Return a 16-bit value. */
sahilmgandhi 18:6a4db94011d3 421 }
sahilmgandhi 18:6a4db94011d3 422 }
sahilmgandhi 18:6a4db94011d3 423
sahilmgandhi 18:6a4db94011d3 424 return -1;
sahilmgandhi 18:6a4db94011d3 425 }
sahilmgandhi 18:6a4db94011d3 426
sahilmgandhi 18:6a4db94011d3 427 static void txdscr_init()
sahilmgandhi 18:6a4db94011d3 428 {
sahilmgandhi 18:6a4db94011d3 429 int i;
sahilmgandhi 18:6a4db94011d3 430
sahilmgandhi 18:6a4db94011d3 431 for(i = 0; i < NUM_TX_FRAG; i++) {
sahilmgandhi 18:6a4db94011d3 432 txdesc[i].Status = TX_LAST_SEGM | TX_FIRST_SEGM;;
sahilmgandhi 18:6a4db94011d3 433 txdesc[i].Ctrl = 0;
sahilmgandhi 18:6a4db94011d3 434 txdesc[i].BufAddr1 = (uint32_t)&txbuf[i];
sahilmgandhi 18:6a4db94011d3 435 if (i == (NUM_TX_FRAG - 1)) {
sahilmgandhi 18:6a4db94011d3 436 txdesc[i].Status |= TX_END_RING;
sahilmgandhi 18:6a4db94011d3 437 }
sahilmgandhi 18:6a4db94011d3 438 }
sahilmgandhi 18:6a4db94011d3 439
sahilmgandhi 18:6a4db94011d3 440 LPC_ETHERNET->DMA_TRANS_DES_ADDR = (uint32_t)txdesc; /* Set EMAC Transmit Descriptor Registers. */
sahilmgandhi 18:6a4db94011d3 441 }
sahilmgandhi 18:6a4db94011d3 442
sahilmgandhi 18:6a4db94011d3 443
sahilmgandhi 18:6a4db94011d3 444 static void rxdscr_init()
sahilmgandhi 18:6a4db94011d3 445 {
sahilmgandhi 18:6a4db94011d3 446 int i;
sahilmgandhi 18:6a4db94011d3 447
sahilmgandhi 18:6a4db94011d3 448 for(i = 0; i < NUM_RX_FRAG; i++) {
sahilmgandhi 18:6a4db94011d3 449 rxdesc[i].Status = TRDES_OWN_BIT;
sahilmgandhi 18:6a4db94011d3 450 rxdesc[i].Ctrl = ETH_FRAG_SIZE;
sahilmgandhi 18:6a4db94011d3 451 rxdesc[i].BufAddr1 = (uint32_t)&rxbuf[i];
sahilmgandhi 18:6a4db94011d3 452 if (i == (NUM_RX_FRAG - 1)) {
sahilmgandhi 18:6a4db94011d3 453 rxdesc[i].Ctrl |= RX_END_RING;
sahilmgandhi 18:6a4db94011d3 454 }
sahilmgandhi 18:6a4db94011d3 455 }
sahilmgandhi 18:6a4db94011d3 456
sahilmgandhi 18:6a4db94011d3 457 LPC_ETHERNET->DMA_REC_DES_ADDR = (uint32_t)rxdesc; /* Set EMAC Receive Descriptor Registers. */
sahilmgandhi 18:6a4db94011d3 458 }
sahilmgandhi 18:6a4db94011d3 459
sahilmgandhi 18:6a4db94011d3 460 void ethernet_address(char *mac)
sahilmgandhi 18:6a4db94011d3 461 {
sahilmgandhi 18:6a4db94011d3 462 mbed_mac_address(mac);
sahilmgandhi 18:6a4db94011d3 463 }
sahilmgandhi 18:6a4db94011d3 464
sahilmgandhi 18:6a4db94011d3 465 void ethernet_set_link(int speed, int duplex)
sahilmgandhi 18:6a4db94011d3 466 {
sahilmgandhi 18:6a4db94011d3 467 volatile unsigned short phy_data;
sahilmgandhi 18:6a4db94011d3 468 int tout;
sahilmgandhi 18:6a4db94011d3 469
sahilmgandhi 18:6a4db94011d3 470 if((speed < 0) || (speed > 1)) {
sahilmgandhi 18:6a4db94011d3 471
sahilmgandhi 18:6a4db94011d3 472 phy_data = PHY_AUTO_NEG;
sahilmgandhi 18:6a4db94011d3 473
sahilmgandhi 18:6a4db94011d3 474 } else {
sahilmgandhi 18:6a4db94011d3 475
sahilmgandhi 18:6a4db94011d3 476 phy_data = (((unsigned short) speed << 13) |
sahilmgandhi 18:6a4db94011d3 477 ((unsigned short) duplex << 8));
sahilmgandhi 18:6a4db94011d3 478 }
sahilmgandhi 18:6a4db94011d3 479
sahilmgandhi 18:6a4db94011d3 480 phy_write(PHY_REG_BMCR, phy_data);
sahilmgandhi 18:6a4db94011d3 481
sahilmgandhi 18:6a4db94011d3 482 for(tout = 100; tout; tout--) {
sahilmgandhi 18:6a4db94011d3 483 __NOP(); /* A short delay */
sahilmgandhi 18:6a4db94011d3 484 }
sahilmgandhi 18:6a4db94011d3 485
sahilmgandhi 18:6a4db94011d3 486 switch(phy_id) {
sahilmgandhi 18:6a4db94011d3 487 case DP83848C_ID:
sahilmgandhi 18:6a4db94011d3 488
sahilmgandhi 18:6a4db94011d3 489 phy_data = phy_read(PHY_REG_STS);
sahilmgandhi 18:6a4db94011d3 490
sahilmgandhi 18:6a4db94011d3 491 if(phy_data & PHY_STS_DUPLEX) {
sahilmgandhi 18:6a4db94011d3 492 /* Full duplex is enabled. */
sahilmgandhi 18:6a4db94011d3 493 LPC_ETHERNET->MAC_CONFIG |= MAC_DUPLEX_MODE;
sahilmgandhi 18:6a4db94011d3 494 } else {
sahilmgandhi 18:6a4db94011d3 495 LPC_ETHERNET->MAC_CONFIG &= ~MAC_DUPLEX_MODE;
sahilmgandhi 18:6a4db94011d3 496 }
sahilmgandhi 18:6a4db94011d3 497
sahilmgandhi 18:6a4db94011d3 498 if(phy_data & PHY_STS_SPEED) {
sahilmgandhi 18:6a4db94011d3 499 LPC_ETHERNET->MAC_CONFIG &= ~SUPP_SPEED;
sahilmgandhi 18:6a4db94011d3 500 } else {
sahilmgandhi 18:6a4db94011d3 501 LPC_ETHERNET->MAC_CONFIG |= SUPP_SPEED;
sahilmgandhi 18:6a4db94011d3 502 }
sahilmgandhi 18:6a4db94011d3 503 break;
sahilmgandhi 18:6a4db94011d3 504
sahilmgandhi 18:6a4db94011d3 505 case LAN8720_ID:
sahilmgandhi 18:6a4db94011d3 506
sahilmgandhi 18:6a4db94011d3 507 for(tout = 100; tout; tout--) {
sahilmgandhi 18:6a4db94011d3 508 phy_data = phy_read(PHY_REG_BMSR);
sahilmgandhi 18:6a4db94011d3 509 if (phy_data & PHY_STS_DUPLEX)
sahilmgandhi 18:6a4db94011d3 510 break;
sahilmgandhi 18:6a4db94011d3 511 }
sahilmgandhi 18:6a4db94011d3 512
sahilmgandhi 18:6a4db94011d3 513 if (phy_data & PHY_STS_DUPLEX) {
sahilmgandhi 18:6a4db94011d3 514 /* Full duplex is enabled. */
sahilmgandhi 18:6a4db94011d3 515 LPC_ETHERNET->MAC_CONFIG |= MAC_DUPLEX_MODE;
sahilmgandhi 18:6a4db94011d3 516 } else {
sahilmgandhi 18:6a4db94011d3 517 LPC_ETHERNET->MAC_CONFIG &= ~MAC_DUPLEX_MODE;
sahilmgandhi 18:6a4db94011d3 518 }
sahilmgandhi 18:6a4db94011d3 519
sahilmgandhi 18:6a4db94011d3 520 if(phy_data & PHY_STS_SPEED) {
sahilmgandhi 18:6a4db94011d3 521 LPC_ETHERNET->MAC_CONFIG &= ~SUPP_SPEED;
sahilmgandhi 18:6a4db94011d3 522 } else {
sahilmgandhi 18:6a4db94011d3 523 LPC_ETHERNET->MAC_CONFIG |= SUPP_SPEED;
sahilmgandhi 18:6a4db94011d3 524 }
sahilmgandhi 18:6a4db94011d3 525 break;
sahilmgandhi 18:6a4db94011d3 526 }
sahilmgandhi 18:6a4db94011d3 527 }
sahilmgandhi 18:6a4db94011d3 528