MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NXP/TARGET_LPC43XX/README.txt@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 mbed port to NXP LPC43xx
sahilmgandhi 18:6a4db94011d3 2 ========================
sahilmgandhi 18:6a4db94011d3 3 Updated: 07/11/14
sahilmgandhi 18:6a4db94011d3 4
sahilmgandhi 18:6a4db94011d3 5 The NXP LPC43xx microcontrollers includes multiple Cortex-M cores in a single
sahilmgandhi 18:6a4db94011d3 6 microcontroller package. This port allows mbed developers to take advantage
sahilmgandhi 18:6a4db94011d3 7 of the LPC43xx in their application using APIs that they are familiar with.
sahilmgandhi 18:6a4db94011d3 8 Some of the key features of the LPC43xx include:
sahilmgandhi 18:6a4db94011d3 9
sahilmgandhi 18:6a4db94011d3 10 * Dual core ARM Cortex-M4/M0 both capable of up to 204 MHz
sahilmgandhi 18:6a4db94011d3 11 * Up to 264 KB SRAM, 1 MB internal flash
sahilmgandhi 18:6a4db94011d3 12 * Two High-speed USB 2.0 interfaces
sahilmgandhi 18:6a4db94011d3 13 * Ethernet MAC
sahilmgandhi 18:6a4db94011d3 14 * LCD interface
sahilmgandhi 18:6a4db94011d3 15 * Quad-SPI Flash Interface (SPIFI)
sahilmgandhi 18:6a4db94011d3 16 * State Configurable Timer (SCT)
sahilmgandhi 18:6a4db94011d3 17 * Serial GPIO (SGPIO)
sahilmgandhi 18:6a4db94011d3 18 * Up to 164 GPIO
sahilmgandhi 18:6a4db94011d3 19
sahilmgandhi 18:6a4db94011d3 20 The NXP LPC18xx is a single core Cortex-M3 implementation that is compatible
sahilmgandhi 18:6a4db94011d3 21 with the LPC43XX for cost-sensitive applications not requiring multiple cores.
sahilmgandhi 18:6a4db94011d3 22
sahilmgandhi 18:6a4db94011d3 23 mbed port to the LPC43XX - Micromint USA <support@micromint.com>
sahilmgandhi 18:6a4db94011d3 24
sahilmgandhi 18:6a4db94011d3 25 Compatibility
sahilmgandhi 18:6a4db94011d3 26 -------------
sahilmgandhi 18:6a4db94011d3 27 * This port has been tested with the following boards:
sahilmgandhi 18:6a4db94011d3 28 Board MCU RAM/Flash
sahilmgandhi 18:6a4db94011d3 29 Micromint Bambino 200 LPC4330 264K SRAM/4 MB SPIFI flash
sahilmgandhi 18:6a4db94011d3 30 Micromint Bambino 200E LPC4330 264K SRAM/8 MB SPIFI flash
sahilmgandhi 18:6a4db94011d3 31 Micromint Bambino 210 LPC4330 264K SRAM/4 MB SPIFI flash
sahilmgandhi 18:6a4db94011d3 32 Micromint Bambino 210E LPC4330 264K SRAM/8 MB SPIFI flash
sahilmgandhi 18:6a4db94011d3 33
sahilmgandhi 18:6a4db94011d3 34 * CMSIS-DAP debugging is implemented with the Micromint Bambino 210/210E.
sahilmgandhi 18:6a4db94011d3 35 To debug other LPC4330 targets, use a JTAG. The NXP DFU tool can be used
sahilmgandhi 18:6a4db94011d3 36 for flash programming.
sahilmgandhi 18:6a4db94011d3 37
sahilmgandhi 18:6a4db94011d3 38 * This port should support NXP LPC43XX and LPC18XX variants with a single
sahilmgandhi 18:6a4db94011d3 39 codebase. The core declaration specifies the binaries to be built:
sahilmgandhi 18:6a4db94011d3 40 mbed define CMSIS define MCU Target
sahilmgandhi 18:6a4db94011d3 41 __CORTEX_M4 CORE_M4 LPC43xx Cortex-M4
sahilmgandhi 18:6a4db94011d3 42 __CORTEX_M0 CORE_M0 LPC43xx Cortex-M0
sahilmgandhi 18:6a4db94011d3 43 __CORTEX_M3 CORE_M3 LPC18xx Cortex-M3
sahilmgandhi 18:6a4db94011d3 44 These MCUs all share the peripheral IP, common driver code is feasible.
sahilmgandhi 18:6a4db94011d3 45 Yet each variant can have different memory segments, peripherals, etc.
sahilmgandhi 18:6a4db94011d3 46 Plus, each board design can integrate different external peripherals
sahilmgandhi 18:6a4db94011d3 47 or interfaces. A future release of the mbed SDK and its build tools will
sahilmgandhi 18:6a4db94011d3 48 support specifying the target board when building binaries. At this time
sahilmgandhi 18:6a4db94011d3 49 building binaries for different targets requires an external project or
sahilmgandhi 18:6a4db94011d3 50 Makefile.
sahilmgandhi 18:6a4db94011d3 51
sahilmgandhi 18:6a4db94011d3 52 * No testing has been done with LPC18xx hardware.
sahilmgandhi 18:6a4db94011d3 53
sahilmgandhi 18:6a4db94011d3 54 Notes
sahilmgandhi 18:6a4db94011d3 55 -----
sahilmgandhi 18:6a4db94011d3 56 * On the LPC43xx the hardware pin name and the GPIO pin name are not the same,
sahilmgandhi 18:6a4db94011d3 57 requiring different offsets for the SCU and GPIO registers. To simplify logic
sahilmgandhi 18:6a4db94011d3 58 the pin identifier encodes the offsets. Macros are used for decoding.
sahilmgandhi 18:6a4db94011d3 59 For example, P6_11 corresponds to GPIO3[7] and is encoded/decoded as follows:
sahilmgandhi 18:6a4db94011d3 60
sahilmgandhi 18:6a4db94011d3 61 P6_11 = MBED_PIN(0x06, 11, 3, 7) = 0x032C0067
sahilmgandhi 18:6a4db94011d3 62
sahilmgandhi 18:6a4db94011d3 63 MBED_SCU_REG(P6_11) = 0x4008632C MBED_GPIO_PORT(P6_11) = 3
sahilmgandhi 18:6a4db94011d3 64 MBED_GPIO_REG(P6_11) = 0x400F4000 MBED_GPIO_PIN(P6_11) = 7
sahilmgandhi 18:6a4db94011d3 65
sahilmgandhi 18:6a4db94011d3 66 * Pin names use multiple aliases to support Arduino naming conventions as well
sahilmgandhi 18:6a4db94011d3 67 as others. For example, to use pin p21 on the Bambino 210 from mbed applications
sahilmgandhi 18:6a4db94011d3 68 the following aliases are equivalent: p21, D0, UART0_TX, COM1_TX, P6_4.
sahilmgandhi 18:6a4db94011d3 69 See the board pinout graphic and the PinNames.h for available aliases.
sahilmgandhi 18:6a4db94011d3 70
sahilmgandhi 18:6a4db94011d3 71 * The LPC43xx implements GPIO pin and group interrupts. Any pin in the 8 32-bit
sahilmgandhi 18:6a4db94011d3 72 GPIO ports can interrupt (LPC4350 supports up to 164). On group interrupts a
sahilmgandhi 18:6a4db94011d3 73 pin can only interrupt on the rising or falling edge, not both as required
sahilmgandhi 18:6a4db94011d3 74 by the mbed InterruptIn class. Also, group interrupts can't be cleared
sahilmgandhi 18:6a4db94011d3 75 individually. This implementation uses pin interrupts (8 on M4/M3, 1 on M0).
sahilmgandhi 18:6a4db94011d3 76 A future implementation may provide group interrupt support.
sahilmgandhi 18:6a4db94011d3 77
sahilmgandhi 18:6a4db94011d3 78 * The LPC3xx PWM driver uses the State Configurable Timer (SCT). The default
sahilmgandhi 18:6a4db94011d3 79 build (PWM_MODE=0) uses the unified 32-bit times. Applications that use PWM
sahilmgandhi 18:6a4db94011d3 80 and require other SCT uses can use the dual 16-bit mode by changing PWM_MODE
sahilmgandhi 18:6a4db94011d3 81 when building the library.