MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NUVOTON/TARGET_NUC472/serial_api.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2015-2016 Nuvoton
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 */
sahilmgandhi 18:6a4db94011d3 16
sahilmgandhi 18:6a4db94011d3 17 #include "serial_api.h"
sahilmgandhi 18:6a4db94011d3 18
sahilmgandhi 18:6a4db94011d3 19 #if DEVICE_SERIAL
sahilmgandhi 18:6a4db94011d3 20
sahilmgandhi 18:6a4db94011d3 21 #include "cmsis.h"
sahilmgandhi 18:6a4db94011d3 22 #include "mbed_error.h"
sahilmgandhi 18:6a4db94011d3 23 #include "mbed_assert.h"
sahilmgandhi 18:6a4db94011d3 24 #include "PeripheralPins.h"
sahilmgandhi 18:6a4db94011d3 25 #include "nu_modutil.h"
sahilmgandhi 18:6a4db94011d3 26 #include "nu_bitutil.h"
sahilmgandhi 18:6a4db94011d3 27
sahilmgandhi 18:6a4db94011d3 28 #if DEVICE_SERIAL_ASYNCH
sahilmgandhi 18:6a4db94011d3 29 #include "dma_api.h"
sahilmgandhi 18:6a4db94011d3 30 #include "dma.h"
sahilmgandhi 18:6a4db94011d3 31 #endif
sahilmgandhi 18:6a4db94011d3 32
sahilmgandhi 18:6a4db94011d3 33 struct nu_uart_var {
sahilmgandhi 18:6a4db94011d3 34 uint32_t ref_cnt; // Reference count of the H/W module
sahilmgandhi 18:6a4db94011d3 35 serial_t * obj;
sahilmgandhi 18:6a4db94011d3 36 uint32_t fifo_size_tx;
sahilmgandhi 18:6a4db94011d3 37 uint32_t fifo_size_rx;
sahilmgandhi 18:6a4db94011d3 38 void (*vec)(void);
sahilmgandhi 18:6a4db94011d3 39 #if DEVICE_SERIAL_ASYNCH
sahilmgandhi 18:6a4db94011d3 40 void (*vec_async)(void);
sahilmgandhi 18:6a4db94011d3 41 uint8_t pdma_perp_tx;
sahilmgandhi 18:6a4db94011d3 42 uint8_t pdma_perp_rx;
sahilmgandhi 18:6a4db94011d3 43 #endif
sahilmgandhi 18:6a4db94011d3 44 };
sahilmgandhi 18:6a4db94011d3 45
sahilmgandhi 18:6a4db94011d3 46 static void uart0_vec(void);
sahilmgandhi 18:6a4db94011d3 47 static void uart1_vec(void);
sahilmgandhi 18:6a4db94011d3 48 static void uart2_vec(void);
sahilmgandhi 18:6a4db94011d3 49 static void uart3_vec(void);
sahilmgandhi 18:6a4db94011d3 50 static void uart4_vec(void);
sahilmgandhi 18:6a4db94011d3 51 static void uart5_vec(void);
sahilmgandhi 18:6a4db94011d3 52 static void uart_irq(serial_t *obj);
sahilmgandhi 18:6a4db94011d3 53
sahilmgandhi 18:6a4db94011d3 54 #if DEVICE_SERIAL_ASYNCH
sahilmgandhi 18:6a4db94011d3 55 static void uart0_vec_async(void);
sahilmgandhi 18:6a4db94011d3 56 static void uart1_vec_async(void);
sahilmgandhi 18:6a4db94011d3 57 static void uart2_vec_async(void);
sahilmgandhi 18:6a4db94011d3 58 static void uart3_vec_async(void);
sahilmgandhi 18:6a4db94011d3 59 static void uart4_vec_async(void);
sahilmgandhi 18:6a4db94011d3 60 static void uart5_vec_async(void);
sahilmgandhi 18:6a4db94011d3 61 static void uart_irq_async(serial_t *obj);
sahilmgandhi 18:6a4db94011d3 62
sahilmgandhi 18:6a4db94011d3 63 static void uart_dma_handler_tx(uint32_t id, uint32_t event);
sahilmgandhi 18:6a4db94011d3 64 static void uart_dma_handler_rx(uint32_t id, uint32_t event);
sahilmgandhi 18:6a4db94011d3 65
sahilmgandhi 18:6a4db94011d3 66 static void serial_tx_enable_interrupt(serial_t *obj, uint32_t address, uint8_t enable);
sahilmgandhi 18:6a4db94011d3 67 static void serial_rx_enable_interrupt(serial_t *obj, uint32_t address, uint8_t enable);
sahilmgandhi 18:6a4db94011d3 68 static int serial_write_async(serial_t *obj);
sahilmgandhi 18:6a4db94011d3 69 static int serial_read_async(serial_t *obj);
sahilmgandhi 18:6a4db94011d3 70
sahilmgandhi 18:6a4db94011d3 71 static uint32_t serial_rx_event_check(serial_t *obj);
sahilmgandhi 18:6a4db94011d3 72 static uint32_t serial_tx_event_check(serial_t *obj);
sahilmgandhi 18:6a4db94011d3 73
sahilmgandhi 18:6a4db94011d3 74 static int serial_is_tx_complete(serial_t *obj);
sahilmgandhi 18:6a4db94011d3 75 static void serial_tx_enable_event(serial_t *obj, int event, uint8_t enable);
sahilmgandhi 18:6a4db94011d3 76
sahilmgandhi 18:6a4db94011d3 77 static void serial_tx_buffer_set(serial_t *obj, const void *tx, size_t length, uint8_t width);
sahilmgandhi 18:6a4db94011d3 78 static void serial_rx_buffer_set(serial_t *obj, void *rx, size_t length, uint8_t width);
sahilmgandhi 18:6a4db94011d3 79 static void serial_rx_set_char_match(serial_t *obj, uint8_t char_match);
sahilmgandhi 18:6a4db94011d3 80 static void serial_rx_enable_event(serial_t *obj, int event, uint8_t enable);
sahilmgandhi 18:6a4db94011d3 81 static int serial_is_rx_complete(serial_t *obj);
sahilmgandhi 18:6a4db94011d3 82
sahilmgandhi 18:6a4db94011d3 83 static void serial_check_dma_usage(DMAUsage *dma_usage, int *dma_ch);
sahilmgandhi 18:6a4db94011d3 84 static int serial_is_irq_en(serial_t *obj, SerialIrq irq);
sahilmgandhi 18:6a4db94011d3 85 #endif
sahilmgandhi 18:6a4db94011d3 86
sahilmgandhi 18:6a4db94011d3 87 static struct nu_uart_var uart0_var = {
sahilmgandhi 18:6a4db94011d3 88 .ref_cnt = 0,
sahilmgandhi 18:6a4db94011d3 89 .obj = NULL,
sahilmgandhi 18:6a4db94011d3 90 .fifo_size_tx = 64,
sahilmgandhi 18:6a4db94011d3 91 .fifo_size_rx = 64,
sahilmgandhi 18:6a4db94011d3 92 .vec = uart0_vec,
sahilmgandhi 18:6a4db94011d3 93 #if DEVICE_SERIAL_ASYNCH
sahilmgandhi 18:6a4db94011d3 94 .vec_async = uart0_vec_async,
sahilmgandhi 18:6a4db94011d3 95 .pdma_perp_tx = PDMA_UART0_TX,
sahilmgandhi 18:6a4db94011d3 96 .pdma_perp_rx = PDMA_UART0_RX
sahilmgandhi 18:6a4db94011d3 97 #endif
sahilmgandhi 18:6a4db94011d3 98 };
sahilmgandhi 18:6a4db94011d3 99 static struct nu_uart_var uart1_var = {
sahilmgandhi 18:6a4db94011d3 100 .ref_cnt = 0,
sahilmgandhi 18:6a4db94011d3 101 .obj = NULL,
sahilmgandhi 18:6a4db94011d3 102 .fifo_size_tx = 16,
sahilmgandhi 18:6a4db94011d3 103 .fifo_size_rx = 16,
sahilmgandhi 18:6a4db94011d3 104 .vec = uart1_vec,
sahilmgandhi 18:6a4db94011d3 105 #if DEVICE_SERIAL_ASYNCH
sahilmgandhi 18:6a4db94011d3 106 .vec_async = uart1_vec_async,
sahilmgandhi 18:6a4db94011d3 107 .pdma_perp_tx = PDMA_UART1_TX,
sahilmgandhi 18:6a4db94011d3 108 .pdma_perp_rx = PDMA_UART1_RX
sahilmgandhi 18:6a4db94011d3 109 #endif
sahilmgandhi 18:6a4db94011d3 110 };
sahilmgandhi 18:6a4db94011d3 111 static struct nu_uart_var uart2_var = {
sahilmgandhi 18:6a4db94011d3 112 .ref_cnt = 0,
sahilmgandhi 18:6a4db94011d3 113 .obj = NULL,
sahilmgandhi 18:6a4db94011d3 114 .fifo_size_tx = 16,
sahilmgandhi 18:6a4db94011d3 115 .fifo_size_rx = 16,
sahilmgandhi 18:6a4db94011d3 116 .vec = uart2_vec,
sahilmgandhi 18:6a4db94011d3 117 #if DEVICE_SERIAL_ASYNCH
sahilmgandhi 18:6a4db94011d3 118 .vec_async = uart2_vec_async,
sahilmgandhi 18:6a4db94011d3 119 .pdma_perp_tx = PDMA_UART2_TX,
sahilmgandhi 18:6a4db94011d3 120 .pdma_perp_rx = PDMA_UART2_RX
sahilmgandhi 18:6a4db94011d3 121 #endif
sahilmgandhi 18:6a4db94011d3 122 };
sahilmgandhi 18:6a4db94011d3 123 static struct nu_uart_var uart3_var = {
sahilmgandhi 18:6a4db94011d3 124 .ref_cnt = 0,
sahilmgandhi 18:6a4db94011d3 125 .obj = NULL,
sahilmgandhi 18:6a4db94011d3 126 .fifo_size_tx = 16,
sahilmgandhi 18:6a4db94011d3 127 .fifo_size_rx = 16,
sahilmgandhi 18:6a4db94011d3 128 .vec = uart3_vec,
sahilmgandhi 18:6a4db94011d3 129 #if DEVICE_SERIAL_ASYNCH
sahilmgandhi 18:6a4db94011d3 130 .vec_async = uart3_vec_async,
sahilmgandhi 18:6a4db94011d3 131 .pdma_perp_tx = PDMA_UART3_TX,
sahilmgandhi 18:6a4db94011d3 132 .pdma_perp_rx = PDMA_UART3_RX
sahilmgandhi 18:6a4db94011d3 133 #endif
sahilmgandhi 18:6a4db94011d3 134 };
sahilmgandhi 18:6a4db94011d3 135 static struct nu_uart_var uart4_var = {
sahilmgandhi 18:6a4db94011d3 136 .ref_cnt = 0,
sahilmgandhi 18:6a4db94011d3 137 .obj = NULL,
sahilmgandhi 18:6a4db94011d3 138 .fifo_size_tx = 16,
sahilmgandhi 18:6a4db94011d3 139 .fifo_size_rx = 16,
sahilmgandhi 18:6a4db94011d3 140 .vec = uart4_vec,
sahilmgandhi 18:6a4db94011d3 141 #if DEVICE_SERIAL_ASYNCH
sahilmgandhi 18:6a4db94011d3 142 .vec_async = uart4_vec_async,
sahilmgandhi 18:6a4db94011d3 143 .pdma_perp_tx = PDMA_UART4_TX,
sahilmgandhi 18:6a4db94011d3 144 .pdma_perp_rx = PDMA_UART4_RX
sahilmgandhi 18:6a4db94011d3 145 #endif
sahilmgandhi 18:6a4db94011d3 146 };
sahilmgandhi 18:6a4db94011d3 147 static struct nu_uart_var uart5_var = {
sahilmgandhi 18:6a4db94011d3 148 .ref_cnt = 0,
sahilmgandhi 18:6a4db94011d3 149 .obj = NULL,
sahilmgandhi 18:6a4db94011d3 150 .fifo_size_tx = 16,
sahilmgandhi 18:6a4db94011d3 151 .fifo_size_rx = 16,
sahilmgandhi 18:6a4db94011d3 152 .vec = uart5_vec,
sahilmgandhi 18:6a4db94011d3 153 #if DEVICE_SERIAL_ASYNCH
sahilmgandhi 18:6a4db94011d3 154 .vec_async = uart5_vec_async,
sahilmgandhi 18:6a4db94011d3 155 .pdma_perp_tx = PDMA_UART5_TX,
sahilmgandhi 18:6a4db94011d3 156 .pdma_perp_rx = PDMA_UART5_RX
sahilmgandhi 18:6a4db94011d3 157 #endif
sahilmgandhi 18:6a4db94011d3 158 };
sahilmgandhi 18:6a4db94011d3 159
sahilmgandhi 18:6a4db94011d3 160
sahilmgandhi 18:6a4db94011d3 161 int stdio_uart_inited = 0;
sahilmgandhi 18:6a4db94011d3 162 serial_t stdio_uart;
sahilmgandhi 18:6a4db94011d3 163 static uint32_t uart_modinit_mask = 0;
sahilmgandhi 18:6a4db94011d3 164
sahilmgandhi 18:6a4db94011d3 165 static const struct nu_modinit_s uart_modinit_tab[] = {
sahilmgandhi 18:6a4db94011d3 166 {UART_0, UART0_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART0_RST, UART0_IRQn, &uart0_var},
sahilmgandhi 18:6a4db94011d3 167 {UART_1, UART1_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART1_RST, UART1_IRQn, &uart1_var},
sahilmgandhi 18:6a4db94011d3 168 {UART_2, UART2_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART2_RST, UART2_IRQn, &uart2_var},
sahilmgandhi 18:6a4db94011d3 169 {UART_3, UART3_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART3_RST, UART3_IRQn, &uart3_var},
sahilmgandhi 18:6a4db94011d3 170 {UART_4, UART4_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART4_RST, UART4_IRQn, &uart4_var},
sahilmgandhi 18:6a4db94011d3 171 {UART_5, UART5_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART5_RST, UART5_IRQn, &uart5_var},
sahilmgandhi 18:6a4db94011d3 172
sahilmgandhi 18:6a4db94011d3 173 {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL}
sahilmgandhi 18:6a4db94011d3 174 };
sahilmgandhi 18:6a4db94011d3 175
sahilmgandhi 18:6a4db94011d3 176 extern void mbed_sdk_init(void);
sahilmgandhi 18:6a4db94011d3 177
sahilmgandhi 18:6a4db94011d3 178 void serial_init(serial_t *obj, PinName tx, PinName rx)
sahilmgandhi 18:6a4db94011d3 179 {
sahilmgandhi 18:6a4db94011d3 180 // NOTE: With armcc, serial_init() gets called from _sys_open() timing of which is before main()/mbed_sdk_init().
sahilmgandhi 18:6a4db94011d3 181 mbed_sdk_init();
sahilmgandhi 18:6a4db94011d3 182
sahilmgandhi 18:6a4db94011d3 183 // Determine which UART_x the pins are used for
sahilmgandhi 18:6a4db94011d3 184 uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX);
sahilmgandhi 18:6a4db94011d3 185 uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX);
sahilmgandhi 18:6a4db94011d3 186 // Get the peripheral name (UART_x) from the pins and assign it to the object
sahilmgandhi 18:6a4db94011d3 187 obj->serial.uart = (UARTName) pinmap_merge(uart_tx, uart_rx);
sahilmgandhi 18:6a4db94011d3 188 MBED_ASSERT((int)obj->serial.uart != NC);
sahilmgandhi 18:6a4db94011d3 189
sahilmgandhi 18:6a4db94011d3 190 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
sahilmgandhi 18:6a4db94011d3 191 MBED_ASSERT(modinit != NULL);
sahilmgandhi 18:6a4db94011d3 192 MBED_ASSERT(modinit->modname == obj->serial.uart);
sahilmgandhi 18:6a4db94011d3 193
sahilmgandhi 18:6a4db94011d3 194 struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
sahilmgandhi 18:6a4db94011d3 195
sahilmgandhi 18:6a4db94011d3 196 if (! var->ref_cnt) {
sahilmgandhi 18:6a4db94011d3 197 // Reset this module
sahilmgandhi 18:6a4db94011d3 198 SYS_ResetModule(modinit->rsetidx);
sahilmgandhi 18:6a4db94011d3 199
sahilmgandhi 18:6a4db94011d3 200 // Select IP clock source
sahilmgandhi 18:6a4db94011d3 201 CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
sahilmgandhi 18:6a4db94011d3 202 // Enable IP clock
sahilmgandhi 18:6a4db94011d3 203 CLK_EnableModuleClock(modinit->clkidx);
sahilmgandhi 18:6a4db94011d3 204
sahilmgandhi 18:6a4db94011d3 205 pinmap_pinout(tx, PinMap_UART_TX);
sahilmgandhi 18:6a4db94011d3 206 pinmap_pinout(rx, PinMap_UART_RX);
sahilmgandhi 18:6a4db94011d3 207
sahilmgandhi 18:6a4db94011d3 208 obj->serial.pin_tx = tx;
sahilmgandhi 18:6a4db94011d3 209 obj->serial.pin_rx = rx;
sahilmgandhi 18:6a4db94011d3 210 }
sahilmgandhi 18:6a4db94011d3 211 var->ref_cnt ++;
sahilmgandhi 18:6a4db94011d3 212
sahilmgandhi 18:6a4db94011d3 213 // Configure the UART module and set its baudrate
sahilmgandhi 18:6a4db94011d3 214 serial_baud(obj, 9600);
sahilmgandhi 18:6a4db94011d3 215 // Configure data bits, parity, and stop bits
sahilmgandhi 18:6a4db94011d3 216 serial_format(obj, 8, ParityNone, 1);
sahilmgandhi 18:6a4db94011d3 217
sahilmgandhi 18:6a4db94011d3 218 obj->serial.vec = var->vec;
sahilmgandhi 18:6a4db94011d3 219
sahilmgandhi 18:6a4db94011d3 220 #if DEVICE_SERIAL_ASYNCH
sahilmgandhi 18:6a4db94011d3 221 obj->serial.dma_usage_tx = DMA_USAGE_NEVER;
sahilmgandhi 18:6a4db94011d3 222 obj->serial.dma_usage_rx = DMA_USAGE_NEVER;
sahilmgandhi 18:6a4db94011d3 223 obj->serial.event = 0;
sahilmgandhi 18:6a4db94011d3 224 obj->serial.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
sahilmgandhi 18:6a4db94011d3 225 obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
sahilmgandhi 18:6a4db94011d3 226 #endif
sahilmgandhi 18:6a4db94011d3 227
sahilmgandhi 18:6a4db94011d3 228 // For stdio management
sahilmgandhi 18:6a4db94011d3 229 if (obj->serial.uart == STDIO_UART) {
sahilmgandhi 18:6a4db94011d3 230 stdio_uart_inited = 1;
sahilmgandhi 18:6a4db94011d3 231 memcpy(&stdio_uart, obj, sizeof(serial_t));
sahilmgandhi 18:6a4db94011d3 232 }
sahilmgandhi 18:6a4db94011d3 233
sahilmgandhi 18:6a4db94011d3 234 if (var->ref_cnt) {
sahilmgandhi 18:6a4db94011d3 235 // Mark this module to be inited.
sahilmgandhi 18:6a4db94011d3 236 int i = modinit - uart_modinit_tab;
sahilmgandhi 18:6a4db94011d3 237 uart_modinit_mask |= 1 << i;
sahilmgandhi 18:6a4db94011d3 238 }
sahilmgandhi 18:6a4db94011d3 239 }
sahilmgandhi 18:6a4db94011d3 240
sahilmgandhi 18:6a4db94011d3 241 void serial_free(serial_t *obj)
sahilmgandhi 18:6a4db94011d3 242 {
sahilmgandhi 18:6a4db94011d3 243 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
sahilmgandhi 18:6a4db94011d3 244 MBED_ASSERT(modinit != NULL);
sahilmgandhi 18:6a4db94011d3 245 MBED_ASSERT(modinit->modname == obj->serial.uart);
sahilmgandhi 18:6a4db94011d3 246
sahilmgandhi 18:6a4db94011d3 247 struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
sahilmgandhi 18:6a4db94011d3 248
sahilmgandhi 18:6a4db94011d3 249 var->ref_cnt --;
sahilmgandhi 18:6a4db94011d3 250 if (! var->ref_cnt) {
sahilmgandhi 18:6a4db94011d3 251 #if DEVICE_SERIAL_ASYNCH
sahilmgandhi 18:6a4db94011d3 252 if (obj->serial.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) {
sahilmgandhi 18:6a4db94011d3 253 dma_channel_free(obj->serial.dma_chn_id_tx);
sahilmgandhi 18:6a4db94011d3 254 obj->serial.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
sahilmgandhi 18:6a4db94011d3 255 }
sahilmgandhi 18:6a4db94011d3 256 if (obj->serial.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) {
sahilmgandhi 18:6a4db94011d3 257 dma_channel_free(obj->serial.dma_chn_id_rx);
sahilmgandhi 18:6a4db94011d3 258 obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
sahilmgandhi 18:6a4db94011d3 259 }
sahilmgandhi 18:6a4db94011d3 260 #endif
sahilmgandhi 18:6a4db94011d3 261
sahilmgandhi 18:6a4db94011d3 262 UART_Close((UART_T *) NU_MODBASE(obj->serial.uart));
sahilmgandhi 18:6a4db94011d3 263
sahilmgandhi 18:6a4db94011d3 264 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_THREIEN_Msk | UART_INTEN_RXTOIEN_Msk));
sahilmgandhi 18:6a4db94011d3 265 NVIC_DisableIRQ(modinit->irq_n);
sahilmgandhi 18:6a4db94011d3 266
sahilmgandhi 18:6a4db94011d3 267 // Disable IP clock
sahilmgandhi 18:6a4db94011d3 268 CLK_DisableModuleClock(modinit->clkidx);
sahilmgandhi 18:6a4db94011d3 269 }
sahilmgandhi 18:6a4db94011d3 270
sahilmgandhi 18:6a4db94011d3 271 if (var->obj == obj) {
sahilmgandhi 18:6a4db94011d3 272 var->obj = NULL;
sahilmgandhi 18:6a4db94011d3 273 }
sahilmgandhi 18:6a4db94011d3 274
sahilmgandhi 18:6a4db94011d3 275 if (obj->serial.uart == STDIO_UART) {
sahilmgandhi 18:6a4db94011d3 276 stdio_uart_inited = 0;
sahilmgandhi 18:6a4db94011d3 277 }
sahilmgandhi 18:6a4db94011d3 278
sahilmgandhi 18:6a4db94011d3 279 if (! var->ref_cnt) {
sahilmgandhi 18:6a4db94011d3 280 // Mark this module to be deinited.
sahilmgandhi 18:6a4db94011d3 281 int i = modinit - uart_modinit_tab;
sahilmgandhi 18:6a4db94011d3 282 uart_modinit_mask &= ~(1 << i);
sahilmgandhi 18:6a4db94011d3 283 }
sahilmgandhi 18:6a4db94011d3 284 }
sahilmgandhi 18:6a4db94011d3 285
sahilmgandhi 18:6a4db94011d3 286 void serial_baud(serial_t *obj, int baudrate) {
sahilmgandhi 18:6a4db94011d3 287 // Flush Tx FIFO. Otherwise, output data may get lost on this change.
sahilmgandhi 18:6a4db94011d3 288 while (! UART_IS_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart))));
sahilmgandhi 18:6a4db94011d3 289
sahilmgandhi 18:6a4db94011d3 290 obj->serial.baudrate = baudrate;
sahilmgandhi 18:6a4db94011d3 291 UART_Open((UART_T *) NU_MODBASE(obj->serial.uart), baudrate);
sahilmgandhi 18:6a4db94011d3 292 }
sahilmgandhi 18:6a4db94011d3 293
sahilmgandhi 18:6a4db94011d3 294 void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
sahilmgandhi 18:6a4db94011d3 295 // Flush Tx FIFO. Otherwise, output data may get lost on this change.
sahilmgandhi 18:6a4db94011d3 296 while (! UART_IS_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart))));
sahilmgandhi 18:6a4db94011d3 297
sahilmgandhi 18:6a4db94011d3 298 // TODO: Assert for not supported parity and data bits
sahilmgandhi 18:6a4db94011d3 299 obj->serial.databits = data_bits;
sahilmgandhi 18:6a4db94011d3 300 obj->serial.parity = parity;
sahilmgandhi 18:6a4db94011d3 301 obj->serial.stopbits = stop_bits;
sahilmgandhi 18:6a4db94011d3 302
sahilmgandhi 18:6a4db94011d3 303 uint32_t databits_intern = (data_bits == 5) ? UART_WORD_LEN_5 :
sahilmgandhi 18:6a4db94011d3 304 (data_bits == 6) ? UART_WORD_LEN_6 :
sahilmgandhi 18:6a4db94011d3 305 (data_bits == 7) ? UART_WORD_LEN_7 :
sahilmgandhi 18:6a4db94011d3 306 UART_WORD_LEN_8;
sahilmgandhi 18:6a4db94011d3 307 uint32_t parity_intern = (parity == ParityOdd || parity == ParityForced1) ? UART_PARITY_ODD :
sahilmgandhi 18:6a4db94011d3 308 (parity == ParityEven || parity == ParityForced0) ? UART_PARITY_EVEN :
sahilmgandhi 18:6a4db94011d3 309 UART_PARITY_NONE;
sahilmgandhi 18:6a4db94011d3 310 uint32_t stopbits_intern = (stop_bits == 2) ? UART_STOP_BIT_2 : UART_STOP_BIT_1;
sahilmgandhi 18:6a4db94011d3 311 UART_SetLine_Config((UART_T *) NU_MODBASE(obj->serial.uart),
sahilmgandhi 18:6a4db94011d3 312 0, // Don't change baudrate
sahilmgandhi 18:6a4db94011d3 313 databits_intern,
sahilmgandhi 18:6a4db94011d3 314 parity_intern,
sahilmgandhi 18:6a4db94011d3 315 stopbits_intern);
sahilmgandhi 18:6a4db94011d3 316 }
sahilmgandhi 18:6a4db94011d3 317
sahilmgandhi 18:6a4db94011d3 318 #if DEVICE_SERIAL_FC
sahilmgandhi 18:6a4db94011d3 319
sahilmgandhi 18:6a4db94011d3 320 void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
sahilmgandhi 18:6a4db94011d3 321 {
sahilmgandhi 18:6a4db94011d3 322 UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
sahilmgandhi 18:6a4db94011d3 323
sahilmgandhi 18:6a4db94011d3 324 // First, disable flow control completely.
sahilmgandhi 18:6a4db94011d3 325 uart_base->INTEN &= ~(UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk);
sahilmgandhi 18:6a4db94011d3 326
sahilmgandhi 18:6a4db94011d3 327 if ((type == FlowControlRTS || type == FlowControlRTSCTS) && rxflow != NC) {
sahilmgandhi 18:6a4db94011d3 328 // Check if RTS pin matches.
sahilmgandhi 18:6a4db94011d3 329 uint32_t uart_rts = pinmap_peripheral(rxflow, PinMap_UART_RTS);
sahilmgandhi 18:6a4db94011d3 330 MBED_ASSERT(uart_rts == obj->serial.uart);
sahilmgandhi 18:6a4db94011d3 331 // Enable the pin for RTS function
sahilmgandhi 18:6a4db94011d3 332 pinmap_pinout(rxflow, PinMap_UART_RTS);
sahilmgandhi 18:6a4db94011d3 333 // nRTS pin output is low level active
sahilmgandhi 18:6a4db94011d3 334 uart_base->MODEM |= UART_MODEM_RTSACTLV_Msk;
sahilmgandhi 18:6a4db94011d3 335 uart_base->MODEM &= ~UART_MODEM_RTS_Msk;
sahilmgandhi 18:6a4db94011d3 336
sahilmgandhi 18:6a4db94011d3 337 uart_base->FIFO = (uart_base->FIFO & ~UART_FIFO_RTSTRGLV_Msk) | UART_FIFO_RTSTRGLV_8BYTES;
sahilmgandhi 18:6a4db94011d3 338 // Enable RTS
sahilmgandhi 18:6a4db94011d3 339 uart_base->INTEN |= UART_INTEN_ATORTSEN_Msk;
sahilmgandhi 18:6a4db94011d3 340 }
sahilmgandhi 18:6a4db94011d3 341
sahilmgandhi 18:6a4db94011d3 342 if ((type == FlowControlCTS || type == FlowControlRTSCTS) && txflow != NC) {
sahilmgandhi 18:6a4db94011d3 343 // Check if CTS pin matches.
sahilmgandhi 18:6a4db94011d3 344 uint32_t uart_cts = pinmap_peripheral(txflow, PinMap_UART_CTS);
sahilmgandhi 18:6a4db94011d3 345 MBED_ASSERT(uart_cts == obj->serial.uart);
sahilmgandhi 18:6a4db94011d3 346 // Enable the pin for CTS function
sahilmgandhi 18:6a4db94011d3 347 pinmap_pinout(txflow, PinMap_UART_CTS);
sahilmgandhi 18:6a4db94011d3 348 // nCTS pin input is low level active
sahilmgandhi 18:6a4db94011d3 349 uart_base->MODEMSTS |= UART_MODEMSTS_CTSACTLV_Msk;
sahilmgandhi 18:6a4db94011d3 350 // Enable CTS
sahilmgandhi 18:6a4db94011d3 351 uart_base->INTEN |= UART_INTEN_ATOCTSEN_Msk;
sahilmgandhi 18:6a4db94011d3 352 }
sahilmgandhi 18:6a4db94011d3 353 }
sahilmgandhi 18:6a4db94011d3 354
sahilmgandhi 18:6a4db94011d3 355 #endif //DEVICE_SERIAL_FC
sahilmgandhi 18:6a4db94011d3 356
sahilmgandhi 18:6a4db94011d3 357 void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
sahilmgandhi 18:6a4db94011d3 358 {
sahilmgandhi 18:6a4db94011d3 359 // Flush Tx FIFO. Otherwise, output data may get lost on this change.
sahilmgandhi 18:6a4db94011d3 360 while (! UART_IS_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart))));
sahilmgandhi 18:6a4db94011d3 361
sahilmgandhi 18:6a4db94011d3 362 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
sahilmgandhi 18:6a4db94011d3 363 MBED_ASSERT(modinit != NULL);
sahilmgandhi 18:6a4db94011d3 364 MBED_ASSERT(modinit->modname == obj->serial.uart);
sahilmgandhi 18:6a4db94011d3 365
sahilmgandhi 18:6a4db94011d3 366 obj->serial.irq_handler = (uint32_t) handler;
sahilmgandhi 18:6a4db94011d3 367 obj->serial.irq_id = id;
sahilmgandhi 18:6a4db94011d3 368
sahilmgandhi 18:6a4db94011d3 369 // Restore sync-mode vector
sahilmgandhi 18:6a4db94011d3 370 obj->serial.vec = ((struct nu_uart_var *) modinit->var)->vec;
sahilmgandhi 18:6a4db94011d3 371 }
sahilmgandhi 18:6a4db94011d3 372
sahilmgandhi 18:6a4db94011d3 373 void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
sahilmgandhi 18:6a4db94011d3 374 {
sahilmgandhi 18:6a4db94011d3 375 if (enable) {
sahilmgandhi 18:6a4db94011d3 376 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
sahilmgandhi 18:6a4db94011d3 377 MBED_ASSERT(modinit != NULL);
sahilmgandhi 18:6a4db94011d3 378 MBED_ASSERT(modinit->modname == obj->serial.uart);
sahilmgandhi 18:6a4db94011d3 379
sahilmgandhi 18:6a4db94011d3 380 NVIC_SetVector(modinit->irq_n, (uint32_t) obj->serial.vec);
sahilmgandhi 18:6a4db94011d3 381 NVIC_EnableIRQ(modinit->irq_n);
sahilmgandhi 18:6a4db94011d3 382
sahilmgandhi 18:6a4db94011d3 383 struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
sahilmgandhi 18:6a4db94011d3 384 // Multiple serial S/W objects for single UART H/W module possibly.
sahilmgandhi 18:6a4db94011d3 385 // Bind serial S/W object to UART H/W module as interrupt is enabled.
sahilmgandhi 18:6a4db94011d3 386 var->obj = obj;
sahilmgandhi 18:6a4db94011d3 387
sahilmgandhi 18:6a4db94011d3 388 switch (irq) {
sahilmgandhi 18:6a4db94011d3 389 // NOTE: Setting inten_msk first to avoid race condition
sahilmgandhi 18:6a4db94011d3 390 case RxIrq:
sahilmgandhi 18:6a4db94011d3 391 obj->serial.inten_msk = obj->serial.inten_msk | (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk);
sahilmgandhi 18:6a4db94011d3 392 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
sahilmgandhi 18:6a4db94011d3 393 break;
sahilmgandhi 18:6a4db94011d3 394 case TxIrq:
sahilmgandhi 18:6a4db94011d3 395 obj->serial.inten_msk = obj->serial.inten_msk | UART_INTEN_THREIEN_Msk;
sahilmgandhi 18:6a4db94011d3 396 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
sahilmgandhi 18:6a4db94011d3 397 break;
sahilmgandhi 18:6a4db94011d3 398 }
sahilmgandhi 18:6a4db94011d3 399 } else { // disable
sahilmgandhi 18:6a4db94011d3 400 switch (irq) {
sahilmgandhi 18:6a4db94011d3 401 case RxIrq:
sahilmgandhi 18:6a4db94011d3 402 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
sahilmgandhi 18:6a4db94011d3 403 obj->serial.inten_msk = obj->serial.inten_msk & ~(UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk);
sahilmgandhi 18:6a4db94011d3 404 break;
sahilmgandhi 18:6a4db94011d3 405 case TxIrq:
sahilmgandhi 18:6a4db94011d3 406 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
sahilmgandhi 18:6a4db94011d3 407 obj->serial.inten_msk = obj->serial.inten_msk & ~UART_INTEN_THREIEN_Msk;
sahilmgandhi 18:6a4db94011d3 408 break;
sahilmgandhi 18:6a4db94011d3 409 }
sahilmgandhi 18:6a4db94011d3 410 }
sahilmgandhi 18:6a4db94011d3 411 }
sahilmgandhi 18:6a4db94011d3 412
sahilmgandhi 18:6a4db94011d3 413 int serial_getc(serial_t *obj)
sahilmgandhi 18:6a4db94011d3 414 {
sahilmgandhi 18:6a4db94011d3 415 // TODO: Fix every byte access requires accompaniness of one interrupt. This degrades performance much.
sahilmgandhi 18:6a4db94011d3 416 while (! serial_readable(obj));
sahilmgandhi 18:6a4db94011d3 417 int c = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
sahilmgandhi 18:6a4db94011d3 418
sahilmgandhi 18:6a4db94011d3 419 // Simulate clear of the interrupt flag
sahilmgandhi 18:6a4db94011d3 420 if (obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) {
sahilmgandhi 18:6a4db94011d3 421 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
sahilmgandhi 18:6a4db94011d3 422 }
sahilmgandhi 18:6a4db94011d3 423
sahilmgandhi 18:6a4db94011d3 424 return c;
sahilmgandhi 18:6a4db94011d3 425 }
sahilmgandhi 18:6a4db94011d3 426
sahilmgandhi 18:6a4db94011d3 427 void serial_putc(serial_t *obj, int c)
sahilmgandhi 18:6a4db94011d3 428 {
sahilmgandhi 18:6a4db94011d3 429 // TODO: Fix every byte access requires accompaniness of one interrupt. This degrades performance much.
sahilmgandhi 18:6a4db94011d3 430 while (! serial_writable(obj));
sahilmgandhi 18:6a4db94011d3 431 UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), c);
sahilmgandhi 18:6a4db94011d3 432
sahilmgandhi 18:6a4db94011d3 433 // Simulate clear of the interrupt flag
sahilmgandhi 18:6a4db94011d3 434 if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) {
sahilmgandhi 18:6a4db94011d3 435 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
sahilmgandhi 18:6a4db94011d3 436 }
sahilmgandhi 18:6a4db94011d3 437 }
sahilmgandhi 18:6a4db94011d3 438
sahilmgandhi 18:6a4db94011d3 439 int serial_readable(serial_t *obj)
sahilmgandhi 18:6a4db94011d3 440 {
sahilmgandhi 18:6a4db94011d3 441 //return UART_IS_RX_READY(((UART_T *) NU_MODBASE(obj->serial.uart)));
sahilmgandhi 18:6a4db94011d3 442 return ! (((UART_T *) NU_MODBASE(obj->serial.uart))->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk);
sahilmgandhi 18:6a4db94011d3 443 }
sahilmgandhi 18:6a4db94011d3 444
sahilmgandhi 18:6a4db94011d3 445 int serial_writable(serial_t *obj)
sahilmgandhi 18:6a4db94011d3 446 {
sahilmgandhi 18:6a4db94011d3 447 return ! UART_IS_TX_FULL(((UART_T *) NU_MODBASE(obj->serial.uart)));
sahilmgandhi 18:6a4db94011d3 448 }
sahilmgandhi 18:6a4db94011d3 449
sahilmgandhi 18:6a4db94011d3 450 void serial_pinout_tx(PinName tx)
sahilmgandhi 18:6a4db94011d3 451 {
sahilmgandhi 18:6a4db94011d3 452 pinmap_pinout(tx, PinMap_UART_TX);
sahilmgandhi 18:6a4db94011d3 453 }
sahilmgandhi 18:6a4db94011d3 454
sahilmgandhi 18:6a4db94011d3 455 void serial_break_set(serial_t *obj)
sahilmgandhi 18:6a4db94011d3 456 {
sahilmgandhi 18:6a4db94011d3 457 ((UART_T *) NU_MODBASE(obj->serial.uart))->LINE |= UART_LINE_BCB_Msk;
sahilmgandhi 18:6a4db94011d3 458 }
sahilmgandhi 18:6a4db94011d3 459
sahilmgandhi 18:6a4db94011d3 460 void serial_break_clear(serial_t *obj)
sahilmgandhi 18:6a4db94011d3 461 {
sahilmgandhi 18:6a4db94011d3 462 ((UART_T *) NU_MODBASE(obj->serial.uart))->LINE &= ~UART_LINE_BCB_Msk;
sahilmgandhi 18:6a4db94011d3 463 }
sahilmgandhi 18:6a4db94011d3 464
sahilmgandhi 18:6a4db94011d3 465 static void uart0_vec(void)
sahilmgandhi 18:6a4db94011d3 466 {
sahilmgandhi 18:6a4db94011d3 467 uart_irq(uart0_var.obj);
sahilmgandhi 18:6a4db94011d3 468 }
sahilmgandhi 18:6a4db94011d3 469
sahilmgandhi 18:6a4db94011d3 470 static void uart1_vec(void)
sahilmgandhi 18:6a4db94011d3 471 {
sahilmgandhi 18:6a4db94011d3 472 uart_irq(uart1_var.obj);
sahilmgandhi 18:6a4db94011d3 473 }
sahilmgandhi 18:6a4db94011d3 474
sahilmgandhi 18:6a4db94011d3 475 static void uart2_vec(void)
sahilmgandhi 18:6a4db94011d3 476 {
sahilmgandhi 18:6a4db94011d3 477 uart_irq(uart2_var.obj);
sahilmgandhi 18:6a4db94011d3 478 }
sahilmgandhi 18:6a4db94011d3 479
sahilmgandhi 18:6a4db94011d3 480 static void uart3_vec(void)
sahilmgandhi 18:6a4db94011d3 481 {
sahilmgandhi 18:6a4db94011d3 482 uart_irq(uart3_var.obj);
sahilmgandhi 18:6a4db94011d3 483 }
sahilmgandhi 18:6a4db94011d3 484
sahilmgandhi 18:6a4db94011d3 485 static void uart4_vec(void)
sahilmgandhi 18:6a4db94011d3 486 {
sahilmgandhi 18:6a4db94011d3 487 uart_irq(uart4_var.obj);
sahilmgandhi 18:6a4db94011d3 488 }
sahilmgandhi 18:6a4db94011d3 489
sahilmgandhi 18:6a4db94011d3 490 static void uart5_vec(void)
sahilmgandhi 18:6a4db94011d3 491 {
sahilmgandhi 18:6a4db94011d3 492 uart_irq(uart5_var.obj);
sahilmgandhi 18:6a4db94011d3 493 }
sahilmgandhi 18:6a4db94011d3 494
sahilmgandhi 18:6a4db94011d3 495 static void uart_irq(serial_t *obj)
sahilmgandhi 18:6a4db94011d3 496 {
sahilmgandhi 18:6a4db94011d3 497 UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
sahilmgandhi 18:6a4db94011d3 498
sahilmgandhi 18:6a4db94011d3 499 if (uart_base->INTSTS & (UART_INTSTS_RDAINT_Msk | UART_INTSTS_RXTOINT_Msk)) {
sahilmgandhi 18:6a4db94011d3 500 // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next read.
sahilmgandhi 18:6a4db94011d3 501 UART_DISABLE_INT(uart_base, (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
sahilmgandhi 18:6a4db94011d3 502 if (obj->serial.irq_handler) {
sahilmgandhi 18:6a4db94011d3 503 ((uart_irq_handler) obj->serial.irq_handler)(obj->serial.irq_id, RxIrq);
sahilmgandhi 18:6a4db94011d3 504 }
sahilmgandhi 18:6a4db94011d3 505 }
sahilmgandhi 18:6a4db94011d3 506
sahilmgandhi 18:6a4db94011d3 507 if (uart_base->INTSTS & UART_INTSTS_THREINT_Msk) {
sahilmgandhi 18:6a4db94011d3 508 // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next write.
sahilmgandhi 18:6a4db94011d3 509 UART_DISABLE_INT(uart_base, UART_INTEN_THREIEN_Msk);
sahilmgandhi 18:6a4db94011d3 510 if (obj->serial.irq_handler) {
sahilmgandhi 18:6a4db94011d3 511 ((uart_irq_handler) obj->serial.irq_handler)(obj->serial.irq_id, TxIrq);
sahilmgandhi 18:6a4db94011d3 512 }
sahilmgandhi 18:6a4db94011d3 513 }
sahilmgandhi 18:6a4db94011d3 514
sahilmgandhi 18:6a4db94011d3 515 // FIXME: Ignore all other interrupt flags. Clear them. Otherwise, program will get stuck in interrupt.
sahilmgandhi 18:6a4db94011d3 516 uart_base->INTSTS = uart_base->INTSTS;
sahilmgandhi 18:6a4db94011d3 517 uart_base->FIFOSTS = uart_base->FIFOSTS;
sahilmgandhi 18:6a4db94011d3 518 }
sahilmgandhi 18:6a4db94011d3 519
sahilmgandhi 18:6a4db94011d3 520
sahilmgandhi 18:6a4db94011d3 521 #if DEVICE_SERIAL_ASYNCH
sahilmgandhi 18:6a4db94011d3 522 int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint)
sahilmgandhi 18:6a4db94011d3 523 {
sahilmgandhi 18:6a4db94011d3 524 MBED_ASSERT(tx_width == 8 || tx_width == 16 || tx_width == 32);
sahilmgandhi 18:6a4db94011d3 525
sahilmgandhi 18:6a4db94011d3 526 obj->serial.dma_usage_tx = hint;
sahilmgandhi 18:6a4db94011d3 527 serial_check_dma_usage(&obj->serial.dma_usage_tx, &obj->serial.dma_chn_id_tx);
sahilmgandhi 18:6a4db94011d3 528
sahilmgandhi 18:6a4db94011d3 529 // UART IRQ is necessary for both interrupt way and DMA way
sahilmgandhi 18:6a4db94011d3 530 serial_tx_enable_event(obj, event, 1);
sahilmgandhi 18:6a4db94011d3 531 serial_tx_buffer_set(obj, tx, tx_length, tx_width);
sahilmgandhi 18:6a4db94011d3 532 //UART_HAL_DisableTransmitter(obj->serial.address);
sahilmgandhi 18:6a4db94011d3 533 //UART_HAL_FlushTxFifo(obj->serial.address);
sahilmgandhi 18:6a4db94011d3 534 //UART_HAL_EnableTransmitter(obj->serial.address);
sahilmgandhi 18:6a4db94011d3 535
sahilmgandhi 18:6a4db94011d3 536 int n_word = 0;
sahilmgandhi 18:6a4db94011d3 537 if (obj->serial.dma_usage_tx == DMA_USAGE_NEVER) {
sahilmgandhi 18:6a4db94011d3 538 // Interrupt way
sahilmgandhi 18:6a4db94011d3 539 n_word = serial_write_async(obj);
sahilmgandhi 18:6a4db94011d3 540 serial_tx_enable_interrupt(obj, handler, 1);
sahilmgandhi 18:6a4db94011d3 541 } else {
sahilmgandhi 18:6a4db94011d3 542 // DMA way
sahilmgandhi 18:6a4db94011d3 543 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
sahilmgandhi 18:6a4db94011d3 544 MBED_ASSERT(modinit != NULL);
sahilmgandhi 18:6a4db94011d3 545 MBED_ASSERT(modinit->modname == obj->serial.uart);
sahilmgandhi 18:6a4db94011d3 546
sahilmgandhi 18:6a4db94011d3 547 PDMA_T *pdma_base = dma_modbase();
sahilmgandhi 18:6a4db94011d3 548
sahilmgandhi 18:6a4db94011d3 549 pdma_base->CHCTL |= 1 << obj->serial.dma_chn_id_tx; // Enable this DMA channel
sahilmgandhi 18:6a4db94011d3 550 PDMA_SetTransferMode(obj->serial.dma_chn_id_tx,
sahilmgandhi 18:6a4db94011d3 551 ((struct nu_uart_var *) modinit->var)->pdma_perp_tx, // Peripheral connected to this PDMA
sahilmgandhi 18:6a4db94011d3 552 0, // Scatter-gather disabled
sahilmgandhi 18:6a4db94011d3 553 0); // Scatter-gather descriptor address
sahilmgandhi 18:6a4db94011d3 554 PDMA_SetTransferCnt(obj->serial.dma_chn_id_tx,
sahilmgandhi 18:6a4db94011d3 555 (tx_width == 8) ? PDMA_WIDTH_8 : (tx_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32,
sahilmgandhi 18:6a4db94011d3 556 tx_length);
sahilmgandhi 18:6a4db94011d3 557 PDMA_SetTransferAddr(obj->serial.dma_chn_id_tx,
sahilmgandhi 18:6a4db94011d3 558 ((uint32_t) tx) + (tx_width / 8) * tx_length, // NOTE: End of source address
sahilmgandhi 18:6a4db94011d3 559 PDMA_SAR_INC, // Source address incremental
sahilmgandhi 18:6a4db94011d3 560 (uint32_t) NU_MODBASE(obj->serial.uart), // Destination address
sahilmgandhi 18:6a4db94011d3 561 PDMA_DAR_FIX); // Destination address fixed
sahilmgandhi 18:6a4db94011d3 562 PDMA_SetBurstType(obj->serial.dma_chn_id_tx,
sahilmgandhi 18:6a4db94011d3 563 PDMA_REQ_SINGLE, // Single mode
sahilmgandhi 18:6a4db94011d3 564 0); // Burst size
sahilmgandhi 18:6a4db94011d3 565 PDMA_EnableInt(obj->serial.dma_chn_id_tx,
sahilmgandhi 18:6a4db94011d3 566 0); // Interrupt type. No use here
sahilmgandhi 18:6a4db94011d3 567 // Register DMA event handler
sahilmgandhi 18:6a4db94011d3 568 dma_set_handler(obj->serial.dma_chn_id_tx, (uint32_t) uart_dma_handler_tx, (uint32_t) obj, DMA_EVENT_ALL);
sahilmgandhi 18:6a4db94011d3 569 serial_tx_enable_interrupt(obj, handler, 1);
sahilmgandhi 18:6a4db94011d3 570 ((UART_T *) NU_MODBASE(obj->serial.uart))->INTEN |= UART_INTEN_TXPDMAEN_Msk; // Start DMA transfer
sahilmgandhi 18:6a4db94011d3 571 }
sahilmgandhi 18:6a4db94011d3 572
sahilmgandhi 18:6a4db94011d3 573 return n_word;
sahilmgandhi 18:6a4db94011d3 574 }
sahilmgandhi 18:6a4db94011d3 575
sahilmgandhi 18:6a4db94011d3 576 void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint)
sahilmgandhi 18:6a4db94011d3 577 {
sahilmgandhi 18:6a4db94011d3 578 MBED_ASSERT(rx_width == 8 || rx_width == 16 || rx_width == 32);
sahilmgandhi 18:6a4db94011d3 579
sahilmgandhi 18:6a4db94011d3 580 obj->serial.dma_usage_rx = hint;
sahilmgandhi 18:6a4db94011d3 581 serial_check_dma_usage(&obj->serial.dma_usage_rx, &obj->serial.dma_chn_id_rx);
sahilmgandhi 18:6a4db94011d3 582 // DMA doesn't support char match, so fall back to IRQ if it is requested.
sahilmgandhi 18:6a4db94011d3 583 if (obj->serial.dma_usage_rx != DMA_USAGE_NEVER &&
sahilmgandhi 18:6a4db94011d3 584 (event & SERIAL_EVENT_RX_CHARACTER_MATCH) &&
sahilmgandhi 18:6a4db94011d3 585 char_match != SERIAL_RESERVED_CHAR_MATCH) {
sahilmgandhi 18:6a4db94011d3 586 obj->serial.dma_usage_rx = DMA_USAGE_NEVER;
sahilmgandhi 18:6a4db94011d3 587 dma_channel_free(obj->serial.dma_chn_id_rx);
sahilmgandhi 18:6a4db94011d3 588 obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
sahilmgandhi 18:6a4db94011d3 589 }
sahilmgandhi 18:6a4db94011d3 590
sahilmgandhi 18:6a4db94011d3 591 // UART IRQ is necessary for both interrupt way and DMA way
sahilmgandhi 18:6a4db94011d3 592 serial_rx_enable_event(obj, event, 1);
sahilmgandhi 18:6a4db94011d3 593 serial_rx_buffer_set(obj, rx, rx_length, rx_width);
sahilmgandhi 18:6a4db94011d3 594 serial_rx_set_char_match(obj, char_match);
sahilmgandhi 18:6a4db94011d3 595 //UART_HAL_DisableReceiver(obj->serial.address);
sahilmgandhi 18:6a4db94011d3 596 //UART_HAL_FlushRxFifo(obj->serial.address);
sahilmgandhi 18:6a4db94011d3 597 //UART_HAL_EnableReceiver(obj->serial.address);
sahilmgandhi 18:6a4db94011d3 598
sahilmgandhi 18:6a4db94011d3 599 if (obj->serial.dma_usage_rx == DMA_USAGE_NEVER) {
sahilmgandhi 18:6a4db94011d3 600 // Interrupt way
sahilmgandhi 18:6a4db94011d3 601 serial_rx_enable_interrupt(obj, handler, 1);
sahilmgandhi 18:6a4db94011d3 602 } else {
sahilmgandhi 18:6a4db94011d3 603 // DMA way
sahilmgandhi 18:6a4db94011d3 604 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
sahilmgandhi 18:6a4db94011d3 605 MBED_ASSERT(modinit != NULL);
sahilmgandhi 18:6a4db94011d3 606 MBED_ASSERT(modinit->modname == obj->serial.uart);
sahilmgandhi 18:6a4db94011d3 607
sahilmgandhi 18:6a4db94011d3 608 PDMA_T *pdma_base = dma_modbase();
sahilmgandhi 18:6a4db94011d3 609
sahilmgandhi 18:6a4db94011d3 610 pdma_base->CHCTL |= 1 << obj->serial.dma_chn_id_rx; // Enable this DMA channel
sahilmgandhi 18:6a4db94011d3 611 PDMA_SetTransferMode(obj->serial.dma_chn_id_rx,
sahilmgandhi 18:6a4db94011d3 612 ((struct nu_uart_var *) modinit->var)->pdma_perp_rx, // Peripheral connected to this PDMA
sahilmgandhi 18:6a4db94011d3 613 0, // Scatter-gather disabled
sahilmgandhi 18:6a4db94011d3 614 0); // Scatter-gather descriptor address
sahilmgandhi 18:6a4db94011d3 615 PDMA_SetTransferCnt(obj->serial.dma_chn_id_rx,
sahilmgandhi 18:6a4db94011d3 616 (rx_width == 8) ? PDMA_WIDTH_8 : (rx_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32,
sahilmgandhi 18:6a4db94011d3 617 rx_length);
sahilmgandhi 18:6a4db94011d3 618 PDMA_SetTransferAddr(obj->serial.dma_chn_id_rx,
sahilmgandhi 18:6a4db94011d3 619 (uint32_t) NU_MODBASE(obj->serial.uart), // Source address
sahilmgandhi 18:6a4db94011d3 620 PDMA_SAR_FIX, // Source address fixed
sahilmgandhi 18:6a4db94011d3 621 ((uint32_t) rx) + (rx_width / 8) * rx_length, // NOTE: End of destination address
sahilmgandhi 18:6a4db94011d3 622 PDMA_DAR_INC); // Destination address incremental
sahilmgandhi 18:6a4db94011d3 623 PDMA_SetBurstType(obj->serial.dma_chn_id_rx,
sahilmgandhi 18:6a4db94011d3 624 PDMA_REQ_SINGLE, // Single mode
sahilmgandhi 18:6a4db94011d3 625 0); // Burst size
sahilmgandhi 18:6a4db94011d3 626 PDMA_EnableInt(obj->serial.dma_chn_id_rx,
sahilmgandhi 18:6a4db94011d3 627 0); // Interrupt type. No use here
sahilmgandhi 18:6a4db94011d3 628 // Register DMA event handler
sahilmgandhi 18:6a4db94011d3 629 dma_set_handler(obj->serial.dma_chn_id_rx, (uint32_t) uart_dma_handler_rx, (uint32_t) obj, DMA_EVENT_ALL);
sahilmgandhi 18:6a4db94011d3 630 serial_rx_enable_interrupt(obj, handler, 1);
sahilmgandhi 18:6a4db94011d3 631 ((UART_T *) NU_MODBASE(obj->serial.uart))->INTEN |= UART_INTEN_RXPDMAEN_Msk; // Start DMA transfer
sahilmgandhi 18:6a4db94011d3 632 }
sahilmgandhi 18:6a4db94011d3 633 }
sahilmgandhi 18:6a4db94011d3 634
sahilmgandhi 18:6a4db94011d3 635 void serial_tx_abort_asynch(serial_t *obj)
sahilmgandhi 18:6a4db94011d3 636 {
sahilmgandhi 18:6a4db94011d3 637 // Flush Tx FIFO. Otherwise, output data may get lost on this change.
sahilmgandhi 18:6a4db94011d3 638 while (! UART_IS_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart))));
sahilmgandhi 18:6a4db94011d3 639
sahilmgandhi 18:6a4db94011d3 640 if (obj->serial.dma_usage_tx != DMA_USAGE_NEVER) {
sahilmgandhi 18:6a4db94011d3 641 PDMA_T *pdma_base = dma_modbase();
sahilmgandhi 18:6a4db94011d3 642
sahilmgandhi 18:6a4db94011d3 643 if (obj->serial.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) {
sahilmgandhi 18:6a4db94011d3 644 PDMA_DisableInt(obj->serial.dma_chn_id_tx, 0);
sahilmgandhi 18:6a4db94011d3 645 // FIXME: Next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown.
sahilmgandhi 18:6a4db94011d3 646 //PDMA_STOP(obj->serial.dma_chn_id_tx);
sahilmgandhi 18:6a4db94011d3 647 pdma_base->CHCTL &= ~(1 << obj->serial.dma_chn_id_tx);
sahilmgandhi 18:6a4db94011d3 648 }
sahilmgandhi 18:6a4db94011d3 649 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_TXPDMAEN_Msk);
sahilmgandhi 18:6a4db94011d3 650 }
sahilmgandhi 18:6a4db94011d3 651
sahilmgandhi 18:6a4db94011d3 652 // Necessary for both interrupt way and DMA way
sahilmgandhi 18:6a4db94011d3 653 serial_irq_set(obj, TxIrq, 0);
sahilmgandhi 18:6a4db94011d3 654 // FIXME: more complete abort operation
sahilmgandhi 18:6a4db94011d3 655 //UART_HAL_DisableTransmitter(obj->serial.serial.address);
sahilmgandhi 18:6a4db94011d3 656 //UART_HAL_FlushTxFifo(obj->serial.serial.address);
sahilmgandhi 18:6a4db94011d3 657 }
sahilmgandhi 18:6a4db94011d3 658
sahilmgandhi 18:6a4db94011d3 659 void serial_rx_abort_asynch(serial_t *obj)
sahilmgandhi 18:6a4db94011d3 660 {
sahilmgandhi 18:6a4db94011d3 661 if (obj->serial.dma_usage_rx != DMA_USAGE_NEVER) {
sahilmgandhi 18:6a4db94011d3 662 PDMA_T *pdma_base = dma_modbase();
sahilmgandhi 18:6a4db94011d3 663
sahilmgandhi 18:6a4db94011d3 664 if (obj->serial.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) {
sahilmgandhi 18:6a4db94011d3 665 PDMA_DisableInt(obj->serial.dma_chn_id_rx, 0);
sahilmgandhi 18:6a4db94011d3 666 // FIXME: Next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown.
sahilmgandhi 18:6a4db94011d3 667 //PDMA_STOP(obj->serial.dma_chn_id_rx);
sahilmgandhi 18:6a4db94011d3 668 pdma_base->CHCTL &= ~(1 << obj->serial.dma_chn_id_rx);
sahilmgandhi 18:6a4db94011d3 669 }
sahilmgandhi 18:6a4db94011d3 670 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RXPDMAEN_Msk);
sahilmgandhi 18:6a4db94011d3 671 }
sahilmgandhi 18:6a4db94011d3 672
sahilmgandhi 18:6a4db94011d3 673 // Necessary for both interrupt way and DMA way
sahilmgandhi 18:6a4db94011d3 674 serial_irq_set(obj, RxIrq, 0);
sahilmgandhi 18:6a4db94011d3 675 // FIXME: more complete abort operation
sahilmgandhi 18:6a4db94011d3 676 //UART_HAL_DisableReceiver(obj->serial.serial.address);
sahilmgandhi 18:6a4db94011d3 677 //UART_HAL_FlushRxFifo(obj->serial.serial.address);
sahilmgandhi 18:6a4db94011d3 678 }
sahilmgandhi 18:6a4db94011d3 679
sahilmgandhi 18:6a4db94011d3 680 uint8_t serial_tx_active(serial_t *obj)
sahilmgandhi 18:6a4db94011d3 681 {
sahilmgandhi 18:6a4db94011d3 682 return serial_is_irq_en(obj, TxIrq);
sahilmgandhi 18:6a4db94011d3 683 }
sahilmgandhi 18:6a4db94011d3 684
sahilmgandhi 18:6a4db94011d3 685 uint8_t serial_rx_active(serial_t *obj)
sahilmgandhi 18:6a4db94011d3 686 {
sahilmgandhi 18:6a4db94011d3 687 return serial_is_irq_en(obj, RxIrq);
sahilmgandhi 18:6a4db94011d3 688 }
sahilmgandhi 18:6a4db94011d3 689
sahilmgandhi 18:6a4db94011d3 690 int serial_irq_handler_asynch(serial_t *obj)
sahilmgandhi 18:6a4db94011d3 691 {
sahilmgandhi 18:6a4db94011d3 692 int event_rx = 0;
sahilmgandhi 18:6a4db94011d3 693 int event_tx = 0;
sahilmgandhi 18:6a4db94011d3 694
sahilmgandhi 18:6a4db94011d3 695 // Necessary for both interrupt way and DMA way
sahilmgandhi 18:6a4db94011d3 696 if (serial_is_irq_en(obj, RxIrq)) {
sahilmgandhi 18:6a4db94011d3 697 event_rx = serial_rx_event_check(obj);
sahilmgandhi 18:6a4db94011d3 698 if (event_rx) {
sahilmgandhi 18:6a4db94011d3 699 serial_rx_abort_asynch(obj);
sahilmgandhi 18:6a4db94011d3 700 }
sahilmgandhi 18:6a4db94011d3 701 }
sahilmgandhi 18:6a4db94011d3 702
sahilmgandhi 18:6a4db94011d3 703 if (serial_is_irq_en(obj, TxIrq)) {
sahilmgandhi 18:6a4db94011d3 704 event_tx = serial_tx_event_check(obj);
sahilmgandhi 18:6a4db94011d3 705 if (event_tx) {
sahilmgandhi 18:6a4db94011d3 706 serial_tx_abort_asynch(obj);
sahilmgandhi 18:6a4db94011d3 707 }
sahilmgandhi 18:6a4db94011d3 708 }
sahilmgandhi 18:6a4db94011d3 709
sahilmgandhi 18:6a4db94011d3 710 return (obj->serial.event & (event_rx | event_tx));
sahilmgandhi 18:6a4db94011d3 711 }
sahilmgandhi 18:6a4db94011d3 712
sahilmgandhi 18:6a4db94011d3 713 int serial_allow_powerdown(void)
sahilmgandhi 18:6a4db94011d3 714 {
sahilmgandhi 18:6a4db94011d3 715 uint32_t modinit_mask = uart_modinit_mask;
sahilmgandhi 18:6a4db94011d3 716 while (modinit_mask) {
sahilmgandhi 18:6a4db94011d3 717 int uart_idx = nu_ctz(modinit_mask);
sahilmgandhi 18:6a4db94011d3 718 const struct nu_modinit_s *modinit = uart_modinit_tab + uart_idx;
sahilmgandhi 18:6a4db94011d3 719 if (modinit->modname != NC) {
sahilmgandhi 18:6a4db94011d3 720 UART_T *uart_base = (UART_T *) NU_MODBASE(modinit->modname);
sahilmgandhi 18:6a4db94011d3 721 // Disallow entering power-down mode if Tx FIFO has data to flush
sahilmgandhi 18:6a4db94011d3 722 if (! UART_IS_TX_EMPTY((uart_base))) {
sahilmgandhi 18:6a4db94011d3 723 return 0;
sahilmgandhi 18:6a4db94011d3 724 }
sahilmgandhi 18:6a4db94011d3 725 // Disallow entering power-down mode if async Rx transfer (not PDMA) is on-going
sahilmgandhi 18:6a4db94011d3 726 if (uart_base->INTEN & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) {
sahilmgandhi 18:6a4db94011d3 727 return 0;
sahilmgandhi 18:6a4db94011d3 728 }
sahilmgandhi 18:6a4db94011d3 729 // Disallow entering power-down mode if async Rx transfer (PDMA) is on-going
sahilmgandhi 18:6a4db94011d3 730 if (uart_base->INTEN & UART_INTEN_RXPDMAEN_Msk) {
sahilmgandhi 18:6a4db94011d3 731 return 0;
sahilmgandhi 18:6a4db94011d3 732 }
sahilmgandhi 18:6a4db94011d3 733 }
sahilmgandhi 18:6a4db94011d3 734 modinit_mask &= ~(1 << uart_idx);
sahilmgandhi 18:6a4db94011d3 735 }
sahilmgandhi 18:6a4db94011d3 736
sahilmgandhi 18:6a4db94011d3 737 return 1;
sahilmgandhi 18:6a4db94011d3 738 }
sahilmgandhi 18:6a4db94011d3 739
sahilmgandhi 18:6a4db94011d3 740 static void uart0_vec_async(void)
sahilmgandhi 18:6a4db94011d3 741 {
sahilmgandhi 18:6a4db94011d3 742 uart_irq_async(uart0_var.obj);
sahilmgandhi 18:6a4db94011d3 743 }
sahilmgandhi 18:6a4db94011d3 744
sahilmgandhi 18:6a4db94011d3 745 static void uart1_vec_async(void)
sahilmgandhi 18:6a4db94011d3 746 {
sahilmgandhi 18:6a4db94011d3 747 uart_irq_async(uart1_var.obj);
sahilmgandhi 18:6a4db94011d3 748 }
sahilmgandhi 18:6a4db94011d3 749
sahilmgandhi 18:6a4db94011d3 750 static void uart2_vec_async(void)
sahilmgandhi 18:6a4db94011d3 751 {
sahilmgandhi 18:6a4db94011d3 752 uart_irq_async(uart2_var.obj);
sahilmgandhi 18:6a4db94011d3 753 }
sahilmgandhi 18:6a4db94011d3 754
sahilmgandhi 18:6a4db94011d3 755 static void uart3_vec_async(void)
sahilmgandhi 18:6a4db94011d3 756 {
sahilmgandhi 18:6a4db94011d3 757 uart_irq_async(uart3_var.obj);
sahilmgandhi 18:6a4db94011d3 758 }
sahilmgandhi 18:6a4db94011d3 759
sahilmgandhi 18:6a4db94011d3 760 static void uart4_vec_async(void)
sahilmgandhi 18:6a4db94011d3 761 {
sahilmgandhi 18:6a4db94011d3 762 uart_irq_async(uart4_var.obj);
sahilmgandhi 18:6a4db94011d3 763 }
sahilmgandhi 18:6a4db94011d3 764
sahilmgandhi 18:6a4db94011d3 765 static void uart5_vec_async(void)
sahilmgandhi 18:6a4db94011d3 766 {
sahilmgandhi 18:6a4db94011d3 767 uart_irq_async(uart5_var.obj);
sahilmgandhi 18:6a4db94011d3 768 }
sahilmgandhi 18:6a4db94011d3 769
sahilmgandhi 18:6a4db94011d3 770 static void uart_irq_async(serial_t *obj)
sahilmgandhi 18:6a4db94011d3 771 {
sahilmgandhi 18:6a4db94011d3 772 if (serial_is_irq_en(obj, RxIrq)) {
sahilmgandhi 18:6a4db94011d3 773 (*obj->serial.irq_handler_rx_async)();
sahilmgandhi 18:6a4db94011d3 774 }
sahilmgandhi 18:6a4db94011d3 775 if (serial_is_irq_en(obj, TxIrq)) {
sahilmgandhi 18:6a4db94011d3 776 (*obj->serial.irq_handler_tx_async)();
sahilmgandhi 18:6a4db94011d3 777 }
sahilmgandhi 18:6a4db94011d3 778 }
sahilmgandhi 18:6a4db94011d3 779
sahilmgandhi 18:6a4db94011d3 780 static void serial_rx_set_char_match(serial_t *obj, uint8_t char_match)
sahilmgandhi 18:6a4db94011d3 781 {
sahilmgandhi 18:6a4db94011d3 782 obj->char_match = char_match;
sahilmgandhi 18:6a4db94011d3 783 obj->char_found = 0;
sahilmgandhi 18:6a4db94011d3 784 }
sahilmgandhi 18:6a4db94011d3 785
sahilmgandhi 18:6a4db94011d3 786 static void serial_tx_enable_event(serial_t *obj, int event, uint8_t enable)
sahilmgandhi 18:6a4db94011d3 787 {
sahilmgandhi 18:6a4db94011d3 788 obj->serial.event &= ~SERIAL_EVENT_TX_MASK;
sahilmgandhi 18:6a4db94011d3 789 obj->serial.event |= (event & SERIAL_EVENT_TX_MASK);
sahilmgandhi 18:6a4db94011d3 790
sahilmgandhi 18:6a4db94011d3 791 //if (event & SERIAL_EVENT_TX_COMPLETE) {
sahilmgandhi 18:6a4db94011d3 792 //}
sahilmgandhi 18:6a4db94011d3 793 }
sahilmgandhi 18:6a4db94011d3 794
sahilmgandhi 18:6a4db94011d3 795 static void serial_rx_enable_event(serial_t *obj, int event, uint8_t enable)
sahilmgandhi 18:6a4db94011d3 796 {
sahilmgandhi 18:6a4db94011d3 797 obj->serial.event &= ~SERIAL_EVENT_RX_MASK;
sahilmgandhi 18:6a4db94011d3 798 obj->serial.event |= (event & SERIAL_EVENT_RX_MASK);
sahilmgandhi 18:6a4db94011d3 799
sahilmgandhi 18:6a4db94011d3 800 //if (event & SERIAL_EVENT_RX_COMPLETE) {
sahilmgandhi 18:6a4db94011d3 801 //}
sahilmgandhi 18:6a4db94011d3 802 //if (event & SERIAL_EVENT_RX_OVERRUN_ERROR) {
sahilmgandhi 18:6a4db94011d3 803 //}
sahilmgandhi 18:6a4db94011d3 804 if (event & SERIAL_EVENT_RX_FRAMING_ERROR) {
sahilmgandhi 18:6a4db94011d3 805 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RLSIEN_Msk);
sahilmgandhi 18:6a4db94011d3 806 }
sahilmgandhi 18:6a4db94011d3 807 if (event & SERIAL_EVENT_RX_PARITY_ERROR) {
sahilmgandhi 18:6a4db94011d3 808 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RLSIEN_Msk);
sahilmgandhi 18:6a4db94011d3 809 }
sahilmgandhi 18:6a4db94011d3 810 if (event & SERIAL_EVENT_RX_OVERFLOW) {
sahilmgandhi 18:6a4db94011d3 811 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_BUFERRIEN_Msk);
sahilmgandhi 18:6a4db94011d3 812 }
sahilmgandhi 18:6a4db94011d3 813 //if (event & SERIAL_EVENT_RX_CHARACTER_MATCH) {
sahilmgandhi 18:6a4db94011d3 814 //}
sahilmgandhi 18:6a4db94011d3 815 }
sahilmgandhi 18:6a4db94011d3 816
sahilmgandhi 18:6a4db94011d3 817 static int serial_is_tx_complete(serial_t *obj)
sahilmgandhi 18:6a4db94011d3 818 {
sahilmgandhi 18:6a4db94011d3 819 // NOTE: Exclude tx fifo empty check due to no such interrupt on DMA way
sahilmgandhi 18:6a4db94011d3 820 //return (obj->tx_buff.pos == obj->tx_buff.length) && UART_GET_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart)));
sahilmgandhi 18:6a4db94011d3 821 // FIXME: Premature abort???
sahilmgandhi 18:6a4db94011d3 822 return (obj->tx_buff.pos == obj->tx_buff.length);
sahilmgandhi 18:6a4db94011d3 823 }
sahilmgandhi 18:6a4db94011d3 824
sahilmgandhi 18:6a4db94011d3 825 static int serial_is_rx_complete(serial_t *obj)
sahilmgandhi 18:6a4db94011d3 826 {
sahilmgandhi 18:6a4db94011d3 827 //return (obj->rx_buff.pos == obj->rx_buff.length) && UART_GET_RX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart)));
sahilmgandhi 18:6a4db94011d3 828 return (obj->rx_buff.pos == obj->rx_buff.length);
sahilmgandhi 18:6a4db94011d3 829 }
sahilmgandhi 18:6a4db94011d3 830
sahilmgandhi 18:6a4db94011d3 831 static uint32_t serial_tx_event_check(serial_t *obj)
sahilmgandhi 18:6a4db94011d3 832 {
sahilmgandhi 18:6a4db94011d3 833 UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
sahilmgandhi 18:6a4db94011d3 834
sahilmgandhi 18:6a4db94011d3 835 if (uart_base->INTSTS & UART_INTSTS_THREINT_Msk) {
sahilmgandhi 18:6a4db94011d3 836 // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next write.
sahilmgandhi 18:6a4db94011d3 837 UART_DISABLE_INT(uart_base, UART_INTEN_THREIEN_Msk);
sahilmgandhi 18:6a4db94011d3 838 }
sahilmgandhi 18:6a4db94011d3 839
sahilmgandhi 18:6a4db94011d3 840 uint32_t event = 0;
sahilmgandhi 18:6a4db94011d3 841
sahilmgandhi 18:6a4db94011d3 842 if (obj->serial.dma_usage_tx == DMA_USAGE_NEVER) {
sahilmgandhi 18:6a4db94011d3 843 serial_write_async(obj);
sahilmgandhi 18:6a4db94011d3 844 }
sahilmgandhi 18:6a4db94011d3 845
sahilmgandhi 18:6a4db94011d3 846 if (serial_is_tx_complete(obj)) {
sahilmgandhi 18:6a4db94011d3 847 event |= SERIAL_EVENT_TX_COMPLETE;
sahilmgandhi 18:6a4db94011d3 848 }
sahilmgandhi 18:6a4db94011d3 849
sahilmgandhi 18:6a4db94011d3 850 return event;
sahilmgandhi 18:6a4db94011d3 851 }
sahilmgandhi 18:6a4db94011d3 852
sahilmgandhi 18:6a4db94011d3 853 static uint32_t serial_rx_event_check(serial_t *obj)
sahilmgandhi 18:6a4db94011d3 854 {
sahilmgandhi 18:6a4db94011d3 855 UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
sahilmgandhi 18:6a4db94011d3 856
sahilmgandhi 18:6a4db94011d3 857 if (uart_base->INTSTS & (UART_INTSTS_RDAINT_Msk | UART_INTSTS_RXTOINT_Msk)) {
sahilmgandhi 18:6a4db94011d3 858 // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next read.
sahilmgandhi 18:6a4db94011d3 859 UART_DISABLE_INT(uart_base, (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
sahilmgandhi 18:6a4db94011d3 860 }
sahilmgandhi 18:6a4db94011d3 861
sahilmgandhi 18:6a4db94011d3 862 uint32_t event = 0;
sahilmgandhi 18:6a4db94011d3 863
sahilmgandhi 18:6a4db94011d3 864 if (uart_base->FIFOSTS & UART_FIFOSTS_BIF_Msk) {
sahilmgandhi 18:6a4db94011d3 865 uart_base->FIFOSTS = UART_FIFOSTS_BIF_Msk;
sahilmgandhi 18:6a4db94011d3 866 }
sahilmgandhi 18:6a4db94011d3 867 if (uart_base->FIFOSTS & UART_FIFOSTS_FEF_Msk) {
sahilmgandhi 18:6a4db94011d3 868 uart_base->FIFOSTS = UART_FIFOSTS_FEF_Msk;
sahilmgandhi 18:6a4db94011d3 869 event |= SERIAL_EVENT_RX_FRAMING_ERROR;
sahilmgandhi 18:6a4db94011d3 870 }
sahilmgandhi 18:6a4db94011d3 871 if (uart_base->FIFOSTS & UART_FIFOSTS_PEF_Msk) {
sahilmgandhi 18:6a4db94011d3 872 uart_base->FIFOSTS = UART_FIFOSTS_PEF_Msk;
sahilmgandhi 18:6a4db94011d3 873 event |= SERIAL_EVENT_RX_PARITY_ERROR;
sahilmgandhi 18:6a4db94011d3 874 }
sahilmgandhi 18:6a4db94011d3 875
sahilmgandhi 18:6a4db94011d3 876 if (uart_base->FIFOSTS & UART_FIFOSTS_RXOVIF_Msk) {
sahilmgandhi 18:6a4db94011d3 877 uart_base->FIFOSTS = UART_FIFOSTS_RXOVIF_Msk;
sahilmgandhi 18:6a4db94011d3 878 event |= SERIAL_EVENT_RX_OVERFLOW;
sahilmgandhi 18:6a4db94011d3 879 }
sahilmgandhi 18:6a4db94011d3 880
sahilmgandhi 18:6a4db94011d3 881 if (obj->serial.dma_usage_rx == DMA_USAGE_NEVER) {
sahilmgandhi 18:6a4db94011d3 882 serial_read_async(obj);
sahilmgandhi 18:6a4db94011d3 883 }
sahilmgandhi 18:6a4db94011d3 884
sahilmgandhi 18:6a4db94011d3 885 if (serial_is_rx_complete(obj)) {
sahilmgandhi 18:6a4db94011d3 886 event |= SERIAL_EVENT_RX_COMPLETE;
sahilmgandhi 18:6a4db94011d3 887 }
sahilmgandhi 18:6a4db94011d3 888 if ((obj->char_match != SERIAL_RESERVED_CHAR_MATCH) && obj->char_found) {
sahilmgandhi 18:6a4db94011d3 889 event |= SERIAL_EVENT_RX_CHARACTER_MATCH;
sahilmgandhi 18:6a4db94011d3 890 // FIXME: Timing to reset char_found?
sahilmgandhi 18:6a4db94011d3 891 //obj->char_found = 0;
sahilmgandhi 18:6a4db94011d3 892 }
sahilmgandhi 18:6a4db94011d3 893
sahilmgandhi 18:6a4db94011d3 894 return event;
sahilmgandhi 18:6a4db94011d3 895 }
sahilmgandhi 18:6a4db94011d3 896
sahilmgandhi 18:6a4db94011d3 897 static void uart_dma_handler_tx(uint32_t id, uint32_t event_dma)
sahilmgandhi 18:6a4db94011d3 898 {
sahilmgandhi 18:6a4db94011d3 899 serial_t *obj = (serial_t *) id;
sahilmgandhi 18:6a4db94011d3 900
sahilmgandhi 18:6a4db94011d3 901 // FIXME: Pass this error to caller
sahilmgandhi 18:6a4db94011d3 902 if (event_dma & DMA_EVENT_ABORT) {
sahilmgandhi 18:6a4db94011d3 903 }
sahilmgandhi 18:6a4db94011d3 904 // Expect UART IRQ will catch this transfer done event
sahilmgandhi 18:6a4db94011d3 905 if (event_dma & DMA_EVENT_TRANSFER_DONE) {
sahilmgandhi 18:6a4db94011d3 906 obj->tx_buff.pos = obj->tx_buff.length;
sahilmgandhi 18:6a4db94011d3 907 }
sahilmgandhi 18:6a4db94011d3 908 // FIXME: Pass this error to caller
sahilmgandhi 18:6a4db94011d3 909 if (event_dma & DMA_EVENT_TIMEOUT) {
sahilmgandhi 18:6a4db94011d3 910 }
sahilmgandhi 18:6a4db94011d3 911
sahilmgandhi 18:6a4db94011d3 912 uart_irq_async(obj);
sahilmgandhi 18:6a4db94011d3 913 }
sahilmgandhi 18:6a4db94011d3 914
sahilmgandhi 18:6a4db94011d3 915 static void uart_dma_handler_rx(uint32_t id, uint32_t event_dma)
sahilmgandhi 18:6a4db94011d3 916 {
sahilmgandhi 18:6a4db94011d3 917 serial_t *obj = (serial_t *) id;
sahilmgandhi 18:6a4db94011d3 918
sahilmgandhi 18:6a4db94011d3 919 // FIXME: Pass this error to caller
sahilmgandhi 18:6a4db94011d3 920 if (event_dma & DMA_EVENT_ABORT) {
sahilmgandhi 18:6a4db94011d3 921 }
sahilmgandhi 18:6a4db94011d3 922 // Expect UART IRQ will catch this transfer done event
sahilmgandhi 18:6a4db94011d3 923 if (event_dma & DMA_EVENT_TRANSFER_DONE) {
sahilmgandhi 18:6a4db94011d3 924 obj->rx_buff.pos = obj->rx_buff.length;
sahilmgandhi 18:6a4db94011d3 925 }
sahilmgandhi 18:6a4db94011d3 926 // FIXME: Pass this error to caller
sahilmgandhi 18:6a4db94011d3 927 if (event_dma & DMA_EVENT_TIMEOUT) {
sahilmgandhi 18:6a4db94011d3 928 }
sahilmgandhi 18:6a4db94011d3 929
sahilmgandhi 18:6a4db94011d3 930 uart_irq_async(obj);
sahilmgandhi 18:6a4db94011d3 931 }
sahilmgandhi 18:6a4db94011d3 932
sahilmgandhi 18:6a4db94011d3 933 static int serial_write_async(serial_t *obj)
sahilmgandhi 18:6a4db94011d3 934 {
sahilmgandhi 18:6a4db94011d3 935 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
sahilmgandhi 18:6a4db94011d3 936 MBED_ASSERT(modinit != NULL);
sahilmgandhi 18:6a4db94011d3 937 MBED_ASSERT(modinit->modname == obj->serial.uart);
sahilmgandhi 18:6a4db94011d3 938
sahilmgandhi 18:6a4db94011d3 939 UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
sahilmgandhi 18:6a4db94011d3 940
sahilmgandhi 18:6a4db94011d3 941 uint32_t tx_fifo_max = ((struct nu_uart_var *) modinit->var)->fifo_size_tx;
sahilmgandhi 18:6a4db94011d3 942 uint32_t tx_fifo_busy = (uart_base->FIFOSTS & UART_FIFOSTS_TXPTR_Msk) >> UART_FIFOSTS_TXPTR_Pos;
sahilmgandhi 18:6a4db94011d3 943 if (uart_base->FIFOSTS & UART_FIFOSTS_TXFULL_Msk) {
sahilmgandhi 18:6a4db94011d3 944 tx_fifo_busy = tx_fifo_max;
sahilmgandhi 18:6a4db94011d3 945 }
sahilmgandhi 18:6a4db94011d3 946 uint32_t tx_fifo_free = tx_fifo_max - tx_fifo_busy;
sahilmgandhi 18:6a4db94011d3 947 if (tx_fifo_free == 0) {
sahilmgandhi 18:6a4db94011d3 948 // Simulate clear of the interrupt flag
sahilmgandhi 18:6a4db94011d3 949 if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) {
sahilmgandhi 18:6a4db94011d3 950 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
sahilmgandhi 18:6a4db94011d3 951 }
sahilmgandhi 18:6a4db94011d3 952 return 0;
sahilmgandhi 18:6a4db94011d3 953 }
sahilmgandhi 18:6a4db94011d3 954
sahilmgandhi 18:6a4db94011d3 955 uint32_t bytes_per_word = obj->tx_buff.width / 8;
sahilmgandhi 18:6a4db94011d3 956
sahilmgandhi 18:6a4db94011d3 957 uint8_t *tx = (uint8_t *)(obj->tx_buff.buffer) + bytes_per_word * obj->tx_buff.pos;
sahilmgandhi 18:6a4db94011d3 958 int n_words = 0;
sahilmgandhi 18:6a4db94011d3 959 while (obj->tx_buff.pos < obj->tx_buff.length && tx_fifo_free >= bytes_per_word) {
sahilmgandhi 18:6a4db94011d3 960 switch (bytes_per_word) {
sahilmgandhi 18:6a4db94011d3 961 case 4:
sahilmgandhi 18:6a4db94011d3 962 UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
sahilmgandhi 18:6a4db94011d3 963 UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
sahilmgandhi 18:6a4db94011d3 964 case 2:
sahilmgandhi 18:6a4db94011d3 965 UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
sahilmgandhi 18:6a4db94011d3 966 case 1:
sahilmgandhi 18:6a4db94011d3 967 UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
sahilmgandhi 18:6a4db94011d3 968 }
sahilmgandhi 18:6a4db94011d3 969
sahilmgandhi 18:6a4db94011d3 970 n_words ++;
sahilmgandhi 18:6a4db94011d3 971 tx_fifo_free -= bytes_per_word;
sahilmgandhi 18:6a4db94011d3 972 obj->tx_buff.pos ++;
sahilmgandhi 18:6a4db94011d3 973 }
sahilmgandhi 18:6a4db94011d3 974
sahilmgandhi 18:6a4db94011d3 975 if (n_words) {
sahilmgandhi 18:6a4db94011d3 976 // Simulate clear of the interrupt flag
sahilmgandhi 18:6a4db94011d3 977 if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) {
sahilmgandhi 18:6a4db94011d3 978 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
sahilmgandhi 18:6a4db94011d3 979 }
sahilmgandhi 18:6a4db94011d3 980 }
sahilmgandhi 18:6a4db94011d3 981
sahilmgandhi 18:6a4db94011d3 982 return n_words;
sahilmgandhi 18:6a4db94011d3 983 }
sahilmgandhi 18:6a4db94011d3 984
sahilmgandhi 18:6a4db94011d3 985 static int serial_read_async(serial_t *obj)
sahilmgandhi 18:6a4db94011d3 986 {
sahilmgandhi 18:6a4db94011d3 987 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
sahilmgandhi 18:6a4db94011d3 988 MBED_ASSERT(modinit != NULL);
sahilmgandhi 18:6a4db94011d3 989 MBED_ASSERT(modinit->modname == obj->serial.uart);
sahilmgandhi 18:6a4db94011d3 990
sahilmgandhi 18:6a4db94011d3 991 uint32_t rx_fifo_busy = (((UART_T *) NU_MODBASE(obj->serial.uart))->FIFOSTS & UART_FIFOSTS_RXPTR_Msk) >> UART_FIFOSTS_RXPTR_Pos;
sahilmgandhi 18:6a4db94011d3 992 //uint32_t rx_fifo_free = ((struct nu_uart_var *) modinit->var)->fifo_size_rx - rx_fifo_busy;
sahilmgandhi 18:6a4db94011d3 993 //if (rx_fifo_free == 0) {
sahilmgandhi 18:6a4db94011d3 994 // return 0;
sahilmgandhi 18:6a4db94011d3 995 //}
sahilmgandhi 18:6a4db94011d3 996
sahilmgandhi 18:6a4db94011d3 997 uint32_t bytes_per_word = obj->rx_buff.width / 8;
sahilmgandhi 18:6a4db94011d3 998
sahilmgandhi 18:6a4db94011d3 999 uint8_t *rx = (uint8_t *)(obj->rx_buff.buffer) + bytes_per_word * obj->rx_buff.pos;
sahilmgandhi 18:6a4db94011d3 1000 int n_words = 0;
sahilmgandhi 18:6a4db94011d3 1001 while (obj->rx_buff.pos < obj->rx_buff.length && rx_fifo_busy >= bytes_per_word) {
sahilmgandhi 18:6a4db94011d3 1002 switch (bytes_per_word) {
sahilmgandhi 18:6a4db94011d3 1003 case 4:
sahilmgandhi 18:6a4db94011d3 1004 *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
sahilmgandhi 18:6a4db94011d3 1005 *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
sahilmgandhi 18:6a4db94011d3 1006 case 2:
sahilmgandhi 18:6a4db94011d3 1007 *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
sahilmgandhi 18:6a4db94011d3 1008 case 1:
sahilmgandhi 18:6a4db94011d3 1009 *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
sahilmgandhi 18:6a4db94011d3 1010 }
sahilmgandhi 18:6a4db94011d3 1011
sahilmgandhi 18:6a4db94011d3 1012 n_words ++;
sahilmgandhi 18:6a4db94011d3 1013 rx_fifo_busy -= bytes_per_word;
sahilmgandhi 18:6a4db94011d3 1014 obj->rx_buff.pos ++;
sahilmgandhi 18:6a4db94011d3 1015
sahilmgandhi 18:6a4db94011d3 1016 if ((obj->serial.event & SERIAL_EVENT_RX_CHARACTER_MATCH) &&
sahilmgandhi 18:6a4db94011d3 1017 obj->char_match != SERIAL_RESERVED_CHAR_MATCH) {
sahilmgandhi 18:6a4db94011d3 1018 uint8_t *rx_cmp = rx;
sahilmgandhi 18:6a4db94011d3 1019 switch (bytes_per_word) {
sahilmgandhi 18:6a4db94011d3 1020 case 4:
sahilmgandhi 18:6a4db94011d3 1021 rx_cmp -= 2;
sahilmgandhi 18:6a4db94011d3 1022 case 2:
sahilmgandhi 18:6a4db94011d3 1023 rx_cmp --;
sahilmgandhi 18:6a4db94011d3 1024 case 1:
sahilmgandhi 18:6a4db94011d3 1025 rx_cmp --;
sahilmgandhi 18:6a4db94011d3 1026 }
sahilmgandhi 18:6a4db94011d3 1027 if (*rx_cmp == obj->char_match) {
sahilmgandhi 18:6a4db94011d3 1028 obj->char_found = 1;
sahilmgandhi 18:6a4db94011d3 1029 break;
sahilmgandhi 18:6a4db94011d3 1030 }
sahilmgandhi 18:6a4db94011d3 1031 }
sahilmgandhi 18:6a4db94011d3 1032 }
sahilmgandhi 18:6a4db94011d3 1033
sahilmgandhi 18:6a4db94011d3 1034 if (n_words) {
sahilmgandhi 18:6a4db94011d3 1035 // Simulate clear of the interrupt flag
sahilmgandhi 18:6a4db94011d3 1036 if (obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) {
sahilmgandhi 18:6a4db94011d3 1037 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
sahilmgandhi 18:6a4db94011d3 1038 }
sahilmgandhi 18:6a4db94011d3 1039 }
sahilmgandhi 18:6a4db94011d3 1040
sahilmgandhi 18:6a4db94011d3 1041 return n_words;
sahilmgandhi 18:6a4db94011d3 1042 }
sahilmgandhi 18:6a4db94011d3 1043
sahilmgandhi 18:6a4db94011d3 1044 static void serial_tx_buffer_set(serial_t *obj, const void *tx, size_t length, uint8_t width)
sahilmgandhi 18:6a4db94011d3 1045 {
sahilmgandhi 18:6a4db94011d3 1046 obj->tx_buff.buffer = (void *) tx;
sahilmgandhi 18:6a4db94011d3 1047 obj->tx_buff.length = length;
sahilmgandhi 18:6a4db94011d3 1048 obj->tx_buff.pos = 0;
sahilmgandhi 18:6a4db94011d3 1049 obj->tx_buff.width = width;
sahilmgandhi 18:6a4db94011d3 1050 }
sahilmgandhi 18:6a4db94011d3 1051
sahilmgandhi 18:6a4db94011d3 1052 static void serial_rx_buffer_set(serial_t *obj, void *rx, size_t length, uint8_t width)
sahilmgandhi 18:6a4db94011d3 1053 {
sahilmgandhi 18:6a4db94011d3 1054 obj->rx_buff.buffer = rx;
sahilmgandhi 18:6a4db94011d3 1055 obj->rx_buff.length = length;
sahilmgandhi 18:6a4db94011d3 1056 obj->rx_buff.pos = 0;
sahilmgandhi 18:6a4db94011d3 1057 obj->rx_buff.width = width;
sahilmgandhi 18:6a4db94011d3 1058 }
sahilmgandhi 18:6a4db94011d3 1059
sahilmgandhi 18:6a4db94011d3 1060 static void serial_tx_enable_interrupt(serial_t *obj, uint32_t handler, uint8_t enable)
sahilmgandhi 18:6a4db94011d3 1061 {
sahilmgandhi 18:6a4db94011d3 1062 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
sahilmgandhi 18:6a4db94011d3 1063 MBED_ASSERT(modinit != NULL);
sahilmgandhi 18:6a4db94011d3 1064 MBED_ASSERT(modinit->modname == obj->serial.uart);
sahilmgandhi 18:6a4db94011d3 1065
sahilmgandhi 18:6a4db94011d3 1066 // Necessary for both interrupt way and DMA way
sahilmgandhi 18:6a4db94011d3 1067 struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
sahilmgandhi 18:6a4db94011d3 1068 // With our own async vector, tx/rx handlers can be different.
sahilmgandhi 18:6a4db94011d3 1069 obj->serial.vec = var->vec_async;
sahilmgandhi 18:6a4db94011d3 1070 obj->serial.irq_handler_tx_async = (void (*)(void)) handler;
sahilmgandhi 18:6a4db94011d3 1071 serial_irq_set(obj, TxIrq, enable);
sahilmgandhi 18:6a4db94011d3 1072 }
sahilmgandhi 18:6a4db94011d3 1073
sahilmgandhi 18:6a4db94011d3 1074 static void serial_rx_enable_interrupt(serial_t *obj, uint32_t handler, uint8_t enable)
sahilmgandhi 18:6a4db94011d3 1075 {
sahilmgandhi 18:6a4db94011d3 1076 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
sahilmgandhi 18:6a4db94011d3 1077 MBED_ASSERT(modinit != NULL);
sahilmgandhi 18:6a4db94011d3 1078 MBED_ASSERT(modinit->modname == obj->serial.uart);
sahilmgandhi 18:6a4db94011d3 1079
sahilmgandhi 18:6a4db94011d3 1080 // Necessary for both interrupt way and DMA way
sahilmgandhi 18:6a4db94011d3 1081 struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
sahilmgandhi 18:6a4db94011d3 1082 // With our own async vector, tx/rx handlers can be different.
sahilmgandhi 18:6a4db94011d3 1083 obj->serial.vec = var->vec_async;
sahilmgandhi 18:6a4db94011d3 1084 obj->serial.irq_handler_rx_async = (void (*) (void)) handler;
sahilmgandhi 18:6a4db94011d3 1085 serial_irq_set(obj, RxIrq, enable);
sahilmgandhi 18:6a4db94011d3 1086 }
sahilmgandhi 18:6a4db94011d3 1087
sahilmgandhi 18:6a4db94011d3 1088 static void serial_check_dma_usage(DMAUsage *dma_usage, int *dma_ch)
sahilmgandhi 18:6a4db94011d3 1089 {
sahilmgandhi 18:6a4db94011d3 1090 if (*dma_usage != DMA_USAGE_NEVER) {
sahilmgandhi 18:6a4db94011d3 1091 if (*dma_ch == DMA_ERROR_OUT_OF_CHANNELS) {
sahilmgandhi 18:6a4db94011d3 1092 *dma_ch = dma_channel_allocate(DMA_CAP_NONE);
sahilmgandhi 18:6a4db94011d3 1093 }
sahilmgandhi 18:6a4db94011d3 1094 if (*dma_ch == DMA_ERROR_OUT_OF_CHANNELS) {
sahilmgandhi 18:6a4db94011d3 1095 *dma_usage = DMA_USAGE_NEVER;
sahilmgandhi 18:6a4db94011d3 1096 }
sahilmgandhi 18:6a4db94011d3 1097 }
sahilmgandhi 18:6a4db94011d3 1098 else {
sahilmgandhi 18:6a4db94011d3 1099 dma_channel_free(*dma_ch);
sahilmgandhi 18:6a4db94011d3 1100 *dma_ch = DMA_ERROR_OUT_OF_CHANNELS;
sahilmgandhi 18:6a4db94011d3 1101 }
sahilmgandhi 18:6a4db94011d3 1102 }
sahilmgandhi 18:6a4db94011d3 1103
sahilmgandhi 18:6a4db94011d3 1104 static int serial_is_irq_en(serial_t *obj, SerialIrq irq)
sahilmgandhi 18:6a4db94011d3 1105 {
sahilmgandhi 18:6a4db94011d3 1106 int inten_msk = 0;
sahilmgandhi 18:6a4db94011d3 1107
sahilmgandhi 18:6a4db94011d3 1108 switch (irq) {
sahilmgandhi 18:6a4db94011d3 1109 case RxIrq:
sahilmgandhi 18:6a4db94011d3 1110 inten_msk = obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk);
sahilmgandhi 18:6a4db94011d3 1111 break;
sahilmgandhi 18:6a4db94011d3 1112 case TxIrq:
sahilmgandhi 18:6a4db94011d3 1113 inten_msk = obj->serial.inten_msk & UART_INTEN_THREIEN_Msk;
sahilmgandhi 18:6a4db94011d3 1114 break;
sahilmgandhi 18:6a4db94011d3 1115 }
sahilmgandhi 18:6a4db94011d3 1116
sahilmgandhi 18:6a4db94011d3 1117 return !! inten_msk;
sahilmgandhi 18:6a4db94011d3 1118 }
sahilmgandhi 18:6a4db94011d3 1119
sahilmgandhi 18:6a4db94011d3 1120 #endif // #if DEVICE_SERIAL_ASYNCH
sahilmgandhi 18:6a4db94011d3 1121 #endif // #if DEVICE_SERIAL