MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NUVOTON/TARGET_NUC472/pwmout_api.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2015-2016 Nuvoton
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 */
sahilmgandhi 18:6a4db94011d3 16
sahilmgandhi 18:6a4db94011d3 17 #include "pwmout_api.h"
sahilmgandhi 18:6a4db94011d3 18
sahilmgandhi 18:6a4db94011d3 19 #if DEVICE_PWMOUT
sahilmgandhi 18:6a4db94011d3 20
sahilmgandhi 18:6a4db94011d3 21 #include "cmsis.h"
sahilmgandhi 18:6a4db94011d3 22 #include "pinmap.h"
sahilmgandhi 18:6a4db94011d3 23 #include "PeripheralPins.h"
sahilmgandhi 18:6a4db94011d3 24 #include "nu_modutil.h"
sahilmgandhi 18:6a4db94011d3 25 #include "nu_miscutil.h"
sahilmgandhi 18:6a4db94011d3 26 #include "nu_bitutil.h"
sahilmgandhi 18:6a4db94011d3 27
sahilmgandhi 18:6a4db94011d3 28 struct nu_pwm_var {
sahilmgandhi 18:6a4db94011d3 29 uint32_t en_msk;
sahilmgandhi 18:6a4db94011d3 30 };
sahilmgandhi 18:6a4db94011d3 31
sahilmgandhi 18:6a4db94011d3 32 static struct nu_pwm_var pwm0_var = {
sahilmgandhi 18:6a4db94011d3 33 .en_msk = 0
sahilmgandhi 18:6a4db94011d3 34 };
sahilmgandhi 18:6a4db94011d3 35
sahilmgandhi 18:6a4db94011d3 36 static struct nu_pwm_var pwm1_var = {
sahilmgandhi 18:6a4db94011d3 37 .en_msk = 0
sahilmgandhi 18:6a4db94011d3 38 };
sahilmgandhi 18:6a4db94011d3 39
sahilmgandhi 18:6a4db94011d3 40 static uint32_t pwm_modinit_mask = 0;
sahilmgandhi 18:6a4db94011d3 41
sahilmgandhi 18:6a4db94011d3 42 // FIXME: PWM1 2/3 channels fail. PWM registers cannot write after their respective clocks are enabled.
sahilmgandhi 18:6a4db94011d3 43 static const struct nu_modinit_s pwm_modinit_tab[] = {
sahilmgandhi 18:6a4db94011d3 44 {PWM_0_0, PWM0CH01_MODULE, CLK_CLKSEL2_PWM0CH01SEL_HIRC, 0, PWM0_RST, PWM0CH0_IRQn, &pwm0_var},
sahilmgandhi 18:6a4db94011d3 45 {PWM_0_1, PWM0CH01_MODULE, CLK_CLKSEL2_PWM0CH01SEL_HIRC, 0, PWM0_RST, PWM0CH1_IRQn, &pwm0_var},
sahilmgandhi 18:6a4db94011d3 46 {PWM_0_2, PWM0CH23_MODULE, CLK_CLKSEL2_PWM0CH23SEL_HIRC, 0, PWM0_RST, PWM0CH2_IRQn, &pwm0_var},
sahilmgandhi 18:6a4db94011d3 47 {PWM_0_3, PWM0CH23_MODULE, CLK_CLKSEL2_PWM0CH23SEL_HIRC, 0, PWM0_RST, PWM0CH3_IRQn, &pwm0_var},
sahilmgandhi 18:6a4db94011d3 48 {PWM_0_4, PWM0CH45_MODULE, CLK_CLKSEL2_PWM0CH45SEL_HIRC, 0, PWM0_RST, PWM0CH4_IRQn, &pwm0_var},
sahilmgandhi 18:6a4db94011d3 49 {PWM_0_5, PWM0CH45_MODULE, CLK_CLKSEL2_PWM0CH45SEL_HIRC, 0, PWM0_RST, PWM0CH5_IRQn, &pwm0_var},
sahilmgandhi 18:6a4db94011d3 50
sahilmgandhi 18:6a4db94011d3 51 {PWM_1_0, PWM1CH01_MODULE, CLK_CLKSEL2_PWM1CH01SEL_HIRC, 0, PWM1_RST, PWM1CH0_IRQn, &pwm1_var},
sahilmgandhi 18:6a4db94011d3 52 {PWM_1_1, PWM1CH01_MODULE, CLK_CLKSEL2_PWM1CH01SEL_HIRC, 0, PWM1_RST, PWM1CH1_IRQn, &pwm1_var},
sahilmgandhi 18:6a4db94011d3 53 {PWM_1_2, PWM1CH23_MODULE, CLK_CLKSEL2_PWM1CH23SEL_HIRC, 0, PWM1_RST, PWM1CH2_IRQn, &pwm1_var},
sahilmgandhi 18:6a4db94011d3 54 {PWM_1_3, PWM1CH23_MODULE, CLK_CLKSEL2_PWM1CH23SEL_HIRC, 0, PWM1_RST, PWM1CH3_IRQn, &pwm1_var},
sahilmgandhi 18:6a4db94011d3 55 {PWM_1_4, PWM1CH45_MODULE, CLK_CLKSEL2_PWM1CH45SEL_HIRC, 0, PWM1_RST, PWM1CH4_IRQn, &pwm1_var},
sahilmgandhi 18:6a4db94011d3 56 {PWM_1_5, PWM1CH45_MODULE, CLK_CLKSEL2_PWM1CH45SEL_HIRC, 0, PWM1_RST, PWM1CH5_IRQn, &pwm1_var},
sahilmgandhi 18:6a4db94011d3 57
sahilmgandhi 18:6a4db94011d3 58 {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL}
sahilmgandhi 18:6a4db94011d3 59 };
sahilmgandhi 18:6a4db94011d3 60
sahilmgandhi 18:6a4db94011d3 61 static void pwmout_config(pwmout_t* obj);
sahilmgandhi 18:6a4db94011d3 62
sahilmgandhi 18:6a4db94011d3 63 void pwmout_init(pwmout_t* obj, PinName pin)
sahilmgandhi 18:6a4db94011d3 64 {
sahilmgandhi 18:6a4db94011d3 65 obj->pwm = (PWMName) pinmap_peripheral(pin, PinMap_PWM);
sahilmgandhi 18:6a4db94011d3 66 MBED_ASSERT((int) obj->pwm != NC);
sahilmgandhi 18:6a4db94011d3 67
sahilmgandhi 18:6a4db94011d3 68 const struct nu_modinit_s *modinit = get_modinit(obj->pwm, pwm_modinit_tab);
sahilmgandhi 18:6a4db94011d3 69 MBED_ASSERT(modinit != NULL);
sahilmgandhi 18:6a4db94011d3 70 MBED_ASSERT(modinit->modname == obj->pwm);
sahilmgandhi 18:6a4db94011d3 71
sahilmgandhi 18:6a4db94011d3 72 // NOTE: All channels (identified by PWMName) share a PWM module. This reset will also affect other channels of the same PWM module.
sahilmgandhi 18:6a4db94011d3 73 if (! ((struct nu_pwm_var *) modinit->var)->en_msk) {
sahilmgandhi 18:6a4db94011d3 74 // Reset this module if no channel enabled
sahilmgandhi 18:6a4db94011d3 75 SYS_ResetModule(modinit->rsetidx);
sahilmgandhi 18:6a4db94011d3 76 }
sahilmgandhi 18:6a4db94011d3 77
sahilmgandhi 18:6a4db94011d3 78 PWM_T *pwm_base = (PWM_T *) NU_MODBASE(obj->pwm);
sahilmgandhi 18:6a4db94011d3 79 uint32_t chn = NU_MODSUBINDEX(obj->pwm);
sahilmgandhi 18:6a4db94011d3 80
sahilmgandhi 18:6a4db94011d3 81 // NOTE: Channels 0/1, 2/3, and 4/5 share a clock source.
sahilmgandhi 18:6a4db94011d3 82 if ((((struct nu_pwm_var *) modinit->var)->en_msk & (0x3 << (chn / 2 * 2))) == 0) {
sahilmgandhi 18:6a4db94011d3 83 // Select clock source of paired channels
sahilmgandhi 18:6a4db94011d3 84 CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
sahilmgandhi 18:6a4db94011d3 85 // Enable clock of paired channels
sahilmgandhi 18:6a4db94011d3 86 CLK_EnableModuleClock(modinit->clkidx);
sahilmgandhi 18:6a4db94011d3 87
sahilmgandhi 18:6a4db94011d3 88 // FIXME: PWM_1_2/3 design bug. PWM_1_2/3 also require PWM_1_0/1 clock enabled.
sahilmgandhi 18:6a4db94011d3 89 if (obj->pwm == PWM_1_2 || obj->pwm == PWM_1_3) {
sahilmgandhi 18:6a4db94011d3 90 CLK_EnableModuleClock(PWM1CH01_MODULE);
sahilmgandhi 18:6a4db94011d3 91 }
sahilmgandhi 18:6a4db94011d3 92 }
sahilmgandhi 18:6a4db94011d3 93
sahilmgandhi 18:6a4db94011d3 94 // Wire pinout
sahilmgandhi 18:6a4db94011d3 95 pinmap_pinout(pin, PinMap_PWM);
sahilmgandhi 18:6a4db94011d3 96
sahilmgandhi 18:6a4db94011d3 97 // Default: period = 10 ms, pulse width = 0 ms
sahilmgandhi 18:6a4db94011d3 98 obj->period_us = 1000 * 10;
sahilmgandhi 18:6a4db94011d3 99 obj->pulsewidth_us = 0;
sahilmgandhi 18:6a4db94011d3 100 pwmout_config(obj);
sahilmgandhi 18:6a4db94011d3 101
sahilmgandhi 18:6a4db94011d3 102 // Enable output of the specified PWM channel
sahilmgandhi 18:6a4db94011d3 103 PWM_EnableOutput(pwm_base, 1 << chn);
sahilmgandhi 18:6a4db94011d3 104 PWM_Start(pwm_base, 1 << chn);
sahilmgandhi 18:6a4db94011d3 105
sahilmgandhi 18:6a4db94011d3 106 ((struct nu_pwm_var *) modinit->var)->en_msk |= 1 << chn;
sahilmgandhi 18:6a4db94011d3 107
sahilmgandhi 18:6a4db94011d3 108 if (((struct nu_pwm_var *) modinit->var)->en_msk) {
sahilmgandhi 18:6a4db94011d3 109 // Mark this module to be inited.
sahilmgandhi 18:6a4db94011d3 110 int i = modinit - pwm_modinit_tab;
sahilmgandhi 18:6a4db94011d3 111 pwm_modinit_mask |= 1 << i;
sahilmgandhi 18:6a4db94011d3 112 }
sahilmgandhi 18:6a4db94011d3 113 }
sahilmgandhi 18:6a4db94011d3 114
sahilmgandhi 18:6a4db94011d3 115 void pwmout_free(pwmout_t* obj)
sahilmgandhi 18:6a4db94011d3 116 {
sahilmgandhi 18:6a4db94011d3 117 PWM_T *pwm_base = (PWM_T *) NU_MODBASE(obj->pwm);
sahilmgandhi 18:6a4db94011d3 118 uint32_t chn = NU_MODSUBINDEX(obj->pwm);
sahilmgandhi 18:6a4db94011d3 119 PWM_ForceStop(pwm_base, 1 << chn);
sahilmgandhi 18:6a4db94011d3 120
sahilmgandhi 18:6a4db94011d3 121 const struct nu_modinit_s *modinit = get_modinit(obj->pwm, pwm_modinit_tab);
sahilmgandhi 18:6a4db94011d3 122 MBED_ASSERT(modinit != NULL);
sahilmgandhi 18:6a4db94011d3 123 MBED_ASSERT(modinit->modname == obj->pwm);
sahilmgandhi 18:6a4db94011d3 124 ((struct nu_pwm_var *) modinit->var)->en_msk &= ~(1 << chn);
sahilmgandhi 18:6a4db94011d3 125
sahilmgandhi 18:6a4db94011d3 126
sahilmgandhi 18:6a4db94011d3 127 if ((((struct nu_pwm_var *) modinit->var)->en_msk & (0x3 << (chn / 2 * 2))) == 0) {
sahilmgandhi 18:6a4db94011d3 128 // FIXME: PWM_1_2/3 design bug. PWM_1_2/3 also require PWM_1_0/1 clock enabled.
sahilmgandhi 18:6a4db94011d3 129 switch (obj->pwm) {
sahilmgandhi 18:6a4db94011d3 130 case PWM_1_0:
sahilmgandhi 18:6a4db94011d3 131 case PWM_1_1:
sahilmgandhi 18:6a4db94011d3 132 if (pwm1_var.en_msk & 0xC) {
sahilmgandhi 18:6a4db94011d3 133 break;
sahilmgandhi 18:6a4db94011d3 134 }
sahilmgandhi 18:6a4db94011d3 135
sahilmgandhi 18:6a4db94011d3 136 case PWM_1_2:
sahilmgandhi 18:6a4db94011d3 137 case PWM_1_3:
sahilmgandhi 18:6a4db94011d3 138 if (! (pwm1_var.en_msk & 0x3)) {
sahilmgandhi 18:6a4db94011d3 139 CLK_DisableModuleClock(PWM1CH01_MODULE);
sahilmgandhi 18:6a4db94011d3 140 }
sahilmgandhi 18:6a4db94011d3 141
sahilmgandhi 18:6a4db94011d3 142 default:
sahilmgandhi 18:6a4db94011d3 143 // Disable clock of paired channels
sahilmgandhi 18:6a4db94011d3 144 CLK_DisableModuleClock(modinit->clkidx);
sahilmgandhi 18:6a4db94011d3 145 }
sahilmgandhi 18:6a4db94011d3 146 }
sahilmgandhi 18:6a4db94011d3 147
sahilmgandhi 18:6a4db94011d3 148 if (((struct nu_pwm_var *) modinit->var)->en_msk == 0) {
sahilmgandhi 18:6a4db94011d3 149 // Mark this module to be deinited.
sahilmgandhi 18:6a4db94011d3 150 int i = modinit - pwm_modinit_tab;
sahilmgandhi 18:6a4db94011d3 151 pwm_modinit_mask &= ~(1 << i);
sahilmgandhi 18:6a4db94011d3 152 }
sahilmgandhi 18:6a4db94011d3 153 }
sahilmgandhi 18:6a4db94011d3 154
sahilmgandhi 18:6a4db94011d3 155 void pwmout_write(pwmout_t* obj, float value)
sahilmgandhi 18:6a4db94011d3 156 {
sahilmgandhi 18:6a4db94011d3 157 obj->pulsewidth_us = NU_CLAMP((uint32_t) (value * obj->period_us), 0, obj->period_us);
sahilmgandhi 18:6a4db94011d3 158 pwmout_config(obj);
sahilmgandhi 18:6a4db94011d3 159 }
sahilmgandhi 18:6a4db94011d3 160
sahilmgandhi 18:6a4db94011d3 161 float pwmout_read(pwmout_t* obj)
sahilmgandhi 18:6a4db94011d3 162 {
sahilmgandhi 18:6a4db94011d3 163 return NU_CLAMP((((float) obj->pulsewidth_us) / obj->period_us), 0.0f, 1.0f);
sahilmgandhi 18:6a4db94011d3 164 }
sahilmgandhi 18:6a4db94011d3 165
sahilmgandhi 18:6a4db94011d3 166 void pwmout_period(pwmout_t* obj, float seconds)
sahilmgandhi 18:6a4db94011d3 167 {
sahilmgandhi 18:6a4db94011d3 168 pwmout_period_us(obj, seconds * 1000000.0f);
sahilmgandhi 18:6a4db94011d3 169 }
sahilmgandhi 18:6a4db94011d3 170
sahilmgandhi 18:6a4db94011d3 171 void pwmout_period_ms(pwmout_t* obj, int ms)
sahilmgandhi 18:6a4db94011d3 172 {
sahilmgandhi 18:6a4db94011d3 173 pwmout_period_us(obj, ms * 1000);
sahilmgandhi 18:6a4db94011d3 174 }
sahilmgandhi 18:6a4db94011d3 175
sahilmgandhi 18:6a4db94011d3 176 // Set the PWM period, keeping the duty cycle the same.
sahilmgandhi 18:6a4db94011d3 177 void pwmout_period_us(pwmout_t* obj, int us)
sahilmgandhi 18:6a4db94011d3 178 {
sahilmgandhi 18:6a4db94011d3 179 uint32_t period_us_old = obj->period_us;
sahilmgandhi 18:6a4db94011d3 180 uint32_t pulsewidth_us_old = obj->pulsewidth_us;
sahilmgandhi 18:6a4db94011d3 181 obj->period_us = us;
sahilmgandhi 18:6a4db94011d3 182 obj->pulsewidth_us = NU_CLAMP(obj->period_us * pulsewidth_us_old / period_us_old, 0, obj->period_us);
sahilmgandhi 18:6a4db94011d3 183 pwmout_config(obj);
sahilmgandhi 18:6a4db94011d3 184 }
sahilmgandhi 18:6a4db94011d3 185
sahilmgandhi 18:6a4db94011d3 186 void pwmout_pulsewidth(pwmout_t* obj, float seconds)
sahilmgandhi 18:6a4db94011d3 187 {
sahilmgandhi 18:6a4db94011d3 188 pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
sahilmgandhi 18:6a4db94011d3 189 }
sahilmgandhi 18:6a4db94011d3 190
sahilmgandhi 18:6a4db94011d3 191 void pwmout_pulsewidth_ms(pwmout_t* obj, int ms)
sahilmgandhi 18:6a4db94011d3 192 {
sahilmgandhi 18:6a4db94011d3 193 pwmout_pulsewidth_us(obj, ms * 1000);
sahilmgandhi 18:6a4db94011d3 194 }
sahilmgandhi 18:6a4db94011d3 195
sahilmgandhi 18:6a4db94011d3 196 void pwmout_pulsewidth_us(pwmout_t* obj, int us)
sahilmgandhi 18:6a4db94011d3 197 {
sahilmgandhi 18:6a4db94011d3 198 obj->pulsewidth_us = NU_CLAMP(us, 0, obj->period_us);
sahilmgandhi 18:6a4db94011d3 199 pwmout_config(obj);
sahilmgandhi 18:6a4db94011d3 200 }
sahilmgandhi 18:6a4db94011d3 201
sahilmgandhi 18:6a4db94011d3 202 int pwmout_allow_powerdown(void)
sahilmgandhi 18:6a4db94011d3 203 {
sahilmgandhi 18:6a4db94011d3 204 uint32_t modinit_mask = pwm_modinit_mask;
sahilmgandhi 18:6a4db94011d3 205 while (modinit_mask) {
sahilmgandhi 18:6a4db94011d3 206 int pwm_idx = nu_ctz(modinit_mask);
sahilmgandhi 18:6a4db94011d3 207 const struct nu_modinit_s *modinit = pwm_modinit_tab + pwm_idx;
sahilmgandhi 18:6a4db94011d3 208 if (modinit->modname != NC) {
sahilmgandhi 18:6a4db94011d3 209 PWM_T *pwm_base = (PWM_T *) NU_MODBASE(modinit->modname);
sahilmgandhi 18:6a4db94011d3 210 uint32_t chn = NU_MODSUBINDEX(modinit->modname);
sahilmgandhi 18:6a4db94011d3 211 // Disallow entering power-down mode if PWM counter is enabled.
sahilmgandhi 18:6a4db94011d3 212 if ((pwm_base->CNTEN & (1 << chn)) && pwm_base->CMPDAT[chn]) {
sahilmgandhi 18:6a4db94011d3 213 return 0;
sahilmgandhi 18:6a4db94011d3 214 }
sahilmgandhi 18:6a4db94011d3 215 }
sahilmgandhi 18:6a4db94011d3 216 modinit_mask &= ~(1 << pwm_idx);
sahilmgandhi 18:6a4db94011d3 217 }
sahilmgandhi 18:6a4db94011d3 218
sahilmgandhi 18:6a4db94011d3 219 return 1;
sahilmgandhi 18:6a4db94011d3 220 }
sahilmgandhi 18:6a4db94011d3 221
sahilmgandhi 18:6a4db94011d3 222 static void pwmout_config(pwmout_t* obj)
sahilmgandhi 18:6a4db94011d3 223 {
sahilmgandhi 18:6a4db94011d3 224 PWM_T *pwm_base = (PWM_T *) NU_MODBASE(obj->pwm);
sahilmgandhi 18:6a4db94011d3 225 uint32_t chn = NU_MODSUBINDEX(obj->pwm);
sahilmgandhi 18:6a4db94011d3 226 // NOTE: Support period < 1s
sahilmgandhi 18:6a4db94011d3 227 //PWM_ConfigOutputChannel(pwm_base, chn, 1000 * 1000 / obj->period_us, obj->pulsewidth_us * 100 / obj->period_us);
sahilmgandhi 18:6a4db94011d3 228 PWM_ConfigOutputChannel2(pwm_base, chn, 1000 * 1000, obj->pulsewidth_us * 100 / obj->period_us, obj->period_us);
sahilmgandhi 18:6a4db94011d3 229 }
sahilmgandhi 18:6a4db94011d3 230
sahilmgandhi 18:6a4db94011d3 231 #endif