MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_Freescale/TARGET_K20XX/spi_api.c@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2015 ARM Limited
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 */
sahilmgandhi 18:6a4db94011d3 16 #include "mbed_assert.h"
sahilmgandhi 18:6a4db94011d3 17 #include "spi_api.h"
sahilmgandhi 18:6a4db94011d3 18
sahilmgandhi 18:6a4db94011d3 19 #include <math.h>
sahilmgandhi 18:6a4db94011d3 20
sahilmgandhi 18:6a4db94011d3 21 #include "cmsis.h"
sahilmgandhi 18:6a4db94011d3 22 #include "pinmap.h"
sahilmgandhi 18:6a4db94011d3 23 #include "clk_freqs.h"
sahilmgandhi 18:6a4db94011d3 24 #include "PeripheralPins.h"
sahilmgandhi 18:6a4db94011d3 25
sahilmgandhi 18:6a4db94011d3 26 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
sahilmgandhi 18:6a4db94011d3 27 // determine the SPI to use
sahilmgandhi 18:6a4db94011d3 28 SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
sahilmgandhi 18:6a4db94011d3 29 SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
sahilmgandhi 18:6a4db94011d3 30 SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
sahilmgandhi 18:6a4db94011d3 31 SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
sahilmgandhi 18:6a4db94011d3 32 SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
sahilmgandhi 18:6a4db94011d3 33 SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
sahilmgandhi 18:6a4db94011d3 34
sahilmgandhi 18:6a4db94011d3 35 obj->spi = (SPI_Type*)pinmap_merge(spi_data, spi_cntl);
sahilmgandhi 18:6a4db94011d3 36 MBED_ASSERT((int)obj->spi != NC);
sahilmgandhi 18:6a4db94011d3 37
sahilmgandhi 18:6a4db94011d3 38 SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK | SIM_SCGC5_PORTD_MASK;
sahilmgandhi 18:6a4db94011d3 39 SIM->SCGC6 |= SIM_SCGC6_SPI0_MASK;
sahilmgandhi 18:6a4db94011d3 40
sahilmgandhi 18:6a4db94011d3 41 obj->spi->MCR &= ~(SPI_MCR_MDIS_MASK | SPI_MCR_HALT_MASK);
sahilmgandhi 18:6a4db94011d3 42 //obj->spi->MCR |= SPI_MCR_DIS_RXF_MASK | SPI_MCR_DIS_TXF_MASK;
sahilmgandhi 18:6a4db94011d3 43
sahilmgandhi 18:6a4db94011d3 44 // not halt in the debug mode
sahilmgandhi 18:6a4db94011d3 45 obj->spi->SR |= SPI_SR_EOQF_MASK;
sahilmgandhi 18:6a4db94011d3 46
sahilmgandhi 18:6a4db94011d3 47 // pin out the spi pins
sahilmgandhi 18:6a4db94011d3 48 pinmap_pinout(mosi, PinMap_SPI_MOSI);
sahilmgandhi 18:6a4db94011d3 49 pinmap_pinout(miso, PinMap_SPI_MISO);
sahilmgandhi 18:6a4db94011d3 50 pinmap_pinout(sclk, PinMap_SPI_SCLK);
sahilmgandhi 18:6a4db94011d3 51 if (ssel != NC) {
sahilmgandhi 18:6a4db94011d3 52 pinmap_pinout(ssel, PinMap_SPI_SSEL);
sahilmgandhi 18:6a4db94011d3 53 }
sahilmgandhi 18:6a4db94011d3 54 }
sahilmgandhi 18:6a4db94011d3 55
sahilmgandhi 18:6a4db94011d3 56 void spi_free(spi_t *obj) {
sahilmgandhi 18:6a4db94011d3 57 // [TODO]
sahilmgandhi 18:6a4db94011d3 58 }
sahilmgandhi 18:6a4db94011d3 59 void spi_format(spi_t *obj, int bits, int mode, int slave) {
sahilmgandhi 18:6a4db94011d3 60 MBED_ASSERT((bits > 4) || (bits < 16));
sahilmgandhi 18:6a4db94011d3 61 MBED_ASSERT((mode >= 0) && (mode <= 3));
sahilmgandhi 18:6a4db94011d3 62
sahilmgandhi 18:6a4db94011d3 63 uint8_t polarity = (mode & 0x2) ? 1 : 0;
sahilmgandhi 18:6a4db94011d3 64 uint8_t phase = (mode & 0x1) ? 1 : 0;
sahilmgandhi 18:6a4db94011d3 65 uint8_t old_polarity = (obj->spi->CTAR[0] & SPI_CTAR_CPOL_MASK) != 0;
sahilmgandhi 18:6a4db94011d3 66
sahilmgandhi 18:6a4db94011d3 67 // set master/slave
sahilmgandhi 18:6a4db94011d3 68 if (slave) {
sahilmgandhi 18:6a4db94011d3 69 obj->spi->MCR &= ~SPI_MCR_MSTR_MASK;
sahilmgandhi 18:6a4db94011d3 70 } else {
sahilmgandhi 18:6a4db94011d3 71 obj->spi->MCR |= (1UL << SPI_MCR_MSTR_SHIFT);
sahilmgandhi 18:6a4db94011d3 72 }
sahilmgandhi 18:6a4db94011d3 73
sahilmgandhi 18:6a4db94011d3 74 // CTAR0 is used
sahilmgandhi 18:6a4db94011d3 75 obj->spi->CTAR[0] &= ~(SPI_CTAR_CPHA_MASK | SPI_CTAR_CPOL_MASK | SPI_CTAR_FMSZ_MASK);
sahilmgandhi 18:6a4db94011d3 76 obj->spi->CTAR[0] |= (polarity << SPI_CTAR_CPOL_SHIFT) | (phase << SPI_CTAR_CPHA_SHIFT) | ((bits - 1) << SPI_CTAR_FMSZ_SHIFT);
sahilmgandhi 18:6a4db94011d3 77
sahilmgandhi 18:6a4db94011d3 78 //If clk idle state was changed, start a dummy transmission
sahilmgandhi 18:6a4db94011d3 79 //This is a 'feature' in DSPI: https://community.freescale.com/thread/105526
sahilmgandhi 18:6a4db94011d3 80 if ((old_polarity != polarity) && (slave == 0)) {
sahilmgandhi 18:6a4db94011d3 81 //Start transfer (CS should be high, so shouldn't matter)
sahilmgandhi 18:6a4db94011d3 82 spi_master_write(obj, 0xFFFF);
sahilmgandhi 18:6a4db94011d3 83 }
sahilmgandhi 18:6a4db94011d3 84 }
sahilmgandhi 18:6a4db94011d3 85
sahilmgandhi 18:6a4db94011d3 86 static const uint8_t baudrate_prescaler[] = {2,3,5,7};
sahilmgandhi 18:6a4db94011d3 87 static const uint16_t baudrate_scaler[] = {2,4,6,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768};
sahilmgandhi 18:6a4db94011d3 88
sahilmgandhi 18:6a4db94011d3 89 void spi_frequency(spi_t *obj, int hz) {
sahilmgandhi 18:6a4db94011d3 90 uint32_t f_error = 0;
sahilmgandhi 18:6a4db94011d3 91 uint32_t p_error = 0xffffffff;
sahilmgandhi 18:6a4db94011d3 92 uint32_t ref = 0;
sahilmgandhi 18:6a4db94011d3 93 uint32_t br = 0;
sahilmgandhi 18:6a4db94011d3 94 uint32_t ref_spr = 0;
sahilmgandhi 18:6a4db94011d3 95 uint32_t ref_prescaler = 0;
sahilmgandhi 18:6a4db94011d3 96 uint32_t ref_dr = 0;
sahilmgandhi 18:6a4db94011d3 97
sahilmgandhi 18:6a4db94011d3 98 // bus clk
sahilmgandhi 18:6a4db94011d3 99 uint32_t PCLK = bus_frequency();
sahilmgandhi 18:6a4db94011d3 100
sahilmgandhi 18:6a4db94011d3 101 for (uint32_t i = 0; i < 4; i++) {
sahilmgandhi 18:6a4db94011d3 102 for (br = 0; br <= 15; br++) {
sahilmgandhi 18:6a4db94011d3 103 for (uint32_t dr = 0; dr < 2; dr++) {
sahilmgandhi 18:6a4db94011d3 104 ref = (PCLK * (1U + dr) / baudrate_prescaler[i]) / baudrate_scaler[br];
sahilmgandhi 18:6a4db94011d3 105 if (ref > (uint32_t)hz)
sahilmgandhi 18:6a4db94011d3 106 continue;
sahilmgandhi 18:6a4db94011d3 107 f_error = hz - ref;
sahilmgandhi 18:6a4db94011d3 108 if (f_error < p_error) {
sahilmgandhi 18:6a4db94011d3 109 ref_spr = br;
sahilmgandhi 18:6a4db94011d3 110 ref_prescaler = i;
sahilmgandhi 18:6a4db94011d3 111 ref_dr = dr;
sahilmgandhi 18:6a4db94011d3 112 p_error = f_error;
sahilmgandhi 18:6a4db94011d3 113 }
sahilmgandhi 18:6a4db94011d3 114 }
sahilmgandhi 18:6a4db94011d3 115 }
sahilmgandhi 18:6a4db94011d3 116 }
sahilmgandhi 18:6a4db94011d3 117
sahilmgandhi 18:6a4db94011d3 118 // set PBR and BR
sahilmgandhi 18:6a4db94011d3 119 obj->spi->CTAR[0] &= ~(SPI_CTAR_PBR_MASK | SPI_CTAR_BR_MASK | SPI_CTAR_DBR_MASK);
sahilmgandhi 18:6a4db94011d3 120 obj->spi->CTAR[0] |= (ref_prescaler << SPI_CTAR_PBR_SHIFT) | (ref_spr << SPI_CTAR_BR_SHIFT) | (ref_dr << SPI_CTAR_DBR_SHIFT);
sahilmgandhi 18:6a4db94011d3 121 }
sahilmgandhi 18:6a4db94011d3 122
sahilmgandhi 18:6a4db94011d3 123 static inline int spi_writeable(spi_t *obj) {
sahilmgandhi 18:6a4db94011d3 124 return (obj->spi->SR & SPI_SR_TFFF_MASK) ? 1 : 0;
sahilmgandhi 18:6a4db94011d3 125 }
sahilmgandhi 18:6a4db94011d3 126
sahilmgandhi 18:6a4db94011d3 127 static inline int spi_readable(spi_t *obj) {
sahilmgandhi 18:6a4db94011d3 128 return (obj->spi->SR & SPI_SR_RFDF_MASK) ? 1 : 0;
sahilmgandhi 18:6a4db94011d3 129 }
sahilmgandhi 18:6a4db94011d3 130
sahilmgandhi 18:6a4db94011d3 131 int spi_master_write(spi_t *obj, int value) {
sahilmgandhi 18:6a4db94011d3 132 //clear RX buffer flag
sahilmgandhi 18:6a4db94011d3 133 obj->spi->SR |= SPI_SR_RFDF_MASK;
sahilmgandhi 18:6a4db94011d3 134 // wait tx buffer empty
sahilmgandhi 18:6a4db94011d3 135 while(!spi_writeable(obj));
sahilmgandhi 18:6a4db94011d3 136 obj->spi->PUSHR = SPI_PUSHR_TXDATA(value & 0xffff) /*| SPI_PUSHR_EOQ_MASK*/;
sahilmgandhi 18:6a4db94011d3 137
sahilmgandhi 18:6a4db94011d3 138 // wait rx buffer full
sahilmgandhi 18:6a4db94011d3 139 while (!spi_readable(obj));
sahilmgandhi 18:6a4db94011d3 140 return obj->spi->POPR;
sahilmgandhi 18:6a4db94011d3 141 }
sahilmgandhi 18:6a4db94011d3 142
sahilmgandhi 18:6a4db94011d3 143 int spi_slave_receive(spi_t *obj) {
sahilmgandhi 18:6a4db94011d3 144 return spi_readable(obj);
sahilmgandhi 18:6a4db94011d3 145 }
sahilmgandhi 18:6a4db94011d3 146
sahilmgandhi 18:6a4db94011d3 147 int spi_slave_read(spi_t *obj) {
sahilmgandhi 18:6a4db94011d3 148 obj->spi->SR |= SPI_SR_RFDF_MASK;
sahilmgandhi 18:6a4db94011d3 149 return obj->spi->POPR;
sahilmgandhi 18:6a4db94011d3 150 }
sahilmgandhi 18:6a4db94011d3 151
sahilmgandhi 18:6a4db94011d3 152 void spi_slave_write(spi_t *obj, int value) {
sahilmgandhi 18:6a4db94011d3 153 while (!spi_writeable(obj));
sahilmgandhi 18:6a4db94011d3 154 }