MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_Freescale/TARGET_K20XX/sleep.c@34:69342782fb68, 2017-05-26 (annotated)

Committer:
sahilmgandhi
Date:
Fri May 26 17:21:04 2017 +0000
Revision:
34:69342782fb68
Parent:
18:6a4db94011d3 
Added small reverse turns before the break so that we can stop faster.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2006-2015 ARM Limited
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 */
sahilmgandhi 18:6a4db94011d3 16 #include "sleep_api.h"
sahilmgandhi 18:6a4db94011d3 17 #include "cmsis.h"
sahilmgandhi 18:6a4db94011d3 18
sahilmgandhi 18:6a4db94011d3 19 //Normal wait mode
sahilmgandhi 18:6a4db94011d3 20 void hal_sleep(void)
sahilmgandhi 18:6a4db94011d3 21 {
sahilmgandhi 18:6a4db94011d3 22 SMC->PMPROT = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK;
sahilmgandhi 18:6a4db94011d3 23
sahilmgandhi 18:6a4db94011d3 24 //Normal sleep mode for ARM core:
sahilmgandhi 18:6a4db94011d3 25 SCB->SCR = 0;
sahilmgandhi 18:6a4db94011d3 26 __WFI();
sahilmgandhi 18:6a4db94011d3 27 }
sahilmgandhi 18:6a4db94011d3 28
sahilmgandhi 18:6a4db94011d3 29 //Very low-power stop mode
sahilmgandhi 18:6a4db94011d3 30 void hal_deepsleep(void)
sahilmgandhi 18:6a4db94011d3 31 {
sahilmgandhi 18:6a4db94011d3 32 //Check if ADC is enabled and HS mode is set, if yes disable it (lowers power consumption by 60uA)
sahilmgandhi 18:6a4db94011d3 33 uint8_t ADC_HSC = 0;
sahilmgandhi 18:6a4db94011d3 34 if (SIM->SCGC6 & SIM_SCGC6_ADC0_MASK) {
sahilmgandhi 18:6a4db94011d3 35 if (ADC0->CFG2 & ADC_CFG2_ADHSC_MASK) {
sahilmgandhi 18:6a4db94011d3 36 ADC_HSC = 1;
sahilmgandhi 18:6a4db94011d3 37 ADC0->CFG2 &= ~(ADC_CFG2_ADHSC_MASK);
sahilmgandhi 18:6a4db94011d3 38 }
sahilmgandhi 18:6a4db94011d3 39 }
sahilmgandhi 18:6a4db94011d3 40
sahilmgandhi 18:6a4db94011d3 41 //Check if PLL/FLL is enabled:
sahilmgandhi 18:6a4db94011d3 42 uint32_t PLL_FLL_en = (MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0);
sahilmgandhi 18:6a4db94011d3 43
sahilmgandhi 18:6a4db94011d3 44 SMC->PMPROT = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK;
sahilmgandhi 18:6a4db94011d3 45 SMC->PMCTRL = SMC_PMCTRL_STOPM(2);
sahilmgandhi 18:6a4db94011d3 46
sahilmgandhi 18:6a4db94011d3 47 //Deep sleep for ARM core:
sahilmgandhi 18:6a4db94011d3 48 SCB->SCR = 1<<SCB_SCR_SLEEPDEEP_Pos;
sahilmgandhi 18:6a4db94011d3 49
sahilmgandhi 18:6a4db94011d3 50 __WFI();
sahilmgandhi 18:6a4db94011d3 51 //Switch back to PLL as clock source if needed
sahilmgandhi 18:6a4db94011d3 52 //The interrupt that woke up the device will run at reduced speed
sahilmgandhi 18:6a4db94011d3 53 if (PLL_FLL_en) {
sahilmgandhi 18:6a4db94011d3 54
sahilmgandhi 18:6a4db94011d3 55 #if defined (TARGET_K20D50M)
sahilmgandhi 18:6a4db94011d3 56 if (MCG->C6 & (1<<MCG_C6_PLLS_SHIFT) != 0) /* If PLL */
sahilmgandhi 18:6a4db94011d3 57 while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U); /* Wait until locked */
sahilmgandhi 18:6a4db94011d3 58 MCG->C1 &= ~MCG_C1_CLKS_MASK;
sahilmgandhi 18:6a4db94011d3 59 #else
sahilmgandhi 18:6a4db94011d3 60 // MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0
sahilmgandhi 18:6a4db94011d3 61 MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3) | MCG_C1_IRCLKEN_MASK;
sahilmgandhi 18:6a4db94011d3 62 // MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0
sahilmgandhi 18:6a4db94011d3 63 MCG->C6 = MCG_C6_VDIV0(0);
sahilmgandhi 18:6a4db94011d3 64 while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { } // Check that the oscillator is running
sahilmgandhi 18:6a4db94011d3 65 while((MCG->S & 0x0Cu) != 0x08u) { } // Wait until external reference clock is selected as MCG output
sahilmgandhi 18:6a4db94011d3 66 // MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=3
sahilmgandhi 18:6a4db94011d3 67 MCG->C5 = MCG_C5_PRDIV0(5);
sahilmgandhi 18:6a4db94011d3 68 // MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=3
sahilmgandhi 18:6a4db94011d3 69 MCG->C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV0(3);
sahilmgandhi 18:6a4db94011d3 70 while((MCG->S & 0x0Cu) != 0x08u) { } // Wait until external reference clock is selected as MCG output
sahilmgandhi 18:6a4db94011d3 71 while((MCG->S & MCG_S_PLLST_MASK) == 0u) { } // Wait until the source of the PLLS clock has switched to the PLL
sahilmgandhi 18:6a4db94011d3 72 while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } // Wait until locked
sahilmgandhi 18:6a4db94011d3 73 // MCG->C1: CLKS=0,FRDIV=2,IREFS=0,IRCLKEN=1,IREFSTEN=0
sahilmgandhi 18:6a4db94011d3 74 MCG->C1 = MCG_C1_FRDIV(2) | MCG_C1_IRCLKEN_MASK;;
sahilmgandhi 18:6a4db94011d3 75 while((MCG->S & 0x0Cu) != 0x0Cu) { } // Wait until output of the PLL is selected
sahilmgandhi 18:6a4db94011d3 76 while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } // Wait until locked
sahilmgandhi 18:6a4db94011d3 77 #endif
sahilmgandhi 18:6a4db94011d3 78 }
sahilmgandhi 18:6a4db94011d3 79
sahilmgandhi 18:6a4db94011d3 80 if (ADC_HSC) {
sahilmgandhi 18:6a4db94011d3 81 ADC0->CFG2 |= (ADC_CFG2_ADHSC_MASK);
sahilmgandhi 18:6a4db94011d3 82 }
sahilmgandhi 18:6a4db94011d3 83 }