MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_Freescale/TARGET_K20XX/rtc_api.c@34:69342782fb68, 2017-05-26 (annotated)

Committer:
sahilmgandhi
Date:
Fri May 26 17:21:04 2017 +0000
Revision:
34:69342782fb68
Parent:
18:6a4db94011d3 
Added small reverse turns before the break so that we can stop faster.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2006-2015 ARM Limited
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 */
sahilmgandhi 18:6a4db94011d3 16 #include "rtc_api.h"
sahilmgandhi 18:6a4db94011d3 17
sahilmgandhi 18:6a4db94011d3 18 static void init(void) {
sahilmgandhi 18:6a4db94011d3 19 // enable PORTC clock
sahilmgandhi 18:6a4db94011d3 20 SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK;
sahilmgandhi 18:6a4db94011d3 21
sahilmgandhi 18:6a4db94011d3 22 // enable RTC clock
sahilmgandhi 18:6a4db94011d3 23 SIM->SCGC6 |= SIM_SCGC6_RTC_MASK;
sahilmgandhi 18:6a4db94011d3 24
sahilmgandhi 18:6a4db94011d3 25 // OSC32 as source
sahilmgandhi 18:6a4db94011d3 26 SIM->SOPT1 &= ~SIM_SOPT1_OSC32KSEL_MASK;
sahilmgandhi 18:6a4db94011d3 27 SIM->SOPT1 |= SIM_SOPT1_OSC32KSEL(0);
sahilmgandhi 18:6a4db94011d3 28 }
sahilmgandhi 18:6a4db94011d3 29
sahilmgandhi 18:6a4db94011d3 30 void rtc_init(void) {
sahilmgandhi 18:6a4db94011d3 31 init();
sahilmgandhi 18:6a4db94011d3 32
sahilmgandhi 18:6a4db94011d3 33 // Enable the oscillator
sahilmgandhi 18:6a4db94011d3 34 #if defined (TARGET_K20D50M)
sahilmgandhi 18:6a4db94011d3 35 RTC->CR |= RTC_CR_OSCE_MASK;
sahilmgandhi 18:6a4db94011d3 36 #else
sahilmgandhi 18:6a4db94011d3 37 // Teensy3.1 requires 20pF MCU loading capacitors for 32KHz RTC oscillator
sahilmgandhi 18:6a4db94011d3 38 /* RTC->CR: SC2P=0,SC4P=1,SC8P=0,SC16P=1,CLKO=0,OSCE=1,UM=0,SUP=0,SPE=0,SWR=0 */
sahilmgandhi 18:6a4db94011d3 39 RTC->CR |= RTC_CR_OSCE_MASK |RTC_CR_SC16P_MASK | RTC_CR_SC4P_MASK;
sahilmgandhi 18:6a4db94011d3 40 #endif
sahilmgandhi 18:6a4db94011d3 41
sahilmgandhi 18:6a4db94011d3 42 //Configure the TSR. default value: 1
sahilmgandhi 18:6a4db94011d3 43 RTC->TSR = 1;
sahilmgandhi 18:6a4db94011d3 44
sahilmgandhi 18:6a4db94011d3 45 // enable counter
sahilmgandhi 18:6a4db94011d3 46 RTC->SR |= RTC_SR_TCE_MASK;
sahilmgandhi 18:6a4db94011d3 47 }
sahilmgandhi 18:6a4db94011d3 48
sahilmgandhi 18:6a4db94011d3 49 void rtc_free(void) {
sahilmgandhi 18:6a4db94011d3 50 // [TODO]
sahilmgandhi 18:6a4db94011d3 51 }
sahilmgandhi 18:6a4db94011d3 52
sahilmgandhi 18:6a4db94011d3 53 /*
sahilmgandhi 18:6a4db94011d3 54 * Little check routine to see if the RTC has been enabled
sahilmgandhi 18:6a4db94011d3 55 * 0 = Disabled, 1 = Enabled
sahilmgandhi 18:6a4db94011d3 56 */
sahilmgandhi 18:6a4db94011d3 57 int rtc_isenabled(void) {
sahilmgandhi 18:6a4db94011d3 58 // even if the RTC module is enabled,
sahilmgandhi 18:6a4db94011d3 59 // as we use RTC_CLKIN and an external clock,
sahilmgandhi 18:6a4db94011d3 60 // we need to reconfigure the pins. That is why we
sahilmgandhi 18:6a4db94011d3 61 // call init() if the rtc is enabled
sahilmgandhi 18:6a4db94011d3 62
sahilmgandhi 18:6a4db94011d3 63 // if RTC not enabled return 0
sahilmgandhi 18:6a4db94011d3 64 SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK;
sahilmgandhi 18:6a4db94011d3 65 SIM->SCGC6 |= SIM_SCGC6_RTC_MASK;
sahilmgandhi 18:6a4db94011d3 66 if ((RTC->SR & RTC_SR_TCE_MASK) == 0)
sahilmgandhi 18:6a4db94011d3 67 return 0;
sahilmgandhi 18:6a4db94011d3 68
sahilmgandhi 18:6a4db94011d3 69 init();
sahilmgandhi 18:6a4db94011d3 70 return 1;
sahilmgandhi 18:6a4db94011d3 71 }
sahilmgandhi 18:6a4db94011d3 72
sahilmgandhi 18:6a4db94011d3 73 time_t rtc_read(void) {
sahilmgandhi 18:6a4db94011d3 74 return RTC->TSR;
sahilmgandhi 18:6a4db94011d3 75 }
sahilmgandhi 18:6a4db94011d3 76
sahilmgandhi 18:6a4db94011d3 77 void rtc_write(time_t t) {
sahilmgandhi 18:6a4db94011d3 78 // disable counter
sahilmgandhi 18:6a4db94011d3 79 RTC->SR &= ~RTC_SR_TCE_MASK;
sahilmgandhi 18:6a4db94011d3 80
sahilmgandhi 18:6a4db94011d3 81 // we do not write 0 into TSR
sahilmgandhi 18:6a4db94011d3 82 // to avoid invalid time
sahilmgandhi 18:6a4db94011d3 83 if (t == 0)
sahilmgandhi 18:6a4db94011d3 84 t = 1;
sahilmgandhi 18:6a4db94011d3 85
sahilmgandhi 18:6a4db94011d3 86 // write seconds
sahilmgandhi 18:6a4db94011d3 87 RTC->TSR = t;
sahilmgandhi 18:6a4db94011d3 88
sahilmgandhi 18:6a4db94011d3 89 // re-enable counter
sahilmgandhi 18:6a4db94011d3 90 RTC->SR |= RTC_SR_TCE_MASK;
sahilmgandhi 18:6a4db94011d3 91 }