MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_Freescale/TARGET_K20XX/clk_freqs.h@34:69342782fb68, 2017-05-26 (annotated)

Committer:
sahilmgandhi
Date:
Fri May 26 17:21:04 2017 +0000
Revision:
34:69342782fb68
Parent:
18:6a4db94011d3 
Added small reverse turns before the break so that we can stop faster.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2006-2015 ARM Limited
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 */
sahilmgandhi 18:6a4db94011d3 16 #ifndef CLK_FREQS_H
sahilmgandhi 18:6a4db94011d3 17 #define CLK_FREQS_H
sahilmgandhi 18:6a4db94011d3 18
sahilmgandhi 18:6a4db94011d3 19 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 20 extern "C" {
sahilmgandhi 18:6a4db94011d3 21 #endif
sahilmgandhi 18:6a4db94011d3 22
sahilmgandhi 18:6a4db94011d3 23 /*!
sahilmgandhi 18:6a4db94011d3 24 * \brief Get the peripheral bus clock frequency
sahilmgandhi 18:6a4db94011d3 25 * \return Bus frequency
sahilmgandhi 18:6a4db94011d3 26 */
sahilmgandhi 18:6a4db94011d3 27 static inline uint32_t bus_frequency(void) {
sahilmgandhi 18:6a4db94011d3 28 return SystemCoreClock / (((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV2_MASK) >> SIM_CLKDIV1_OUTDIV2_SHIFT) + 1);
sahilmgandhi 18:6a4db94011d3 29 }
sahilmgandhi 18:6a4db94011d3 30
sahilmgandhi 18:6a4db94011d3 31 /*!
sahilmgandhi 18:6a4db94011d3 32 * \brief Get external oscillator (crystal) frequency
sahilmgandhi 18:6a4db94011d3 33 * \return External osc frequency
sahilmgandhi 18:6a4db94011d3 34 */
sahilmgandhi 18:6a4db94011d3 35 static uint32_t extosc_frequency(void) {
sahilmgandhi 18:6a4db94011d3 36 uint32_t MCGClock = SystemCoreClock * (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT));
sahilmgandhi 18:6a4db94011d3 37
sahilmgandhi 18:6a4db94011d3 38 if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(2)) //MCG clock = external reference clock
sahilmgandhi 18:6a4db94011d3 39 return MCGClock;
sahilmgandhi 18:6a4db94011d3 40
sahilmgandhi 18:6a4db94011d3 41 if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0)) { //PLL/FLL is selected
sahilmgandhi 18:6a4db94011d3 42 uint32_t divider, multiplier;
sahilmgandhi 18:6a4db94011d3 43 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { //FLL is selected
sahilmgandhi 18:6a4db94011d3 44 if ((MCG->S & MCG_S_IREFST_MASK) == 0x0u) { //FLL uses external reference
sahilmgandhi 18:6a4db94011d3 45 divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
sahilmgandhi 18:6a4db94011d3 46 if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u)
sahilmgandhi 18:6a4db94011d3 47 divider <<= 5u;
sahilmgandhi 18:6a4db94011d3 48 /* Select correct multiplier to calculate the MCG output clock */
sahilmgandhi 18:6a4db94011d3 49 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
sahilmgandhi 18:6a4db94011d3 50 case 0x0u:
sahilmgandhi 18:6a4db94011d3 51 multiplier = 640u;
sahilmgandhi 18:6a4db94011d3 52 break;
sahilmgandhi 18:6a4db94011d3 53 case 0x20u:
sahilmgandhi 18:6a4db94011d3 54 multiplier = 1280u;
sahilmgandhi 18:6a4db94011d3 55 break;
sahilmgandhi 18:6a4db94011d3 56 case 0x40u:
sahilmgandhi 18:6a4db94011d3 57 multiplier = 1920u;
sahilmgandhi 18:6a4db94011d3 58 break;
sahilmgandhi 18:6a4db94011d3 59 case 0x60u:
sahilmgandhi 18:6a4db94011d3 60 multiplier = 2560u;
sahilmgandhi 18:6a4db94011d3 61 break;
sahilmgandhi 18:6a4db94011d3 62 case 0x80u:
sahilmgandhi 18:6a4db94011d3 63 multiplier = 732u;
sahilmgandhi 18:6a4db94011d3 64 break;
sahilmgandhi 18:6a4db94011d3 65 case 0xA0u:
sahilmgandhi 18:6a4db94011d3 66 multiplier = 1464u;
sahilmgandhi 18:6a4db94011d3 67 break;
sahilmgandhi 18:6a4db94011d3 68 case 0xC0u:
sahilmgandhi 18:6a4db94011d3 69 multiplier = 2197u;
sahilmgandhi 18:6a4db94011d3 70 break;
sahilmgandhi 18:6a4db94011d3 71 case 0xE0u:
sahilmgandhi 18:6a4db94011d3 72 default:
sahilmgandhi 18:6a4db94011d3 73 multiplier = 2929u;
sahilmgandhi 18:6a4db94011d3 74 break;
sahilmgandhi 18:6a4db94011d3 75 }
sahilmgandhi 18:6a4db94011d3 76
sahilmgandhi 18:6a4db94011d3 77 return MCGClock * divider / multiplier;
sahilmgandhi 18:6a4db94011d3 78 }
sahilmgandhi 18:6a4db94011d3 79 } else { //PLL is selected
sahilmgandhi 18:6a4db94011d3 80 divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
sahilmgandhi 18:6a4db94011d3 81 multiplier = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
sahilmgandhi 18:6a4db94011d3 82 return MCGClock * divider / multiplier;
sahilmgandhi 18:6a4db94011d3 83 }
sahilmgandhi 18:6a4db94011d3 84 }
sahilmgandhi 18:6a4db94011d3 85
sahilmgandhi 18:6a4db94011d3 86 //In all other cases either there is no crystal or we cannot determine it
sahilmgandhi 18:6a4db94011d3 87 //For example when the FLL is running on the internal reference, and there is also an
sahilmgandhi 18:6a4db94011d3 88 //external crystal. However these are unlikely situations
sahilmgandhi 18:6a4db94011d3 89 return 0;
sahilmgandhi 18:6a4db94011d3 90 }
sahilmgandhi 18:6a4db94011d3 91
sahilmgandhi 18:6a4db94011d3 92 //Get MCG PLL/2 or FLL frequency, depending on which one is active, sets PLLFLLSEL bit
sahilmgandhi 18:6a4db94011d3 93 static uint32_t mcgpllfll_frequency(void) {
sahilmgandhi 18:6a4db94011d3 94 if ((MCG->C1 & MCG_C1_CLKS_MASK) != MCG_C1_CLKS(0)) //PLL/FLL is not selected
sahilmgandhi 18:6a4db94011d3 95 return 0;
sahilmgandhi 18:6a4db94011d3 96
sahilmgandhi 18:6a4db94011d3 97 uint32_t MCGClock = SystemCoreClock * (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT));
sahilmgandhi 18:6a4db94011d3 98 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { //FLL is selected
sahilmgandhi 18:6a4db94011d3 99 SIM->SOPT2 &= ~SIM_SOPT2_PLLFLLSEL_MASK; //MCG peripheral clock is FLL output
sahilmgandhi 18:6a4db94011d3 100 return MCGClock;
sahilmgandhi 18:6a4db94011d3 101 } else { //PLL is selected
sahilmgandhi 18:6a4db94011d3 102 SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; //MCG peripheral clock is PLL output
sahilmgandhi 18:6a4db94011d3 103 return MCGClock;
sahilmgandhi 18:6a4db94011d3 104 }
sahilmgandhi 18:6a4db94011d3 105
sahilmgandhi 18:6a4db94011d3 106 //It is possible the SystemCoreClock isn't running on the PLL, and the PLL is still active
sahilmgandhi 18:6a4db94011d3 107 //for the peripherals, this is however an unlikely setup
sahilmgandhi 18:6a4db94011d3 108 }
sahilmgandhi 18:6a4db94011d3 109
sahilmgandhi 18:6a4db94011d3 110
sahilmgandhi 18:6a4db94011d3 111 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 112 }
sahilmgandhi 18:6a4db94011d3 113 #endif
sahilmgandhi 18:6a4db94011d3 114
sahilmgandhi 18:6a4db94011d3 115 #endif