MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/device/cmsis_nvic.c@34:69342782fb68, 2017-05-26 (annotated)

Committer:
sahilmgandhi
Date:
Fri May 26 17:21:04 2017 +0000
Revision:
34:69342782fb68
Parent:
18:6a4db94011d3 
Added small reverse turns before the break so that we can stop faster.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * CMSIS-style functionality to support dynamic vectors
sahilmgandhi 18:6a4db94011d3 3 *******************************************************************************
sahilmgandhi 18:6a4db94011d3 4 * Copyright (c) 2012 ARM Limited. All rights reserved.
sahilmgandhi 18:6a4db94011d3 5 * All rights reserved.
sahilmgandhi 18:6a4db94011d3 6 *
sahilmgandhi 18:6a4db94011d3 7 * Redistribution and use in source and binary forms, with or without
sahilmgandhi 18:6a4db94011d3 8 * modification, are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 11 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 12 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 13 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 14 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 15 * 3. Neither the name of ARM Limited nor the names of its contributors
sahilmgandhi 18:6a4db94011d3 16 * may be used to endorse or promote products derived from this software
sahilmgandhi 18:6a4db94011d3 17 * without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 18 *
sahilmgandhi 18:6a4db94011d3 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi 18:6a4db94011d3 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi 18:6a4db94011d3 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi 18:6a4db94011d3 26 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi 18:6a4db94011d3 27 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi 18:6a4db94011d3 28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 29 *******************************************************************************
sahilmgandhi 18:6a4db94011d3 30 */
sahilmgandhi 18:6a4db94011d3 31 #include "cmsis_nvic.h"
sahilmgandhi 18:6a4db94011d3 32
sahilmgandhi 18:6a4db94011d3 33 #define NVIC_RAM_VECTOR_ADDRESS (0x1FFF8000) // Vectors positioned at start of RAM
sahilmgandhi 18:6a4db94011d3 34 #define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
sahilmgandhi 18:6a4db94011d3 35
sahilmgandhi 18:6a4db94011d3 36 void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
sahilmgandhi 18:6a4db94011d3 37 uint32_t *vectors = (uint32_t*)SCB->VTOR;
sahilmgandhi 18:6a4db94011d3 38 uint32_t i;
sahilmgandhi 18:6a4db94011d3 39
sahilmgandhi 18:6a4db94011d3 40 // Copy and switch to dynamic vectors if the first time called
sahilmgandhi 18:6a4db94011d3 41 if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
sahilmgandhi 18:6a4db94011d3 42 uint32_t *old_vectors = vectors;
sahilmgandhi 18:6a4db94011d3 43 vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
sahilmgandhi 18:6a4db94011d3 44 for (i=0; i<NVIC_NUM_VECTORS; i++) {
sahilmgandhi 18:6a4db94011d3 45 vectors[i] = old_vectors[i];
sahilmgandhi 18:6a4db94011d3 46 }
sahilmgandhi 18:6a4db94011d3 47 SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
sahilmgandhi 18:6a4db94011d3 48 }
sahilmgandhi 18:6a4db94011d3 49 vectors[IRQn + 16] = vector;
sahilmgandhi 18:6a4db94011d3 50 }
sahilmgandhi 18:6a4db94011d3 51
sahilmgandhi 18:6a4db94011d3 52 uint32_t NVIC_GetVector(IRQn_Type IRQn) {
sahilmgandhi 18:6a4db94011d3 53 uint32_t *vectors = (uint32_t*)SCB->VTOR;
sahilmgandhi 18:6a4db94011d3 54 return vectors[IRQn + 16];
sahilmgandhi 18:6a4db94011d3 55 }