MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/device/MK20DX256.h@34:69342782fb68, 2017-05-26 (annotated)

Committer:
sahilmgandhi
Date:
Fri May 26 17:21:04 2017 +0000
Revision:
34:69342782fb68
Parent:
18:6a4db94011d3 
Added small reverse turns before the break so that we can stop faster.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /*
sahilmgandhi 18:6a4db94011d3 2 ** ###################################################################
sahilmgandhi 18:6a4db94011d3 3 ** Processors: MK20DX64VLH7
sahilmgandhi 18:6a4db94011d3 4 ** MK20DX128VLH7
sahilmgandhi 18:6a4db94011d3 5 ** MK20DX256VLH7
sahilmgandhi 18:6a4db94011d3 6 ** MK20DX64VLK7
sahilmgandhi 18:6a4db94011d3 7 ** MK20DX128VLK7
sahilmgandhi 18:6a4db94011d3 8 ** MK20DX256VLK7
sahilmgandhi 18:6a4db94011d3 9 ** MK20DX128VLL7
sahilmgandhi 18:6a4db94011d3 10 ** MK20DX256VLL7
sahilmgandhi 18:6a4db94011d3 11 ** MK20DX64VMB7
sahilmgandhi 18:6a4db94011d3 12 ** MK20DX128VMB7
sahilmgandhi 18:6a4db94011d3 13 ** MK20DX256VMB7
sahilmgandhi 18:6a4db94011d3 14 ** MK20DX128VML7
sahilmgandhi 18:6a4db94011d3 15 ** MK20DX256VML7
sahilmgandhi 18:6a4db94011d3 16 **
sahilmgandhi 18:6a4db94011d3 17 ** Compilers: ARM Compiler
sahilmgandhi 18:6a4db94011d3 18 ** Freescale C/C++ for Embedded ARM
sahilmgandhi 18:6a4db94011d3 19 ** GNU C Compiler
sahilmgandhi 18:6a4db94011d3 20 ** IAR ANSI C/C++ Compiler for ARM
sahilmgandhi 18:6a4db94011d3 21 **
sahilmgandhi 18:6a4db94011d3 22 ** Reference manual: Kxx (P1 silicon) Sub-Family Reference Manual Rev. 0, draft A Oct 2011
sahilmgandhi 18:6a4db94011d3 23 ** Version: rev. 1.0, 2012-01-15
sahilmgandhi 18:6a4db94011d3 24 **
sahilmgandhi 18:6a4db94011d3 25 ** Abstract:
sahilmgandhi 18:6a4db94011d3 26 ** Provides a system configuration function and a global variable that
sahilmgandhi 18:6a4db94011d3 27 ** contains the system frequency. It configures the device and initializes
sahilmgandhi 18:6a4db94011d3 28 ** the oscillator (PLL) that is part of the microcontroller device.
sahilmgandhi 18:6a4db94011d3 29 **
sahilmgandhi 18:6a4db94011d3 30 ** Copyright: 2015 Freescale Semiconductor, Inc. All Rights Reserved.
sahilmgandhi 18:6a4db94011d3 31 **
sahilmgandhi 18:6a4db94011d3 32 ** http: www.freescale.com
sahilmgandhi 18:6a4db94011d3 33 ** mail: support@freescale.com
sahilmgandhi 18:6a4db94011d3 34 **
sahilmgandhi 18:6a4db94011d3 35 ** Revisions:
sahilmgandhi 18:6a4db94011d3 36 ** - rev. 1.0 (2012-01-15)
sahilmgandhi 18:6a4db94011d3 37 ** Initial public version.
sahilmgandhi 18:6a4db94011d3 38 **
sahilmgandhi 18:6a4db94011d3 39 ** ###################################################################
sahilmgandhi 18:6a4db94011d3 40 */
sahilmgandhi 18:6a4db94011d3 41
sahilmgandhi 18:6a4db94011d3 42 /**
sahilmgandhi 18:6a4db94011d3 43 * @file MK20DX256.h
sahilmgandhi 18:6a4db94011d3 44 * @version 2.0
sahilmgandhi 18:6a4db94011d3 45 * @date 2012-03-19
sahilmgandhi 18:6a4db94011d3 46 * @brief CMSIS Peripheral Access Layer for MK20DX256
sahilmgandhi 18:6a4db94011d3 47 *
sahilmgandhi 18:6a4db94011d3 48 * CMSIS Peripheral Access Layer for MK20DX256
sahilmgandhi 18:6a4db94011d3 49 */
sahilmgandhi 18:6a4db94011d3 50
sahilmgandhi 18:6a4db94011d3 51 #if !defined(MK20DX256_H_)
sahilmgandhi 18:6a4db94011d3 52 #define MK20DX256_H_ /**< Symbol preventing repeated inclusion */
sahilmgandhi 18:6a4db94011d3 53 #define MCU_MK20DX256
sahilmgandhi 18:6a4db94011d3 54 /** Memory map major version (memory maps with equal major version number are
sahilmgandhi 18:6a4db94011d3 55 * compatible) */
sahilmgandhi 18:6a4db94011d3 56 #define MCU_MEM_MAP_VERSION 0x0200u
sahilmgandhi 18:6a4db94011d3 57 /** Memory map minor version */
sahilmgandhi 18:6a4db94011d3 58 #define MCU_MEM_MAP_VERSION_MINOR 0x0000u
sahilmgandhi 18:6a4db94011d3 59
sahilmgandhi 18:6a4db94011d3 60 /**
sahilmgandhi 18:6a4db94011d3 61 * @brief Macro to access a single bit of a peripheral register (bit band region
sahilmgandhi 18:6a4db94011d3 62 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access.
sahilmgandhi 18:6a4db94011d3 63 * @param Reg Register to access.
sahilmgandhi 18:6a4db94011d3 64 * @param Bit Bit number to access.
sahilmgandhi 18:6a4db94011d3 65 * @return Value of the targeted bit in the bit band region.
sahilmgandhi 18:6a4db94011d3 66 */
sahilmgandhi 18:6a4db94011d3 67 #define BITBAND_REG(Reg,Bit) (*((uint32_t volatile*)(0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))))
sahilmgandhi 18:6a4db94011d3 68
sahilmgandhi 18:6a4db94011d3 69 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 70 -- Interrupt vector numbers
sahilmgandhi 18:6a4db94011d3 71 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 72
sahilmgandhi 18:6a4db94011d3 73 /**
sahilmgandhi 18:6a4db94011d3 74 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
sahilmgandhi 18:6a4db94011d3 75 * @{
sahilmgandhi 18:6a4db94011d3 76 */
sahilmgandhi 18:6a4db94011d3 77
sahilmgandhi 18:6a4db94011d3 78 /** Interrupt Number Definitions */
sahilmgandhi 18:6a4db94011d3 79 typedef enum IRQn {
sahilmgandhi 18:6a4db94011d3 80 /* Core interrupts */
sahilmgandhi 18:6a4db94011d3 81 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
sahilmgandhi 18:6a4db94011d3 82 MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
sahilmgandhi 18:6a4db94011d3 83 BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
sahilmgandhi 18:6a4db94011d3 84 UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
sahilmgandhi 18:6a4db94011d3 85 SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
sahilmgandhi 18:6a4db94011d3 86 DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
sahilmgandhi 18:6a4db94011d3 87 PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
sahilmgandhi 18:6a4db94011d3 88 SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
sahilmgandhi 18:6a4db94011d3 89
sahilmgandhi 18:6a4db94011d3 90 /* Device specific interrupts */
sahilmgandhi 18:6a4db94011d3 91
sahilmgandhi 18:6a4db94011d3 92 DMA0_IRQn = 0, /**< DMA channel 0 transfer complete interrupt */
sahilmgandhi 18:6a4db94011d3 93 DMA1_IRQn = 1, /**< DMA channel 1 transfer complete interrupt */
sahilmgandhi 18:6a4db94011d3 94 DMA2_IRQn = 2, /**< DMA channel 2 transfer complete interrupt */
sahilmgandhi 18:6a4db94011d3 95 DMA3_IRQn = 3, /**< DMA channel 3 transfer complete interrupt */
sahilmgandhi 18:6a4db94011d3 96 DMA4_IRQn = 4,
sahilmgandhi 18:6a4db94011d3 97 DMA5_IRQn = 5,
sahilmgandhi 18:6a4db94011d3 98 DMA6_IRQn = 6,
sahilmgandhi 18:6a4db94011d3 99 DMA7_IRQn = 7,
sahilmgandhi 18:6a4db94011d3 100 DMA8_IRQn = 8,
sahilmgandhi 18:6a4db94011d3 101 DMA9_IRQn = 9,
sahilmgandhi 18:6a4db94011d3 102 DMA10_IRQn = 10,
sahilmgandhi 18:6a4db94011d3 103 DMA11_IRQn = 11,
sahilmgandhi 18:6a4db94011d3 104 DMA12_IRQn = 12,
sahilmgandhi 18:6a4db94011d3 105 DMA13_IRQn = 13,
sahilmgandhi 18:6a4db94011d3 106 DMA14_IRQn = 14,
sahilmgandhi 18:6a4db94011d3 107 DMA15_IRQn = 15,
sahilmgandhi 18:6a4db94011d3 108 DMA_Error_IRQn = 16, /**< DMA error interrupt */
sahilmgandhi 18:6a4db94011d3 109 Reserved33_IRQn = 17,
sahilmgandhi 18:6a4db94011d3 110 FTFL_IRQn = 18, /**< FTFL interrupt */
sahilmgandhi 18:6a4db94011d3 111 Read_Collision_IRQn = 19, /**< Read collision interrupt */
sahilmgandhi 18:6a4db94011d3 112 LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */
sahilmgandhi 18:6a4db94011d3 113 LLW_IRQn = 21, /**< Low Leakage Wakeup */
sahilmgandhi 18:6a4db94011d3 114 Watchdog_IRQn = 22, /**< WDOG interrupt */
sahilmgandhi 18:6a4db94011d3 115 Reserved39_IRQn = 23,
sahilmgandhi 18:6a4db94011d3 116 I2C0_IRQn = 24, /**< I2C0 interrupt */
sahilmgandhi 18:6a4db94011d3 117 I2C1_IRQn = 25,
sahilmgandhi 18:6a4db94011d3 118 SPI0_IRQn = 26, /**< SPI0 interrupt */
sahilmgandhi 18:6a4db94011d3 119 SPI1_IRQn = 27,
sahilmgandhi 18:6a4db94011d3 120 Reserved44_IRQn = 28,
sahilmgandhi 18:6a4db94011d3 121 CAN0_ORed_Message_buffer_IRQn = 29, /**< CAN0 OR'd message buffers interrupt */
sahilmgandhi 18:6a4db94011d3 122 CAN0_Bus_Off_IRQn = 30, /**< CAN0 bus off interrupt */
sahilmgandhi 18:6a4db94011d3 123 CAN0_Error_IRQn = 31, /**< CAN0 error interrupt */
sahilmgandhi 18:6a4db94011d3 124 CAN0_Tx_Warning_IRQn = 32, /**< CAN0 Tx warning interrupt */
sahilmgandhi 18:6a4db94011d3 125 CAN0_Rx_Warning_IRQn = 33, /**< CAN0 Rx warning interrupt */
sahilmgandhi 18:6a4db94011d3 126 CAN0_Wake_Up_IRQn = 34, /**< CAN0 wake up interrupt */
sahilmgandhi 18:6a4db94011d3 127 I2S0_Tx_IRQn = 35, /**< I2S0 transmit interrupt */
sahilmgandhi 18:6a4db94011d3 128 I2S0_Rx_IRQn = 36, /**< I2S0 receive interrupt */
sahilmgandhi 18:6a4db94011d3 129 Reserved53_IRQn = 37,
sahilmgandhi 18:6a4db94011d3 130 Reserved54_IRQn = 38,
sahilmgandhi 18:6a4db94011d3 131 Reserved55_IRQn = 39,
sahilmgandhi 18:6a4db94011d3 132 Reserved56_IRQn = 40,
sahilmgandhi 18:6a4db94011d3 133 Reserved57_IRQn = 41,
sahilmgandhi 18:6a4db94011d3 134 Reserved58_IRQn = 42,
sahilmgandhi 18:6a4db94011d3 135 Reserved59_IRQn = 43,
sahilmgandhi 18:6a4db94011d3 136 UART0_LON_IRQn = 44, /**< UART0 LON interrupt */
sahilmgandhi 18:6a4db94011d3 137 UART0_RX_TX_IRQn = 45, /**< UART0 receive/transmit interrupt */
sahilmgandhi 18:6a4db94011d3 138 UART0_ERR_IRQn = 46, /**< UART0 error interrupt */
sahilmgandhi 18:6a4db94011d3 139 UART1_RX_TX_IRQn = 47, /**< UART1 receive/transmit interrupt */
sahilmgandhi 18:6a4db94011d3 140 UART1_ERR_IRQn = 48, /**< UART1 error interrupt */
sahilmgandhi 18:6a4db94011d3 141 UART2_RX_TX_IRQn = 49, /**< UART2 receive/transmit interrupt */
sahilmgandhi 18:6a4db94011d3 142 UART2_ERR_IRQn = 50, /**< UART2 error interrupt */
sahilmgandhi 18:6a4db94011d3 143 Reserved67_IRQn = 51,
sahilmgandhi 18:6a4db94011d3 144 Reserved68_IRQn = 52,
sahilmgandhi 18:6a4db94011d3 145 Reserved69_IRQn = 53,
sahilmgandhi 18:6a4db94011d3 146 Reserved70_IRQn = 54,
sahilmgandhi 18:6a4db94011d3 147 Reserved71_IRQn = 55,
sahilmgandhi 18:6a4db94011d3 148 Reserved72_IRQn = 56,
sahilmgandhi 18:6a4db94011d3 149 ADC0_IRQn = 57, /**< ADC0 interrupt */
sahilmgandhi 18:6a4db94011d3 150 ADC1_IRQn = 58,
sahilmgandhi 18:6a4db94011d3 151 CMP0_IRQn = 59, /**< CMP0 interrupt */
sahilmgandhi 18:6a4db94011d3 152 CMP1_IRQn = 60, /**< CMP1 interrupt */
sahilmgandhi 18:6a4db94011d3 153 CMP2_IRQn = 61,
sahilmgandhi 18:6a4db94011d3 154 FTM0_IRQn = 62, /**< FTM0 fault, overflow and channels interrupt */
sahilmgandhi 18:6a4db94011d3 155 FTM1_IRQn = 63, /**< FTM1 fault, overflow and channels interrupt */
sahilmgandhi 18:6a4db94011d3 156 FTM2_IRQn = 64,
sahilmgandhi 18:6a4db94011d3 157 CMT_IRQn = 65, /**< CMT interrupt */
sahilmgandhi 18:6a4db94011d3 158 RTC_IRQn = 66, /**< RTC interrupt */
sahilmgandhi 18:6a4db94011d3 159 RTC_Seconds_IRQn = 67, /**< RTC seconds interrupt */
sahilmgandhi 18:6a4db94011d3 160 PIT0_IRQn = 68, /**< PIT timer channel 0 interrupt */
sahilmgandhi 18:6a4db94011d3 161 PIT1_IRQn = 69, /**< PIT timer channel 1 interrupt */
sahilmgandhi 18:6a4db94011d3 162 PIT2_IRQn = 70, /**< PIT timer channel 2 interrupt */
sahilmgandhi 18:6a4db94011d3 163 PIT3_IRQn = 71, /**< PIT timer channel 3 interrupt */
sahilmgandhi 18:6a4db94011d3 164 PDB0_IRQn = 72, /**< PDB0 interrupt */
sahilmgandhi 18:6a4db94011d3 165 USB0_IRQn = 73, /**< USB0 interrupt */
sahilmgandhi 18:6a4db94011d3 166 USBDCD_IRQn = 74, /**< USBDCD interrupt */
sahilmgandhi 18:6a4db94011d3 167 Reserved91_IRQn = 75,
sahilmgandhi 18:6a4db94011d3 168 Reserved92_IRQn = 76,
sahilmgandhi 18:6a4db94011d3 169 Reserved93_IRQn = 77,
sahilmgandhi 18:6a4db94011d3 170 Reserved94_IRQn = 78,
sahilmgandhi 18:6a4db94011d3 171 Reserved95_IRQn = 79,
sahilmgandhi 18:6a4db94011d3 172 Reserved96_IRQn = 80,
sahilmgandhi 18:6a4db94011d3 173 DAC0_IRQn = 81,
sahilmgandhi 18:6a4db94011d3 174 Reserved98_IRQn = 82,
sahilmgandhi 18:6a4db94011d3 175 TSI0_IRQn = 83, /**< TSI0 interrupt */
sahilmgandhi 18:6a4db94011d3 176 MCG_IRQn = 84, /**< MCG interrupt */
sahilmgandhi 18:6a4db94011d3 177 LPTimer_IRQn = 85, /**< LPTimer interrupt */
sahilmgandhi 18:6a4db94011d3 178 Reserved102_IRQn = 86,
sahilmgandhi 18:6a4db94011d3 179 PORTA_IRQn = 87, /**< Port A interrupt */
sahilmgandhi 18:6a4db94011d3 180 PORTB_IRQn = 88, /**< Port B interrupt */
sahilmgandhi 18:6a4db94011d3 181 PORTC_IRQn = 89, /**< Port C interrupt */
sahilmgandhi 18:6a4db94011d3 182 PORTD_IRQn = 90, /**< Port D interrupt */
sahilmgandhi 18:6a4db94011d3 183 PORTE_IRQn = 91, /**< Port E interrupt */
sahilmgandhi 18:6a4db94011d3 184 Reserved108_IRQn = 92,
sahilmgandhi 18:6a4db94011d3 185 Reserved109_IRQn = 93,
sahilmgandhi 18:6a4db94011d3 186 SWI_IRQn = 94 /**< Software interrupt */
sahilmgandhi 18:6a4db94011d3 187
sahilmgandhi 18:6a4db94011d3 188 } IRQn_Type;
sahilmgandhi 18:6a4db94011d3 189
sahilmgandhi 18:6a4db94011d3 190 /**
sahilmgandhi 18:6a4db94011d3 191 * @}
sahilmgandhi 18:6a4db94011d3 192 */ /* end of group Interrupt_vector_numbers */
sahilmgandhi 18:6a4db94011d3 193
sahilmgandhi 18:6a4db94011d3 194
sahilmgandhi 18:6a4db94011d3 195 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 196 -- Cortex M4 Core Configuration
sahilmgandhi 18:6a4db94011d3 197 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 198
sahilmgandhi 18:6a4db94011d3 199 /**
sahilmgandhi 18:6a4db94011d3 200 * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
sahilmgandhi 18:6a4db94011d3 201 * @{
sahilmgandhi 18:6a4db94011d3 202 */
sahilmgandhi 18:6a4db94011d3 203
sahilmgandhi 18:6a4db94011d3 204 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
sahilmgandhi 18:6a4db94011d3 205 #define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
sahilmgandhi 18:6a4db94011d3 206 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
sahilmgandhi 18:6a4db94011d3 207
sahilmgandhi 18:6a4db94011d3 208 #include "core_cm4.h" /* Core Peripheral Access Layer */
sahilmgandhi 18:6a4db94011d3 209 #include "system_MK20DX256.h" /* Device specific configuration file */
sahilmgandhi 18:6a4db94011d3 210
sahilmgandhi 18:6a4db94011d3 211 /**
sahilmgandhi 18:6a4db94011d3 212 * @}
sahilmgandhi 18:6a4db94011d3 213 */ /* end of group Cortex_Core_Configuration */
sahilmgandhi 18:6a4db94011d3 214
sahilmgandhi 18:6a4db94011d3 215
sahilmgandhi 18:6a4db94011d3 216 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 217 -- Device Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 218 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 219
sahilmgandhi 18:6a4db94011d3 220 /**
sahilmgandhi 18:6a4db94011d3 221 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 222 * @{
sahilmgandhi 18:6a4db94011d3 223 */
sahilmgandhi 18:6a4db94011d3 224
sahilmgandhi 18:6a4db94011d3 225
sahilmgandhi 18:6a4db94011d3 226 /*
sahilmgandhi 18:6a4db94011d3 227 ** Start of section using anonymous unions
sahilmgandhi 18:6a4db94011d3 228 */
sahilmgandhi 18:6a4db94011d3 229
sahilmgandhi 18:6a4db94011d3 230 #if defined(__ARMCC_VERSION)
sahilmgandhi 18:6a4db94011d3 231 #pragma push
sahilmgandhi 18:6a4db94011d3 232 #pragma anon_unions
sahilmgandhi 18:6a4db94011d3 233 #elif defined(__CWCC__)
sahilmgandhi 18:6a4db94011d3 234 #pragma push
sahilmgandhi 18:6a4db94011d3 235 #pragma cpp_extensions on
sahilmgandhi 18:6a4db94011d3 236 #elif defined(__GNUC__)
sahilmgandhi 18:6a4db94011d3 237 /* anonymous unions are enabled by default */
sahilmgandhi 18:6a4db94011d3 238 #elif defined(__IAR_SYSTEMS_ICC__)
sahilmgandhi 18:6a4db94011d3 239 #pragma language=extended
sahilmgandhi 18:6a4db94011d3 240 #else
sahilmgandhi 18:6a4db94011d3 241 #error Not supported compiler type
sahilmgandhi 18:6a4db94011d3 242 #endif
sahilmgandhi 18:6a4db94011d3 243
sahilmgandhi 18:6a4db94011d3 244 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 245 -- ADC Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 246 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 247
sahilmgandhi 18:6a4db94011d3 248 /**
sahilmgandhi 18:6a4db94011d3 249 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 250 * @{
sahilmgandhi 18:6a4db94011d3 251 */
sahilmgandhi 18:6a4db94011d3 252
sahilmgandhi 18:6a4db94011d3 253 /** ADC - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 254 typedef struct {
sahilmgandhi 18:6a4db94011d3 255 __IO uint32_t SC1[2]; /**< ADC status and control registers 1, array offset: 0x0, array step: 0x4 */
sahilmgandhi 18:6a4db94011d3 256 __IO uint32_t CFG1; /**< ADC configuration register 1, offset: 0x8 */
sahilmgandhi 18:6a4db94011d3 257 __IO uint32_t CFG2; /**< Configuration register 2, offset: 0xC */
sahilmgandhi 18:6a4db94011d3 258 __I uint32_t R[2]; /**< ADC data result register, array offset: 0x10, array step: 0x4 */
sahilmgandhi 18:6a4db94011d3 259 __IO uint32_t CV1; /**< Compare value registers, offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 260 __IO uint32_t CV2; /**< Compare value registers, offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 261 __IO uint32_t SC2; /**< Status and control register 2, offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 262 __IO uint32_t SC3; /**< Status and control register 3, offset: 0x24 */
sahilmgandhi 18:6a4db94011d3 263 __IO uint32_t OFS; /**< ADC offset correction register, offset: 0x28 */
sahilmgandhi 18:6a4db94011d3 264 __IO uint32_t PG; /**< ADC plus-side gain register, offset: 0x2C */
sahilmgandhi 18:6a4db94011d3 265 __IO uint32_t MG; /**< ADC minus-side gain register, offset: 0x30 */
sahilmgandhi 18:6a4db94011d3 266 __IO uint32_t CLPD; /**< ADC plus-side general calibration value register, offset: 0x34 */
sahilmgandhi 18:6a4db94011d3 267 __IO uint32_t CLPS; /**< ADC plus-side general calibration value register, offset: 0x38 */
sahilmgandhi 18:6a4db94011d3 268 __IO uint32_t CLP4; /**< ADC plus-side general calibration value register, offset: 0x3C */
sahilmgandhi 18:6a4db94011d3 269 __IO uint32_t CLP3; /**< ADC plus-side general calibration value register, offset: 0x40 */
sahilmgandhi 18:6a4db94011d3 270 __IO uint32_t CLP2; /**< ADC plus-side general calibration value register, offset: 0x44 */
sahilmgandhi 18:6a4db94011d3 271 __IO uint32_t CLP1; /**< ADC plus-side general calibration value register, offset: 0x48 */
sahilmgandhi 18:6a4db94011d3 272 __IO uint32_t CLP0; /**< ADC plus-side general calibration value register, offset: 0x4C */
sahilmgandhi 18:6a4db94011d3 273 uint8_t RESERVED_0[4];
sahilmgandhi 18:6a4db94011d3 274 __IO uint32_t CLMD; /**< ADC minus-side general calibration value register, offset: 0x54 */
sahilmgandhi 18:6a4db94011d3 275 __IO uint32_t CLMS; /**< ADC minus-side general calibration value register, offset: 0x58 */
sahilmgandhi 18:6a4db94011d3 276 __IO uint32_t CLM4; /**< ADC minus-side general calibration value register, offset: 0x5C */
sahilmgandhi 18:6a4db94011d3 277 __IO uint32_t CLM3; /**< ADC minus-side general calibration value register, offset: 0x60 */
sahilmgandhi 18:6a4db94011d3 278 __IO uint32_t CLM2; /**< ADC minus-side general calibration value register, offset: 0x64 */
sahilmgandhi 18:6a4db94011d3 279 __IO uint32_t CLM1; /**< ADC minus-side general calibration value register, offset: 0x68 */
sahilmgandhi 18:6a4db94011d3 280 __IO uint32_t CLM0; /**< ADC minus-side general calibration value register, offset: 0x6C */
sahilmgandhi 18:6a4db94011d3 281 } ADC_Type;
sahilmgandhi 18:6a4db94011d3 282
sahilmgandhi 18:6a4db94011d3 283 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 284 -- ADC Register Masks
sahilmgandhi 18:6a4db94011d3 285 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 286
sahilmgandhi 18:6a4db94011d3 287 /**
sahilmgandhi 18:6a4db94011d3 288 * @addtogroup ADC_Register_Masks ADC Register Masks
sahilmgandhi 18:6a4db94011d3 289 * @{
sahilmgandhi 18:6a4db94011d3 290 */
sahilmgandhi 18:6a4db94011d3 291
sahilmgandhi 18:6a4db94011d3 292 /* SC1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 293 #define ADC_SC1_ADCH_MASK 0x1Fu
sahilmgandhi 18:6a4db94011d3 294 #define ADC_SC1_ADCH_SHIFT 0
sahilmgandhi 18:6a4db94011d3 295 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
sahilmgandhi 18:6a4db94011d3 296 #define ADC_SC1_DIFF_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 297 #define ADC_SC1_DIFF_SHIFT 5
sahilmgandhi 18:6a4db94011d3 298 #define ADC_SC1_AIEN_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 299 #define ADC_SC1_AIEN_SHIFT 6
sahilmgandhi 18:6a4db94011d3 300 #define ADC_SC1_COCO_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 301 #define ADC_SC1_COCO_SHIFT 7
sahilmgandhi 18:6a4db94011d3 302 /* CFG1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 303 #define ADC_CFG1_ADICLK_MASK 0x3u
sahilmgandhi 18:6a4db94011d3 304 #define ADC_CFG1_ADICLK_SHIFT 0
sahilmgandhi 18:6a4db94011d3 305 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
sahilmgandhi 18:6a4db94011d3 306 #define ADC_CFG1_MODE_MASK 0xCu
sahilmgandhi 18:6a4db94011d3 307 #define ADC_CFG1_MODE_SHIFT 2
sahilmgandhi 18:6a4db94011d3 308 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
sahilmgandhi 18:6a4db94011d3 309 #define ADC_CFG1_ADLSMP_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 310 #define ADC_CFG1_ADLSMP_SHIFT 4
sahilmgandhi 18:6a4db94011d3 311 #define ADC_CFG1_ADIV_MASK 0x60u
sahilmgandhi 18:6a4db94011d3 312 #define ADC_CFG1_ADIV_SHIFT 5
sahilmgandhi 18:6a4db94011d3 313 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
sahilmgandhi 18:6a4db94011d3 314 #define ADC_CFG1_ADLPC_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 315 #define ADC_CFG1_ADLPC_SHIFT 7
sahilmgandhi 18:6a4db94011d3 316 /* CFG2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 317 #define ADC_CFG2_ADLSTS_MASK 0x3u
sahilmgandhi 18:6a4db94011d3 318 #define ADC_CFG2_ADLSTS_SHIFT 0
sahilmgandhi 18:6a4db94011d3 319 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
sahilmgandhi 18:6a4db94011d3 320 #define ADC_CFG2_ADHSC_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 321 #define ADC_CFG2_ADHSC_SHIFT 2
sahilmgandhi 18:6a4db94011d3 322 #define ADC_CFG2_ADACKEN_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 323 #define ADC_CFG2_ADACKEN_SHIFT 3
sahilmgandhi 18:6a4db94011d3 324 #define ADC_CFG2_MUXSEL_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 325 #define ADC_CFG2_MUXSEL_SHIFT 4
sahilmgandhi 18:6a4db94011d3 326 /* R Bit Fields */
sahilmgandhi 18:6a4db94011d3 327 #define ADC_R_D_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 328 #define ADC_R_D_SHIFT 0
sahilmgandhi 18:6a4db94011d3 329 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
sahilmgandhi 18:6a4db94011d3 330 /* CV1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 331 #define ADC_CV1_CV_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 332 #define ADC_CV1_CV_SHIFT 0
sahilmgandhi 18:6a4db94011d3 333 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
sahilmgandhi 18:6a4db94011d3 334 /* CV2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 335 #define ADC_CV2_CV_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 336 #define ADC_CV2_CV_SHIFT 0
sahilmgandhi 18:6a4db94011d3 337 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
sahilmgandhi 18:6a4db94011d3 338 /* SC2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 339 #define ADC_SC2_REFSEL_MASK 0x3u
sahilmgandhi 18:6a4db94011d3 340 #define ADC_SC2_REFSEL_SHIFT 0
sahilmgandhi 18:6a4db94011d3 341 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
sahilmgandhi 18:6a4db94011d3 342 #define ADC_SC2_DMAEN_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 343 #define ADC_SC2_DMAEN_SHIFT 2
sahilmgandhi 18:6a4db94011d3 344 #define ADC_SC2_ACREN_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 345 #define ADC_SC2_ACREN_SHIFT 3
sahilmgandhi 18:6a4db94011d3 346 #define ADC_SC2_ACFGT_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 347 #define ADC_SC2_ACFGT_SHIFT 4
sahilmgandhi 18:6a4db94011d3 348 #define ADC_SC2_ACFE_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 349 #define ADC_SC2_ACFE_SHIFT 5
sahilmgandhi 18:6a4db94011d3 350 #define ADC_SC2_ADTRG_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 351 #define ADC_SC2_ADTRG_SHIFT 6
sahilmgandhi 18:6a4db94011d3 352 #define ADC_SC2_ADACT_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 353 #define ADC_SC2_ADACT_SHIFT 7
sahilmgandhi 18:6a4db94011d3 354 /* SC3 Bit Fields */
sahilmgandhi 18:6a4db94011d3 355 #define ADC_SC3_AVGS_MASK 0x3u
sahilmgandhi 18:6a4db94011d3 356 #define ADC_SC3_AVGS_SHIFT 0
sahilmgandhi 18:6a4db94011d3 357 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
sahilmgandhi 18:6a4db94011d3 358 #define ADC_SC3_AVGE_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 359 #define ADC_SC3_AVGE_SHIFT 2
sahilmgandhi 18:6a4db94011d3 360 #define ADC_SC3_ADCO_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 361 #define ADC_SC3_ADCO_SHIFT 3
sahilmgandhi 18:6a4db94011d3 362 #define ADC_SC3_CALF_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 363 #define ADC_SC3_CALF_SHIFT 6
sahilmgandhi 18:6a4db94011d3 364 #define ADC_SC3_CAL_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 365 #define ADC_SC3_CAL_SHIFT 7
sahilmgandhi 18:6a4db94011d3 366 /* OFS Bit Fields */
sahilmgandhi 18:6a4db94011d3 367 #define ADC_OFS_OFS_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 368 #define ADC_OFS_OFS_SHIFT 0
sahilmgandhi 18:6a4db94011d3 369 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
sahilmgandhi 18:6a4db94011d3 370 /* PG Bit Fields */
sahilmgandhi 18:6a4db94011d3 371 #define ADC_PG_PG_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 372 #define ADC_PG_PG_SHIFT 0
sahilmgandhi 18:6a4db94011d3 373 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
sahilmgandhi 18:6a4db94011d3 374 /* MG Bit Fields */
sahilmgandhi 18:6a4db94011d3 375 #define ADC_MG_MG_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 376 #define ADC_MG_MG_SHIFT 0
sahilmgandhi 18:6a4db94011d3 377 #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
sahilmgandhi 18:6a4db94011d3 378 /* CLPD Bit Fields */
sahilmgandhi 18:6a4db94011d3 379 #define ADC_CLPD_CLPD_MASK 0x3Fu
sahilmgandhi 18:6a4db94011d3 380 #define ADC_CLPD_CLPD_SHIFT 0
sahilmgandhi 18:6a4db94011d3 381 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
sahilmgandhi 18:6a4db94011d3 382 /* CLPS Bit Fields */
sahilmgandhi 18:6a4db94011d3 383 #define ADC_CLPS_CLPS_MASK 0x3Fu
sahilmgandhi 18:6a4db94011d3 384 #define ADC_CLPS_CLPS_SHIFT 0
sahilmgandhi 18:6a4db94011d3 385 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
sahilmgandhi 18:6a4db94011d3 386 /* CLP4 Bit Fields */
sahilmgandhi 18:6a4db94011d3 387 #define ADC_CLP4_CLP4_MASK 0x3FFu
sahilmgandhi 18:6a4db94011d3 388 #define ADC_CLP4_CLP4_SHIFT 0
sahilmgandhi 18:6a4db94011d3 389 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
sahilmgandhi 18:6a4db94011d3 390 /* CLP3 Bit Fields */
sahilmgandhi 18:6a4db94011d3 391 #define ADC_CLP3_CLP3_MASK 0x1FFu
sahilmgandhi 18:6a4db94011d3 392 #define ADC_CLP3_CLP3_SHIFT 0
sahilmgandhi 18:6a4db94011d3 393 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
sahilmgandhi 18:6a4db94011d3 394 /* CLP2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 395 #define ADC_CLP2_CLP2_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 396 #define ADC_CLP2_CLP2_SHIFT 0
sahilmgandhi 18:6a4db94011d3 397 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
sahilmgandhi 18:6a4db94011d3 398 /* CLP1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 399 #define ADC_CLP1_CLP1_MASK 0x7Fu
sahilmgandhi 18:6a4db94011d3 400 #define ADC_CLP1_CLP1_SHIFT 0
sahilmgandhi 18:6a4db94011d3 401 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
sahilmgandhi 18:6a4db94011d3 402 /* CLP0 Bit Fields */
sahilmgandhi 18:6a4db94011d3 403 #define ADC_CLP0_CLP0_MASK 0x3Fu
sahilmgandhi 18:6a4db94011d3 404 #define ADC_CLP0_CLP0_SHIFT 0
sahilmgandhi 18:6a4db94011d3 405 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
sahilmgandhi 18:6a4db94011d3 406 /* CLMD Bit Fields */
sahilmgandhi 18:6a4db94011d3 407 #define ADC_CLMD_CLMD_MASK 0x3Fu
sahilmgandhi 18:6a4db94011d3 408 #define ADC_CLMD_CLMD_SHIFT 0
sahilmgandhi 18:6a4db94011d3 409 #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
sahilmgandhi 18:6a4db94011d3 410 /* CLMS Bit Fields */
sahilmgandhi 18:6a4db94011d3 411 #define ADC_CLMS_CLMS_MASK 0x3Fu
sahilmgandhi 18:6a4db94011d3 412 #define ADC_CLMS_CLMS_SHIFT 0
sahilmgandhi 18:6a4db94011d3 413 #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
sahilmgandhi 18:6a4db94011d3 414 /* CLM4 Bit Fields */
sahilmgandhi 18:6a4db94011d3 415 #define ADC_CLM4_CLM4_MASK 0x3FFu
sahilmgandhi 18:6a4db94011d3 416 #define ADC_CLM4_CLM4_SHIFT 0
sahilmgandhi 18:6a4db94011d3 417 #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
sahilmgandhi 18:6a4db94011d3 418 /* CLM3 Bit Fields */
sahilmgandhi 18:6a4db94011d3 419 #define ADC_CLM3_CLM3_MASK 0x1FFu
sahilmgandhi 18:6a4db94011d3 420 #define ADC_CLM3_CLM3_SHIFT 0
sahilmgandhi 18:6a4db94011d3 421 #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
sahilmgandhi 18:6a4db94011d3 422 /* CLM2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 423 #define ADC_CLM2_CLM2_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 424 #define ADC_CLM2_CLM2_SHIFT 0
sahilmgandhi 18:6a4db94011d3 425 #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
sahilmgandhi 18:6a4db94011d3 426 /* CLM1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 427 #define ADC_CLM1_CLM1_MASK 0x7Fu
sahilmgandhi 18:6a4db94011d3 428 #define ADC_CLM1_CLM1_SHIFT 0
sahilmgandhi 18:6a4db94011d3 429 #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
sahilmgandhi 18:6a4db94011d3 430 /* CLM0 Bit Fields */
sahilmgandhi 18:6a4db94011d3 431 #define ADC_CLM0_CLM0_MASK 0x3Fu
sahilmgandhi 18:6a4db94011d3 432 #define ADC_CLM0_CLM0_SHIFT 0
sahilmgandhi 18:6a4db94011d3 433 #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
sahilmgandhi 18:6a4db94011d3 434
sahilmgandhi 18:6a4db94011d3 435 /**
sahilmgandhi 18:6a4db94011d3 436 * @}
sahilmgandhi 18:6a4db94011d3 437 */ /* end of group ADC_Register_Masks */
sahilmgandhi 18:6a4db94011d3 438
sahilmgandhi 18:6a4db94011d3 439
sahilmgandhi 18:6a4db94011d3 440 /* ADC - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 441 /** Peripheral ADC0 base address */
sahilmgandhi 18:6a4db94011d3 442 #define ADC0_BASE (0x4003B000u)
sahilmgandhi 18:6a4db94011d3 443 /** Peripheral ADC0 base pointer */
sahilmgandhi 18:6a4db94011d3 444 #define ADC0 ((ADC_Type *)ADC0_BASE)
sahilmgandhi 18:6a4db94011d3 445
sahilmgandhi 18:6a4db94011d3 446 /**
sahilmgandhi 18:6a4db94011d3 447 * @}
sahilmgandhi 18:6a4db94011d3 448 */ /* end of group ADC_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 449
sahilmgandhi 18:6a4db94011d3 450
sahilmgandhi 18:6a4db94011d3 451 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 452 -- CMP Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 453 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 454
sahilmgandhi 18:6a4db94011d3 455 /**
sahilmgandhi 18:6a4db94011d3 456 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 457 * @{
sahilmgandhi 18:6a4db94011d3 458 */
sahilmgandhi 18:6a4db94011d3 459
sahilmgandhi 18:6a4db94011d3 460 /** CMP - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 461 typedef struct {
sahilmgandhi 18:6a4db94011d3 462 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 463 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
sahilmgandhi 18:6a4db94011d3 464 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
sahilmgandhi 18:6a4db94011d3 465 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
sahilmgandhi 18:6a4db94011d3 466 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
sahilmgandhi 18:6a4db94011d3 467 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
sahilmgandhi 18:6a4db94011d3 468 } CMP_Type;
sahilmgandhi 18:6a4db94011d3 469
sahilmgandhi 18:6a4db94011d3 470 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 471 -- CMP Register Masks
sahilmgandhi 18:6a4db94011d3 472 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 473
sahilmgandhi 18:6a4db94011d3 474 /**
sahilmgandhi 18:6a4db94011d3 475 * @addtogroup CMP_Register_Masks CMP Register Masks
sahilmgandhi 18:6a4db94011d3 476 * @{
sahilmgandhi 18:6a4db94011d3 477 */
sahilmgandhi 18:6a4db94011d3 478
sahilmgandhi 18:6a4db94011d3 479 /* CR0 Bit Fields */
sahilmgandhi 18:6a4db94011d3 480 #define CMP_CR0_HYSTCTR_MASK 0x3u
sahilmgandhi 18:6a4db94011d3 481 #define CMP_CR0_HYSTCTR_SHIFT 0
sahilmgandhi 18:6a4db94011d3 482 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
sahilmgandhi 18:6a4db94011d3 483 #define CMP_CR0_FILTER_CNT_MASK 0x70u
sahilmgandhi 18:6a4db94011d3 484 #define CMP_CR0_FILTER_CNT_SHIFT 4
sahilmgandhi 18:6a4db94011d3 485 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
sahilmgandhi 18:6a4db94011d3 486 /* CR1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 487 #define CMP_CR1_EN_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 488 #define CMP_CR1_EN_SHIFT 0
sahilmgandhi 18:6a4db94011d3 489 #define CMP_CR1_OPE_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 490 #define CMP_CR1_OPE_SHIFT 1
sahilmgandhi 18:6a4db94011d3 491 #define CMP_CR1_COS_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 492 #define CMP_CR1_COS_SHIFT 2
sahilmgandhi 18:6a4db94011d3 493 #define CMP_CR1_INV_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 494 #define CMP_CR1_INV_SHIFT 3
sahilmgandhi 18:6a4db94011d3 495 #define CMP_CR1_PMODE_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 496 #define CMP_CR1_PMODE_SHIFT 4
sahilmgandhi 18:6a4db94011d3 497 #define CMP_CR1_WE_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 498 #define CMP_CR1_WE_SHIFT 6
sahilmgandhi 18:6a4db94011d3 499 #define CMP_CR1_SE_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 500 #define CMP_CR1_SE_SHIFT 7
sahilmgandhi 18:6a4db94011d3 501 /* FPR Bit Fields */
sahilmgandhi 18:6a4db94011d3 502 #define CMP_FPR_FILT_PER_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 503 #define CMP_FPR_FILT_PER_SHIFT 0
sahilmgandhi 18:6a4db94011d3 504 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
sahilmgandhi 18:6a4db94011d3 505 /* SCR Bit Fields */
sahilmgandhi 18:6a4db94011d3 506 #define CMP_SCR_COUT_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 507 #define CMP_SCR_COUT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 508 #define CMP_SCR_CFF_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 509 #define CMP_SCR_CFF_SHIFT 1
sahilmgandhi 18:6a4db94011d3 510 #define CMP_SCR_CFR_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 511 #define CMP_SCR_CFR_SHIFT 2
sahilmgandhi 18:6a4db94011d3 512 #define CMP_SCR_IEF_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 513 #define CMP_SCR_IEF_SHIFT 3
sahilmgandhi 18:6a4db94011d3 514 #define CMP_SCR_IER_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 515 #define CMP_SCR_IER_SHIFT 4
sahilmgandhi 18:6a4db94011d3 516 #define CMP_SCR_DMAEN_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 517 #define CMP_SCR_DMAEN_SHIFT 6
sahilmgandhi 18:6a4db94011d3 518 /* DACCR Bit Fields */
sahilmgandhi 18:6a4db94011d3 519 #define CMP_DACCR_VOSEL_MASK 0x3Fu
sahilmgandhi 18:6a4db94011d3 520 #define CMP_DACCR_VOSEL_SHIFT 0
sahilmgandhi 18:6a4db94011d3 521 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
sahilmgandhi 18:6a4db94011d3 522 #define CMP_DACCR_VRSEL_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 523 #define CMP_DACCR_VRSEL_SHIFT 6
sahilmgandhi 18:6a4db94011d3 524 #define CMP_DACCR_DACEN_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 525 #define CMP_DACCR_DACEN_SHIFT 7
sahilmgandhi 18:6a4db94011d3 526 /* MUXCR Bit Fields */
sahilmgandhi 18:6a4db94011d3 527 #define CMP_MUXCR_MSEL_MASK 0x7u
sahilmgandhi 18:6a4db94011d3 528 #define CMP_MUXCR_MSEL_SHIFT 0
sahilmgandhi 18:6a4db94011d3 529 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
sahilmgandhi 18:6a4db94011d3 530 #define CMP_MUXCR_PSEL_MASK 0x38u
sahilmgandhi 18:6a4db94011d3 531 #define CMP_MUXCR_PSEL_SHIFT 3
sahilmgandhi 18:6a4db94011d3 532 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
sahilmgandhi 18:6a4db94011d3 533
sahilmgandhi 18:6a4db94011d3 534 /**
sahilmgandhi 18:6a4db94011d3 535 * @}
sahilmgandhi 18:6a4db94011d3 536 */ /* end of group CMP_Register_Masks */
sahilmgandhi 18:6a4db94011d3 537
sahilmgandhi 18:6a4db94011d3 538
sahilmgandhi 18:6a4db94011d3 539 /* CMP - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 540 /** Peripheral CMP0 base address */
sahilmgandhi 18:6a4db94011d3 541 #define CMP0_BASE (0x40073000u)
sahilmgandhi 18:6a4db94011d3 542 /** Peripheral CMP0 base pointer */
sahilmgandhi 18:6a4db94011d3 543 #define CMP0 ((CMP_Type *)CMP0_BASE)
sahilmgandhi 18:6a4db94011d3 544 /** Peripheral CMP1 base address */
sahilmgandhi 18:6a4db94011d3 545 #define CMP1_BASE (0x40073008u)
sahilmgandhi 18:6a4db94011d3 546 /** Peripheral CMP1 base pointer */
sahilmgandhi 18:6a4db94011d3 547 #define CMP1 ((CMP_Type *)CMP1_BASE)
sahilmgandhi 18:6a4db94011d3 548
sahilmgandhi 18:6a4db94011d3 549 /**
sahilmgandhi 18:6a4db94011d3 550 * @}
sahilmgandhi 18:6a4db94011d3 551 */ /* end of group CMP_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 552
sahilmgandhi 18:6a4db94011d3 553
sahilmgandhi 18:6a4db94011d3 554 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 555 -- CMT Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 556 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 557
sahilmgandhi 18:6a4db94011d3 558 /**
sahilmgandhi 18:6a4db94011d3 559 * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 560 * @{
sahilmgandhi 18:6a4db94011d3 561 */
sahilmgandhi 18:6a4db94011d3 562
sahilmgandhi 18:6a4db94011d3 563 /** CMT - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 564 typedef struct {
sahilmgandhi 18:6a4db94011d3 565 __IO uint8_t CGH1; /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 566 __IO uint8_t CGL1; /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */
sahilmgandhi 18:6a4db94011d3 567 __IO uint8_t CGH2; /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */
sahilmgandhi 18:6a4db94011d3 568 __IO uint8_t CGL2; /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */
sahilmgandhi 18:6a4db94011d3 569 __IO uint8_t OC; /**< CMT Output Control Register, offset: 0x4 */
sahilmgandhi 18:6a4db94011d3 570 __IO uint8_t MSC; /**< CMT Modulator Status and Control Register, offset: 0x5 */
sahilmgandhi 18:6a4db94011d3 571 __IO uint8_t CMD1; /**< CMT Modulator Data Register Mark High, offset: 0x6 */
sahilmgandhi 18:6a4db94011d3 572 __IO uint8_t CMD2; /**< CMT Modulator Data Register Mark Low, offset: 0x7 */
sahilmgandhi 18:6a4db94011d3 573 __IO uint8_t CMD3; /**< CMT Modulator Data Register Space High, offset: 0x8 */
sahilmgandhi 18:6a4db94011d3 574 __IO uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */
sahilmgandhi 18:6a4db94011d3 575 __IO uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */
sahilmgandhi 18:6a4db94011d3 576 __IO uint8_t DMA; /**< CMT Direct Memory Access, offset: 0xB */
sahilmgandhi 18:6a4db94011d3 577 } CMT_Type;
sahilmgandhi 18:6a4db94011d3 578
sahilmgandhi 18:6a4db94011d3 579 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 580 -- CMT Register Masks
sahilmgandhi 18:6a4db94011d3 581 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 582
sahilmgandhi 18:6a4db94011d3 583 /**
sahilmgandhi 18:6a4db94011d3 584 * @addtogroup CMT_Register_Masks CMT Register Masks
sahilmgandhi 18:6a4db94011d3 585 * @{
sahilmgandhi 18:6a4db94011d3 586 */
sahilmgandhi 18:6a4db94011d3 587
sahilmgandhi 18:6a4db94011d3 588 /* CGH1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 589 #define CMT_CGH1_PH_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 590 #define CMT_CGH1_PH_SHIFT 0
sahilmgandhi 18:6a4db94011d3 591 #define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH1_PH_SHIFT))&CMT_CGH1_PH_MASK)
sahilmgandhi 18:6a4db94011d3 592 /* CGL1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 593 #define CMT_CGL1_PL_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 594 #define CMT_CGL1_PL_SHIFT 0
sahilmgandhi 18:6a4db94011d3 595 #define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL1_PL_SHIFT))&CMT_CGL1_PL_MASK)
sahilmgandhi 18:6a4db94011d3 596 /* CGH2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 597 #define CMT_CGH2_SH_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 598 #define CMT_CGH2_SH_SHIFT 0
sahilmgandhi 18:6a4db94011d3 599 #define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH2_SH_SHIFT))&CMT_CGH2_SH_MASK)
sahilmgandhi 18:6a4db94011d3 600 /* CGL2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 601 #define CMT_CGL2_SL_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 602 #define CMT_CGL2_SL_SHIFT 0
sahilmgandhi 18:6a4db94011d3 603 #define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL2_SL_SHIFT))&CMT_CGL2_SL_MASK)
sahilmgandhi 18:6a4db94011d3 604 /* OC Bit Fields */
sahilmgandhi 18:6a4db94011d3 605 #define CMT_OC_IROPEN_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 606 #define CMT_OC_IROPEN_SHIFT 5
sahilmgandhi 18:6a4db94011d3 607 #define CMT_OC_CMTPOL_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 608 #define CMT_OC_CMTPOL_SHIFT 6
sahilmgandhi 18:6a4db94011d3 609 #define CMT_OC_IROL_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 610 #define CMT_OC_IROL_SHIFT 7
sahilmgandhi 18:6a4db94011d3 611 /* MSC Bit Fields */
sahilmgandhi 18:6a4db94011d3 612 #define CMT_MSC_MCGEN_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 613 #define CMT_MSC_MCGEN_SHIFT 0
sahilmgandhi 18:6a4db94011d3 614 #define CMT_MSC_EOCIE_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 615 #define CMT_MSC_EOCIE_SHIFT 1
sahilmgandhi 18:6a4db94011d3 616 #define CMT_MSC_FSK_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 617 #define CMT_MSC_FSK_SHIFT 2
sahilmgandhi 18:6a4db94011d3 618 #define CMT_MSC_BASE_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 619 #define CMT_MSC_BASE_SHIFT 3
sahilmgandhi 18:6a4db94011d3 620 #define CMT_MSC_EXSPC_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 621 #define CMT_MSC_EXSPC_SHIFT 4
sahilmgandhi 18:6a4db94011d3 622 #define CMT_MSC_CMTDIV_MASK 0x60u
sahilmgandhi 18:6a4db94011d3 623 #define CMT_MSC_CMTDIV_SHIFT 5
sahilmgandhi 18:6a4db94011d3 624 #define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_MSC_CMTDIV_SHIFT))&CMT_MSC_CMTDIV_MASK)
sahilmgandhi 18:6a4db94011d3 625 #define CMT_MSC_EOCF_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 626 #define CMT_MSC_EOCF_SHIFT 7
sahilmgandhi 18:6a4db94011d3 627 /* CMD1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 628 #define CMT_CMD1_MB_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 629 #define CMT_CMD1_MB_SHIFT 0
sahilmgandhi 18:6a4db94011d3 630 #define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD1_MB_SHIFT))&CMT_CMD1_MB_MASK)
sahilmgandhi 18:6a4db94011d3 631 /* CMD2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 632 #define CMT_CMD2_MB_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 633 #define CMT_CMD2_MB_SHIFT 0
sahilmgandhi 18:6a4db94011d3 634 #define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD2_MB_SHIFT))&CMT_CMD2_MB_MASK)
sahilmgandhi 18:6a4db94011d3 635 /* CMD3 Bit Fields */
sahilmgandhi 18:6a4db94011d3 636 #define CMT_CMD3_SB_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 637 #define CMT_CMD3_SB_SHIFT 0
sahilmgandhi 18:6a4db94011d3 638 #define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD3_SB_SHIFT))&CMT_CMD3_SB_MASK)
sahilmgandhi 18:6a4db94011d3 639 /* CMD4 Bit Fields */
sahilmgandhi 18:6a4db94011d3 640 #define CMT_CMD4_SB_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 641 #define CMT_CMD4_SB_SHIFT 0
sahilmgandhi 18:6a4db94011d3 642 #define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD4_SB_SHIFT))&CMT_CMD4_SB_MASK)
sahilmgandhi 18:6a4db94011d3 643 /* PPS Bit Fields */
sahilmgandhi 18:6a4db94011d3 644 #define CMT_PPS_PPSDIV_MASK 0xFu
sahilmgandhi 18:6a4db94011d3 645 #define CMT_PPS_PPSDIV_SHIFT 0
sahilmgandhi 18:6a4db94011d3 646 #define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_PPS_PPSDIV_SHIFT))&CMT_PPS_PPSDIV_MASK)
sahilmgandhi 18:6a4db94011d3 647 /* DMA Bit Fields */
sahilmgandhi 18:6a4db94011d3 648 #define CMT_DMA_DMA_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 649 #define CMT_DMA_DMA_SHIFT 0
sahilmgandhi 18:6a4db94011d3 650
sahilmgandhi 18:6a4db94011d3 651 /**
sahilmgandhi 18:6a4db94011d3 652 * @}
sahilmgandhi 18:6a4db94011d3 653 */ /* end of group CMT_Register_Masks */
sahilmgandhi 18:6a4db94011d3 654
sahilmgandhi 18:6a4db94011d3 655
sahilmgandhi 18:6a4db94011d3 656 /* CMT - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 657 /** Peripheral CMT base address */
sahilmgandhi 18:6a4db94011d3 658 #define CMT_BASE (0x40062000u)
sahilmgandhi 18:6a4db94011d3 659 /** Peripheral CMT base pointer */
sahilmgandhi 18:6a4db94011d3 660 #define CMT ((CMT_Type *)CMT_BASE)
sahilmgandhi 18:6a4db94011d3 661
sahilmgandhi 18:6a4db94011d3 662 /**
sahilmgandhi 18:6a4db94011d3 663 * @}
sahilmgandhi 18:6a4db94011d3 664 */ /* end of group CMT_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 665
sahilmgandhi 18:6a4db94011d3 666
sahilmgandhi 18:6a4db94011d3 667 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 668 -- CRC Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 669 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 670
sahilmgandhi 18:6a4db94011d3 671 /**
sahilmgandhi 18:6a4db94011d3 672 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 673 * @{
sahilmgandhi 18:6a4db94011d3 674 */
sahilmgandhi 18:6a4db94011d3 675
sahilmgandhi 18:6a4db94011d3 676 /** CRC - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 677 typedef struct {
sahilmgandhi 18:6a4db94011d3 678 union { /* offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 679 struct { /* offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 680 __IO uint16_t CRCL; /**< CRC_CRCL register., offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 681 __IO uint16_t CRCH; /**< CRC_CRCH register., offset: 0x2 */
sahilmgandhi 18:6a4db94011d3 682 } ACCESS16BIT;
sahilmgandhi 18:6a4db94011d3 683 __IO uint32_t CRC; /**< CRC Data Register, offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 684 struct { /* offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 685 __IO uint8_t CRCLL; /**< CRC_CRCLL register., offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 686 __IO uint8_t CRCLU; /**< CRC_CRCLU register., offset: 0x1 */
sahilmgandhi 18:6a4db94011d3 687 __IO uint8_t CRCHL; /**< CRC_CRCHL register., offset: 0x2 */
sahilmgandhi 18:6a4db94011d3 688 __IO uint8_t CRCHU; /**< CRC_CRCHU register., offset: 0x3 */
sahilmgandhi 18:6a4db94011d3 689 } ACCESS8BIT;
sahilmgandhi 18:6a4db94011d3 690 };
sahilmgandhi 18:6a4db94011d3 691 union { /* offset: 0x4 */
sahilmgandhi 18:6a4db94011d3 692 struct { /* offset: 0x4 */
sahilmgandhi 18:6a4db94011d3 693 __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */
sahilmgandhi 18:6a4db94011d3 694 __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */
sahilmgandhi 18:6a4db94011d3 695 } GPOLY_ACCESS16BIT;
sahilmgandhi 18:6a4db94011d3 696 __IO uint32_t GPOLY; /**< CRC Polynomial Register, offset: 0x4 */
sahilmgandhi 18:6a4db94011d3 697 struct { /* offset: 0x4 */
sahilmgandhi 18:6a4db94011d3 698 __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */
sahilmgandhi 18:6a4db94011d3 699 __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */
sahilmgandhi 18:6a4db94011d3 700 __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */
sahilmgandhi 18:6a4db94011d3 701 __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */
sahilmgandhi 18:6a4db94011d3 702 } GPOLY_ACCESS8BIT;
sahilmgandhi 18:6a4db94011d3 703 };
sahilmgandhi 18:6a4db94011d3 704 union { /* offset: 0x8 */
sahilmgandhi 18:6a4db94011d3 705 __IO uint32_t CTRL; /**< CRC Control Register, offset: 0x8 */
sahilmgandhi 18:6a4db94011d3 706 struct { /* offset: 0x8 */
sahilmgandhi 18:6a4db94011d3 707 uint8_t RESERVED_0[3];
sahilmgandhi 18:6a4db94011d3 708 __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
sahilmgandhi 18:6a4db94011d3 709 } CTRL_ACCESS8BIT;
sahilmgandhi 18:6a4db94011d3 710 };
sahilmgandhi 18:6a4db94011d3 711 } CRC_Type;
sahilmgandhi 18:6a4db94011d3 712
sahilmgandhi 18:6a4db94011d3 713 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 714 -- CRC Register Masks
sahilmgandhi 18:6a4db94011d3 715 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 716
sahilmgandhi 18:6a4db94011d3 717 /**
sahilmgandhi 18:6a4db94011d3 718 * @addtogroup CRC_Register_Masks CRC Register Masks
sahilmgandhi 18:6a4db94011d3 719 * @{
sahilmgandhi 18:6a4db94011d3 720 */
sahilmgandhi 18:6a4db94011d3 721
sahilmgandhi 18:6a4db94011d3 722 /* CRCL Bit Fields */
sahilmgandhi 18:6a4db94011d3 723 #define CRC_CRCL_CRCL_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 724 #define CRC_CRCL_CRCL_SHIFT 0
sahilmgandhi 18:6a4db94011d3 725 #define CRC_CRCL_CRCL(x) (((uint16_t)(((uint16_t)(x))<<CRC_CRCL_CRCL_SHIFT))&CRC_CRCL_CRCL_MASK)
sahilmgandhi 18:6a4db94011d3 726 /* CRCH Bit Fields */
sahilmgandhi 18:6a4db94011d3 727 #define CRC_CRCH_CRCH_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 728 #define CRC_CRCH_CRCH_SHIFT 0
sahilmgandhi 18:6a4db94011d3 729 #define CRC_CRCH_CRCH(x) (((uint16_t)(((uint16_t)(x))<<CRC_CRCH_CRCH_SHIFT))&CRC_CRCH_CRCH_MASK)
sahilmgandhi 18:6a4db94011d3 730 /* CRC Bit Fields */
sahilmgandhi 18:6a4db94011d3 731 #define CRC_CRC_LL_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 732 #define CRC_CRC_LL_SHIFT 0
sahilmgandhi 18:6a4db94011d3 733 #define CRC_CRC_LL(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_LL_SHIFT))&CRC_CRC_LL_MASK)
sahilmgandhi 18:6a4db94011d3 734 #define CRC_CRC_LU_MASK 0xFF00u
sahilmgandhi 18:6a4db94011d3 735 #define CRC_CRC_LU_SHIFT 8
sahilmgandhi 18:6a4db94011d3 736 #define CRC_CRC_LU(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_LU_SHIFT))&CRC_CRC_LU_MASK)
sahilmgandhi 18:6a4db94011d3 737 #define CRC_CRC_HL_MASK 0xFF0000u
sahilmgandhi 18:6a4db94011d3 738 #define CRC_CRC_HL_SHIFT 16
sahilmgandhi 18:6a4db94011d3 739 #define CRC_CRC_HL(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_HL_SHIFT))&CRC_CRC_HL_MASK)
sahilmgandhi 18:6a4db94011d3 740 #define CRC_CRC_HU_MASK 0xFF000000u
sahilmgandhi 18:6a4db94011d3 741 #define CRC_CRC_HU_SHIFT 24
sahilmgandhi 18:6a4db94011d3 742 #define CRC_CRC_HU(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_HU_SHIFT))&CRC_CRC_HU_MASK)
sahilmgandhi 18:6a4db94011d3 743 /* CRCLL Bit Fields */
sahilmgandhi 18:6a4db94011d3 744 #define CRC_CRCLL_CRCLL_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 745 #define CRC_CRCLL_CRCLL_SHIFT 0
sahilmgandhi 18:6a4db94011d3 746 #define CRC_CRCLL_CRCLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCLL_CRCLL_SHIFT))&CRC_CRCLL_CRCLL_MASK)
sahilmgandhi 18:6a4db94011d3 747 /* CRCLU Bit Fields */
sahilmgandhi 18:6a4db94011d3 748 #define CRC_CRCLU_CRCLU_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 749 #define CRC_CRCLU_CRCLU_SHIFT 0
sahilmgandhi 18:6a4db94011d3 750 #define CRC_CRCLU_CRCLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCLU_CRCLU_SHIFT))&CRC_CRCLU_CRCLU_MASK)
sahilmgandhi 18:6a4db94011d3 751 /* CRCHL Bit Fields */
sahilmgandhi 18:6a4db94011d3 752 #define CRC_CRCHL_CRCHL_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 753 #define CRC_CRCHL_CRCHL_SHIFT 0
sahilmgandhi 18:6a4db94011d3 754 #define CRC_CRCHL_CRCHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCHL_CRCHL_SHIFT))&CRC_CRCHL_CRCHL_MASK)
sahilmgandhi 18:6a4db94011d3 755 /* CRCHU Bit Fields */
sahilmgandhi 18:6a4db94011d3 756 #define CRC_CRCHU_CRCHU_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 757 #define CRC_CRCHU_CRCHU_SHIFT 0
sahilmgandhi 18:6a4db94011d3 758 #define CRC_CRCHU_CRCHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCHU_CRCHU_SHIFT))&CRC_CRCHU_CRCHU_MASK)
sahilmgandhi 18:6a4db94011d3 759 /* GPOLYL Bit Fields */
sahilmgandhi 18:6a4db94011d3 760 #define CRC_GPOLYL_GPOLYL_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 761 #define CRC_GPOLYL_GPOLYL_SHIFT 0
sahilmgandhi 18:6a4db94011d3 762 #define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK)
sahilmgandhi 18:6a4db94011d3 763 /* GPOLYH Bit Fields */
sahilmgandhi 18:6a4db94011d3 764 #define CRC_GPOLYH_GPOLYH_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 765 #define CRC_GPOLYH_GPOLYH_SHIFT 0
sahilmgandhi 18:6a4db94011d3 766 #define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK)
sahilmgandhi 18:6a4db94011d3 767 /* GPOLY Bit Fields */
sahilmgandhi 18:6a4db94011d3 768 #define CRC_GPOLY_LOW_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 769 #define CRC_GPOLY_LOW_SHIFT 0
sahilmgandhi 18:6a4db94011d3 770 #define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
sahilmgandhi 18:6a4db94011d3 771 #define CRC_GPOLY_HIGH_MASK 0xFFFF0000u
sahilmgandhi 18:6a4db94011d3 772 #define CRC_GPOLY_HIGH_SHIFT 16
sahilmgandhi 18:6a4db94011d3 773 #define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
sahilmgandhi 18:6a4db94011d3 774 /* GPOLYLL Bit Fields */
sahilmgandhi 18:6a4db94011d3 775 #define CRC_GPOLYLL_GPOLYLL_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 776 #define CRC_GPOLYLL_GPOLYLL_SHIFT 0
sahilmgandhi 18:6a4db94011d3 777 #define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK)
sahilmgandhi 18:6a4db94011d3 778 /* GPOLYLU Bit Fields */
sahilmgandhi 18:6a4db94011d3 779 #define CRC_GPOLYLU_GPOLYLU_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 780 #define CRC_GPOLYLU_GPOLYLU_SHIFT 0
sahilmgandhi 18:6a4db94011d3 781 #define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK)
sahilmgandhi 18:6a4db94011d3 782 /* GPOLYHL Bit Fields */
sahilmgandhi 18:6a4db94011d3 783 #define CRC_GPOLYHL_GPOLYHL_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 784 #define CRC_GPOLYHL_GPOLYHL_SHIFT 0
sahilmgandhi 18:6a4db94011d3 785 #define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK)
sahilmgandhi 18:6a4db94011d3 786 /* GPOLYHU Bit Fields */
sahilmgandhi 18:6a4db94011d3 787 #define CRC_GPOLYHU_GPOLYHU_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 788 #define CRC_GPOLYHU_GPOLYHU_SHIFT 0
sahilmgandhi 18:6a4db94011d3 789 #define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK)
sahilmgandhi 18:6a4db94011d3 790 /* CTRL Bit Fields */
sahilmgandhi 18:6a4db94011d3 791 #define CRC_CTRL_TCRC_MASK 0x1000000u
sahilmgandhi 18:6a4db94011d3 792 #define CRC_CTRL_TCRC_SHIFT 24
sahilmgandhi 18:6a4db94011d3 793 #define CRC_CTRL_WAS_MASK 0x2000000u
sahilmgandhi 18:6a4db94011d3 794 #define CRC_CTRL_WAS_SHIFT 25
sahilmgandhi 18:6a4db94011d3 795 #define CRC_CTRL_FXOR_MASK 0x4000000u
sahilmgandhi 18:6a4db94011d3 796 #define CRC_CTRL_FXOR_SHIFT 26
sahilmgandhi 18:6a4db94011d3 797 #define CRC_CTRL_TOTR_MASK 0x30000000u
sahilmgandhi 18:6a4db94011d3 798 #define CRC_CTRL_TOTR_SHIFT 28
sahilmgandhi 18:6a4db94011d3 799 #define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
sahilmgandhi 18:6a4db94011d3 800 #define CRC_CTRL_TOT_MASK 0xC0000000u
sahilmgandhi 18:6a4db94011d3 801 #define CRC_CTRL_TOT_SHIFT 30
sahilmgandhi 18:6a4db94011d3 802 #define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
sahilmgandhi 18:6a4db94011d3 803 /* CTRLHU Bit Fields */
sahilmgandhi 18:6a4db94011d3 804 #define CRC_CTRLHU_TCRC_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 805 #define CRC_CTRLHU_TCRC_SHIFT 0
sahilmgandhi 18:6a4db94011d3 806 #define CRC_CTRLHU_WAS_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 807 #define CRC_CTRLHU_WAS_SHIFT 1
sahilmgandhi 18:6a4db94011d3 808 #define CRC_CTRLHU_FXOR_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 809 #define CRC_CTRLHU_FXOR_SHIFT 2
sahilmgandhi 18:6a4db94011d3 810 #define CRC_CTRLHU_TOTR_MASK 0x30u
sahilmgandhi 18:6a4db94011d3 811 #define CRC_CTRLHU_TOTR_SHIFT 4
sahilmgandhi 18:6a4db94011d3 812 #define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK)
sahilmgandhi 18:6a4db94011d3 813 #define CRC_CTRLHU_TOT_MASK 0xC0u
sahilmgandhi 18:6a4db94011d3 814 #define CRC_CTRLHU_TOT_SHIFT 6
sahilmgandhi 18:6a4db94011d3 815 #define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK)
sahilmgandhi 18:6a4db94011d3 816
sahilmgandhi 18:6a4db94011d3 817 /**
sahilmgandhi 18:6a4db94011d3 818 * @}
sahilmgandhi 18:6a4db94011d3 819 */ /* end of group CRC_Register_Masks */
sahilmgandhi 18:6a4db94011d3 820
sahilmgandhi 18:6a4db94011d3 821
sahilmgandhi 18:6a4db94011d3 822 /* CRC - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 823 /** Peripheral CRC base address */
sahilmgandhi 18:6a4db94011d3 824 #define CRC_BASE (0x40032000u)
sahilmgandhi 18:6a4db94011d3 825 /** Peripheral CRC base pointer */
sahilmgandhi 18:6a4db94011d3 826 #define CRC0 ((CRC_Type *)CRC_BASE)
sahilmgandhi 18:6a4db94011d3 827
sahilmgandhi 18:6a4db94011d3 828 /**
sahilmgandhi 18:6a4db94011d3 829 * @}
sahilmgandhi 18:6a4db94011d3 830 */ /* end of group CRC_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 831
sahilmgandhi 18:6a4db94011d3 832
sahilmgandhi 18:6a4db94011d3 833 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 834 -- DAC Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 835 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 836
sahilmgandhi 18:6a4db94011d3 837 /**
sahilmgandhi 18:6a4db94011d3 838 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 839 * @{
sahilmgandhi 18:6a4db94011d3 840 */
sahilmgandhi 18:6a4db94011d3 841
sahilmgandhi 18:6a4db94011d3 842 /** DAC - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 843 typedef struct {
sahilmgandhi 18:6a4db94011d3 844 struct { /* offset: 0x0, array step: 0x2 */
sahilmgandhi 18:6a4db94011d3 845 __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
sahilmgandhi 18:6a4db94011d3 846 __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
sahilmgandhi 18:6a4db94011d3 847 } DAT[16];
sahilmgandhi 18:6a4db94011d3 848 __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 849 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
sahilmgandhi 18:6a4db94011d3 850 __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
sahilmgandhi 18:6a4db94011d3 851 __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
sahilmgandhi 18:6a4db94011d3 852 } DAC_Type, *DAC_MemMapPtr;
sahilmgandhi 18:6a4db94011d3 853
sahilmgandhi 18:6a4db94011d3 854 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 855 -- DAC Register Masks
sahilmgandhi 18:6a4db94011d3 856 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 857
sahilmgandhi 18:6a4db94011d3 858 /**
sahilmgandhi 18:6a4db94011d3 859 * @addtogroup DAC_Register_Masks DAC Register Masks
sahilmgandhi 18:6a4db94011d3 860 * @{
sahilmgandhi 18:6a4db94011d3 861 */
sahilmgandhi 18:6a4db94011d3 862
sahilmgandhi 18:6a4db94011d3 863 /* DATL Bit Fields */
sahilmgandhi 18:6a4db94011d3 864 #define DAC_DATL_DATA0_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 865 #define DAC_DATL_DATA0_SHIFT 0
sahilmgandhi 18:6a4db94011d3 866 #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
sahilmgandhi 18:6a4db94011d3 867 /* DATH Bit Fields */
sahilmgandhi 18:6a4db94011d3 868 #define DAC_DATH_DATA1_MASK 0xFu
sahilmgandhi 18:6a4db94011d3 869 #define DAC_DATH_DATA1_SHIFT 0
sahilmgandhi 18:6a4db94011d3 870 #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
sahilmgandhi 18:6a4db94011d3 871 /* SR Bit Fields */
sahilmgandhi 18:6a4db94011d3 872 #define DAC_SR_DACBFRPBF_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 873 #define DAC_SR_DACBFRPBF_SHIFT 0
sahilmgandhi 18:6a4db94011d3 874 #define DAC_SR_DACBFRPTF_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 875 #define DAC_SR_DACBFRPTF_SHIFT 1
sahilmgandhi 18:6a4db94011d3 876 #define DAC_SR_DACBFWMF_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 877 #define DAC_SR_DACBFWMF_SHIFT 2
sahilmgandhi 18:6a4db94011d3 878 /* C0 Bit Fields */
sahilmgandhi 18:6a4db94011d3 879 #define DAC_C0_DACBBIEN_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 880 #define DAC_C0_DACBBIEN_SHIFT 0
sahilmgandhi 18:6a4db94011d3 881 #define DAC_C0_DACBTIEN_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 882 #define DAC_C0_DACBTIEN_SHIFT 1
sahilmgandhi 18:6a4db94011d3 883 #define DAC_C0_DACBWIEN_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 884 #define DAC_C0_DACBWIEN_SHIFT 2
sahilmgandhi 18:6a4db94011d3 885 #define DAC_C0_LPEN_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 886 #define DAC_C0_LPEN_SHIFT 3
sahilmgandhi 18:6a4db94011d3 887 #define DAC_C0_DACSWTRG_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 888 #define DAC_C0_DACSWTRG_SHIFT 4
sahilmgandhi 18:6a4db94011d3 889 #define DAC_C0_DACTRGSEL_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 890 #define DAC_C0_DACTRGSEL_SHIFT 5
sahilmgandhi 18:6a4db94011d3 891 #define DAC_C0_DACRFS_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 892 #define DAC_C0_DACRFS_SHIFT 6
sahilmgandhi 18:6a4db94011d3 893 #define DAC_C0_DACEN_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 894 #define DAC_C0_DACEN_SHIFT 7
sahilmgandhi 18:6a4db94011d3 895 /* C1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 896 #define DAC_C1_DACBFEN_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 897 #define DAC_C1_DACBFEN_SHIFT 0
sahilmgandhi 18:6a4db94011d3 898 #define DAC_C1_DACBFMD_MASK 0x6u
sahilmgandhi 18:6a4db94011d3 899 #define DAC_C1_DACBFMD_SHIFT 1
sahilmgandhi 18:6a4db94011d3 900 #define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFMD_SHIFT))&DAC_C1_DACBFMD_MASK)
sahilmgandhi 18:6a4db94011d3 901 #define DAC_C1_DACBFWM_MASK 0x18u
sahilmgandhi 18:6a4db94011d3 902 #define DAC_C1_DACBFWM_SHIFT 3
sahilmgandhi 18:6a4db94011d3 903 #define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFWM_SHIFT))&DAC_C1_DACBFWM_MASK)
sahilmgandhi 18:6a4db94011d3 904 #define DAC_C1_DMAEN_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 905 #define DAC_C1_DMAEN_SHIFT 7
sahilmgandhi 18:6a4db94011d3 906 /* C2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 907 #define DAC_C2_DACBFUP_MASK 0xFu
sahilmgandhi 18:6a4db94011d3 908 #define DAC_C2_DACBFUP_SHIFT 0
sahilmgandhi 18:6a4db94011d3 909 #define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFUP_SHIFT))&DAC_C2_DACBFUP_MASK)
sahilmgandhi 18:6a4db94011d3 910 #define DAC_C2_DACBFRP_MASK 0xF0u
sahilmgandhi 18:6a4db94011d3 911 #define DAC_C2_DACBFRP_SHIFT 4
sahilmgandhi 18:6a4db94011d3 912 #define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFRP_SHIFT))&DAC_C2_DACBFRP_MASK)
sahilmgandhi 18:6a4db94011d3 913
sahilmgandhi 18:6a4db94011d3 914 /**
sahilmgandhi 18:6a4db94011d3 915 * @}
sahilmgandhi 18:6a4db94011d3 916 */ /* end of group DAC_Register_Masks */
sahilmgandhi 18:6a4db94011d3 917
sahilmgandhi 18:6a4db94011d3 918
sahilmgandhi 18:6a4db94011d3 919 /* DAC - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 920 /** Peripheral DAC0 base address */
sahilmgandhi 18:6a4db94011d3 921 #define DAC0_BASE (0x400CC000u)
sahilmgandhi 18:6a4db94011d3 922 /** Peripheral DAC0 base pointer */
sahilmgandhi 18:6a4db94011d3 923 #define DAC0 ((DAC_Type *)DAC0_BASE)
sahilmgandhi 18:6a4db94011d3 924 /** Array initializer of DAC peripheral base pointers */
sahilmgandhi 18:6a4db94011d3 925 #define DAC_BASES { DAC0 }
sahilmgandhi 18:6a4db94011d3 926
sahilmgandhi 18:6a4db94011d3 927 /**
sahilmgandhi 18:6a4db94011d3 928 * @}
sahilmgandhi 18:6a4db94011d3 929 */ /* end of group DAC_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 930
sahilmgandhi 18:6a4db94011d3 931
sahilmgandhi 18:6a4db94011d3 932 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 933 -- DMA Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 934 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 935
sahilmgandhi 18:6a4db94011d3 936 /**
sahilmgandhi 18:6a4db94011d3 937 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 938 * @{
sahilmgandhi 18:6a4db94011d3 939 */
sahilmgandhi 18:6a4db94011d3 940
sahilmgandhi 18:6a4db94011d3 941 /** DMA - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 942 typedef struct {
sahilmgandhi 18:6a4db94011d3 943 __IO uint32_t CR; /**< Control Register, offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 944 __I uint32_t ES; /**< Error Status Register, offset: 0x4 */
sahilmgandhi 18:6a4db94011d3 945 uint8_t RESERVED_0[4];
sahilmgandhi 18:6a4db94011d3 946 __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
sahilmgandhi 18:6a4db94011d3 947 uint8_t RESERVED_1[4];
sahilmgandhi 18:6a4db94011d3 948 __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 949 __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 950 __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
sahilmgandhi 18:6a4db94011d3 951 __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
sahilmgandhi 18:6a4db94011d3 952 __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
sahilmgandhi 18:6a4db94011d3 953 __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 954 __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
sahilmgandhi 18:6a4db94011d3 955 __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
sahilmgandhi 18:6a4db94011d3 956 __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
sahilmgandhi 18:6a4db94011d3 957 uint8_t RESERVED_2[4];
sahilmgandhi 18:6a4db94011d3 958 __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
sahilmgandhi 18:6a4db94011d3 959 uint8_t RESERVED_3[4];
sahilmgandhi 18:6a4db94011d3 960 __IO uint32_t ERR; /**< Error Register, offset: 0x2C */
sahilmgandhi 18:6a4db94011d3 961 uint8_t RESERVED_4[4];
sahilmgandhi 18:6a4db94011d3 962 __IO uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
sahilmgandhi 18:6a4db94011d3 963 uint8_t RESERVED_5[200];
sahilmgandhi 18:6a4db94011d3 964 __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
sahilmgandhi 18:6a4db94011d3 965 __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
sahilmgandhi 18:6a4db94011d3 966 __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
sahilmgandhi 18:6a4db94011d3 967 __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
sahilmgandhi 18:6a4db94011d3 968 uint8_t RESERVED_6[3836];
sahilmgandhi 18:6a4db94011d3 969 struct { /* offset: 0x1000, array step: 0x20 */
sahilmgandhi 18:6a4db94011d3 970 __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
sahilmgandhi 18:6a4db94011d3 971 __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
sahilmgandhi 18:6a4db94011d3 972 __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
sahilmgandhi 18:6a4db94011d3 973 union { /* offset: 0x1008, array step: 0x20 */
sahilmgandhi 18:6a4db94011d3 974 __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */
sahilmgandhi 18:6a4db94011d3 975 __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
sahilmgandhi 18:6a4db94011d3 976 __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */
sahilmgandhi 18:6a4db94011d3 977 };
sahilmgandhi 18:6a4db94011d3 978 __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
sahilmgandhi 18:6a4db94011d3 979 __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
sahilmgandhi 18:6a4db94011d3 980 __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
sahilmgandhi 18:6a4db94011d3 981 union { /* offset: 0x1016, array step: 0x20 */
sahilmgandhi 18:6a4db94011d3 982 __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
sahilmgandhi 18:6a4db94011d3 983 __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
sahilmgandhi 18:6a4db94011d3 984 };
sahilmgandhi 18:6a4db94011d3 985 __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
sahilmgandhi 18:6a4db94011d3 986 __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
sahilmgandhi 18:6a4db94011d3 987 union { /* offset: 0x101E, array step: 0x20 */
sahilmgandhi 18:6a4db94011d3 988 __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
sahilmgandhi 18:6a4db94011d3 989 __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
sahilmgandhi 18:6a4db94011d3 990 };
sahilmgandhi 18:6a4db94011d3 991 } TCD[4];
sahilmgandhi 18:6a4db94011d3 992 } DMA_Type;
sahilmgandhi 18:6a4db94011d3 993
sahilmgandhi 18:6a4db94011d3 994 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 995 -- DMA Register Masks
sahilmgandhi 18:6a4db94011d3 996 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 997
sahilmgandhi 18:6a4db94011d3 998 /**
sahilmgandhi 18:6a4db94011d3 999 * @addtogroup DMA_Register_Masks DMA Register Masks
sahilmgandhi 18:6a4db94011d3 1000 * @{
sahilmgandhi 18:6a4db94011d3 1001 */
sahilmgandhi 18:6a4db94011d3 1002
sahilmgandhi 18:6a4db94011d3 1003 /* CR Bit Fields */
sahilmgandhi 18:6a4db94011d3 1004 #define DMA_CR_EDBG_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 1005 #define DMA_CR_EDBG_SHIFT 1
sahilmgandhi 18:6a4db94011d3 1006 #define DMA_CR_ERCA_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 1007 #define DMA_CR_ERCA_SHIFT 2
sahilmgandhi 18:6a4db94011d3 1008 #define DMA_CR_HOE_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 1009 #define DMA_CR_HOE_SHIFT 4
sahilmgandhi 18:6a4db94011d3 1010 #define DMA_CR_HALT_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 1011 #define DMA_CR_HALT_SHIFT 5
sahilmgandhi 18:6a4db94011d3 1012 #define DMA_CR_CLM_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 1013 #define DMA_CR_CLM_SHIFT 6
sahilmgandhi 18:6a4db94011d3 1014 #define DMA_CR_EMLM_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 1015 #define DMA_CR_EMLM_SHIFT 7
sahilmgandhi 18:6a4db94011d3 1016 #define DMA_CR_ECX_MASK 0x10000u
sahilmgandhi 18:6a4db94011d3 1017 #define DMA_CR_ECX_SHIFT 16
sahilmgandhi 18:6a4db94011d3 1018 #define DMA_CR_CX_MASK 0x20000u
sahilmgandhi 18:6a4db94011d3 1019 #define DMA_CR_CX_SHIFT 17
sahilmgandhi 18:6a4db94011d3 1020 /* ES Bit Fields */
sahilmgandhi 18:6a4db94011d3 1021 #define DMA_ES_DBE_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 1022 #define DMA_ES_DBE_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1023 #define DMA_ES_SBE_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 1024 #define DMA_ES_SBE_SHIFT 1
sahilmgandhi 18:6a4db94011d3 1025 #define DMA_ES_SGE_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 1026 #define DMA_ES_SGE_SHIFT 2
sahilmgandhi 18:6a4db94011d3 1027 #define DMA_ES_NCE_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 1028 #define DMA_ES_NCE_SHIFT 3
sahilmgandhi 18:6a4db94011d3 1029 #define DMA_ES_DOE_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 1030 #define DMA_ES_DOE_SHIFT 4
sahilmgandhi 18:6a4db94011d3 1031 #define DMA_ES_DAE_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 1032 #define DMA_ES_DAE_SHIFT 5
sahilmgandhi 18:6a4db94011d3 1033 #define DMA_ES_SOE_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 1034 #define DMA_ES_SOE_SHIFT 6
sahilmgandhi 18:6a4db94011d3 1035 #define DMA_ES_SAE_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 1036 #define DMA_ES_SAE_SHIFT 7
sahilmgandhi 18:6a4db94011d3 1037 #define DMA_ES_ERRCHN_MASK 0xF00u
sahilmgandhi 18:6a4db94011d3 1038 #define DMA_ES_ERRCHN_SHIFT 8
sahilmgandhi 18:6a4db94011d3 1039 #define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)
sahilmgandhi 18:6a4db94011d3 1040 #define DMA_ES_CPE_MASK 0x4000u
sahilmgandhi 18:6a4db94011d3 1041 #define DMA_ES_CPE_SHIFT 14
sahilmgandhi 18:6a4db94011d3 1042 #define DMA_ES_ECX_MASK 0x10000u
sahilmgandhi 18:6a4db94011d3 1043 #define DMA_ES_ECX_SHIFT 16
sahilmgandhi 18:6a4db94011d3 1044 #define DMA_ES_VLD_MASK 0x80000000u
sahilmgandhi 18:6a4db94011d3 1045 #define DMA_ES_VLD_SHIFT 31
sahilmgandhi 18:6a4db94011d3 1046 /* ERQ Bit Fields */
sahilmgandhi 18:6a4db94011d3 1047 #define DMA_ERQ_ERQ0_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 1048 #define DMA_ERQ_ERQ0_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1049 #define DMA_ERQ_ERQ1_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 1050 #define DMA_ERQ_ERQ1_SHIFT 1
sahilmgandhi 18:6a4db94011d3 1051 #define DMA_ERQ_ERQ2_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 1052 #define DMA_ERQ_ERQ2_SHIFT 2
sahilmgandhi 18:6a4db94011d3 1053 #define DMA_ERQ_ERQ3_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 1054 #define DMA_ERQ_ERQ3_SHIFT 3
sahilmgandhi 18:6a4db94011d3 1055 /* EEI Bit Fields */
sahilmgandhi 18:6a4db94011d3 1056 #define DMA_EEI_EEI0_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 1057 #define DMA_EEI_EEI0_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1058 #define DMA_EEI_EEI1_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 1059 #define DMA_EEI_EEI1_SHIFT 1
sahilmgandhi 18:6a4db94011d3 1060 #define DMA_EEI_EEI2_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 1061 #define DMA_EEI_EEI2_SHIFT 2
sahilmgandhi 18:6a4db94011d3 1062 #define DMA_EEI_EEI3_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 1063 #define DMA_EEI_EEI3_SHIFT 3
sahilmgandhi 18:6a4db94011d3 1064 /* CEEI Bit Fields */
sahilmgandhi 18:6a4db94011d3 1065 #define DMA_CEEI_CEEI_MASK 0xFu
sahilmgandhi 18:6a4db94011d3 1066 #define DMA_CEEI_CEEI_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1067 #define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)
sahilmgandhi 18:6a4db94011d3 1068 #define DMA_CEEI_CAEE_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 1069 #define DMA_CEEI_CAEE_SHIFT 6
sahilmgandhi 18:6a4db94011d3 1070 #define DMA_CEEI_NOP_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 1071 #define DMA_CEEI_NOP_SHIFT 7
sahilmgandhi 18:6a4db94011d3 1072 /* SEEI Bit Fields */
sahilmgandhi 18:6a4db94011d3 1073 #define DMA_SEEI_SEEI_MASK 0xFu
sahilmgandhi 18:6a4db94011d3 1074 #define DMA_SEEI_SEEI_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1075 #define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)
sahilmgandhi 18:6a4db94011d3 1076 #define DMA_SEEI_SAEE_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 1077 #define DMA_SEEI_SAEE_SHIFT 6
sahilmgandhi 18:6a4db94011d3 1078 #define DMA_SEEI_NOP_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 1079 #define DMA_SEEI_NOP_SHIFT 7
sahilmgandhi 18:6a4db94011d3 1080 /* CERQ Bit Fields */
sahilmgandhi 18:6a4db94011d3 1081 #define DMA_CERQ_CERQ_MASK 0xFu
sahilmgandhi 18:6a4db94011d3 1082 #define DMA_CERQ_CERQ_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1083 #define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)
sahilmgandhi 18:6a4db94011d3 1084 #define DMA_CERQ_CAER_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 1085 #define DMA_CERQ_CAER_SHIFT 6
sahilmgandhi 18:6a4db94011d3 1086 #define DMA_CERQ_NOP_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 1087 #define DMA_CERQ_NOP_SHIFT 7
sahilmgandhi 18:6a4db94011d3 1088 /* SERQ Bit Fields */
sahilmgandhi 18:6a4db94011d3 1089 #define DMA_SERQ_SERQ_MASK 0xFu
sahilmgandhi 18:6a4db94011d3 1090 #define DMA_SERQ_SERQ_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1091 #define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)
sahilmgandhi 18:6a4db94011d3 1092 #define DMA_SERQ_SAER_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 1093 #define DMA_SERQ_SAER_SHIFT 6
sahilmgandhi 18:6a4db94011d3 1094 #define DMA_SERQ_NOP_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 1095 #define DMA_SERQ_NOP_SHIFT 7
sahilmgandhi 18:6a4db94011d3 1096 /* CDNE Bit Fields */
sahilmgandhi 18:6a4db94011d3 1097 #define DMA_CDNE_CDNE_MASK 0xFu
sahilmgandhi 18:6a4db94011d3 1098 #define DMA_CDNE_CDNE_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1099 #define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)
sahilmgandhi 18:6a4db94011d3 1100 #define DMA_CDNE_CADN_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 1101 #define DMA_CDNE_CADN_SHIFT 6
sahilmgandhi 18:6a4db94011d3 1102 #define DMA_CDNE_NOP_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 1103 #define DMA_CDNE_NOP_SHIFT 7
sahilmgandhi 18:6a4db94011d3 1104 /* SSRT Bit Fields */
sahilmgandhi 18:6a4db94011d3 1105 #define DMA_SSRT_SSRT_MASK 0xFu
sahilmgandhi 18:6a4db94011d3 1106 #define DMA_SSRT_SSRT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1107 #define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)
sahilmgandhi 18:6a4db94011d3 1108 #define DMA_SSRT_SAST_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 1109 #define DMA_SSRT_SAST_SHIFT 6
sahilmgandhi 18:6a4db94011d3 1110 #define DMA_SSRT_NOP_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 1111 #define DMA_SSRT_NOP_SHIFT 7
sahilmgandhi 18:6a4db94011d3 1112 /* CERR Bit Fields */
sahilmgandhi 18:6a4db94011d3 1113 #define DMA_CERR_CERR_MASK 0xFu
sahilmgandhi 18:6a4db94011d3 1114 #define DMA_CERR_CERR_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1115 #define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)
sahilmgandhi 18:6a4db94011d3 1116 #define DMA_CERR_CAEI_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 1117 #define DMA_CERR_CAEI_SHIFT 6
sahilmgandhi 18:6a4db94011d3 1118 #define DMA_CERR_NOP_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 1119 #define DMA_CERR_NOP_SHIFT 7
sahilmgandhi 18:6a4db94011d3 1120 /* CINT Bit Fields */
sahilmgandhi 18:6a4db94011d3 1121 #define DMA_CINT_CINT_MASK 0xFu
sahilmgandhi 18:6a4db94011d3 1122 #define DMA_CINT_CINT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1123 #define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)
sahilmgandhi 18:6a4db94011d3 1124 #define DMA_CINT_CAIR_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 1125 #define DMA_CINT_CAIR_SHIFT 6
sahilmgandhi 18:6a4db94011d3 1126 #define DMA_CINT_NOP_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 1127 #define DMA_CINT_NOP_SHIFT 7
sahilmgandhi 18:6a4db94011d3 1128 /* INT Bit Fields */
sahilmgandhi 18:6a4db94011d3 1129 #define DMA_INT_INT0_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 1130 #define DMA_INT_INT0_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1131 #define DMA_INT_INT1_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 1132 #define DMA_INT_INT1_SHIFT 1
sahilmgandhi 18:6a4db94011d3 1133 #define DMA_INT_INT2_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 1134 #define DMA_INT_INT2_SHIFT 2
sahilmgandhi 18:6a4db94011d3 1135 #define DMA_INT_INT3_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 1136 #define DMA_INT_INT3_SHIFT 3
sahilmgandhi 18:6a4db94011d3 1137 /* ERR Bit Fields */
sahilmgandhi 18:6a4db94011d3 1138 #define DMA_ERR_ERR0_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 1139 #define DMA_ERR_ERR0_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1140 #define DMA_ERR_ERR1_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 1141 #define DMA_ERR_ERR1_SHIFT 1
sahilmgandhi 18:6a4db94011d3 1142 #define DMA_ERR_ERR2_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 1143 #define DMA_ERR_ERR2_SHIFT 2
sahilmgandhi 18:6a4db94011d3 1144 #define DMA_ERR_ERR3_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 1145 #define DMA_ERR_ERR3_SHIFT 3
sahilmgandhi 18:6a4db94011d3 1146 /* HRS Bit Fields */
sahilmgandhi 18:6a4db94011d3 1147 #define DMA_HRS_HRS0_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 1148 #define DMA_HRS_HRS0_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1149 #define DMA_HRS_HRS1_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 1150 #define DMA_HRS_HRS1_SHIFT 1
sahilmgandhi 18:6a4db94011d3 1151 #define DMA_HRS_HRS2_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 1152 #define DMA_HRS_HRS2_SHIFT 2
sahilmgandhi 18:6a4db94011d3 1153 #define DMA_HRS_HRS3_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 1154 #define DMA_HRS_HRS3_SHIFT 3
sahilmgandhi 18:6a4db94011d3 1155 /* DCHPRI3 Bit Fields */
sahilmgandhi 18:6a4db94011d3 1156 #define DMA_DCHPRI3_CHPRI_MASK 0xFu
sahilmgandhi 18:6a4db94011d3 1157 #define DMA_DCHPRI3_CHPRI_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1158 #define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK)
sahilmgandhi 18:6a4db94011d3 1159 #define DMA_DCHPRI3_DPA_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 1160 #define DMA_DCHPRI3_DPA_SHIFT 6
sahilmgandhi 18:6a4db94011d3 1161 #define DMA_DCHPRI3_ECP_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 1162 #define DMA_DCHPRI3_ECP_SHIFT 7
sahilmgandhi 18:6a4db94011d3 1163 /* DCHPRI2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 1164 #define DMA_DCHPRI2_CHPRI_MASK 0xFu
sahilmgandhi 18:6a4db94011d3 1165 #define DMA_DCHPRI2_CHPRI_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1166 #define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK)
sahilmgandhi 18:6a4db94011d3 1167 #define DMA_DCHPRI2_DPA_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 1168 #define DMA_DCHPRI2_DPA_SHIFT 6
sahilmgandhi 18:6a4db94011d3 1169 #define DMA_DCHPRI2_ECP_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 1170 #define DMA_DCHPRI2_ECP_SHIFT 7
sahilmgandhi 18:6a4db94011d3 1171 /* DCHPRI1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 1172 #define DMA_DCHPRI1_CHPRI_MASK 0xFu
sahilmgandhi 18:6a4db94011d3 1173 #define DMA_DCHPRI1_CHPRI_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1174 #define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK)
sahilmgandhi 18:6a4db94011d3 1175 #define DMA_DCHPRI1_DPA_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 1176 #define DMA_DCHPRI1_DPA_SHIFT 6
sahilmgandhi 18:6a4db94011d3 1177 #define DMA_DCHPRI1_ECP_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 1178 #define DMA_DCHPRI1_ECP_SHIFT 7
sahilmgandhi 18:6a4db94011d3 1179 /* DCHPRI0 Bit Fields */
sahilmgandhi 18:6a4db94011d3 1180 #define DMA_DCHPRI0_CHPRI_MASK 0xFu
sahilmgandhi 18:6a4db94011d3 1181 #define DMA_DCHPRI0_CHPRI_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1182 #define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK)
sahilmgandhi 18:6a4db94011d3 1183 #define DMA_DCHPRI0_DPA_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 1184 #define DMA_DCHPRI0_DPA_SHIFT 6
sahilmgandhi 18:6a4db94011d3 1185 #define DMA_DCHPRI0_ECP_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 1186 #define DMA_DCHPRI0_ECP_SHIFT 7
sahilmgandhi 18:6a4db94011d3 1187 /* SADDR Bit Fields */
sahilmgandhi 18:6a4db94011d3 1188 #define DMA_SADDR_SADDR_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 1189 #define DMA_SADDR_SADDR_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1190 #define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK)
sahilmgandhi 18:6a4db94011d3 1191 /* SOFF Bit Fields */
sahilmgandhi 18:6a4db94011d3 1192 #define DMA_SOFF_SOFF_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 1193 #define DMA_SOFF_SOFF_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1194 #define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK)
sahilmgandhi 18:6a4db94011d3 1195 /* ATTR Bit Fields */
sahilmgandhi 18:6a4db94011d3 1196 #define DMA_ATTR_DSIZE_MASK 0x7u
sahilmgandhi 18:6a4db94011d3 1197 #define DMA_ATTR_DSIZE_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1198 #define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK)
sahilmgandhi 18:6a4db94011d3 1199 #define DMA_ATTR_DMOD_MASK 0xF8u
sahilmgandhi 18:6a4db94011d3 1200 #define DMA_ATTR_DMOD_SHIFT 3
sahilmgandhi 18:6a4db94011d3 1201 #define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK)
sahilmgandhi 18:6a4db94011d3 1202 #define DMA_ATTR_SSIZE_MASK 0x700u
sahilmgandhi 18:6a4db94011d3 1203 #define DMA_ATTR_SSIZE_SHIFT 8
sahilmgandhi 18:6a4db94011d3 1204 #define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK)
sahilmgandhi 18:6a4db94011d3 1205 #define DMA_ATTR_SMOD_MASK 0xF800u
sahilmgandhi 18:6a4db94011d3 1206 #define DMA_ATTR_SMOD_SHIFT 11
sahilmgandhi 18:6a4db94011d3 1207 #define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK)
sahilmgandhi 18:6a4db94011d3 1208 /* NBYTES_MLNO Bit Fields */
sahilmgandhi 18:6a4db94011d3 1209 #define DMA_NBYTES_MLNO_NBYTES_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 1210 #define DMA_NBYTES_MLNO_NBYTES_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1211 #define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK)
sahilmgandhi 18:6a4db94011d3 1212 /* NBYTES_MLOFFNO Bit Fields */
sahilmgandhi 18:6a4db94011d3 1213 #define DMA_NBYTES_MLOFFNO_NBYTES_MASK 0x3FFFFFFFu
sahilmgandhi 18:6a4db94011d3 1214 #define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1215 #define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK)
sahilmgandhi 18:6a4db94011d3 1216 #define DMA_NBYTES_MLOFFNO_DMLOE_MASK 0x40000000u
sahilmgandhi 18:6a4db94011d3 1217 #define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT 30
sahilmgandhi 18:6a4db94011d3 1218 #define DMA_NBYTES_MLOFFNO_SMLOE_MASK 0x80000000u
sahilmgandhi 18:6a4db94011d3 1219 #define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT 31
sahilmgandhi 18:6a4db94011d3 1220 /* NBYTES_MLOFFYES Bit Fields */
sahilmgandhi 18:6a4db94011d3 1221 #define DMA_NBYTES_MLOFFYES_NBYTES_MASK 0x3FFu
sahilmgandhi 18:6a4db94011d3 1222 #define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1223 #define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK)
sahilmgandhi 18:6a4db94011d3 1224 #define DMA_NBYTES_MLOFFYES_MLOFF_MASK 0x3FFFFC00u
sahilmgandhi 18:6a4db94011d3 1225 #define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT 10
sahilmgandhi 18:6a4db94011d3 1226 #define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK)
sahilmgandhi 18:6a4db94011d3 1227 #define DMA_NBYTES_MLOFFYES_DMLOE_MASK 0x40000000u
sahilmgandhi 18:6a4db94011d3 1228 #define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT 30
sahilmgandhi 18:6a4db94011d3 1229 #define DMA_NBYTES_MLOFFYES_SMLOE_MASK 0x80000000u
sahilmgandhi 18:6a4db94011d3 1230 #define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT 31
sahilmgandhi 18:6a4db94011d3 1231 /* SLAST Bit Fields */
sahilmgandhi 18:6a4db94011d3 1232 #define DMA_SLAST_SLAST_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 1233 #define DMA_SLAST_SLAST_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1234 #define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK)
sahilmgandhi 18:6a4db94011d3 1235 /* DADDR Bit Fields */
sahilmgandhi 18:6a4db94011d3 1236 #define DMA_DADDR_DADDR_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 1237 #define DMA_DADDR_DADDR_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1238 #define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK)
sahilmgandhi 18:6a4db94011d3 1239 /* DOFF Bit Fields */
sahilmgandhi 18:6a4db94011d3 1240 #define DMA_DOFF_DOFF_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 1241 #define DMA_DOFF_DOFF_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1242 #define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK)
sahilmgandhi 18:6a4db94011d3 1243 /* CITER_ELINKNO Bit Fields */
sahilmgandhi 18:6a4db94011d3 1244 #define DMA_CITER_ELINKNO_CITER_MASK 0x7FFFu
sahilmgandhi 18:6a4db94011d3 1245 #define DMA_CITER_ELINKNO_CITER_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1246 #define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK)
sahilmgandhi 18:6a4db94011d3 1247 #define DMA_CITER_ELINKNO_ELINK_MASK 0x8000u
sahilmgandhi 18:6a4db94011d3 1248 #define DMA_CITER_ELINKNO_ELINK_SHIFT 15
sahilmgandhi 18:6a4db94011d3 1249 /* CITER_ELINKYES Bit Fields */
sahilmgandhi 18:6a4db94011d3 1250 #define DMA_CITER_ELINKYES_CITER_MASK 0x1FFu
sahilmgandhi 18:6a4db94011d3 1251 #define DMA_CITER_ELINKYES_CITER_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1252 #define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK)
sahilmgandhi 18:6a4db94011d3 1253 #define DMA_CITER_ELINKYES_LINKCH_MASK 0x1E00u
sahilmgandhi 18:6a4db94011d3 1254 #define DMA_CITER_ELINKYES_LINKCH_SHIFT 9
sahilmgandhi 18:6a4db94011d3 1255 #define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK)
sahilmgandhi 18:6a4db94011d3 1256 #define DMA_CITER_ELINKYES_ELINK_MASK 0x8000u
sahilmgandhi 18:6a4db94011d3 1257 #define DMA_CITER_ELINKYES_ELINK_SHIFT 15
sahilmgandhi 18:6a4db94011d3 1258 /* DLAST_SGA Bit Fields */
sahilmgandhi 18:6a4db94011d3 1259 #define DMA_DLAST_SGA_DLASTSGA_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 1260 #define DMA_DLAST_SGA_DLASTSGA_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1261 #define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK)
sahilmgandhi 18:6a4db94011d3 1262 /* CSR Bit Fields */
sahilmgandhi 18:6a4db94011d3 1263 #define DMA_CSR_START_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 1264 #define DMA_CSR_START_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1265 #define DMA_CSR_INTMAJOR_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 1266 #define DMA_CSR_INTMAJOR_SHIFT 1
sahilmgandhi 18:6a4db94011d3 1267 #define DMA_CSR_INTHALF_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 1268 #define DMA_CSR_INTHALF_SHIFT 2
sahilmgandhi 18:6a4db94011d3 1269 #define DMA_CSR_DREQ_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 1270 #define DMA_CSR_DREQ_SHIFT 3
sahilmgandhi 18:6a4db94011d3 1271 #define DMA_CSR_ESG_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 1272 #define DMA_CSR_ESG_SHIFT 4
sahilmgandhi 18:6a4db94011d3 1273 #define DMA_CSR_MAJORELINK_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 1274 #define DMA_CSR_MAJORELINK_SHIFT 5
sahilmgandhi 18:6a4db94011d3 1275 #define DMA_CSR_ACTIVE_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 1276 #define DMA_CSR_ACTIVE_SHIFT 6
sahilmgandhi 18:6a4db94011d3 1277 #define DMA_CSR_DONE_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 1278 #define DMA_CSR_DONE_SHIFT 7
sahilmgandhi 18:6a4db94011d3 1279 #define DMA_CSR_MAJORLINKCH_MASK 0xF00u
sahilmgandhi 18:6a4db94011d3 1280 #define DMA_CSR_MAJORLINKCH_SHIFT 8
sahilmgandhi 18:6a4db94011d3 1281 #define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK)
sahilmgandhi 18:6a4db94011d3 1282 #define DMA_CSR_BWC_MASK 0xC000u
sahilmgandhi 18:6a4db94011d3 1283 #define DMA_CSR_BWC_SHIFT 14
sahilmgandhi 18:6a4db94011d3 1284 #define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK)
sahilmgandhi 18:6a4db94011d3 1285 /* BITER_ELINKNO Bit Fields */
sahilmgandhi 18:6a4db94011d3 1286 #define DMA_BITER_ELINKNO_BITER_MASK 0x7FFFu
sahilmgandhi 18:6a4db94011d3 1287 #define DMA_BITER_ELINKNO_BITER_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1288 #define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK)
sahilmgandhi 18:6a4db94011d3 1289 #define DMA_BITER_ELINKNO_ELINK_MASK 0x8000u
sahilmgandhi 18:6a4db94011d3 1290 #define DMA_BITER_ELINKNO_ELINK_SHIFT 15
sahilmgandhi 18:6a4db94011d3 1291 /* BITER_ELINKYES Bit Fields */
sahilmgandhi 18:6a4db94011d3 1292 #define DMA_BITER_ELINKYES_BITER_MASK 0x1FFu
sahilmgandhi 18:6a4db94011d3 1293 #define DMA_BITER_ELINKYES_BITER_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1294 #define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK)
sahilmgandhi 18:6a4db94011d3 1295 #define DMA_BITER_ELINKYES_LINKCH_MASK 0x1E00u
sahilmgandhi 18:6a4db94011d3 1296 #define DMA_BITER_ELINKYES_LINKCH_SHIFT 9
sahilmgandhi 18:6a4db94011d3 1297 #define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK)
sahilmgandhi 18:6a4db94011d3 1298 #define DMA_BITER_ELINKYES_ELINK_MASK 0x8000u
sahilmgandhi 18:6a4db94011d3 1299 #define DMA_BITER_ELINKYES_ELINK_SHIFT 15
sahilmgandhi 18:6a4db94011d3 1300
sahilmgandhi 18:6a4db94011d3 1301 /**
sahilmgandhi 18:6a4db94011d3 1302 * @}
sahilmgandhi 18:6a4db94011d3 1303 */ /* end of group DMA_Register_Masks */
sahilmgandhi 18:6a4db94011d3 1304
sahilmgandhi 18:6a4db94011d3 1305
sahilmgandhi 18:6a4db94011d3 1306 /* DMA - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 1307 /** Peripheral DMA base address */
sahilmgandhi 18:6a4db94011d3 1308 #define DMA_BASE (0x40008000u)
sahilmgandhi 18:6a4db94011d3 1309 /** Peripheral DMA base pointer */
sahilmgandhi 18:6a4db94011d3 1310 #define DMA0 ((DMA_Type *)DMA_BASE)
sahilmgandhi 18:6a4db94011d3 1311
sahilmgandhi 18:6a4db94011d3 1312 /**
sahilmgandhi 18:6a4db94011d3 1313 * @}
sahilmgandhi 18:6a4db94011d3 1314 */ /* end of group DMA_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 1315
sahilmgandhi 18:6a4db94011d3 1316
sahilmgandhi 18:6a4db94011d3 1317 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1318 -- DMAMUX Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 1319 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 1320
sahilmgandhi 18:6a4db94011d3 1321 /**
sahilmgandhi 18:6a4db94011d3 1322 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 1323 * @{
sahilmgandhi 18:6a4db94011d3 1324 */
sahilmgandhi 18:6a4db94011d3 1325
sahilmgandhi 18:6a4db94011d3 1326 /** DMAMUX - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 1327 typedef struct {
sahilmgandhi 18:6a4db94011d3 1328 __IO uint8_t CHCFG[16]; /**< Channel Configuration Register, array offset: 0x0, array step: 0x1 */
sahilmgandhi 18:6a4db94011d3 1329 } DMAMUX_Type;
sahilmgandhi 18:6a4db94011d3 1330
sahilmgandhi 18:6a4db94011d3 1331 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1332 -- DMAMUX Register Masks
sahilmgandhi 18:6a4db94011d3 1333 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 1334
sahilmgandhi 18:6a4db94011d3 1335 /**
sahilmgandhi 18:6a4db94011d3 1336 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
sahilmgandhi 18:6a4db94011d3 1337 * @{
sahilmgandhi 18:6a4db94011d3 1338 */
sahilmgandhi 18:6a4db94011d3 1339
sahilmgandhi 18:6a4db94011d3 1340 /* CHCFG Bit Fields */
sahilmgandhi 18:6a4db94011d3 1341 #define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
sahilmgandhi 18:6a4db94011d3 1342 #define DMAMUX_CHCFG_SOURCE_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1343 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
sahilmgandhi 18:6a4db94011d3 1344 #define DMAMUX_CHCFG_TRIG_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 1345 #define DMAMUX_CHCFG_TRIG_SHIFT 6
sahilmgandhi 18:6a4db94011d3 1346 #define DMAMUX_CHCFG_ENBL_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 1347 #define DMAMUX_CHCFG_ENBL_SHIFT 7
sahilmgandhi 18:6a4db94011d3 1348
sahilmgandhi 18:6a4db94011d3 1349 /**
sahilmgandhi 18:6a4db94011d3 1350 * @}
sahilmgandhi 18:6a4db94011d3 1351 */ /* end of group DMAMUX_Register_Masks */
sahilmgandhi 18:6a4db94011d3 1352
sahilmgandhi 18:6a4db94011d3 1353
sahilmgandhi 18:6a4db94011d3 1354 /* DMAMUX - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 1355 /** Peripheral DMAMUX base address */
sahilmgandhi 18:6a4db94011d3 1356 #define DMAMUX_BASE (0x40021000u)
sahilmgandhi 18:6a4db94011d3 1357 /** Peripheral DMAMUX base pointer */
sahilmgandhi 18:6a4db94011d3 1358 #define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
sahilmgandhi 18:6a4db94011d3 1359
sahilmgandhi 18:6a4db94011d3 1360 /**
sahilmgandhi 18:6a4db94011d3 1361 * @}
sahilmgandhi 18:6a4db94011d3 1362 */ /* end of group DMAMUX_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 1363
sahilmgandhi 18:6a4db94011d3 1364
sahilmgandhi 18:6a4db94011d3 1365 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1366 -- EWM Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 1367 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 1368
sahilmgandhi 18:6a4db94011d3 1369 /**
sahilmgandhi 18:6a4db94011d3 1370 * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 1371 * @{
sahilmgandhi 18:6a4db94011d3 1372 */
sahilmgandhi 18:6a4db94011d3 1373
sahilmgandhi 18:6a4db94011d3 1374 /** EWM - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 1375 typedef struct {
sahilmgandhi 18:6a4db94011d3 1376 __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 1377 __O uint8_t SERV; /**< Service Register, offset: 0x1 */
sahilmgandhi 18:6a4db94011d3 1378 __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */
sahilmgandhi 18:6a4db94011d3 1379 __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
sahilmgandhi 18:6a4db94011d3 1380 } EWM_Type;
sahilmgandhi 18:6a4db94011d3 1381
sahilmgandhi 18:6a4db94011d3 1382 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1383 -- EWM Register Masks
sahilmgandhi 18:6a4db94011d3 1384 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 1385
sahilmgandhi 18:6a4db94011d3 1386 /**
sahilmgandhi 18:6a4db94011d3 1387 * @addtogroup EWM_Register_Masks EWM Register Masks
sahilmgandhi 18:6a4db94011d3 1388 * @{
sahilmgandhi 18:6a4db94011d3 1389 */
sahilmgandhi 18:6a4db94011d3 1390
sahilmgandhi 18:6a4db94011d3 1391 /* CTRL Bit Fields */
sahilmgandhi 18:6a4db94011d3 1392 #define EWM_CTRL_EWMEN_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 1393 #define EWM_CTRL_EWMEN_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1394 #define EWM_CTRL_ASSIN_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 1395 #define EWM_CTRL_ASSIN_SHIFT 1
sahilmgandhi 18:6a4db94011d3 1396 #define EWM_CTRL_INEN_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 1397 #define EWM_CTRL_INEN_SHIFT 2
sahilmgandhi 18:6a4db94011d3 1398 #define EWM_CTRL_INTEN_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 1399 #define EWM_CTRL_INTEN_SHIFT 3
sahilmgandhi 18:6a4db94011d3 1400 /* SERV Bit Fields */
sahilmgandhi 18:6a4db94011d3 1401 #define EWM_SERV_SERVICE_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 1402 #define EWM_SERV_SERVICE_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1403 #define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK)
sahilmgandhi 18:6a4db94011d3 1404 /* CMPL Bit Fields */
sahilmgandhi 18:6a4db94011d3 1405 #define EWM_CMPL_COMPAREL_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 1406 #define EWM_CMPL_COMPAREL_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1407 #define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK)
sahilmgandhi 18:6a4db94011d3 1408 /* CMPH Bit Fields */
sahilmgandhi 18:6a4db94011d3 1409 #define EWM_CMPH_COMPAREH_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 1410 #define EWM_CMPH_COMPAREH_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1411 #define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK)
sahilmgandhi 18:6a4db94011d3 1412
sahilmgandhi 18:6a4db94011d3 1413 /**
sahilmgandhi 18:6a4db94011d3 1414 * @}
sahilmgandhi 18:6a4db94011d3 1415 */ /* end of group EWM_Register_Masks */
sahilmgandhi 18:6a4db94011d3 1416
sahilmgandhi 18:6a4db94011d3 1417
sahilmgandhi 18:6a4db94011d3 1418 /* EWM - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 1419 /** Peripheral EWM base address */
sahilmgandhi 18:6a4db94011d3 1420 #define EWM_BASE (0x40061000u)
sahilmgandhi 18:6a4db94011d3 1421 /** Peripheral EWM base pointer */
sahilmgandhi 18:6a4db94011d3 1422 #define EWM ((EWM_Type *)EWM_BASE)
sahilmgandhi 18:6a4db94011d3 1423
sahilmgandhi 18:6a4db94011d3 1424 /**
sahilmgandhi 18:6a4db94011d3 1425 * @}
sahilmgandhi 18:6a4db94011d3 1426 */ /* end of group EWM_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 1427
sahilmgandhi 18:6a4db94011d3 1428
sahilmgandhi 18:6a4db94011d3 1429 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1430 -- FMC Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 1431 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 1432
sahilmgandhi 18:6a4db94011d3 1433 /**
sahilmgandhi 18:6a4db94011d3 1434 * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 1435 * @{
sahilmgandhi 18:6a4db94011d3 1436 */
sahilmgandhi 18:6a4db94011d3 1437
sahilmgandhi 18:6a4db94011d3 1438 /** FMC - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 1439 typedef struct {
sahilmgandhi 18:6a4db94011d3 1440 __IO uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 1441 __IO uint32_t PFB0CR; /**< Flash Control Register, offset: 0x4 */
sahilmgandhi 18:6a4db94011d3 1442 uint8_t RESERVED_0[248];
sahilmgandhi 18:6a4db94011d3 1443 struct { /* offset: 0x100, array step: 0x20 */
sahilmgandhi 18:6a4db94011d3 1444 __IO uint32_t TAGVD[2]; /**< Cache Tag Storage, array offset: 0x100, array step: index*0x20, index2*0x4 */
sahilmgandhi 18:6a4db94011d3 1445 uint8_t RESERVED_0[24];
sahilmgandhi 18:6a4db94011d3 1446 } TAG_WAY[4];
sahilmgandhi 18:6a4db94011d3 1447 uint8_t RESERVED_1[132];
sahilmgandhi 18:6a4db94011d3 1448 struct { /* offset: 0x204, array step: 0x8 */
sahilmgandhi 18:6a4db94011d3 1449 __IO uint32_t DATAW0S; /**< Cache Data Storage, array offset: 0x204, array step: 0x8 */
sahilmgandhi 18:6a4db94011d3 1450 uint8_t RESERVED_0[4];
sahilmgandhi 18:6a4db94011d3 1451 } DATAW0S[2];
sahilmgandhi 18:6a4db94011d3 1452 uint8_t RESERVED_2[48];
sahilmgandhi 18:6a4db94011d3 1453 struct { /* offset: 0x244, array step: 0x8 */
sahilmgandhi 18:6a4db94011d3 1454 __IO uint32_t DATAW1S; /**< Cache Data Storage, array offset: 0x244, array step: 0x8 */
sahilmgandhi 18:6a4db94011d3 1455 uint8_t RESERVED_0[4];
sahilmgandhi 18:6a4db94011d3 1456 } DATAW1S[2];
sahilmgandhi 18:6a4db94011d3 1457 uint8_t RESERVED_3[48];
sahilmgandhi 18:6a4db94011d3 1458 struct { /* offset: 0x284, array step: 0x8 */
sahilmgandhi 18:6a4db94011d3 1459 __IO uint32_t DATAW2S; /**< Cache Data Storage, array offset: 0x284, array step: 0x8 */
sahilmgandhi 18:6a4db94011d3 1460 uint8_t RESERVED_0[4];
sahilmgandhi 18:6a4db94011d3 1461 } DATAW2S[2];
sahilmgandhi 18:6a4db94011d3 1462 uint8_t RESERVED_4[48];
sahilmgandhi 18:6a4db94011d3 1463 struct { /* offset: 0x2C4, array step: 0x8 */
sahilmgandhi 18:6a4db94011d3 1464 __IO uint32_t DATAW3S; /**< Cache Data Storage, array offset: 0x2C4, array step: 0x8 */
sahilmgandhi 18:6a4db94011d3 1465 uint8_t RESERVED_0[4];
sahilmgandhi 18:6a4db94011d3 1466 } DATAW3S[2];
sahilmgandhi 18:6a4db94011d3 1467 } FMC_Type;
sahilmgandhi 18:6a4db94011d3 1468
sahilmgandhi 18:6a4db94011d3 1469 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1470 -- FMC Register Masks
sahilmgandhi 18:6a4db94011d3 1471 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 1472
sahilmgandhi 18:6a4db94011d3 1473 /**
sahilmgandhi 18:6a4db94011d3 1474 * @addtogroup FMC_Register_Masks FMC Register Masks
sahilmgandhi 18:6a4db94011d3 1475 * @{
sahilmgandhi 18:6a4db94011d3 1476 */
sahilmgandhi 18:6a4db94011d3 1477
sahilmgandhi 18:6a4db94011d3 1478 /* PFAPR Bit Fields */
sahilmgandhi 18:6a4db94011d3 1479 #define FMC_PFAPR_M0AP_MASK 0x3u
sahilmgandhi 18:6a4db94011d3 1480 #define FMC_PFAPR_M0AP_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1481 #define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0AP_SHIFT))&FMC_PFAPR_M0AP_MASK)
sahilmgandhi 18:6a4db94011d3 1482 #define FMC_PFAPR_M1AP_MASK 0xCu
sahilmgandhi 18:6a4db94011d3 1483 #define FMC_PFAPR_M1AP_SHIFT 2
sahilmgandhi 18:6a4db94011d3 1484 #define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1AP_SHIFT))&FMC_PFAPR_M1AP_MASK)
sahilmgandhi 18:6a4db94011d3 1485 #define FMC_PFAPR_M2AP_MASK 0x30u
sahilmgandhi 18:6a4db94011d3 1486 #define FMC_PFAPR_M2AP_SHIFT 4
sahilmgandhi 18:6a4db94011d3 1487 #define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2AP_SHIFT))&FMC_PFAPR_M2AP_MASK)
sahilmgandhi 18:6a4db94011d3 1488 #define FMC_PFAPR_M3AP_MASK 0xC0u
sahilmgandhi 18:6a4db94011d3 1489 #define FMC_PFAPR_M3AP_SHIFT 6
sahilmgandhi 18:6a4db94011d3 1490 #define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3AP_SHIFT))&FMC_PFAPR_M3AP_MASK)
sahilmgandhi 18:6a4db94011d3 1491 #define FMC_PFAPR_M0PFD_MASK 0x10000u
sahilmgandhi 18:6a4db94011d3 1492 #define FMC_PFAPR_M0PFD_SHIFT 16
sahilmgandhi 18:6a4db94011d3 1493 #define FMC_PFAPR_M1PFD_MASK 0x20000u
sahilmgandhi 18:6a4db94011d3 1494 #define FMC_PFAPR_M1PFD_SHIFT 17
sahilmgandhi 18:6a4db94011d3 1495 #define FMC_PFAPR_M2PFD_MASK 0x40000u
sahilmgandhi 18:6a4db94011d3 1496 #define FMC_PFAPR_M2PFD_SHIFT 18
sahilmgandhi 18:6a4db94011d3 1497 #define FMC_PFAPR_M3PFD_MASK 0x80000u
sahilmgandhi 18:6a4db94011d3 1498 #define FMC_PFAPR_M3PFD_SHIFT 19
sahilmgandhi 18:6a4db94011d3 1499 /* PFB0CR Bit Fields */
sahilmgandhi 18:6a4db94011d3 1500 #define FMC_PFB0CR_B0SEBE_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 1501 #define FMC_PFB0CR_B0SEBE_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1502 #define FMC_PFB0CR_B0IPE_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 1503 #define FMC_PFB0CR_B0IPE_SHIFT 1
sahilmgandhi 18:6a4db94011d3 1504 #define FMC_PFB0CR_B0DPE_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 1505 #define FMC_PFB0CR_B0DPE_SHIFT 2
sahilmgandhi 18:6a4db94011d3 1506 #define FMC_PFB0CR_B0ICE_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 1507 #define FMC_PFB0CR_B0ICE_SHIFT 3
sahilmgandhi 18:6a4db94011d3 1508 #define FMC_PFB0CR_B0DCE_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 1509 #define FMC_PFB0CR_B0DCE_SHIFT 4
sahilmgandhi 18:6a4db94011d3 1510 #define FMC_PFB0CR_CRC_MASK 0xE0u
sahilmgandhi 18:6a4db94011d3 1511 #define FMC_PFB0CR_CRC_SHIFT 5
sahilmgandhi 18:6a4db94011d3 1512 #define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CRC_SHIFT))&FMC_PFB0CR_CRC_MASK)
sahilmgandhi 18:6a4db94011d3 1513 #define FMC_PFB0CR_B0MW_MASK 0x60000u
sahilmgandhi 18:6a4db94011d3 1514 #define FMC_PFB0CR_B0MW_SHIFT 17
sahilmgandhi 18:6a4db94011d3 1515 #define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0MW_SHIFT))&FMC_PFB0CR_B0MW_MASK)
sahilmgandhi 18:6a4db94011d3 1516 #define FMC_PFB0CR_S_B_INV_MASK 0x80000u
sahilmgandhi 18:6a4db94011d3 1517 #define FMC_PFB0CR_S_B_INV_SHIFT 19
sahilmgandhi 18:6a4db94011d3 1518 #define FMC_PFB0CR_CINV_WAY_MASK 0xF00000u
sahilmgandhi 18:6a4db94011d3 1519 #define FMC_PFB0CR_CINV_WAY_SHIFT 20
sahilmgandhi 18:6a4db94011d3 1520 #define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CINV_WAY_SHIFT))&FMC_PFB0CR_CINV_WAY_MASK)
sahilmgandhi 18:6a4db94011d3 1521 #define FMC_PFB0CR_CLCK_WAY_MASK 0xF000000u
sahilmgandhi 18:6a4db94011d3 1522 #define FMC_PFB0CR_CLCK_WAY_SHIFT 24
sahilmgandhi 18:6a4db94011d3 1523 #define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CLCK_WAY_SHIFT))&FMC_PFB0CR_CLCK_WAY_MASK)
sahilmgandhi 18:6a4db94011d3 1524 #define FMC_PFB0CR_B0RWSC_MASK 0xF0000000u
sahilmgandhi 18:6a4db94011d3 1525 #define FMC_PFB0CR_B0RWSC_SHIFT 28
sahilmgandhi 18:6a4db94011d3 1526 #define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0RWSC_SHIFT))&FMC_PFB0CR_B0RWSC_MASK)
sahilmgandhi 18:6a4db94011d3 1527 /* TAGVD Bit Fields */
sahilmgandhi 18:6a4db94011d3 1528 #define FMC_TAGVD_valid_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 1529 #define FMC_TAGVD_valid_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1530 #define FMC_TAGVD_tag_MASK 0x7FFC0u
sahilmgandhi 18:6a4db94011d3 1531 #define FMC_TAGVD_tag_SHIFT 6
sahilmgandhi 18:6a4db94011d3 1532 #define FMC_TAGVD_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVD_tag_SHIFT))&FMC_TAGVD_tag_MASK)
sahilmgandhi 18:6a4db94011d3 1533 /* DATAW0S Bit Fields */
sahilmgandhi 18:6a4db94011d3 1534 #define FMC_DATAW0S_data_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 1535 #define FMC_DATAW0S_data_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1536 #define FMC_DATAW0S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW0S_data_SHIFT))&FMC_DATAW0S_data_MASK)
sahilmgandhi 18:6a4db94011d3 1537 /* DATAW1S Bit Fields */
sahilmgandhi 18:6a4db94011d3 1538 #define FMC_DATAW1S_data_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 1539 #define FMC_DATAW1S_data_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1540 #define FMC_DATAW1S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW1S_data_SHIFT))&FMC_DATAW1S_data_MASK)
sahilmgandhi 18:6a4db94011d3 1541 /* DATAW2S Bit Fields */
sahilmgandhi 18:6a4db94011d3 1542 #define FMC_DATAW2S_data_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 1543 #define FMC_DATAW2S_data_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1544 #define FMC_DATAW2S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW2S_data_SHIFT))&FMC_DATAW2S_data_MASK)
sahilmgandhi 18:6a4db94011d3 1545 /* DATAW3S Bit Fields */
sahilmgandhi 18:6a4db94011d3 1546 #define FMC_DATAW3S_data_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 1547 #define FMC_DATAW3S_data_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1548 #define FMC_DATAW3S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW3S_data_SHIFT))&FMC_DATAW3S_data_MASK)
sahilmgandhi 18:6a4db94011d3 1549
sahilmgandhi 18:6a4db94011d3 1550 /**
sahilmgandhi 18:6a4db94011d3 1551 * @}
sahilmgandhi 18:6a4db94011d3 1552 */ /* end of group FMC_Register_Masks */
sahilmgandhi 18:6a4db94011d3 1553
sahilmgandhi 18:6a4db94011d3 1554
sahilmgandhi 18:6a4db94011d3 1555 /* FMC - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 1556 /** Peripheral FMC base address */
sahilmgandhi 18:6a4db94011d3 1557 #define FMC_BASE (0x4001F000u)
sahilmgandhi 18:6a4db94011d3 1558 /** Peripheral FMC base pointer */
sahilmgandhi 18:6a4db94011d3 1559 #define FMC ((FMC_Type *)FMC_BASE)
sahilmgandhi 18:6a4db94011d3 1560
sahilmgandhi 18:6a4db94011d3 1561 /**
sahilmgandhi 18:6a4db94011d3 1562 * @}
sahilmgandhi 18:6a4db94011d3 1563 */ /* end of group FMC_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 1564
sahilmgandhi 18:6a4db94011d3 1565
sahilmgandhi 18:6a4db94011d3 1566 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1567 -- FTFL Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 1568 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 1569
sahilmgandhi 18:6a4db94011d3 1570 /**
sahilmgandhi 18:6a4db94011d3 1571 * @addtogroup FTFL_Peripheral_Access_Layer FTFL Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 1572 * @{
sahilmgandhi 18:6a4db94011d3 1573 */
sahilmgandhi 18:6a4db94011d3 1574
sahilmgandhi 18:6a4db94011d3 1575 /** FTFL - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 1576 typedef struct {
sahilmgandhi 18:6a4db94011d3 1577 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 1578 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
sahilmgandhi 18:6a4db94011d3 1579 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
sahilmgandhi 18:6a4db94011d3 1580 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
sahilmgandhi 18:6a4db94011d3 1581 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
sahilmgandhi 18:6a4db94011d3 1582 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
sahilmgandhi 18:6a4db94011d3 1583 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
sahilmgandhi 18:6a4db94011d3 1584 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
sahilmgandhi 18:6a4db94011d3 1585 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
sahilmgandhi 18:6a4db94011d3 1586 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
sahilmgandhi 18:6a4db94011d3 1587 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
sahilmgandhi 18:6a4db94011d3 1588 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
sahilmgandhi 18:6a4db94011d3 1589 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
sahilmgandhi 18:6a4db94011d3 1590 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
sahilmgandhi 18:6a4db94011d3 1591 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
sahilmgandhi 18:6a4db94011d3 1592 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
sahilmgandhi 18:6a4db94011d3 1593 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 1594 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
sahilmgandhi 18:6a4db94011d3 1595 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
sahilmgandhi 18:6a4db94011d3 1596 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
sahilmgandhi 18:6a4db94011d3 1597 uint8_t RESERVED_0[2];
sahilmgandhi 18:6a4db94011d3 1598 __IO uint8_t FEPROT; /**< EEPROM Protection Register, offset: 0x16 */
sahilmgandhi 18:6a4db94011d3 1599 __IO uint8_t FDPROT; /**< Data Flash Protection Register, offset: 0x17 */
sahilmgandhi 18:6a4db94011d3 1600 } FTFL_Type;
sahilmgandhi 18:6a4db94011d3 1601
sahilmgandhi 18:6a4db94011d3 1602 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1603 -- FTFL Register Masks
sahilmgandhi 18:6a4db94011d3 1604 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 1605
sahilmgandhi 18:6a4db94011d3 1606 /**
sahilmgandhi 18:6a4db94011d3 1607 * @addtogroup FTFL_Register_Masks FTFL Register Masks
sahilmgandhi 18:6a4db94011d3 1608 * @{
sahilmgandhi 18:6a4db94011d3 1609 */
sahilmgandhi 18:6a4db94011d3 1610
sahilmgandhi 18:6a4db94011d3 1611 /* FSTAT Bit Fields */
sahilmgandhi 18:6a4db94011d3 1612 #define FTFL_FSTAT_MGSTAT0_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 1613 #define FTFL_FSTAT_MGSTAT0_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1614 #define FTFL_FSTAT_FPVIOL_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 1615 #define FTFL_FSTAT_FPVIOL_SHIFT 4
sahilmgandhi 18:6a4db94011d3 1616 #define FTFL_FSTAT_ACCERR_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 1617 #define FTFL_FSTAT_ACCERR_SHIFT 5
sahilmgandhi 18:6a4db94011d3 1618 #define FTFL_FSTAT_RDCOLERR_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 1619 #define FTFL_FSTAT_RDCOLERR_SHIFT 6
sahilmgandhi 18:6a4db94011d3 1620 #define FTFL_FSTAT_CCIF_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 1621 #define FTFL_FSTAT_CCIF_SHIFT 7
sahilmgandhi 18:6a4db94011d3 1622 /* FCNFG Bit Fields */
sahilmgandhi 18:6a4db94011d3 1623 #define FTFL_FCNFG_EEERDY_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 1624 #define FTFL_FCNFG_EEERDY_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1625 #define FTFL_FCNFG_RAMRDY_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 1626 #define FTFL_FCNFG_RAMRDY_SHIFT 1
sahilmgandhi 18:6a4db94011d3 1627 #define FTFL_FCNFG_PFLSH_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 1628 #define FTFL_FCNFG_PFLSH_SHIFT 2
sahilmgandhi 18:6a4db94011d3 1629 #define FTFL_FCNFG_ERSSUSP_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 1630 #define FTFL_FCNFG_ERSSUSP_SHIFT 4
sahilmgandhi 18:6a4db94011d3 1631 #define FTFL_FCNFG_ERSAREQ_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 1632 #define FTFL_FCNFG_ERSAREQ_SHIFT 5
sahilmgandhi 18:6a4db94011d3 1633 #define FTFL_FCNFG_RDCOLLIE_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 1634 #define FTFL_FCNFG_RDCOLLIE_SHIFT 6
sahilmgandhi 18:6a4db94011d3 1635 #define FTFL_FCNFG_CCIE_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 1636 #define FTFL_FCNFG_CCIE_SHIFT 7
sahilmgandhi 18:6a4db94011d3 1637 /* FSEC Bit Fields */
sahilmgandhi 18:6a4db94011d3 1638 #define FTFL_FSEC_SEC_MASK 0x3u
sahilmgandhi 18:6a4db94011d3 1639 #define FTFL_FSEC_SEC_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1640 #define FTFL_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_SEC_SHIFT))&FTFL_FSEC_SEC_MASK)
sahilmgandhi 18:6a4db94011d3 1641 #define FTFL_FSEC_FSLACC_MASK 0xCu
sahilmgandhi 18:6a4db94011d3 1642 #define FTFL_FSEC_FSLACC_SHIFT 2
sahilmgandhi 18:6a4db94011d3 1643 #define FTFL_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_FSLACC_SHIFT))&FTFL_FSEC_FSLACC_MASK)
sahilmgandhi 18:6a4db94011d3 1644 #define FTFL_FSEC_MEEN_MASK 0x30u
sahilmgandhi 18:6a4db94011d3 1645 #define FTFL_FSEC_MEEN_SHIFT 4
sahilmgandhi 18:6a4db94011d3 1646 #define FTFL_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_MEEN_SHIFT))&FTFL_FSEC_MEEN_MASK)
sahilmgandhi 18:6a4db94011d3 1647 #define FTFL_FSEC_KEYEN_MASK 0xC0u
sahilmgandhi 18:6a4db94011d3 1648 #define FTFL_FSEC_KEYEN_SHIFT 6
sahilmgandhi 18:6a4db94011d3 1649 #define FTFL_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_KEYEN_SHIFT))&FTFL_FSEC_KEYEN_MASK)
sahilmgandhi 18:6a4db94011d3 1650 /* FOPT Bit Fields */
sahilmgandhi 18:6a4db94011d3 1651 #define FTFL_FOPT_OPT_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 1652 #define FTFL_FOPT_OPT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1653 #define FTFL_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FOPT_OPT_SHIFT))&FTFL_FOPT_OPT_MASK)
sahilmgandhi 18:6a4db94011d3 1654 /* FCCOB3 Bit Fields */
sahilmgandhi 18:6a4db94011d3 1655 #define FTFL_FCCOB3_CCOBn_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 1656 #define FTFL_FCCOB3_CCOBn_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1657 #define FTFL_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB3_CCOBn_SHIFT))&FTFL_FCCOB3_CCOBn_MASK)
sahilmgandhi 18:6a4db94011d3 1658 /* FCCOB2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 1659 #define FTFL_FCCOB2_CCOBn_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 1660 #define FTFL_FCCOB2_CCOBn_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1661 #define FTFL_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB2_CCOBn_SHIFT))&FTFL_FCCOB2_CCOBn_MASK)
sahilmgandhi 18:6a4db94011d3 1662 /* FCCOB1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 1663 #define FTFL_FCCOB1_CCOBn_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 1664 #define FTFL_FCCOB1_CCOBn_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1665 #define FTFL_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB1_CCOBn_SHIFT))&FTFL_FCCOB1_CCOBn_MASK)
sahilmgandhi 18:6a4db94011d3 1666 /* FCCOB0 Bit Fields */
sahilmgandhi 18:6a4db94011d3 1667 #define FTFL_FCCOB0_CCOBn_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 1668 #define FTFL_FCCOB0_CCOBn_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1669 #define FTFL_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB0_CCOBn_SHIFT))&FTFL_FCCOB0_CCOBn_MASK)
sahilmgandhi 18:6a4db94011d3 1670 /* FCCOB7 Bit Fields */
sahilmgandhi 18:6a4db94011d3 1671 #define FTFL_FCCOB7_CCOBn_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 1672 #define FTFL_FCCOB7_CCOBn_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1673 #define FTFL_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB7_CCOBn_SHIFT))&FTFL_FCCOB7_CCOBn_MASK)
sahilmgandhi 18:6a4db94011d3 1674 /* FCCOB6 Bit Fields */
sahilmgandhi 18:6a4db94011d3 1675 #define FTFL_FCCOB6_CCOBn_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 1676 #define FTFL_FCCOB6_CCOBn_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1677 #define FTFL_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB6_CCOBn_SHIFT))&FTFL_FCCOB6_CCOBn_MASK)
sahilmgandhi 18:6a4db94011d3 1678 /* FCCOB5 Bit Fields */
sahilmgandhi 18:6a4db94011d3 1679 #define FTFL_FCCOB5_CCOBn_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 1680 #define FTFL_FCCOB5_CCOBn_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1681 #define FTFL_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB5_CCOBn_SHIFT))&FTFL_FCCOB5_CCOBn_MASK)
sahilmgandhi 18:6a4db94011d3 1682 /* FCCOB4 Bit Fields */
sahilmgandhi 18:6a4db94011d3 1683 #define FTFL_FCCOB4_CCOBn_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 1684 #define FTFL_FCCOB4_CCOBn_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1685 #define FTFL_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB4_CCOBn_SHIFT))&FTFL_FCCOB4_CCOBn_MASK)
sahilmgandhi 18:6a4db94011d3 1686 /* FCCOBB Bit Fields */
sahilmgandhi 18:6a4db94011d3 1687 #define FTFL_FCCOBB_CCOBn_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 1688 #define FTFL_FCCOBB_CCOBn_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1689 #define FTFL_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOBB_CCOBn_SHIFT))&FTFL_FCCOBB_CCOBn_MASK)
sahilmgandhi 18:6a4db94011d3 1690 /* FCCOBA Bit Fields */
sahilmgandhi 18:6a4db94011d3 1691 #define FTFL_FCCOBA_CCOBn_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 1692 #define FTFL_FCCOBA_CCOBn_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1693 #define FTFL_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOBA_CCOBn_SHIFT))&FTFL_FCCOBA_CCOBn_MASK)
sahilmgandhi 18:6a4db94011d3 1694 /* FCCOB9 Bit Fields */
sahilmgandhi 18:6a4db94011d3 1695 #define FTFL_FCCOB9_CCOBn_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 1696 #define FTFL_FCCOB9_CCOBn_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1697 #define FTFL_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB9_CCOBn_SHIFT))&FTFL_FCCOB9_CCOBn_MASK)
sahilmgandhi 18:6a4db94011d3 1698 /* FCCOB8 Bit Fields */
sahilmgandhi 18:6a4db94011d3 1699 #define FTFL_FCCOB8_CCOBn_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 1700 #define FTFL_FCCOB8_CCOBn_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1701 #define FTFL_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB8_CCOBn_SHIFT))&FTFL_FCCOB8_CCOBn_MASK)
sahilmgandhi 18:6a4db94011d3 1702 /* FPROT3 Bit Fields */
sahilmgandhi 18:6a4db94011d3 1703 #define FTFL_FPROT3_PROT_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 1704 #define FTFL_FPROT3_PROT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1705 #define FTFL_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT3_PROT_SHIFT))&FTFL_FPROT3_PROT_MASK)
sahilmgandhi 18:6a4db94011d3 1706 /* FPROT2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 1707 #define FTFL_FPROT2_PROT_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 1708 #define FTFL_FPROT2_PROT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1709 #define FTFL_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT2_PROT_SHIFT))&FTFL_FPROT2_PROT_MASK)
sahilmgandhi 18:6a4db94011d3 1710 /* FPROT1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 1711 #define FTFL_FPROT1_PROT_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 1712 #define FTFL_FPROT1_PROT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1713 #define FTFL_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT1_PROT_SHIFT))&FTFL_FPROT1_PROT_MASK)
sahilmgandhi 18:6a4db94011d3 1714 /* FPROT0 Bit Fields */
sahilmgandhi 18:6a4db94011d3 1715 #define FTFL_FPROT0_PROT_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 1716 #define FTFL_FPROT0_PROT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1717 #define FTFL_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT0_PROT_SHIFT))&FTFL_FPROT0_PROT_MASK)
sahilmgandhi 18:6a4db94011d3 1718 /* FEPROT Bit Fields */
sahilmgandhi 18:6a4db94011d3 1719 #define FTFL_FEPROT_EPROT_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 1720 #define FTFL_FEPROT_EPROT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1721 #define FTFL_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FEPROT_EPROT_SHIFT))&FTFL_FEPROT_EPROT_MASK)
sahilmgandhi 18:6a4db94011d3 1722 /* FDPROT Bit Fields */
sahilmgandhi 18:6a4db94011d3 1723 #define FTFL_FDPROT_DPROT_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 1724 #define FTFL_FDPROT_DPROT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1725 #define FTFL_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FDPROT_DPROT_SHIFT))&FTFL_FDPROT_DPROT_MASK)
sahilmgandhi 18:6a4db94011d3 1726
sahilmgandhi 18:6a4db94011d3 1727 /**
sahilmgandhi 18:6a4db94011d3 1728 * @}
sahilmgandhi 18:6a4db94011d3 1729 */ /* end of group FTFL_Register_Masks */
sahilmgandhi 18:6a4db94011d3 1730
sahilmgandhi 18:6a4db94011d3 1731
sahilmgandhi 18:6a4db94011d3 1732 /* FTFL - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 1733 /** Peripheral FTFL base address */
sahilmgandhi 18:6a4db94011d3 1734 #define FTFL_BASE (0x40020000u)
sahilmgandhi 18:6a4db94011d3 1735 /** Peripheral FTFL base pointer */
sahilmgandhi 18:6a4db94011d3 1736 #define FTFL ((FTFL_Type *)FTFL_BASE)
sahilmgandhi 18:6a4db94011d3 1737
sahilmgandhi 18:6a4db94011d3 1738 /**
sahilmgandhi 18:6a4db94011d3 1739 * @}
sahilmgandhi 18:6a4db94011d3 1740 */ /* end of group FTFL_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 1741
sahilmgandhi 18:6a4db94011d3 1742
sahilmgandhi 18:6a4db94011d3 1743 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1744 -- FTM Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 1745 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 1746
sahilmgandhi 18:6a4db94011d3 1747 /**
sahilmgandhi 18:6a4db94011d3 1748 * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 1749 * @{
sahilmgandhi 18:6a4db94011d3 1750 */
sahilmgandhi 18:6a4db94011d3 1751
sahilmgandhi 18:6a4db94011d3 1752 /** FTM - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 1753 typedef struct {
sahilmgandhi 18:6a4db94011d3 1754 __IO uint32_t SC; /**< Status and Control, offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 1755 __IO uint32_t CNT; /**< Counter, offset: 0x4 */
sahilmgandhi 18:6a4db94011d3 1756 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
sahilmgandhi 18:6a4db94011d3 1757 struct { /* offset: 0xC, array step: 0x8 */
sahilmgandhi 18:6a4db94011d3 1758 __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
sahilmgandhi 18:6a4db94011d3 1759 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
sahilmgandhi 18:6a4db94011d3 1760 } CONTROLS[8];
sahilmgandhi 18:6a4db94011d3 1761 __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */
sahilmgandhi 18:6a4db94011d3 1762 __I uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
sahilmgandhi 18:6a4db94011d3 1763 __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */
sahilmgandhi 18:6a4db94011d3 1764 __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */
sahilmgandhi 18:6a4db94011d3 1765 __IO uint32_t OUTINIT; /**< Initial State for Channels Output, offset: 0x5C */
sahilmgandhi 18:6a4db94011d3 1766 __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */
sahilmgandhi 18:6a4db94011d3 1767 __IO uint32_t COMBINE; /**< Function for Linked Channels, offset: 0x64 */
sahilmgandhi 18:6a4db94011d3 1768 __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */
sahilmgandhi 18:6a4db94011d3 1769 __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */
sahilmgandhi 18:6a4db94011d3 1770 __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */
sahilmgandhi 18:6a4db94011d3 1771 __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */
sahilmgandhi 18:6a4db94011d3 1772 __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */
sahilmgandhi 18:6a4db94011d3 1773 __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */
sahilmgandhi 18:6a4db94011d3 1774 __IO uint32_t QDCTRL; /**< Quadrature Decoder Control and Status, offset: 0x80 */
sahilmgandhi 18:6a4db94011d3 1775 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
sahilmgandhi 18:6a4db94011d3 1776 __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */
sahilmgandhi 18:6a4db94011d3 1777 __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */
sahilmgandhi 18:6a4db94011d3 1778 __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */
sahilmgandhi 18:6a4db94011d3 1779 __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */
sahilmgandhi 18:6a4db94011d3 1780 __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */
sahilmgandhi 18:6a4db94011d3 1781 } FTM_Type;
sahilmgandhi 18:6a4db94011d3 1782
sahilmgandhi 18:6a4db94011d3 1783 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1784 -- FTM Register Masks
sahilmgandhi 18:6a4db94011d3 1785 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 1786
sahilmgandhi 18:6a4db94011d3 1787 /**
sahilmgandhi 18:6a4db94011d3 1788 * @addtogroup FTM_Register_Masks FTM Register Masks
sahilmgandhi 18:6a4db94011d3 1789 * @{
sahilmgandhi 18:6a4db94011d3 1790 */
sahilmgandhi 18:6a4db94011d3 1791
sahilmgandhi 18:6a4db94011d3 1792 /* SC Bit Fields */
sahilmgandhi 18:6a4db94011d3 1793 #define FTM_SC_PS_MASK 0x7u
sahilmgandhi 18:6a4db94011d3 1794 #define FTM_SC_PS_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1795 #define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK)
sahilmgandhi 18:6a4db94011d3 1796 #define FTM_SC_CLKS_MASK 0x18u
sahilmgandhi 18:6a4db94011d3 1797 #define FTM_SC_CLKS_SHIFT 3
sahilmgandhi 18:6a4db94011d3 1798 #define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK)
sahilmgandhi 18:6a4db94011d3 1799 #define FTM_SC_CPWMS_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 1800 #define FTM_SC_CPWMS_SHIFT 5
sahilmgandhi 18:6a4db94011d3 1801 #define FTM_SC_TOIE_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 1802 #define FTM_SC_TOIE_SHIFT 6
sahilmgandhi 18:6a4db94011d3 1803 #define FTM_SC_TOF_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 1804 #define FTM_SC_TOF_SHIFT 7
sahilmgandhi 18:6a4db94011d3 1805 /* CNT Bit Fields */
sahilmgandhi 18:6a4db94011d3 1806 #define FTM_CNT_COUNT_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 1807 #define FTM_CNT_COUNT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1808 #define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK)
sahilmgandhi 18:6a4db94011d3 1809 /* MOD Bit Fields */
sahilmgandhi 18:6a4db94011d3 1810 #define FTM_MOD_MOD_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 1811 #define FTM_MOD_MOD_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1812 #define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK)
sahilmgandhi 18:6a4db94011d3 1813 /* CnSC Bit Fields */
sahilmgandhi 18:6a4db94011d3 1814 #define FTM_CnSC_DMA_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 1815 #define FTM_CnSC_DMA_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1816 #define FTM_CnSC_ELSA_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 1817 #define FTM_CnSC_ELSA_SHIFT 2
sahilmgandhi 18:6a4db94011d3 1818 #define FTM_CnSC_ELSB_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 1819 #define FTM_CnSC_ELSB_SHIFT 3
sahilmgandhi 18:6a4db94011d3 1820 #define FTM_CnSC_MSA_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 1821 #define FTM_CnSC_MSA_SHIFT 4
sahilmgandhi 18:6a4db94011d3 1822 #define FTM_CnSC_MSB_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 1823 #define FTM_CnSC_MSB_SHIFT 5
sahilmgandhi 18:6a4db94011d3 1824 #define FTM_CnSC_CHIE_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 1825 #define FTM_CnSC_CHIE_SHIFT 6
sahilmgandhi 18:6a4db94011d3 1826 #define FTM_CnSC_CHF_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 1827 #define FTM_CnSC_CHF_SHIFT 7
sahilmgandhi 18:6a4db94011d3 1828 /* CnV Bit Fields */
sahilmgandhi 18:6a4db94011d3 1829 #define FTM_CnV_VAL_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 1830 #define FTM_CnV_VAL_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1831 #define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK)
sahilmgandhi 18:6a4db94011d3 1832 /* CNTIN Bit Fields */
sahilmgandhi 18:6a4db94011d3 1833 #define FTM_CNTIN_INIT_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 1834 #define FTM_CNTIN_INIT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1835 #define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK)
sahilmgandhi 18:6a4db94011d3 1836 /* STATUS Bit Fields */
sahilmgandhi 18:6a4db94011d3 1837 #define FTM_STATUS_CH0F_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 1838 #define FTM_STATUS_CH0F_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1839 #define FTM_STATUS_CH1F_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 1840 #define FTM_STATUS_CH1F_SHIFT 1
sahilmgandhi 18:6a4db94011d3 1841 #define FTM_STATUS_CH2F_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 1842 #define FTM_STATUS_CH2F_SHIFT 2
sahilmgandhi 18:6a4db94011d3 1843 #define FTM_STATUS_CH3F_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 1844 #define FTM_STATUS_CH3F_SHIFT 3
sahilmgandhi 18:6a4db94011d3 1845 #define FTM_STATUS_CH4F_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 1846 #define FTM_STATUS_CH4F_SHIFT 4
sahilmgandhi 18:6a4db94011d3 1847 #define FTM_STATUS_CH5F_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 1848 #define FTM_STATUS_CH5F_SHIFT 5
sahilmgandhi 18:6a4db94011d3 1849 #define FTM_STATUS_CH6F_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 1850 #define FTM_STATUS_CH6F_SHIFT 6
sahilmgandhi 18:6a4db94011d3 1851 #define FTM_STATUS_CH7F_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 1852 #define FTM_STATUS_CH7F_SHIFT 7
sahilmgandhi 18:6a4db94011d3 1853 /* MODE Bit Fields */
sahilmgandhi 18:6a4db94011d3 1854 #define FTM_MODE_FTMEN_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 1855 #define FTM_MODE_FTMEN_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1856 #define FTM_MODE_INIT_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 1857 #define FTM_MODE_INIT_SHIFT 1
sahilmgandhi 18:6a4db94011d3 1858 #define FTM_MODE_WPDIS_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 1859 #define FTM_MODE_WPDIS_SHIFT 2
sahilmgandhi 18:6a4db94011d3 1860 #define FTM_MODE_PWMSYNC_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 1861 #define FTM_MODE_PWMSYNC_SHIFT 3
sahilmgandhi 18:6a4db94011d3 1862 #define FTM_MODE_CAPTEST_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 1863 #define FTM_MODE_CAPTEST_SHIFT 4
sahilmgandhi 18:6a4db94011d3 1864 #define FTM_MODE_FAULTM_MASK 0x60u
sahilmgandhi 18:6a4db94011d3 1865 #define FTM_MODE_FAULTM_SHIFT 5
sahilmgandhi 18:6a4db94011d3 1866 #define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK)
sahilmgandhi 18:6a4db94011d3 1867 #define FTM_MODE_FAULTIE_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 1868 #define FTM_MODE_FAULTIE_SHIFT 7
sahilmgandhi 18:6a4db94011d3 1869 /* SYNC Bit Fields */
sahilmgandhi 18:6a4db94011d3 1870 #define FTM_SYNC_CNTMIN_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 1871 #define FTM_SYNC_CNTMIN_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1872 #define FTM_SYNC_CNTMAX_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 1873 #define FTM_SYNC_CNTMAX_SHIFT 1
sahilmgandhi 18:6a4db94011d3 1874 #define FTM_SYNC_REINIT_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 1875 #define FTM_SYNC_REINIT_SHIFT 2
sahilmgandhi 18:6a4db94011d3 1876 #define FTM_SYNC_SYNCHOM_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 1877 #define FTM_SYNC_SYNCHOM_SHIFT 3
sahilmgandhi 18:6a4db94011d3 1878 #define FTM_SYNC_TRIG0_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 1879 #define FTM_SYNC_TRIG0_SHIFT 4
sahilmgandhi 18:6a4db94011d3 1880 #define FTM_SYNC_TRIG1_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 1881 #define FTM_SYNC_TRIG1_SHIFT 5
sahilmgandhi 18:6a4db94011d3 1882 #define FTM_SYNC_TRIG2_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 1883 #define FTM_SYNC_TRIG2_SHIFT 6
sahilmgandhi 18:6a4db94011d3 1884 #define FTM_SYNC_SWSYNC_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 1885 #define FTM_SYNC_SWSYNC_SHIFT 7
sahilmgandhi 18:6a4db94011d3 1886 /* OUTINIT Bit Fields */
sahilmgandhi 18:6a4db94011d3 1887 #define FTM_OUTINIT_CH0OI_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 1888 #define FTM_OUTINIT_CH0OI_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1889 #define FTM_OUTINIT_CH1OI_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 1890 #define FTM_OUTINIT_CH1OI_SHIFT 1
sahilmgandhi 18:6a4db94011d3 1891 #define FTM_OUTINIT_CH2OI_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 1892 #define FTM_OUTINIT_CH2OI_SHIFT 2
sahilmgandhi 18:6a4db94011d3 1893 #define FTM_OUTINIT_CH3OI_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 1894 #define FTM_OUTINIT_CH3OI_SHIFT 3
sahilmgandhi 18:6a4db94011d3 1895 #define FTM_OUTINIT_CH4OI_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 1896 #define FTM_OUTINIT_CH4OI_SHIFT 4
sahilmgandhi 18:6a4db94011d3 1897 #define FTM_OUTINIT_CH5OI_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 1898 #define FTM_OUTINIT_CH5OI_SHIFT 5
sahilmgandhi 18:6a4db94011d3 1899 #define FTM_OUTINIT_CH6OI_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 1900 #define FTM_OUTINIT_CH6OI_SHIFT 6
sahilmgandhi 18:6a4db94011d3 1901 #define FTM_OUTINIT_CH7OI_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 1902 #define FTM_OUTINIT_CH7OI_SHIFT 7
sahilmgandhi 18:6a4db94011d3 1903 /* OUTMASK Bit Fields */
sahilmgandhi 18:6a4db94011d3 1904 #define FTM_OUTMASK_CH0OM_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 1905 #define FTM_OUTMASK_CH0OM_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1906 #define FTM_OUTMASK_CH1OM_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 1907 #define FTM_OUTMASK_CH1OM_SHIFT 1
sahilmgandhi 18:6a4db94011d3 1908 #define FTM_OUTMASK_CH2OM_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 1909 #define FTM_OUTMASK_CH2OM_SHIFT 2
sahilmgandhi 18:6a4db94011d3 1910 #define FTM_OUTMASK_CH3OM_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 1911 #define FTM_OUTMASK_CH3OM_SHIFT 3
sahilmgandhi 18:6a4db94011d3 1912 #define FTM_OUTMASK_CH4OM_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 1913 #define FTM_OUTMASK_CH4OM_SHIFT 4
sahilmgandhi 18:6a4db94011d3 1914 #define FTM_OUTMASK_CH5OM_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 1915 #define FTM_OUTMASK_CH5OM_SHIFT 5
sahilmgandhi 18:6a4db94011d3 1916 #define FTM_OUTMASK_CH6OM_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 1917 #define FTM_OUTMASK_CH6OM_SHIFT 6
sahilmgandhi 18:6a4db94011d3 1918 #define FTM_OUTMASK_CH7OM_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 1919 #define FTM_OUTMASK_CH7OM_SHIFT 7
sahilmgandhi 18:6a4db94011d3 1920 /* COMBINE Bit Fields */
sahilmgandhi 18:6a4db94011d3 1921 #define FTM_COMBINE_COMBINE0_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 1922 #define FTM_COMBINE_COMBINE0_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1923 #define FTM_COMBINE_COMP0_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 1924 #define FTM_COMBINE_COMP0_SHIFT 1
sahilmgandhi 18:6a4db94011d3 1925 #define FTM_COMBINE_DECAPEN0_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 1926 #define FTM_COMBINE_DECAPEN0_SHIFT 2
sahilmgandhi 18:6a4db94011d3 1927 #define FTM_COMBINE_DECAP0_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 1928 #define FTM_COMBINE_DECAP0_SHIFT 3
sahilmgandhi 18:6a4db94011d3 1929 #define FTM_COMBINE_DTEN0_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 1930 #define FTM_COMBINE_DTEN0_SHIFT 4
sahilmgandhi 18:6a4db94011d3 1931 #define FTM_COMBINE_SYNCEN0_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 1932 #define FTM_COMBINE_SYNCEN0_SHIFT 5
sahilmgandhi 18:6a4db94011d3 1933 #define FTM_COMBINE_FAULTEN0_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 1934 #define FTM_COMBINE_FAULTEN0_SHIFT 6
sahilmgandhi 18:6a4db94011d3 1935 #define FTM_COMBINE_COMBINE1_MASK 0x100u
sahilmgandhi 18:6a4db94011d3 1936 #define FTM_COMBINE_COMBINE1_SHIFT 8
sahilmgandhi 18:6a4db94011d3 1937 #define FTM_COMBINE_COMP1_MASK 0x200u
sahilmgandhi 18:6a4db94011d3 1938 #define FTM_COMBINE_COMP1_SHIFT 9
sahilmgandhi 18:6a4db94011d3 1939 #define FTM_COMBINE_DECAPEN1_MASK 0x400u
sahilmgandhi 18:6a4db94011d3 1940 #define FTM_COMBINE_DECAPEN1_SHIFT 10
sahilmgandhi 18:6a4db94011d3 1941 #define FTM_COMBINE_DECAP1_MASK 0x800u
sahilmgandhi 18:6a4db94011d3 1942 #define FTM_COMBINE_DECAP1_SHIFT 11
sahilmgandhi 18:6a4db94011d3 1943 #define FTM_COMBINE_DTEN1_MASK 0x1000u
sahilmgandhi 18:6a4db94011d3 1944 #define FTM_COMBINE_DTEN1_SHIFT 12
sahilmgandhi 18:6a4db94011d3 1945 #define FTM_COMBINE_SYNCEN1_MASK 0x2000u
sahilmgandhi 18:6a4db94011d3 1946 #define FTM_COMBINE_SYNCEN1_SHIFT 13
sahilmgandhi 18:6a4db94011d3 1947 #define FTM_COMBINE_FAULTEN1_MASK 0x4000u
sahilmgandhi 18:6a4db94011d3 1948 #define FTM_COMBINE_FAULTEN1_SHIFT 14
sahilmgandhi 18:6a4db94011d3 1949 #define FTM_COMBINE_COMBINE2_MASK 0x10000u
sahilmgandhi 18:6a4db94011d3 1950 #define FTM_COMBINE_COMBINE2_SHIFT 16
sahilmgandhi 18:6a4db94011d3 1951 #define FTM_COMBINE_COMP2_MASK 0x20000u
sahilmgandhi 18:6a4db94011d3 1952 #define FTM_COMBINE_COMP2_SHIFT 17
sahilmgandhi 18:6a4db94011d3 1953 #define FTM_COMBINE_DECAPEN2_MASK 0x40000u
sahilmgandhi 18:6a4db94011d3 1954 #define FTM_COMBINE_DECAPEN2_SHIFT 18
sahilmgandhi 18:6a4db94011d3 1955 #define FTM_COMBINE_DECAP2_MASK 0x80000u
sahilmgandhi 18:6a4db94011d3 1956 #define FTM_COMBINE_DECAP2_SHIFT 19
sahilmgandhi 18:6a4db94011d3 1957 #define FTM_COMBINE_DTEN2_MASK 0x100000u
sahilmgandhi 18:6a4db94011d3 1958 #define FTM_COMBINE_DTEN2_SHIFT 20
sahilmgandhi 18:6a4db94011d3 1959 #define FTM_COMBINE_SYNCEN2_MASK 0x200000u
sahilmgandhi 18:6a4db94011d3 1960 #define FTM_COMBINE_SYNCEN2_SHIFT 21
sahilmgandhi 18:6a4db94011d3 1961 #define FTM_COMBINE_FAULTEN2_MASK 0x400000u
sahilmgandhi 18:6a4db94011d3 1962 #define FTM_COMBINE_FAULTEN2_SHIFT 22
sahilmgandhi 18:6a4db94011d3 1963 #define FTM_COMBINE_COMBINE3_MASK 0x1000000u
sahilmgandhi 18:6a4db94011d3 1964 #define FTM_COMBINE_COMBINE3_SHIFT 24
sahilmgandhi 18:6a4db94011d3 1965 #define FTM_COMBINE_COMP3_MASK 0x2000000u
sahilmgandhi 18:6a4db94011d3 1966 #define FTM_COMBINE_COMP3_SHIFT 25
sahilmgandhi 18:6a4db94011d3 1967 #define FTM_COMBINE_DECAPEN3_MASK 0x4000000u
sahilmgandhi 18:6a4db94011d3 1968 #define FTM_COMBINE_DECAPEN3_SHIFT 26
sahilmgandhi 18:6a4db94011d3 1969 #define FTM_COMBINE_DECAP3_MASK 0x8000000u
sahilmgandhi 18:6a4db94011d3 1970 #define FTM_COMBINE_DECAP3_SHIFT 27
sahilmgandhi 18:6a4db94011d3 1971 #define FTM_COMBINE_DTEN3_MASK 0x10000000u
sahilmgandhi 18:6a4db94011d3 1972 #define FTM_COMBINE_DTEN3_SHIFT 28
sahilmgandhi 18:6a4db94011d3 1973 #define FTM_COMBINE_SYNCEN3_MASK 0x20000000u
sahilmgandhi 18:6a4db94011d3 1974 #define FTM_COMBINE_SYNCEN3_SHIFT 29
sahilmgandhi 18:6a4db94011d3 1975 #define FTM_COMBINE_FAULTEN3_MASK 0x40000000u
sahilmgandhi 18:6a4db94011d3 1976 #define FTM_COMBINE_FAULTEN3_SHIFT 30
sahilmgandhi 18:6a4db94011d3 1977 /* DEADTIME Bit Fields */
sahilmgandhi 18:6a4db94011d3 1978 #define FTM_DEADTIME_DTVAL_MASK 0x3Fu
sahilmgandhi 18:6a4db94011d3 1979 #define FTM_DEADTIME_DTVAL_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1980 #define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK)
sahilmgandhi 18:6a4db94011d3 1981 #define FTM_DEADTIME_DTPS_MASK 0xC0u
sahilmgandhi 18:6a4db94011d3 1982 #define FTM_DEADTIME_DTPS_SHIFT 6
sahilmgandhi 18:6a4db94011d3 1983 #define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK)
sahilmgandhi 18:6a4db94011d3 1984 /* EXTTRIG Bit Fields */
sahilmgandhi 18:6a4db94011d3 1985 #define FTM_EXTTRIG_CH2TRIG_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 1986 #define FTM_EXTTRIG_CH2TRIG_SHIFT 0
sahilmgandhi 18:6a4db94011d3 1987 #define FTM_EXTTRIG_CH3TRIG_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 1988 #define FTM_EXTTRIG_CH3TRIG_SHIFT 1
sahilmgandhi 18:6a4db94011d3 1989 #define FTM_EXTTRIG_CH4TRIG_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 1990 #define FTM_EXTTRIG_CH4TRIG_SHIFT 2
sahilmgandhi 18:6a4db94011d3 1991 #define FTM_EXTTRIG_CH5TRIG_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 1992 #define FTM_EXTTRIG_CH5TRIG_SHIFT 3
sahilmgandhi 18:6a4db94011d3 1993 #define FTM_EXTTRIG_CH0TRIG_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 1994 #define FTM_EXTTRIG_CH0TRIG_SHIFT 4
sahilmgandhi 18:6a4db94011d3 1995 #define FTM_EXTTRIG_CH1TRIG_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 1996 #define FTM_EXTTRIG_CH1TRIG_SHIFT 5
sahilmgandhi 18:6a4db94011d3 1997 #define FTM_EXTTRIG_INITTRIGEN_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 1998 #define FTM_EXTTRIG_INITTRIGEN_SHIFT 6
sahilmgandhi 18:6a4db94011d3 1999 #define FTM_EXTTRIG_TRIGF_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 2000 #define FTM_EXTTRIG_TRIGF_SHIFT 7
sahilmgandhi 18:6a4db94011d3 2001 /* POL Bit Fields */
sahilmgandhi 18:6a4db94011d3 2002 #define FTM_POL_POL0_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 2003 #define FTM_POL_POL0_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2004 #define FTM_POL_POL1_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 2005 #define FTM_POL_POL1_SHIFT 1
sahilmgandhi 18:6a4db94011d3 2006 #define FTM_POL_POL2_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 2007 #define FTM_POL_POL2_SHIFT 2
sahilmgandhi 18:6a4db94011d3 2008 #define FTM_POL_POL3_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 2009 #define FTM_POL_POL3_SHIFT 3
sahilmgandhi 18:6a4db94011d3 2010 #define FTM_POL_POL4_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 2011 #define FTM_POL_POL4_SHIFT 4
sahilmgandhi 18:6a4db94011d3 2012 #define FTM_POL_POL5_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 2013 #define FTM_POL_POL5_SHIFT 5
sahilmgandhi 18:6a4db94011d3 2014 #define FTM_POL_POL6_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 2015 #define FTM_POL_POL6_SHIFT 6
sahilmgandhi 18:6a4db94011d3 2016 #define FTM_POL_POL7_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 2017 #define FTM_POL_POL7_SHIFT 7
sahilmgandhi 18:6a4db94011d3 2018 /* FMS Bit Fields */
sahilmgandhi 18:6a4db94011d3 2019 #define FTM_FMS_FAULTF0_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 2020 #define FTM_FMS_FAULTF0_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2021 #define FTM_FMS_FAULTF1_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 2022 #define FTM_FMS_FAULTF1_SHIFT 1
sahilmgandhi 18:6a4db94011d3 2023 #define FTM_FMS_FAULTF2_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 2024 #define FTM_FMS_FAULTF2_SHIFT 2
sahilmgandhi 18:6a4db94011d3 2025 #define FTM_FMS_FAULTF3_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 2026 #define FTM_FMS_FAULTF3_SHIFT 3
sahilmgandhi 18:6a4db94011d3 2027 #define FTM_FMS_FAULTIN_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 2028 #define FTM_FMS_FAULTIN_SHIFT 5
sahilmgandhi 18:6a4db94011d3 2029 #define FTM_FMS_WPEN_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 2030 #define FTM_FMS_WPEN_SHIFT 6
sahilmgandhi 18:6a4db94011d3 2031 #define FTM_FMS_FAULTF_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 2032 #define FTM_FMS_FAULTF_SHIFT 7
sahilmgandhi 18:6a4db94011d3 2033 /* FILTER Bit Fields */
sahilmgandhi 18:6a4db94011d3 2034 #define FTM_FILTER_CH0FVAL_MASK 0xFu
sahilmgandhi 18:6a4db94011d3 2035 #define FTM_FILTER_CH0FVAL_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2036 #define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK)
sahilmgandhi 18:6a4db94011d3 2037 #define FTM_FILTER_CH1FVAL_MASK 0xF0u
sahilmgandhi 18:6a4db94011d3 2038 #define FTM_FILTER_CH1FVAL_SHIFT 4
sahilmgandhi 18:6a4db94011d3 2039 #define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK)
sahilmgandhi 18:6a4db94011d3 2040 #define FTM_FILTER_CH2FVAL_MASK 0xF00u
sahilmgandhi 18:6a4db94011d3 2041 #define FTM_FILTER_CH2FVAL_SHIFT 8
sahilmgandhi 18:6a4db94011d3 2042 #define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK)
sahilmgandhi 18:6a4db94011d3 2043 #define FTM_FILTER_CH3FVAL_MASK 0xF000u
sahilmgandhi 18:6a4db94011d3 2044 #define FTM_FILTER_CH3FVAL_SHIFT 12
sahilmgandhi 18:6a4db94011d3 2045 #define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK)
sahilmgandhi 18:6a4db94011d3 2046 /* FLTCTRL Bit Fields */
sahilmgandhi 18:6a4db94011d3 2047 #define FTM_FLTCTRL_FAULT0EN_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 2048 #define FTM_FLTCTRL_FAULT0EN_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2049 #define FTM_FLTCTRL_FAULT1EN_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 2050 #define FTM_FLTCTRL_FAULT1EN_SHIFT 1
sahilmgandhi 18:6a4db94011d3 2051 #define FTM_FLTCTRL_FAULT2EN_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 2052 #define FTM_FLTCTRL_FAULT2EN_SHIFT 2
sahilmgandhi 18:6a4db94011d3 2053 #define FTM_FLTCTRL_FAULT3EN_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 2054 #define FTM_FLTCTRL_FAULT3EN_SHIFT 3
sahilmgandhi 18:6a4db94011d3 2055 #define FTM_FLTCTRL_FFLTR0EN_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 2056 #define FTM_FLTCTRL_FFLTR0EN_SHIFT 4
sahilmgandhi 18:6a4db94011d3 2057 #define FTM_FLTCTRL_FFLTR1EN_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 2058 #define FTM_FLTCTRL_FFLTR1EN_SHIFT 5
sahilmgandhi 18:6a4db94011d3 2059 #define FTM_FLTCTRL_FFLTR2EN_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 2060 #define FTM_FLTCTRL_FFLTR2EN_SHIFT 6
sahilmgandhi 18:6a4db94011d3 2061 #define FTM_FLTCTRL_FFLTR3EN_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 2062 #define FTM_FLTCTRL_FFLTR3EN_SHIFT 7
sahilmgandhi 18:6a4db94011d3 2063 #define FTM_FLTCTRL_FFVAL_MASK 0xF00u
sahilmgandhi 18:6a4db94011d3 2064 #define FTM_FLTCTRL_FFVAL_SHIFT 8
sahilmgandhi 18:6a4db94011d3 2065 #define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK)
sahilmgandhi 18:6a4db94011d3 2066 /* QDCTRL Bit Fields */
sahilmgandhi 18:6a4db94011d3 2067 #define FTM_QDCTRL_QUADEN_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 2068 #define FTM_QDCTRL_QUADEN_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2069 #define FTM_QDCTRL_TOFDIR_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 2070 #define FTM_QDCTRL_TOFDIR_SHIFT 1
sahilmgandhi 18:6a4db94011d3 2071 #define FTM_QDCTRL_QUADIR_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 2072 #define FTM_QDCTRL_QUADIR_SHIFT 2
sahilmgandhi 18:6a4db94011d3 2073 #define FTM_QDCTRL_QUADMODE_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 2074 #define FTM_QDCTRL_QUADMODE_SHIFT 3
sahilmgandhi 18:6a4db94011d3 2075 #define FTM_QDCTRL_PHBPOL_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 2076 #define FTM_QDCTRL_PHBPOL_SHIFT 4
sahilmgandhi 18:6a4db94011d3 2077 #define FTM_QDCTRL_PHAPOL_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 2078 #define FTM_QDCTRL_PHAPOL_SHIFT 5
sahilmgandhi 18:6a4db94011d3 2079 #define FTM_QDCTRL_PHBFLTREN_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 2080 #define FTM_QDCTRL_PHBFLTREN_SHIFT 6
sahilmgandhi 18:6a4db94011d3 2081 #define FTM_QDCTRL_PHAFLTREN_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 2082 #define FTM_QDCTRL_PHAFLTREN_SHIFT 7
sahilmgandhi 18:6a4db94011d3 2083 /* CONF Bit Fields */
sahilmgandhi 18:6a4db94011d3 2084 #define FTM_CONF_NUMTOF_MASK 0x1Fu
sahilmgandhi 18:6a4db94011d3 2085 #define FTM_CONF_NUMTOF_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2086 #define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK)
sahilmgandhi 18:6a4db94011d3 2087 #define FTM_CONF_BDMMODE_MASK 0xC0u
sahilmgandhi 18:6a4db94011d3 2088 #define FTM_CONF_BDMMODE_SHIFT 6
sahilmgandhi 18:6a4db94011d3 2089 #define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK)
sahilmgandhi 18:6a4db94011d3 2090 #define FTM_CONF_GTBEEN_MASK 0x200u
sahilmgandhi 18:6a4db94011d3 2091 #define FTM_CONF_GTBEEN_SHIFT 9
sahilmgandhi 18:6a4db94011d3 2092 #define FTM_CONF_GTBEOUT_MASK 0x400u
sahilmgandhi 18:6a4db94011d3 2093 #define FTM_CONF_GTBEOUT_SHIFT 10
sahilmgandhi 18:6a4db94011d3 2094 /* FLTPOL Bit Fields */
sahilmgandhi 18:6a4db94011d3 2095 #define FTM_FLTPOL_FLT0POL_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 2096 #define FTM_FLTPOL_FLT0POL_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2097 #define FTM_FLTPOL_FLT1POL_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 2098 #define FTM_FLTPOL_FLT1POL_SHIFT 1
sahilmgandhi 18:6a4db94011d3 2099 #define FTM_FLTPOL_FLT2POL_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 2100 #define FTM_FLTPOL_FLT2POL_SHIFT 2
sahilmgandhi 18:6a4db94011d3 2101 #define FTM_FLTPOL_FLT3POL_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 2102 #define FTM_FLTPOL_FLT3POL_SHIFT 3
sahilmgandhi 18:6a4db94011d3 2103 /* SYNCONF Bit Fields */
sahilmgandhi 18:6a4db94011d3 2104 #define FTM_SYNCONF_HWTRIGMODE_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 2105 #define FTM_SYNCONF_HWTRIGMODE_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2106 #define FTM_SYNCONF_CNTINC_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 2107 #define FTM_SYNCONF_CNTINC_SHIFT 2
sahilmgandhi 18:6a4db94011d3 2108 #define FTM_SYNCONF_INVC_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 2109 #define FTM_SYNCONF_INVC_SHIFT 4
sahilmgandhi 18:6a4db94011d3 2110 #define FTM_SYNCONF_SWOC_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 2111 #define FTM_SYNCONF_SWOC_SHIFT 5
sahilmgandhi 18:6a4db94011d3 2112 #define FTM_SYNCONF_SYNCMODE_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 2113 #define FTM_SYNCONF_SYNCMODE_SHIFT 7
sahilmgandhi 18:6a4db94011d3 2114 #define FTM_SYNCONF_SWRSTCNT_MASK 0x100u
sahilmgandhi 18:6a4db94011d3 2115 #define FTM_SYNCONF_SWRSTCNT_SHIFT 8
sahilmgandhi 18:6a4db94011d3 2116 #define FTM_SYNCONF_SWWRBUF_MASK 0x200u
sahilmgandhi 18:6a4db94011d3 2117 #define FTM_SYNCONF_SWWRBUF_SHIFT 9
sahilmgandhi 18:6a4db94011d3 2118 #define FTM_SYNCONF_SWOM_MASK 0x400u
sahilmgandhi 18:6a4db94011d3 2119 #define FTM_SYNCONF_SWOM_SHIFT 10
sahilmgandhi 18:6a4db94011d3 2120 #define FTM_SYNCONF_SWINVC_MASK 0x800u
sahilmgandhi 18:6a4db94011d3 2121 #define FTM_SYNCONF_SWINVC_SHIFT 11
sahilmgandhi 18:6a4db94011d3 2122 #define FTM_SYNCONF_SWSOC_MASK 0x1000u
sahilmgandhi 18:6a4db94011d3 2123 #define FTM_SYNCONF_SWSOC_SHIFT 12
sahilmgandhi 18:6a4db94011d3 2124 #define FTM_SYNCONF_HWRSTCNT_MASK 0x10000u
sahilmgandhi 18:6a4db94011d3 2125 #define FTM_SYNCONF_HWRSTCNT_SHIFT 16
sahilmgandhi 18:6a4db94011d3 2126 #define FTM_SYNCONF_HWWRBUF_MASK 0x20000u
sahilmgandhi 18:6a4db94011d3 2127 #define FTM_SYNCONF_HWWRBUF_SHIFT 17
sahilmgandhi 18:6a4db94011d3 2128 #define FTM_SYNCONF_HWOM_MASK 0x40000u
sahilmgandhi 18:6a4db94011d3 2129 #define FTM_SYNCONF_HWOM_SHIFT 18
sahilmgandhi 18:6a4db94011d3 2130 #define FTM_SYNCONF_HWINVC_MASK 0x80000u
sahilmgandhi 18:6a4db94011d3 2131 #define FTM_SYNCONF_HWINVC_SHIFT 19
sahilmgandhi 18:6a4db94011d3 2132 #define FTM_SYNCONF_HWSOC_MASK 0x100000u
sahilmgandhi 18:6a4db94011d3 2133 #define FTM_SYNCONF_HWSOC_SHIFT 20
sahilmgandhi 18:6a4db94011d3 2134 /* INVCTRL Bit Fields */
sahilmgandhi 18:6a4db94011d3 2135 #define FTM_INVCTRL_INV0EN_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 2136 #define FTM_INVCTRL_INV0EN_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2137 #define FTM_INVCTRL_INV1EN_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 2138 #define FTM_INVCTRL_INV1EN_SHIFT 1
sahilmgandhi 18:6a4db94011d3 2139 #define FTM_INVCTRL_INV2EN_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 2140 #define FTM_INVCTRL_INV2EN_SHIFT 2
sahilmgandhi 18:6a4db94011d3 2141 #define FTM_INVCTRL_INV3EN_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 2142 #define FTM_INVCTRL_INV3EN_SHIFT 3
sahilmgandhi 18:6a4db94011d3 2143 /* SWOCTRL Bit Fields */
sahilmgandhi 18:6a4db94011d3 2144 #define FTM_SWOCTRL_CH0OC_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 2145 #define FTM_SWOCTRL_CH0OC_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2146 #define FTM_SWOCTRL_CH1OC_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 2147 #define FTM_SWOCTRL_CH1OC_SHIFT 1
sahilmgandhi 18:6a4db94011d3 2148 #define FTM_SWOCTRL_CH2OC_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 2149 #define FTM_SWOCTRL_CH2OC_SHIFT 2
sahilmgandhi 18:6a4db94011d3 2150 #define FTM_SWOCTRL_CH3OC_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 2151 #define FTM_SWOCTRL_CH3OC_SHIFT 3
sahilmgandhi 18:6a4db94011d3 2152 #define FTM_SWOCTRL_CH4OC_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 2153 #define FTM_SWOCTRL_CH4OC_SHIFT 4
sahilmgandhi 18:6a4db94011d3 2154 #define FTM_SWOCTRL_CH5OC_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 2155 #define FTM_SWOCTRL_CH5OC_SHIFT 5
sahilmgandhi 18:6a4db94011d3 2156 #define FTM_SWOCTRL_CH6OC_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 2157 #define FTM_SWOCTRL_CH6OC_SHIFT 6
sahilmgandhi 18:6a4db94011d3 2158 #define FTM_SWOCTRL_CH7OC_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 2159 #define FTM_SWOCTRL_CH7OC_SHIFT 7
sahilmgandhi 18:6a4db94011d3 2160 #define FTM_SWOCTRL_CH0OCV_MASK 0x100u
sahilmgandhi 18:6a4db94011d3 2161 #define FTM_SWOCTRL_CH0OCV_SHIFT 8
sahilmgandhi 18:6a4db94011d3 2162 #define FTM_SWOCTRL_CH1OCV_MASK 0x200u
sahilmgandhi 18:6a4db94011d3 2163 #define FTM_SWOCTRL_CH1OCV_SHIFT 9
sahilmgandhi 18:6a4db94011d3 2164 #define FTM_SWOCTRL_CH2OCV_MASK 0x400u
sahilmgandhi 18:6a4db94011d3 2165 #define FTM_SWOCTRL_CH2OCV_SHIFT 10
sahilmgandhi 18:6a4db94011d3 2166 #define FTM_SWOCTRL_CH3OCV_MASK 0x800u
sahilmgandhi 18:6a4db94011d3 2167 #define FTM_SWOCTRL_CH3OCV_SHIFT 11
sahilmgandhi 18:6a4db94011d3 2168 #define FTM_SWOCTRL_CH4OCV_MASK 0x1000u
sahilmgandhi 18:6a4db94011d3 2169 #define FTM_SWOCTRL_CH4OCV_SHIFT 12
sahilmgandhi 18:6a4db94011d3 2170 #define FTM_SWOCTRL_CH5OCV_MASK 0x2000u
sahilmgandhi 18:6a4db94011d3 2171 #define FTM_SWOCTRL_CH5OCV_SHIFT 13
sahilmgandhi 18:6a4db94011d3 2172 #define FTM_SWOCTRL_CH6OCV_MASK 0x4000u
sahilmgandhi 18:6a4db94011d3 2173 #define FTM_SWOCTRL_CH6OCV_SHIFT 14
sahilmgandhi 18:6a4db94011d3 2174 #define FTM_SWOCTRL_CH7OCV_MASK 0x8000u
sahilmgandhi 18:6a4db94011d3 2175 #define FTM_SWOCTRL_CH7OCV_SHIFT 15
sahilmgandhi 18:6a4db94011d3 2176 /* PWMLOAD Bit Fields */
sahilmgandhi 18:6a4db94011d3 2177 #define FTM_PWMLOAD_CH0SEL_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 2178 #define FTM_PWMLOAD_CH0SEL_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2179 #define FTM_PWMLOAD_CH1SEL_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 2180 #define FTM_PWMLOAD_CH1SEL_SHIFT 1
sahilmgandhi 18:6a4db94011d3 2181 #define FTM_PWMLOAD_CH2SEL_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 2182 #define FTM_PWMLOAD_CH2SEL_SHIFT 2
sahilmgandhi 18:6a4db94011d3 2183 #define FTM_PWMLOAD_CH3SEL_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 2184 #define FTM_PWMLOAD_CH3SEL_SHIFT 3
sahilmgandhi 18:6a4db94011d3 2185 #define FTM_PWMLOAD_CH4SEL_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 2186 #define FTM_PWMLOAD_CH4SEL_SHIFT 4
sahilmgandhi 18:6a4db94011d3 2187 #define FTM_PWMLOAD_CH5SEL_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 2188 #define FTM_PWMLOAD_CH5SEL_SHIFT 5
sahilmgandhi 18:6a4db94011d3 2189 #define FTM_PWMLOAD_CH6SEL_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 2190 #define FTM_PWMLOAD_CH6SEL_SHIFT 6
sahilmgandhi 18:6a4db94011d3 2191 #define FTM_PWMLOAD_CH7SEL_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 2192 #define FTM_PWMLOAD_CH7SEL_SHIFT 7
sahilmgandhi 18:6a4db94011d3 2193 #define FTM_PWMLOAD_LDOK_MASK 0x200u
sahilmgandhi 18:6a4db94011d3 2194 #define FTM_PWMLOAD_LDOK_SHIFT 9
sahilmgandhi 18:6a4db94011d3 2195
sahilmgandhi 18:6a4db94011d3 2196 /**
sahilmgandhi 18:6a4db94011d3 2197 * @}
sahilmgandhi 18:6a4db94011d3 2198 */ /* end of group FTM_Register_Masks */
sahilmgandhi 18:6a4db94011d3 2199
sahilmgandhi 18:6a4db94011d3 2200
sahilmgandhi 18:6a4db94011d3 2201 /* FTM - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 2202 /** Peripheral FTM0 base address */
sahilmgandhi 18:6a4db94011d3 2203 #define FTM0_BASE (0x40038000u)
sahilmgandhi 18:6a4db94011d3 2204 /** Peripheral FTM0 base pointer */
sahilmgandhi 18:6a4db94011d3 2205 #define FTM0 ((FTM_Type *)FTM0_BASE)
sahilmgandhi 18:6a4db94011d3 2206 /** Peripheral FTM1 base address */
sahilmgandhi 18:6a4db94011d3 2207 #define FTM1_BASE (0x40039000u)
sahilmgandhi 18:6a4db94011d3 2208 /** Peripheral FTM1 base pointer */
sahilmgandhi 18:6a4db94011d3 2209 #define FTM1 ((FTM_Type *)FTM1_BASE)
sahilmgandhi 18:6a4db94011d3 2210
sahilmgandhi 18:6a4db94011d3 2211 /**
sahilmgandhi 18:6a4db94011d3 2212 * @}
sahilmgandhi 18:6a4db94011d3 2213 */ /* end of group FTM_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 2214
sahilmgandhi 18:6a4db94011d3 2215
sahilmgandhi 18:6a4db94011d3 2216 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 2217 -- GPIO Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 2218 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 2219
sahilmgandhi 18:6a4db94011d3 2220 /**
sahilmgandhi 18:6a4db94011d3 2221 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 2222 * @{
sahilmgandhi 18:6a4db94011d3 2223 */
sahilmgandhi 18:6a4db94011d3 2224
sahilmgandhi 18:6a4db94011d3 2225 /** GPIO - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 2226 typedef struct {
sahilmgandhi 18:6a4db94011d3 2227 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 2228 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
sahilmgandhi 18:6a4db94011d3 2229 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
sahilmgandhi 18:6a4db94011d3 2230 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
sahilmgandhi 18:6a4db94011d3 2231 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 2232 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 2233 } GPIO_Type;
sahilmgandhi 18:6a4db94011d3 2234
sahilmgandhi 18:6a4db94011d3 2235 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 2236 -- GPIO Register Masks
sahilmgandhi 18:6a4db94011d3 2237 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 2238
sahilmgandhi 18:6a4db94011d3 2239 /**
sahilmgandhi 18:6a4db94011d3 2240 * @addtogroup GPIO_Register_Masks GPIO Register Masks
sahilmgandhi 18:6a4db94011d3 2241 * @{
sahilmgandhi 18:6a4db94011d3 2242 */
sahilmgandhi 18:6a4db94011d3 2243
sahilmgandhi 18:6a4db94011d3 2244 /* PDOR Bit Fields */
sahilmgandhi 18:6a4db94011d3 2245 #define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 2246 #define GPIO_PDOR_PDO_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2247 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
sahilmgandhi 18:6a4db94011d3 2248 /* PSOR Bit Fields */
sahilmgandhi 18:6a4db94011d3 2249 #define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 2250 #define GPIO_PSOR_PTSO_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2251 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
sahilmgandhi 18:6a4db94011d3 2252 /* PCOR Bit Fields */
sahilmgandhi 18:6a4db94011d3 2253 #define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 2254 #define GPIO_PCOR_PTCO_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2255 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
sahilmgandhi 18:6a4db94011d3 2256 /* PTOR Bit Fields */
sahilmgandhi 18:6a4db94011d3 2257 #define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 2258 #define GPIO_PTOR_PTTO_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2259 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
sahilmgandhi 18:6a4db94011d3 2260 /* PDIR Bit Fields */
sahilmgandhi 18:6a4db94011d3 2261 #define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 2262 #define GPIO_PDIR_PDI_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2263 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
sahilmgandhi 18:6a4db94011d3 2264 /* PDDR Bit Fields */
sahilmgandhi 18:6a4db94011d3 2265 #define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 2266 #define GPIO_PDDR_PDD_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2267 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
sahilmgandhi 18:6a4db94011d3 2268
sahilmgandhi 18:6a4db94011d3 2269 /**
sahilmgandhi 18:6a4db94011d3 2270 * @}
sahilmgandhi 18:6a4db94011d3 2271 */ /* end of group GPIO_Register_Masks */
sahilmgandhi 18:6a4db94011d3 2272
sahilmgandhi 18:6a4db94011d3 2273
sahilmgandhi 18:6a4db94011d3 2274 /* GPIO - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 2275 /** Peripheral PTA base address */
sahilmgandhi 18:6a4db94011d3 2276 #define PTA_BASE (0x400FF000u)
sahilmgandhi 18:6a4db94011d3 2277 /** Peripheral PTA base pointer */
sahilmgandhi 18:6a4db94011d3 2278 #define PTA ((GPIO_Type *)PTA_BASE)
sahilmgandhi 18:6a4db94011d3 2279 /** Peripheral PTB base address */
sahilmgandhi 18:6a4db94011d3 2280 #define PTB_BASE (0x400FF040u)
sahilmgandhi 18:6a4db94011d3 2281 /** Peripheral PTB base pointer */
sahilmgandhi 18:6a4db94011d3 2282 #define PTB ((GPIO_Type *)PTB_BASE)
sahilmgandhi 18:6a4db94011d3 2283 /** Peripheral PTC base address */
sahilmgandhi 18:6a4db94011d3 2284 #define PTC_BASE (0x400FF080u)
sahilmgandhi 18:6a4db94011d3 2285 /** Peripheral PTC base pointer */
sahilmgandhi 18:6a4db94011d3 2286 #define PTC ((GPIO_Type *)PTC_BASE)
sahilmgandhi 18:6a4db94011d3 2287 /** Peripheral PTD base address */
sahilmgandhi 18:6a4db94011d3 2288 #define PTD_BASE (0x400FF0C0u)
sahilmgandhi 18:6a4db94011d3 2289 /** Peripheral PTD base pointer */
sahilmgandhi 18:6a4db94011d3 2290 #define PTD ((GPIO_Type *)PTD_BASE)
sahilmgandhi 18:6a4db94011d3 2291 /** Peripheral PTE base address */
sahilmgandhi 18:6a4db94011d3 2292 #define PTE_BASE (0x400FF100u)
sahilmgandhi 18:6a4db94011d3 2293 /** Peripheral PTE base pointer */
sahilmgandhi 18:6a4db94011d3 2294 #define PTE ((GPIO_Type *)PTE_BASE)
sahilmgandhi 18:6a4db94011d3 2295
sahilmgandhi 18:6a4db94011d3 2296 /**
sahilmgandhi 18:6a4db94011d3 2297 * @}
sahilmgandhi 18:6a4db94011d3 2298 */ /* end of group GPIO_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 2299
sahilmgandhi 18:6a4db94011d3 2300
sahilmgandhi 18:6a4db94011d3 2301 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 2302 -- I2C Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 2303 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 2304
sahilmgandhi 18:6a4db94011d3 2305 /**
sahilmgandhi 18:6a4db94011d3 2306 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 2307 * @{
sahilmgandhi 18:6a4db94011d3 2308 */
sahilmgandhi 18:6a4db94011d3 2309
sahilmgandhi 18:6a4db94011d3 2310 /** I2C - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 2311 typedef struct {
sahilmgandhi 18:6a4db94011d3 2312 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 2313 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
sahilmgandhi 18:6a4db94011d3 2314 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
sahilmgandhi 18:6a4db94011d3 2315 __IO uint8_t S; /**< I2C Status Register, offset: 0x3 */
sahilmgandhi 18:6a4db94011d3 2316 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
sahilmgandhi 18:6a4db94011d3 2317 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
sahilmgandhi 18:6a4db94011d3 2318 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
sahilmgandhi 18:6a4db94011d3 2319 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
sahilmgandhi 18:6a4db94011d3 2320 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
sahilmgandhi 18:6a4db94011d3 2321 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
sahilmgandhi 18:6a4db94011d3 2322 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
sahilmgandhi 18:6a4db94011d3 2323 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
sahilmgandhi 18:6a4db94011d3 2324 } I2C_Type;
sahilmgandhi 18:6a4db94011d3 2325
sahilmgandhi 18:6a4db94011d3 2326 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 2327 -- I2C Register Masks
sahilmgandhi 18:6a4db94011d3 2328 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 2329
sahilmgandhi 18:6a4db94011d3 2330 /**
sahilmgandhi 18:6a4db94011d3 2331 * @addtogroup I2C_Register_Masks I2C Register Masks
sahilmgandhi 18:6a4db94011d3 2332 * @{
sahilmgandhi 18:6a4db94011d3 2333 */
sahilmgandhi 18:6a4db94011d3 2334
sahilmgandhi 18:6a4db94011d3 2335 /* A1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 2336 #define I2C_A1_AD_MASK 0xFEu
sahilmgandhi 18:6a4db94011d3 2337 #define I2C_A1_AD_SHIFT 1
sahilmgandhi 18:6a4db94011d3 2338 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
sahilmgandhi 18:6a4db94011d3 2339 /* F Bit Fields */
sahilmgandhi 18:6a4db94011d3 2340 #define I2C_F_ICR_MASK 0x3Fu
sahilmgandhi 18:6a4db94011d3 2341 #define I2C_F_ICR_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2342 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
sahilmgandhi 18:6a4db94011d3 2343 #define I2C_F_MULT_MASK 0xC0u
sahilmgandhi 18:6a4db94011d3 2344 #define I2C_F_MULT_SHIFT 6
sahilmgandhi 18:6a4db94011d3 2345 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
sahilmgandhi 18:6a4db94011d3 2346 /* C1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 2347 #define I2C_C1_DMAEN_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 2348 #define I2C_C1_DMAEN_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2349 #define I2C_C1_WUEN_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 2350 #define I2C_C1_WUEN_SHIFT 1
sahilmgandhi 18:6a4db94011d3 2351 #define I2C_C1_RSTA_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 2352 #define I2C_C1_RSTA_SHIFT 2
sahilmgandhi 18:6a4db94011d3 2353 #define I2C_C1_TXAK_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 2354 #define I2C_C1_TXAK_SHIFT 3
sahilmgandhi 18:6a4db94011d3 2355 #define I2C_C1_TX_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 2356 #define I2C_C1_TX_SHIFT 4
sahilmgandhi 18:6a4db94011d3 2357 #define I2C_C1_MST_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 2358 #define I2C_C1_MST_SHIFT 5
sahilmgandhi 18:6a4db94011d3 2359 #define I2C_C1_IICIE_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 2360 #define I2C_C1_IICIE_SHIFT 6
sahilmgandhi 18:6a4db94011d3 2361 #define I2C_C1_IICEN_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 2362 #define I2C_C1_IICEN_SHIFT 7
sahilmgandhi 18:6a4db94011d3 2363 /* S Bit Fields */
sahilmgandhi 18:6a4db94011d3 2364 #define I2C_S_RXAK_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 2365 #define I2C_S_RXAK_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2366 #define I2C_S_IICIF_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 2367 #define I2C_S_IICIF_SHIFT 1
sahilmgandhi 18:6a4db94011d3 2368 #define I2C_S_SRW_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 2369 #define I2C_S_SRW_SHIFT 2
sahilmgandhi 18:6a4db94011d3 2370 #define I2C_S_RAM_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 2371 #define I2C_S_RAM_SHIFT 3
sahilmgandhi 18:6a4db94011d3 2372 #define I2C_S_ARBL_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 2373 #define I2C_S_ARBL_SHIFT 4
sahilmgandhi 18:6a4db94011d3 2374 #define I2C_S_BUSY_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 2375 #define I2C_S_BUSY_SHIFT 5
sahilmgandhi 18:6a4db94011d3 2376 #define I2C_S_IAAS_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 2377 #define I2C_S_IAAS_SHIFT 6
sahilmgandhi 18:6a4db94011d3 2378 #define I2C_S_TCF_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 2379 #define I2C_S_TCF_SHIFT 7
sahilmgandhi 18:6a4db94011d3 2380 /* D Bit Fields */
sahilmgandhi 18:6a4db94011d3 2381 #define I2C_D_DATA_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 2382 #define I2C_D_DATA_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2383 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
sahilmgandhi 18:6a4db94011d3 2384 /* C2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 2385 #define I2C_C2_AD_MASK 0x7u
sahilmgandhi 18:6a4db94011d3 2386 #define I2C_C2_AD_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2387 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
sahilmgandhi 18:6a4db94011d3 2388 #define I2C_C2_RMEN_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 2389 #define I2C_C2_RMEN_SHIFT 3
sahilmgandhi 18:6a4db94011d3 2390 #define I2C_C2_SBRC_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 2391 #define I2C_C2_SBRC_SHIFT 4
sahilmgandhi 18:6a4db94011d3 2392 #define I2C_C2_HDRS_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 2393 #define I2C_C2_HDRS_SHIFT 5
sahilmgandhi 18:6a4db94011d3 2394 #define I2C_C2_ADEXT_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 2395 #define I2C_C2_ADEXT_SHIFT 6
sahilmgandhi 18:6a4db94011d3 2396 #define I2C_C2_GCAEN_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 2397 #define I2C_C2_GCAEN_SHIFT 7
sahilmgandhi 18:6a4db94011d3 2398 /* FLT Bit Fields */
sahilmgandhi 18:6a4db94011d3 2399 #define I2C_FLT_FLT_MASK 0x1Fu
sahilmgandhi 18:6a4db94011d3 2400 #define I2C_FLT_FLT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2401 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
sahilmgandhi 18:6a4db94011d3 2402 /* RA Bit Fields */
sahilmgandhi 18:6a4db94011d3 2403 #define I2C_RA_RAD_MASK 0xFEu
sahilmgandhi 18:6a4db94011d3 2404 #define I2C_RA_RAD_SHIFT 1
sahilmgandhi 18:6a4db94011d3 2405 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
sahilmgandhi 18:6a4db94011d3 2406 /* SMB Bit Fields */
sahilmgandhi 18:6a4db94011d3 2407 #define I2C_SMB_SHTF2IE_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 2408 #define I2C_SMB_SHTF2IE_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2409 #define I2C_SMB_SHTF2_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 2410 #define I2C_SMB_SHTF2_SHIFT 1
sahilmgandhi 18:6a4db94011d3 2411 #define I2C_SMB_SHTF1_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 2412 #define I2C_SMB_SHTF1_SHIFT 2
sahilmgandhi 18:6a4db94011d3 2413 #define I2C_SMB_SLTF_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 2414 #define I2C_SMB_SLTF_SHIFT 3
sahilmgandhi 18:6a4db94011d3 2415 #define I2C_SMB_TCKSEL_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 2416 #define I2C_SMB_TCKSEL_SHIFT 4
sahilmgandhi 18:6a4db94011d3 2417 #define I2C_SMB_SIICAEN_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 2418 #define I2C_SMB_SIICAEN_SHIFT 5
sahilmgandhi 18:6a4db94011d3 2419 #define I2C_SMB_ALERTEN_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 2420 #define I2C_SMB_ALERTEN_SHIFT 6
sahilmgandhi 18:6a4db94011d3 2421 #define I2C_SMB_FACK_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 2422 #define I2C_SMB_FACK_SHIFT 7
sahilmgandhi 18:6a4db94011d3 2423 /* A2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 2424 #define I2C_A2_SAD_MASK 0xFEu
sahilmgandhi 18:6a4db94011d3 2425 #define I2C_A2_SAD_SHIFT 1
sahilmgandhi 18:6a4db94011d3 2426 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
sahilmgandhi 18:6a4db94011d3 2427 /* SLTH Bit Fields */
sahilmgandhi 18:6a4db94011d3 2428 #define I2C_SLTH_SSLT_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 2429 #define I2C_SLTH_SSLT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2430 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
sahilmgandhi 18:6a4db94011d3 2431 /* SLTL Bit Fields */
sahilmgandhi 18:6a4db94011d3 2432 #define I2C_SLTL_SSLT_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 2433 #define I2C_SLTL_SSLT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2434 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
sahilmgandhi 18:6a4db94011d3 2435
sahilmgandhi 18:6a4db94011d3 2436 /**
sahilmgandhi 18:6a4db94011d3 2437 * @}
sahilmgandhi 18:6a4db94011d3 2438 */ /* end of group I2C_Register_Masks */
sahilmgandhi 18:6a4db94011d3 2439
sahilmgandhi 18:6a4db94011d3 2440
sahilmgandhi 18:6a4db94011d3 2441 /* I2C - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 2442 /** Peripheral I2C0 base address */
sahilmgandhi 18:6a4db94011d3 2443 #define I2C0_BASE (0x40066000u)
sahilmgandhi 18:6a4db94011d3 2444 #define I2C1_BASE (0x40067000u)
sahilmgandhi 18:6a4db94011d3 2445 /** Peripheral I2C0 base pointer */
sahilmgandhi 18:6a4db94011d3 2446 #define I2C0 ((I2C_Type *)I2C0_BASE)
sahilmgandhi 18:6a4db94011d3 2447 #define I2C1 ((I2C_Type *)I2C1_BASE)
sahilmgandhi 18:6a4db94011d3 2448 /**
sahilmgandhi 18:6a4db94011d3 2449 * @}
sahilmgandhi 18:6a4db94011d3 2450 */ /* end of group I2C_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 2451
sahilmgandhi 18:6a4db94011d3 2452
sahilmgandhi 18:6a4db94011d3 2453 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 2454 -- I2S Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 2455 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 2456
sahilmgandhi 18:6a4db94011d3 2457 /**
sahilmgandhi 18:6a4db94011d3 2458 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 2459 * @{
sahilmgandhi 18:6a4db94011d3 2460 */
sahilmgandhi 18:6a4db94011d3 2461
sahilmgandhi 18:6a4db94011d3 2462 /** I2S - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 2463 typedef struct {
sahilmgandhi 18:6a4db94011d3 2464 __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 2465 __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
sahilmgandhi 18:6a4db94011d3 2466 __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
sahilmgandhi 18:6a4db94011d3 2467 __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
sahilmgandhi 18:6a4db94011d3 2468 __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 2469 __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 2470 uint8_t RESERVED_0[8];
sahilmgandhi 18:6a4db94011d3 2471 __O uint32_t TDR[2]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
sahilmgandhi 18:6a4db94011d3 2472 uint8_t RESERVED_1[24];
sahilmgandhi 18:6a4db94011d3 2473 __I uint32_t TFR[2]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
sahilmgandhi 18:6a4db94011d3 2474 uint8_t RESERVED_2[24];
sahilmgandhi 18:6a4db94011d3 2475 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
sahilmgandhi 18:6a4db94011d3 2476 uint8_t RESERVED_3[28];
sahilmgandhi 18:6a4db94011d3 2477 __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
sahilmgandhi 18:6a4db94011d3 2478 __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */
sahilmgandhi 18:6a4db94011d3 2479 __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
sahilmgandhi 18:6a4db94011d3 2480 __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
sahilmgandhi 18:6a4db94011d3 2481 __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
sahilmgandhi 18:6a4db94011d3 2482 __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
sahilmgandhi 18:6a4db94011d3 2483 uint8_t RESERVED_4[8];
sahilmgandhi 18:6a4db94011d3 2484 __I uint32_t RDR[2]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
sahilmgandhi 18:6a4db94011d3 2485 uint8_t RESERVED_5[24];
sahilmgandhi 18:6a4db94011d3 2486 __I uint32_t RFR[2]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
sahilmgandhi 18:6a4db94011d3 2487 uint8_t RESERVED_6[24];
sahilmgandhi 18:6a4db94011d3 2488 __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
sahilmgandhi 18:6a4db94011d3 2489 uint8_t RESERVED_7[28];
sahilmgandhi 18:6a4db94011d3 2490 __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
sahilmgandhi 18:6a4db94011d3 2491 __IO uint32_t MDR; /**< MCLK Divide Register, offset: 0x104 */
sahilmgandhi 18:6a4db94011d3 2492 } I2S_Type;
sahilmgandhi 18:6a4db94011d3 2493
sahilmgandhi 18:6a4db94011d3 2494 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 2495 -- I2S Register Masks
sahilmgandhi 18:6a4db94011d3 2496 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 2497
sahilmgandhi 18:6a4db94011d3 2498 /**
sahilmgandhi 18:6a4db94011d3 2499 * @addtogroup I2S_Register_Masks I2S Register Masks
sahilmgandhi 18:6a4db94011d3 2500 * @{
sahilmgandhi 18:6a4db94011d3 2501 */
sahilmgandhi 18:6a4db94011d3 2502
sahilmgandhi 18:6a4db94011d3 2503 /* TCSR Bit Fields */
sahilmgandhi 18:6a4db94011d3 2504 #define I2S_TCSR_FRDE_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 2505 #define I2S_TCSR_FRDE_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2506 #define I2S_TCSR_FWDE_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 2507 #define I2S_TCSR_FWDE_SHIFT 1
sahilmgandhi 18:6a4db94011d3 2508 #define I2S_TCSR_FRIE_MASK 0x100u
sahilmgandhi 18:6a4db94011d3 2509 #define I2S_TCSR_FRIE_SHIFT 8
sahilmgandhi 18:6a4db94011d3 2510 #define I2S_TCSR_FWIE_MASK 0x200u
sahilmgandhi 18:6a4db94011d3 2511 #define I2S_TCSR_FWIE_SHIFT 9
sahilmgandhi 18:6a4db94011d3 2512 #define I2S_TCSR_FEIE_MASK 0x400u
sahilmgandhi 18:6a4db94011d3 2513 #define I2S_TCSR_FEIE_SHIFT 10
sahilmgandhi 18:6a4db94011d3 2514 #define I2S_TCSR_SEIE_MASK 0x800u
sahilmgandhi 18:6a4db94011d3 2515 #define I2S_TCSR_SEIE_SHIFT 11
sahilmgandhi 18:6a4db94011d3 2516 #define I2S_TCSR_WSIE_MASK 0x1000u
sahilmgandhi 18:6a4db94011d3 2517 #define I2S_TCSR_WSIE_SHIFT 12
sahilmgandhi 18:6a4db94011d3 2518 #define I2S_TCSR_FRF_MASK 0x10000u
sahilmgandhi 18:6a4db94011d3 2519 #define I2S_TCSR_FRF_SHIFT 16
sahilmgandhi 18:6a4db94011d3 2520 #define I2S_TCSR_FWF_MASK 0x20000u
sahilmgandhi 18:6a4db94011d3 2521 #define I2S_TCSR_FWF_SHIFT 17
sahilmgandhi 18:6a4db94011d3 2522 #define I2S_TCSR_FEF_MASK 0x40000u
sahilmgandhi 18:6a4db94011d3 2523 #define I2S_TCSR_FEF_SHIFT 18
sahilmgandhi 18:6a4db94011d3 2524 #define I2S_TCSR_SEF_MASK 0x80000u
sahilmgandhi 18:6a4db94011d3 2525 #define I2S_TCSR_SEF_SHIFT 19
sahilmgandhi 18:6a4db94011d3 2526 #define I2S_TCSR_WSF_MASK 0x100000u
sahilmgandhi 18:6a4db94011d3 2527 #define I2S_TCSR_WSF_SHIFT 20
sahilmgandhi 18:6a4db94011d3 2528 #define I2S_TCSR_SR_MASK 0x1000000u
sahilmgandhi 18:6a4db94011d3 2529 #define I2S_TCSR_SR_SHIFT 24
sahilmgandhi 18:6a4db94011d3 2530 #define I2S_TCSR_FR_MASK 0x2000000u
sahilmgandhi 18:6a4db94011d3 2531 #define I2S_TCSR_FR_SHIFT 25
sahilmgandhi 18:6a4db94011d3 2532 #define I2S_TCSR_BCE_MASK 0x10000000u
sahilmgandhi 18:6a4db94011d3 2533 #define I2S_TCSR_BCE_SHIFT 28
sahilmgandhi 18:6a4db94011d3 2534 #define I2S_TCSR_DBGE_MASK 0x20000000u
sahilmgandhi 18:6a4db94011d3 2535 #define I2S_TCSR_DBGE_SHIFT 29
sahilmgandhi 18:6a4db94011d3 2536 #define I2S_TCSR_STOPE_MASK 0x40000000u
sahilmgandhi 18:6a4db94011d3 2537 #define I2S_TCSR_STOPE_SHIFT 30
sahilmgandhi 18:6a4db94011d3 2538 #define I2S_TCSR_TE_MASK 0x80000000u
sahilmgandhi 18:6a4db94011d3 2539 #define I2S_TCSR_TE_SHIFT 31
sahilmgandhi 18:6a4db94011d3 2540 /* TCR1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 2541 #define I2S_TCR1_TFW_MASK 0x7u
sahilmgandhi 18:6a4db94011d3 2542 #define I2S_TCR1_TFW_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2543 #define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR1_TFW_SHIFT))&I2S_TCR1_TFW_MASK)
sahilmgandhi 18:6a4db94011d3 2544 /* TCR2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 2545 #define I2S_TCR2_DIV_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 2546 #define I2S_TCR2_DIV_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2547 #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
sahilmgandhi 18:6a4db94011d3 2548 #define I2S_TCR2_BCD_MASK 0x1000000u
sahilmgandhi 18:6a4db94011d3 2549 #define I2S_TCR2_BCD_SHIFT 24
sahilmgandhi 18:6a4db94011d3 2550 #define I2S_TCR2_BCP_MASK 0x2000000u
sahilmgandhi 18:6a4db94011d3 2551 #define I2S_TCR2_BCP_SHIFT 25
sahilmgandhi 18:6a4db94011d3 2552 #define I2S_TCR2_MSEL_MASK 0xC000000u
sahilmgandhi 18:6a4db94011d3 2553 #define I2S_TCR2_MSEL_SHIFT 26
sahilmgandhi 18:6a4db94011d3 2554 #define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK)
sahilmgandhi 18:6a4db94011d3 2555 #define I2S_TCR2_BCI_MASK 0x10000000u
sahilmgandhi 18:6a4db94011d3 2556 #define I2S_TCR2_BCI_SHIFT 28
sahilmgandhi 18:6a4db94011d3 2557 #define I2S_TCR2_BCS_MASK 0x20000000u
sahilmgandhi 18:6a4db94011d3 2558 #define I2S_TCR2_BCS_SHIFT 29
sahilmgandhi 18:6a4db94011d3 2559 #define I2S_TCR2_SYNC_MASK 0xC0000000u
sahilmgandhi 18:6a4db94011d3 2560 #define I2S_TCR2_SYNC_SHIFT 30
sahilmgandhi 18:6a4db94011d3 2561 #define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK)
sahilmgandhi 18:6a4db94011d3 2562 /* TCR3 Bit Fields */
sahilmgandhi 18:6a4db94011d3 2563 #define I2S_TCR3_WDFL_MASK 0x1Fu
sahilmgandhi 18:6a4db94011d3 2564 #define I2S_TCR3_WDFL_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2565 #define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_WDFL_SHIFT))&I2S_TCR3_WDFL_MASK)
sahilmgandhi 18:6a4db94011d3 2566 #define I2S_TCR3_TCE_MASK 0x30000u
sahilmgandhi 18:6a4db94011d3 2567 #define I2S_TCR3_TCE_SHIFT 16
sahilmgandhi 18:6a4db94011d3 2568 #define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_TCE_SHIFT))&I2S_TCR3_TCE_MASK)
sahilmgandhi 18:6a4db94011d3 2569 /* TCR4 Bit Fields */
sahilmgandhi 18:6a4db94011d3 2570 #define I2S_TCR4_FSD_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 2571 #define I2S_TCR4_FSD_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2572 #define I2S_TCR4_FSP_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 2573 #define I2S_TCR4_FSP_SHIFT 1
sahilmgandhi 18:6a4db94011d3 2574 #define I2S_TCR4_FSE_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 2575 #define I2S_TCR4_FSE_SHIFT 3
sahilmgandhi 18:6a4db94011d3 2576 #define I2S_TCR4_MF_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 2577 #define I2S_TCR4_MF_SHIFT 4
sahilmgandhi 18:6a4db94011d3 2578 #define I2S_TCR4_SYWD_MASK 0x1F00u
sahilmgandhi 18:6a4db94011d3 2579 #define I2S_TCR4_SYWD_SHIFT 8
sahilmgandhi 18:6a4db94011d3 2580 #define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
sahilmgandhi 18:6a4db94011d3 2581 #define I2S_TCR4_FRSZ_MASK 0x1F0000u
sahilmgandhi 18:6a4db94011d3 2582 #define I2S_TCR4_FRSZ_SHIFT 16
sahilmgandhi 18:6a4db94011d3 2583 #define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FRSZ_SHIFT))&I2S_TCR4_FRSZ_MASK)
sahilmgandhi 18:6a4db94011d3 2584 /* TCR5 Bit Fields */
sahilmgandhi 18:6a4db94011d3 2585 #define I2S_TCR5_FBT_MASK 0x1F00u
sahilmgandhi 18:6a4db94011d3 2586 #define I2S_TCR5_FBT_SHIFT 8
sahilmgandhi 18:6a4db94011d3 2587 #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
sahilmgandhi 18:6a4db94011d3 2588 #define I2S_TCR5_W0W_MASK 0x1F0000u
sahilmgandhi 18:6a4db94011d3 2589 #define I2S_TCR5_W0W_SHIFT 16
sahilmgandhi 18:6a4db94011d3 2590 #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
sahilmgandhi 18:6a4db94011d3 2591 #define I2S_TCR5_WNW_MASK 0x1F000000u
sahilmgandhi 18:6a4db94011d3 2592 #define I2S_TCR5_WNW_SHIFT 24
sahilmgandhi 18:6a4db94011d3 2593 #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
sahilmgandhi 18:6a4db94011d3 2594 /* TDR Bit Fields */
sahilmgandhi 18:6a4db94011d3 2595 #define I2S_TDR_TDR_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 2596 #define I2S_TDR_TDR_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2597 #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
sahilmgandhi 18:6a4db94011d3 2598 /* TFR Bit Fields */
sahilmgandhi 18:6a4db94011d3 2599 #define I2S_TFR_RFP_MASK 0xFu
sahilmgandhi 18:6a4db94011d3 2600 #define I2S_TFR_RFP_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2601 #define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_RFP_SHIFT))&I2S_TFR_RFP_MASK)
sahilmgandhi 18:6a4db94011d3 2602 #define I2S_TFR_WFP_MASK 0xF0000u
sahilmgandhi 18:6a4db94011d3 2603 #define I2S_TFR_WFP_SHIFT 16
sahilmgandhi 18:6a4db94011d3 2604 #define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_WFP_SHIFT))&I2S_TFR_WFP_MASK)
sahilmgandhi 18:6a4db94011d3 2605 /* TMR Bit Fields */
sahilmgandhi 18:6a4db94011d3 2606 #define I2S_TMR_TWM_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 2607 #define I2S_TMR_TWM_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2608 #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
sahilmgandhi 18:6a4db94011d3 2609 /* RCSR Bit Fields */
sahilmgandhi 18:6a4db94011d3 2610 #define I2S_RCSR_FRDE_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 2611 #define I2S_RCSR_FRDE_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2612 #define I2S_RCSR_FWDE_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 2613 #define I2S_RCSR_FWDE_SHIFT 1
sahilmgandhi 18:6a4db94011d3 2614 #define I2S_RCSR_FRIE_MASK 0x100u
sahilmgandhi 18:6a4db94011d3 2615 #define I2S_RCSR_FRIE_SHIFT 8
sahilmgandhi 18:6a4db94011d3 2616 #define I2S_RCSR_FWIE_MASK 0x200u
sahilmgandhi 18:6a4db94011d3 2617 #define I2S_RCSR_FWIE_SHIFT 9
sahilmgandhi 18:6a4db94011d3 2618 #define I2S_RCSR_FEIE_MASK 0x400u
sahilmgandhi 18:6a4db94011d3 2619 #define I2S_RCSR_FEIE_SHIFT 10
sahilmgandhi 18:6a4db94011d3 2620 #define I2S_RCSR_SEIE_MASK 0x800u
sahilmgandhi 18:6a4db94011d3 2621 #define I2S_RCSR_SEIE_SHIFT 11
sahilmgandhi 18:6a4db94011d3 2622 #define I2S_RCSR_WSIE_MASK 0x1000u
sahilmgandhi 18:6a4db94011d3 2623 #define I2S_RCSR_WSIE_SHIFT 12
sahilmgandhi 18:6a4db94011d3 2624 #define I2S_RCSR_FRF_MASK 0x10000u
sahilmgandhi 18:6a4db94011d3 2625 #define I2S_RCSR_FRF_SHIFT 16
sahilmgandhi 18:6a4db94011d3 2626 #define I2S_RCSR_FWF_MASK 0x20000u
sahilmgandhi 18:6a4db94011d3 2627 #define I2S_RCSR_FWF_SHIFT 17
sahilmgandhi 18:6a4db94011d3 2628 #define I2S_RCSR_FEF_MASK 0x40000u
sahilmgandhi 18:6a4db94011d3 2629 #define I2S_RCSR_FEF_SHIFT 18
sahilmgandhi 18:6a4db94011d3 2630 #define I2S_RCSR_SEF_MASK 0x80000u
sahilmgandhi 18:6a4db94011d3 2631 #define I2S_RCSR_SEF_SHIFT 19
sahilmgandhi 18:6a4db94011d3 2632 #define I2S_RCSR_WSF_MASK 0x100000u
sahilmgandhi 18:6a4db94011d3 2633 #define I2S_RCSR_WSF_SHIFT 20
sahilmgandhi 18:6a4db94011d3 2634 #define I2S_RCSR_SR_MASK 0x1000000u
sahilmgandhi 18:6a4db94011d3 2635 #define I2S_RCSR_SR_SHIFT 24
sahilmgandhi 18:6a4db94011d3 2636 #define I2S_RCSR_FR_MASK 0x2000000u
sahilmgandhi 18:6a4db94011d3 2637 #define I2S_RCSR_FR_SHIFT 25
sahilmgandhi 18:6a4db94011d3 2638 #define I2S_RCSR_BCE_MASK 0x10000000u
sahilmgandhi 18:6a4db94011d3 2639 #define I2S_RCSR_BCE_SHIFT 28
sahilmgandhi 18:6a4db94011d3 2640 #define I2S_RCSR_DBGE_MASK 0x20000000u
sahilmgandhi 18:6a4db94011d3 2641 #define I2S_RCSR_DBGE_SHIFT 29
sahilmgandhi 18:6a4db94011d3 2642 #define I2S_RCSR_STOPE_MASK 0x40000000u
sahilmgandhi 18:6a4db94011d3 2643 #define I2S_RCSR_STOPE_SHIFT 30
sahilmgandhi 18:6a4db94011d3 2644 #define I2S_RCSR_RE_MASK 0x80000000u
sahilmgandhi 18:6a4db94011d3 2645 #define I2S_RCSR_RE_SHIFT 31
sahilmgandhi 18:6a4db94011d3 2646 /* RCR1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 2647 #define I2S_RCR1_RFW_MASK 0x7u
sahilmgandhi 18:6a4db94011d3 2648 #define I2S_RCR1_RFW_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2649 #define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR1_RFW_SHIFT))&I2S_RCR1_RFW_MASK)
sahilmgandhi 18:6a4db94011d3 2650 /* RCR2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 2651 #define I2S_RCR2_DIV_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 2652 #define I2S_RCR2_DIV_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2653 #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
sahilmgandhi 18:6a4db94011d3 2654 #define I2S_RCR2_BCD_MASK 0x1000000u
sahilmgandhi 18:6a4db94011d3 2655 #define I2S_RCR2_BCD_SHIFT 24
sahilmgandhi 18:6a4db94011d3 2656 #define I2S_RCR2_BCP_MASK 0x2000000u
sahilmgandhi 18:6a4db94011d3 2657 #define I2S_RCR2_BCP_SHIFT 25
sahilmgandhi 18:6a4db94011d3 2658 #define I2S_RCR2_MSEL_MASK 0xC000000u
sahilmgandhi 18:6a4db94011d3 2659 #define I2S_RCR2_MSEL_SHIFT 26
sahilmgandhi 18:6a4db94011d3 2660 #define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK)
sahilmgandhi 18:6a4db94011d3 2661 #define I2S_RCR2_BCI_MASK 0x10000000u
sahilmgandhi 18:6a4db94011d3 2662 #define I2S_RCR2_BCI_SHIFT 28
sahilmgandhi 18:6a4db94011d3 2663 #define I2S_RCR2_BCS_MASK 0x20000000u
sahilmgandhi 18:6a4db94011d3 2664 #define I2S_RCR2_BCS_SHIFT 29
sahilmgandhi 18:6a4db94011d3 2665 #define I2S_RCR2_SYNC_MASK 0xC0000000u
sahilmgandhi 18:6a4db94011d3 2666 #define I2S_RCR2_SYNC_SHIFT 30
sahilmgandhi 18:6a4db94011d3 2667 #define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK)
sahilmgandhi 18:6a4db94011d3 2668 /* RCR3 Bit Fields */
sahilmgandhi 18:6a4db94011d3 2669 #define I2S_RCR3_WDFL_MASK 0x1Fu
sahilmgandhi 18:6a4db94011d3 2670 #define I2S_RCR3_WDFL_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2671 #define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_WDFL_SHIFT))&I2S_RCR3_WDFL_MASK)
sahilmgandhi 18:6a4db94011d3 2672 #define I2S_RCR3_RCE_MASK 0x30000u
sahilmgandhi 18:6a4db94011d3 2673 #define I2S_RCR3_RCE_SHIFT 16
sahilmgandhi 18:6a4db94011d3 2674 #define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_RCE_SHIFT))&I2S_RCR3_RCE_MASK)
sahilmgandhi 18:6a4db94011d3 2675 /* RCR4 Bit Fields */
sahilmgandhi 18:6a4db94011d3 2676 #define I2S_RCR4_FSD_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 2677 #define I2S_RCR4_FSD_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2678 #define I2S_RCR4_FSP_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 2679 #define I2S_RCR4_FSP_SHIFT 1
sahilmgandhi 18:6a4db94011d3 2680 #define I2S_RCR4_FSE_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 2681 #define I2S_RCR4_FSE_SHIFT 3
sahilmgandhi 18:6a4db94011d3 2682 #define I2S_RCR4_MF_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 2683 #define I2S_RCR4_MF_SHIFT 4
sahilmgandhi 18:6a4db94011d3 2684 #define I2S_RCR4_SYWD_MASK 0x1F00u
sahilmgandhi 18:6a4db94011d3 2685 #define I2S_RCR4_SYWD_SHIFT 8
sahilmgandhi 18:6a4db94011d3 2686 #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
sahilmgandhi 18:6a4db94011d3 2687 #define I2S_RCR4_FRSZ_MASK 0x1F0000u
sahilmgandhi 18:6a4db94011d3 2688 #define I2S_RCR4_FRSZ_SHIFT 16
sahilmgandhi 18:6a4db94011d3 2689 #define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FRSZ_SHIFT))&I2S_RCR4_FRSZ_MASK)
sahilmgandhi 18:6a4db94011d3 2690 /* RCR5 Bit Fields */
sahilmgandhi 18:6a4db94011d3 2691 #define I2S_RCR5_FBT_MASK 0x1F00u
sahilmgandhi 18:6a4db94011d3 2692 #define I2S_RCR5_FBT_SHIFT 8
sahilmgandhi 18:6a4db94011d3 2693 #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
sahilmgandhi 18:6a4db94011d3 2694 #define I2S_RCR5_W0W_MASK 0x1F0000u
sahilmgandhi 18:6a4db94011d3 2695 #define I2S_RCR5_W0W_SHIFT 16
sahilmgandhi 18:6a4db94011d3 2696 #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
sahilmgandhi 18:6a4db94011d3 2697 #define I2S_RCR5_WNW_MASK 0x1F000000u
sahilmgandhi 18:6a4db94011d3 2698 #define I2S_RCR5_WNW_SHIFT 24
sahilmgandhi 18:6a4db94011d3 2699 #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
sahilmgandhi 18:6a4db94011d3 2700 /* RDR Bit Fields */
sahilmgandhi 18:6a4db94011d3 2701 #define I2S_RDR_RDR_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 2702 #define I2S_RDR_RDR_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2703 #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
sahilmgandhi 18:6a4db94011d3 2704 /* RFR Bit Fields */
sahilmgandhi 18:6a4db94011d3 2705 #define I2S_RFR_RFP_MASK 0xFu
sahilmgandhi 18:6a4db94011d3 2706 #define I2S_RFR_RFP_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2707 #define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_RFP_SHIFT))&I2S_RFR_RFP_MASK)
sahilmgandhi 18:6a4db94011d3 2708 #define I2S_RFR_WFP_MASK 0xF0000u
sahilmgandhi 18:6a4db94011d3 2709 #define I2S_RFR_WFP_SHIFT 16
sahilmgandhi 18:6a4db94011d3 2710 #define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_WFP_SHIFT))&I2S_RFR_WFP_MASK)
sahilmgandhi 18:6a4db94011d3 2711 /* RMR Bit Fields */
sahilmgandhi 18:6a4db94011d3 2712 #define I2S_RMR_RWM_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 2713 #define I2S_RMR_RWM_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2714 #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
sahilmgandhi 18:6a4db94011d3 2715 /* MCR Bit Fields */
sahilmgandhi 18:6a4db94011d3 2716 #define I2S_MCR_MICS_MASK 0x3000000u
sahilmgandhi 18:6a4db94011d3 2717 #define I2S_MCR_MICS_SHIFT 24
sahilmgandhi 18:6a4db94011d3 2718 #define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
sahilmgandhi 18:6a4db94011d3 2719 #define I2S_MCR_MOE_MASK 0x40000000u
sahilmgandhi 18:6a4db94011d3 2720 #define I2S_MCR_MOE_SHIFT 30
sahilmgandhi 18:6a4db94011d3 2721 #define I2S_MCR_DUF_MASK 0x80000000u
sahilmgandhi 18:6a4db94011d3 2722 #define I2S_MCR_DUF_SHIFT 31
sahilmgandhi 18:6a4db94011d3 2723 /* MDR Bit Fields */
sahilmgandhi 18:6a4db94011d3 2724 #define I2S_MDR_DIVIDE_MASK 0xFFFu
sahilmgandhi 18:6a4db94011d3 2725 #define I2S_MDR_DIVIDE_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2726 #define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)
sahilmgandhi 18:6a4db94011d3 2727 #define I2S_MDR_FRACT_MASK 0xFF000u
sahilmgandhi 18:6a4db94011d3 2728 #define I2S_MDR_FRACT_SHIFT 12
sahilmgandhi 18:6a4db94011d3 2729 #define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
sahilmgandhi 18:6a4db94011d3 2730
sahilmgandhi 18:6a4db94011d3 2731 /**
sahilmgandhi 18:6a4db94011d3 2732 * @}
sahilmgandhi 18:6a4db94011d3 2733 */ /* end of group I2S_Register_Masks */
sahilmgandhi 18:6a4db94011d3 2734
sahilmgandhi 18:6a4db94011d3 2735
sahilmgandhi 18:6a4db94011d3 2736 /* I2S - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 2737 /** Peripheral I2S0 base address */
sahilmgandhi 18:6a4db94011d3 2738 #define I2S0_BASE (0x4002F000u)
sahilmgandhi 18:6a4db94011d3 2739 /** Peripheral I2S0 base pointer */
sahilmgandhi 18:6a4db94011d3 2740 #define I2S0 ((I2S_Type *)I2S0_BASE)
sahilmgandhi 18:6a4db94011d3 2741
sahilmgandhi 18:6a4db94011d3 2742 /**
sahilmgandhi 18:6a4db94011d3 2743 * @}
sahilmgandhi 18:6a4db94011d3 2744 */ /* end of group I2S_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 2745
sahilmgandhi 18:6a4db94011d3 2746
sahilmgandhi 18:6a4db94011d3 2747 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 2748 -- LLWU Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 2749 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 2750
sahilmgandhi 18:6a4db94011d3 2751 /**
sahilmgandhi 18:6a4db94011d3 2752 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 2753 * @{
sahilmgandhi 18:6a4db94011d3 2754 */
sahilmgandhi 18:6a4db94011d3 2755
sahilmgandhi 18:6a4db94011d3 2756 /** LLWU - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 2757 typedef struct {
sahilmgandhi 18:6a4db94011d3 2758 __IO uint8_t PE1; /**< LLWU Pin Enable 1 Register, offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 2759 __IO uint8_t PE2; /**< LLWU Pin Enable 2 Register, offset: 0x1 */
sahilmgandhi 18:6a4db94011d3 2760 __IO uint8_t PE3; /**< LLWU Pin Enable 3 Register, offset: 0x2 */
sahilmgandhi 18:6a4db94011d3 2761 __IO uint8_t PE4; /**< LLWU Pin Enable 4 Register, offset: 0x3 */
sahilmgandhi 18:6a4db94011d3 2762 __IO uint8_t ME; /**< LLWU Module Enable Register, offset: 0x4 */
sahilmgandhi 18:6a4db94011d3 2763 __IO uint8_t F1; /**< LLWU Flag 1 Register, offset: 0x5 */
sahilmgandhi 18:6a4db94011d3 2764 __IO uint8_t F2; /**< LLWU Flag 2 Register, offset: 0x6 */
sahilmgandhi 18:6a4db94011d3 2765 __I uint8_t F3; /**< LLWU Flag 3 Register, offset: 0x7 */
sahilmgandhi 18:6a4db94011d3 2766 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 Register, offset: 0x8 */
sahilmgandhi 18:6a4db94011d3 2767 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 Register, offset: 0x9 */
sahilmgandhi 18:6a4db94011d3 2768 __IO uint8_t RST; /**< LLWU Reset Enable Register, offset: 0xA */
sahilmgandhi 18:6a4db94011d3 2769 } LLWU_Type;
sahilmgandhi 18:6a4db94011d3 2770
sahilmgandhi 18:6a4db94011d3 2771 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 2772 -- LLWU Register Masks
sahilmgandhi 18:6a4db94011d3 2773 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 2774
sahilmgandhi 18:6a4db94011d3 2775 /**
sahilmgandhi 18:6a4db94011d3 2776 * @addtogroup LLWU_Register_Masks LLWU Register Masks
sahilmgandhi 18:6a4db94011d3 2777 * @{
sahilmgandhi 18:6a4db94011d3 2778 */
sahilmgandhi 18:6a4db94011d3 2779
sahilmgandhi 18:6a4db94011d3 2780 /* PE1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 2781 #define LLWU_PE1_WUPE0_MASK 0x3u
sahilmgandhi 18:6a4db94011d3 2782 #define LLWU_PE1_WUPE0_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2783 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
sahilmgandhi 18:6a4db94011d3 2784 #define LLWU_PE1_WUPE1_MASK 0xCu
sahilmgandhi 18:6a4db94011d3 2785 #define LLWU_PE1_WUPE1_SHIFT 2
sahilmgandhi 18:6a4db94011d3 2786 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
sahilmgandhi 18:6a4db94011d3 2787 #define LLWU_PE1_WUPE2_MASK 0x30u
sahilmgandhi 18:6a4db94011d3 2788 #define LLWU_PE1_WUPE2_SHIFT 4
sahilmgandhi 18:6a4db94011d3 2789 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
sahilmgandhi 18:6a4db94011d3 2790 #define LLWU_PE1_WUPE3_MASK 0xC0u
sahilmgandhi 18:6a4db94011d3 2791 #define LLWU_PE1_WUPE3_SHIFT 6
sahilmgandhi 18:6a4db94011d3 2792 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
sahilmgandhi 18:6a4db94011d3 2793 /* PE2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 2794 #define LLWU_PE2_WUPE4_MASK 0x3u
sahilmgandhi 18:6a4db94011d3 2795 #define LLWU_PE2_WUPE4_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2796 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
sahilmgandhi 18:6a4db94011d3 2797 #define LLWU_PE2_WUPE5_MASK 0xCu
sahilmgandhi 18:6a4db94011d3 2798 #define LLWU_PE2_WUPE5_SHIFT 2
sahilmgandhi 18:6a4db94011d3 2799 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
sahilmgandhi 18:6a4db94011d3 2800 #define LLWU_PE2_WUPE6_MASK 0x30u
sahilmgandhi 18:6a4db94011d3 2801 #define LLWU_PE2_WUPE6_SHIFT 4
sahilmgandhi 18:6a4db94011d3 2802 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
sahilmgandhi 18:6a4db94011d3 2803 #define LLWU_PE2_WUPE7_MASK 0xC0u
sahilmgandhi 18:6a4db94011d3 2804 #define LLWU_PE2_WUPE7_SHIFT 6
sahilmgandhi 18:6a4db94011d3 2805 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
sahilmgandhi 18:6a4db94011d3 2806 /* PE3 Bit Fields */
sahilmgandhi 18:6a4db94011d3 2807 #define LLWU_PE3_WUPE8_MASK 0x3u
sahilmgandhi 18:6a4db94011d3 2808 #define LLWU_PE3_WUPE8_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2809 #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
sahilmgandhi 18:6a4db94011d3 2810 #define LLWU_PE3_WUPE9_MASK 0xCu
sahilmgandhi 18:6a4db94011d3 2811 #define LLWU_PE3_WUPE9_SHIFT 2
sahilmgandhi 18:6a4db94011d3 2812 #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
sahilmgandhi 18:6a4db94011d3 2813 #define LLWU_PE3_WUPE10_MASK 0x30u
sahilmgandhi 18:6a4db94011d3 2814 #define LLWU_PE3_WUPE10_SHIFT 4
sahilmgandhi 18:6a4db94011d3 2815 #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
sahilmgandhi 18:6a4db94011d3 2816 #define LLWU_PE3_WUPE11_MASK 0xC0u
sahilmgandhi 18:6a4db94011d3 2817 #define LLWU_PE3_WUPE11_SHIFT 6
sahilmgandhi 18:6a4db94011d3 2818 #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
sahilmgandhi 18:6a4db94011d3 2819 /* PE4 Bit Fields */
sahilmgandhi 18:6a4db94011d3 2820 #define LLWU_PE4_WUPE12_MASK 0x3u
sahilmgandhi 18:6a4db94011d3 2821 #define LLWU_PE4_WUPE12_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2822 #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
sahilmgandhi 18:6a4db94011d3 2823 #define LLWU_PE4_WUPE13_MASK 0xCu
sahilmgandhi 18:6a4db94011d3 2824 #define LLWU_PE4_WUPE13_SHIFT 2
sahilmgandhi 18:6a4db94011d3 2825 #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
sahilmgandhi 18:6a4db94011d3 2826 #define LLWU_PE4_WUPE14_MASK 0x30u
sahilmgandhi 18:6a4db94011d3 2827 #define LLWU_PE4_WUPE14_SHIFT 4
sahilmgandhi 18:6a4db94011d3 2828 #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
sahilmgandhi 18:6a4db94011d3 2829 #define LLWU_PE4_WUPE15_MASK 0xC0u
sahilmgandhi 18:6a4db94011d3 2830 #define LLWU_PE4_WUPE15_SHIFT 6
sahilmgandhi 18:6a4db94011d3 2831 #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
sahilmgandhi 18:6a4db94011d3 2832 /* ME Bit Fields */
sahilmgandhi 18:6a4db94011d3 2833 #define LLWU_ME_WUME0_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 2834 #define LLWU_ME_WUME0_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2835 #define LLWU_ME_WUME1_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 2836 #define LLWU_ME_WUME1_SHIFT 1
sahilmgandhi 18:6a4db94011d3 2837 #define LLWU_ME_WUME2_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 2838 #define LLWU_ME_WUME2_SHIFT 2
sahilmgandhi 18:6a4db94011d3 2839 #define LLWU_ME_WUME3_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 2840 #define LLWU_ME_WUME3_SHIFT 3
sahilmgandhi 18:6a4db94011d3 2841 #define LLWU_ME_WUME4_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 2842 #define LLWU_ME_WUME4_SHIFT 4
sahilmgandhi 18:6a4db94011d3 2843 #define LLWU_ME_WUME5_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 2844 #define LLWU_ME_WUME5_SHIFT 5
sahilmgandhi 18:6a4db94011d3 2845 #define LLWU_ME_WUME6_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 2846 #define LLWU_ME_WUME6_SHIFT 6
sahilmgandhi 18:6a4db94011d3 2847 #define LLWU_ME_WUME7_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 2848 #define LLWU_ME_WUME7_SHIFT 7
sahilmgandhi 18:6a4db94011d3 2849 /* F1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 2850 #define LLWU_F1_WUF0_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 2851 #define LLWU_F1_WUF0_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2852 #define LLWU_F1_WUF1_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 2853 #define LLWU_F1_WUF1_SHIFT 1
sahilmgandhi 18:6a4db94011d3 2854 #define LLWU_F1_WUF2_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 2855 #define LLWU_F1_WUF2_SHIFT 2
sahilmgandhi 18:6a4db94011d3 2856 #define LLWU_F1_WUF3_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 2857 #define LLWU_F1_WUF3_SHIFT 3
sahilmgandhi 18:6a4db94011d3 2858 #define LLWU_F1_WUF4_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 2859 #define LLWU_F1_WUF4_SHIFT 4
sahilmgandhi 18:6a4db94011d3 2860 #define LLWU_F1_WUF5_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 2861 #define LLWU_F1_WUF5_SHIFT 5
sahilmgandhi 18:6a4db94011d3 2862 #define LLWU_F1_WUF6_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 2863 #define LLWU_F1_WUF6_SHIFT 6
sahilmgandhi 18:6a4db94011d3 2864 #define LLWU_F1_WUF7_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 2865 #define LLWU_F1_WUF7_SHIFT 7
sahilmgandhi 18:6a4db94011d3 2866 /* F2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 2867 #define LLWU_F2_WUF8_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 2868 #define LLWU_F2_WUF8_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2869 #define LLWU_F2_WUF9_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 2870 #define LLWU_F2_WUF9_SHIFT 1
sahilmgandhi 18:6a4db94011d3 2871 #define LLWU_F2_WUF10_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 2872 #define LLWU_F2_WUF10_SHIFT 2
sahilmgandhi 18:6a4db94011d3 2873 #define LLWU_F2_WUF11_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 2874 #define LLWU_F2_WUF11_SHIFT 3
sahilmgandhi 18:6a4db94011d3 2875 #define LLWU_F2_WUF12_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 2876 #define LLWU_F2_WUF12_SHIFT 4
sahilmgandhi 18:6a4db94011d3 2877 #define LLWU_F2_WUF13_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 2878 #define LLWU_F2_WUF13_SHIFT 5
sahilmgandhi 18:6a4db94011d3 2879 #define LLWU_F2_WUF14_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 2880 #define LLWU_F2_WUF14_SHIFT 6
sahilmgandhi 18:6a4db94011d3 2881 #define LLWU_F2_WUF15_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 2882 #define LLWU_F2_WUF15_SHIFT 7
sahilmgandhi 18:6a4db94011d3 2883 /* F3 Bit Fields */
sahilmgandhi 18:6a4db94011d3 2884 #define LLWU_F3_MWUF0_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 2885 #define LLWU_F3_MWUF0_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2886 #define LLWU_F3_MWUF1_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 2887 #define LLWU_F3_MWUF1_SHIFT 1
sahilmgandhi 18:6a4db94011d3 2888 #define LLWU_F3_MWUF2_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 2889 #define LLWU_F3_MWUF2_SHIFT 2
sahilmgandhi 18:6a4db94011d3 2890 #define LLWU_F3_MWUF3_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 2891 #define LLWU_F3_MWUF3_SHIFT 3
sahilmgandhi 18:6a4db94011d3 2892 #define LLWU_F3_MWUF4_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 2893 #define LLWU_F3_MWUF4_SHIFT 4
sahilmgandhi 18:6a4db94011d3 2894 #define LLWU_F3_MWUF5_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 2895 #define LLWU_F3_MWUF5_SHIFT 5
sahilmgandhi 18:6a4db94011d3 2896 #define LLWU_F3_MWUF6_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 2897 #define LLWU_F3_MWUF6_SHIFT 6
sahilmgandhi 18:6a4db94011d3 2898 #define LLWU_F3_MWUF7_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 2899 #define LLWU_F3_MWUF7_SHIFT 7
sahilmgandhi 18:6a4db94011d3 2900 /* FILT1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 2901 #define LLWU_FILT1_FILTSEL_MASK 0xFu
sahilmgandhi 18:6a4db94011d3 2902 #define LLWU_FILT1_FILTSEL_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2903 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
sahilmgandhi 18:6a4db94011d3 2904 #define LLWU_FILT1_FILTE_MASK 0x60u
sahilmgandhi 18:6a4db94011d3 2905 #define LLWU_FILT1_FILTE_SHIFT 5
sahilmgandhi 18:6a4db94011d3 2906 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
sahilmgandhi 18:6a4db94011d3 2907 #define LLWU_FILT1_FILTF_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 2908 #define LLWU_FILT1_FILTF_SHIFT 7
sahilmgandhi 18:6a4db94011d3 2909 /* FILT2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 2910 #define LLWU_FILT2_FILTSEL_MASK 0xFu
sahilmgandhi 18:6a4db94011d3 2911 #define LLWU_FILT2_FILTSEL_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2912 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
sahilmgandhi 18:6a4db94011d3 2913 #define LLWU_FILT2_FILTE_MASK 0x60u
sahilmgandhi 18:6a4db94011d3 2914 #define LLWU_FILT2_FILTE_SHIFT 5
sahilmgandhi 18:6a4db94011d3 2915 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
sahilmgandhi 18:6a4db94011d3 2916 #define LLWU_FILT2_FILTF_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 2917 #define LLWU_FILT2_FILTF_SHIFT 7
sahilmgandhi 18:6a4db94011d3 2918 /* RST Bit Fields */
sahilmgandhi 18:6a4db94011d3 2919 #define LLWU_RST_RSTFILT_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 2920 #define LLWU_RST_RSTFILT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2921 #define LLWU_RST_LLRSTE_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 2922 #define LLWU_RST_LLRSTE_SHIFT 1
sahilmgandhi 18:6a4db94011d3 2923
sahilmgandhi 18:6a4db94011d3 2924 /**
sahilmgandhi 18:6a4db94011d3 2925 * @}
sahilmgandhi 18:6a4db94011d3 2926 */ /* end of group LLWU_Register_Masks */
sahilmgandhi 18:6a4db94011d3 2927
sahilmgandhi 18:6a4db94011d3 2928
sahilmgandhi 18:6a4db94011d3 2929 /* LLWU - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 2930 /** Peripheral LLWU base address */
sahilmgandhi 18:6a4db94011d3 2931 #define LLWU_BASE (0x4007C000u)
sahilmgandhi 18:6a4db94011d3 2932 /** Peripheral LLWU base pointer */
sahilmgandhi 18:6a4db94011d3 2933 #define LLWU ((LLWU_Type *)LLWU_BASE)
sahilmgandhi 18:6a4db94011d3 2934
sahilmgandhi 18:6a4db94011d3 2935 /**
sahilmgandhi 18:6a4db94011d3 2936 * @}
sahilmgandhi 18:6a4db94011d3 2937 */ /* end of group LLWU_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 2938
sahilmgandhi 18:6a4db94011d3 2939
sahilmgandhi 18:6a4db94011d3 2940 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 2941 -- LPTMR Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 2942 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 2943
sahilmgandhi 18:6a4db94011d3 2944 /**
sahilmgandhi 18:6a4db94011d3 2945 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 2946 * @{
sahilmgandhi 18:6a4db94011d3 2947 */
sahilmgandhi 18:6a4db94011d3 2948
sahilmgandhi 18:6a4db94011d3 2949 /** LPTMR - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 2950 typedef struct {
sahilmgandhi 18:6a4db94011d3 2951 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 2952 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
sahilmgandhi 18:6a4db94011d3 2953 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
sahilmgandhi 18:6a4db94011d3 2954 __I uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
sahilmgandhi 18:6a4db94011d3 2955 } LPTMR_Type;
sahilmgandhi 18:6a4db94011d3 2956
sahilmgandhi 18:6a4db94011d3 2957 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 2958 -- LPTMR Register Masks
sahilmgandhi 18:6a4db94011d3 2959 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 2960
sahilmgandhi 18:6a4db94011d3 2961 /**
sahilmgandhi 18:6a4db94011d3 2962 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
sahilmgandhi 18:6a4db94011d3 2963 * @{
sahilmgandhi 18:6a4db94011d3 2964 */
sahilmgandhi 18:6a4db94011d3 2965
sahilmgandhi 18:6a4db94011d3 2966 /* CSR Bit Fields */
sahilmgandhi 18:6a4db94011d3 2967 #define LPTMR_CSR_TEN_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 2968 #define LPTMR_CSR_TEN_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2969 #define LPTMR_CSR_TMS_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 2970 #define LPTMR_CSR_TMS_SHIFT 1
sahilmgandhi 18:6a4db94011d3 2971 #define LPTMR_CSR_TFC_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 2972 #define LPTMR_CSR_TFC_SHIFT 2
sahilmgandhi 18:6a4db94011d3 2973 #define LPTMR_CSR_TPP_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 2974 #define LPTMR_CSR_TPP_SHIFT 3
sahilmgandhi 18:6a4db94011d3 2975 #define LPTMR_CSR_TPS_MASK 0x30u
sahilmgandhi 18:6a4db94011d3 2976 #define LPTMR_CSR_TPS_SHIFT 4
sahilmgandhi 18:6a4db94011d3 2977 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
sahilmgandhi 18:6a4db94011d3 2978 #define LPTMR_CSR_TIE_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 2979 #define LPTMR_CSR_TIE_SHIFT 6
sahilmgandhi 18:6a4db94011d3 2980 #define LPTMR_CSR_TCF_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 2981 #define LPTMR_CSR_TCF_SHIFT 7
sahilmgandhi 18:6a4db94011d3 2982 /* PSR Bit Fields */
sahilmgandhi 18:6a4db94011d3 2983 #define LPTMR_PSR_PCS_MASK 0x3u
sahilmgandhi 18:6a4db94011d3 2984 #define LPTMR_PSR_PCS_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2985 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
sahilmgandhi 18:6a4db94011d3 2986 #define LPTMR_PSR_PBYP_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 2987 #define LPTMR_PSR_PBYP_SHIFT 2
sahilmgandhi 18:6a4db94011d3 2988 #define LPTMR_PSR_PRESCALE_MASK 0x78u
sahilmgandhi 18:6a4db94011d3 2989 #define LPTMR_PSR_PRESCALE_SHIFT 3
sahilmgandhi 18:6a4db94011d3 2990 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
sahilmgandhi 18:6a4db94011d3 2991 /* CMR Bit Fields */
sahilmgandhi 18:6a4db94011d3 2992 #define LPTMR_CMR_COMPARE_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 2993 #define LPTMR_CMR_COMPARE_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2994 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
sahilmgandhi 18:6a4db94011d3 2995 /* CNR Bit Fields */
sahilmgandhi 18:6a4db94011d3 2996 #define LPTMR_CNR_COUNTER_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 2997 #define LPTMR_CNR_COUNTER_SHIFT 0
sahilmgandhi 18:6a4db94011d3 2998 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
sahilmgandhi 18:6a4db94011d3 2999
sahilmgandhi 18:6a4db94011d3 3000 /**
sahilmgandhi 18:6a4db94011d3 3001 * @}
sahilmgandhi 18:6a4db94011d3 3002 */ /* end of group LPTMR_Register_Masks */
sahilmgandhi 18:6a4db94011d3 3003
sahilmgandhi 18:6a4db94011d3 3004
sahilmgandhi 18:6a4db94011d3 3005 /* LPTMR - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 3006 /** Peripheral LPTMR0 base address */
sahilmgandhi 18:6a4db94011d3 3007 #define LPTMR0_BASE (0x40040000u)
sahilmgandhi 18:6a4db94011d3 3008 /** Peripheral LPTMR0 base pointer */
sahilmgandhi 18:6a4db94011d3 3009 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
sahilmgandhi 18:6a4db94011d3 3010
sahilmgandhi 18:6a4db94011d3 3011 /**
sahilmgandhi 18:6a4db94011d3 3012 * @}
sahilmgandhi 18:6a4db94011d3 3013 */ /* end of group LPTMR_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 3014
sahilmgandhi 18:6a4db94011d3 3015
sahilmgandhi 18:6a4db94011d3 3016 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3017 -- MCG Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 3018 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 3019
sahilmgandhi 18:6a4db94011d3 3020 /**
sahilmgandhi 18:6a4db94011d3 3021 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 3022 * @{
sahilmgandhi 18:6a4db94011d3 3023 */
sahilmgandhi 18:6a4db94011d3 3024
sahilmgandhi 18:6a4db94011d3 3025 /** MCG - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 3026 typedef struct {
sahilmgandhi 18:6a4db94011d3 3027 __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 3028 __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
sahilmgandhi 18:6a4db94011d3 3029 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
sahilmgandhi 18:6a4db94011d3 3030 __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
sahilmgandhi 18:6a4db94011d3 3031 __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
sahilmgandhi 18:6a4db94011d3 3032 __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
sahilmgandhi 18:6a4db94011d3 3033 __I uint8_t S; /**< MCG Status Register, offset: 0x6 */
sahilmgandhi 18:6a4db94011d3 3034 uint8_t RESERVED_0[1];
sahilmgandhi 18:6a4db94011d3 3035 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
sahilmgandhi 18:6a4db94011d3 3036 uint8_t RESERVED_1[1];
sahilmgandhi 18:6a4db94011d3 3037 __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
sahilmgandhi 18:6a4db94011d3 3038 __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
sahilmgandhi 18:6a4db94011d3 3039 __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
sahilmgandhi 18:6a4db94011d3 3040 __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
sahilmgandhi 18:6a4db94011d3 3041 } MCG_Type;
sahilmgandhi 18:6a4db94011d3 3042
sahilmgandhi 18:6a4db94011d3 3043 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3044 -- MCG Register Masks
sahilmgandhi 18:6a4db94011d3 3045 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 3046
sahilmgandhi 18:6a4db94011d3 3047 /**
sahilmgandhi 18:6a4db94011d3 3048 * @addtogroup MCG_Register_Masks MCG Register Masks
sahilmgandhi 18:6a4db94011d3 3049 * @{
sahilmgandhi 18:6a4db94011d3 3050 */
sahilmgandhi 18:6a4db94011d3 3051
sahilmgandhi 18:6a4db94011d3 3052 /* C1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 3053 #define MCG_C1_IREFSTEN_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 3054 #define MCG_C1_IREFSTEN_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3055 #define MCG_C1_IRCLKEN_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 3056 #define MCG_C1_IRCLKEN_SHIFT 1
sahilmgandhi 18:6a4db94011d3 3057 #define MCG_C1_IREFS_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 3058 #define MCG_C1_IREFS_SHIFT 2
sahilmgandhi 18:6a4db94011d3 3059 #define MCG_C1_FRDIV_MASK 0x38u
sahilmgandhi 18:6a4db94011d3 3060 #define MCG_C1_FRDIV_SHIFT 3
sahilmgandhi 18:6a4db94011d3 3061 #define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
sahilmgandhi 18:6a4db94011d3 3062 #define MCG_C1_CLKS_MASK 0xC0u
sahilmgandhi 18:6a4db94011d3 3063 #define MCG_C1_CLKS_SHIFT 6
sahilmgandhi 18:6a4db94011d3 3064 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
sahilmgandhi 18:6a4db94011d3 3065 /* C2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 3066 #define MCG_C2_IRCS_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 3067 #define MCG_C2_IRCS_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3068 #define MCG_C2_LP_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 3069 #define MCG_C2_LP_SHIFT 1
sahilmgandhi 18:6a4db94011d3 3070 #define MCG_C2_EREFS0_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 3071 #define MCG_C2_EREFS0_SHIFT 2
sahilmgandhi 18:6a4db94011d3 3072 #define MCG_C2_HGO0_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 3073 #define MCG_C2_HGO0_SHIFT 3
sahilmgandhi 18:6a4db94011d3 3074 #define MCG_C2_RANGE0_MASK 0x30u
sahilmgandhi 18:6a4db94011d3 3075 #define MCG_C2_RANGE0_SHIFT 4
sahilmgandhi 18:6a4db94011d3 3076 #define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
sahilmgandhi 18:6a4db94011d3 3077 #define MCG_C2_LOCRE0_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 3078 #define MCG_C2_LOCRE0_SHIFT 7
sahilmgandhi 18:6a4db94011d3 3079 /* C3 Bit Fields */
sahilmgandhi 18:6a4db94011d3 3080 #define MCG_C3_SCTRIM_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 3081 #define MCG_C3_SCTRIM_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3082 #define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
sahilmgandhi 18:6a4db94011d3 3083 /* C4 Bit Fields */
sahilmgandhi 18:6a4db94011d3 3084 #define MCG_C4_SCFTRIM_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 3085 #define MCG_C4_SCFTRIM_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3086 #define MCG_C4_FCTRIM_MASK 0x1Eu
sahilmgandhi 18:6a4db94011d3 3087 #define MCG_C4_FCTRIM_SHIFT 1
sahilmgandhi 18:6a4db94011d3 3088 #define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
sahilmgandhi 18:6a4db94011d3 3089 #define MCG_C4_DRST_DRS_MASK 0x60u
sahilmgandhi 18:6a4db94011d3 3090 #define MCG_C4_DRST_DRS_SHIFT 5
sahilmgandhi 18:6a4db94011d3 3091 #define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
sahilmgandhi 18:6a4db94011d3 3092 #define MCG_C4_DMX32_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 3093 #define MCG_C4_DMX32_SHIFT 7
sahilmgandhi 18:6a4db94011d3 3094 /* C5 Bit Fields */
sahilmgandhi 18:6a4db94011d3 3095 #define MCG_C5_PRDIV0_MASK 0x1Fu
sahilmgandhi 18:6a4db94011d3 3096 #define MCG_C5_PRDIV0_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3097 #define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
sahilmgandhi 18:6a4db94011d3 3098 #define MCG_C5_PLLSTEN0_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 3099 #define MCG_C5_PLLSTEN0_SHIFT 5
sahilmgandhi 18:6a4db94011d3 3100 #define MCG_C5_PLLCLKEN0_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 3101 #define MCG_C5_PLLCLKEN0_SHIFT 6
sahilmgandhi 18:6a4db94011d3 3102 /* C6 Bit Fields */
sahilmgandhi 18:6a4db94011d3 3103 #define MCG_C6_VDIV0_MASK 0x1Fu
sahilmgandhi 18:6a4db94011d3 3104 #define MCG_C6_VDIV0_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3105 #define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
sahilmgandhi 18:6a4db94011d3 3106 #define MCG_C6_CME0_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 3107 #define MCG_C6_CME0_SHIFT 5
sahilmgandhi 18:6a4db94011d3 3108 #define MCG_C6_PLLS_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 3109 #define MCG_C6_PLLS_SHIFT 6
sahilmgandhi 18:6a4db94011d3 3110 #define MCG_C6_LOLIE0_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 3111 #define MCG_C6_LOLIE0_SHIFT 7
sahilmgandhi 18:6a4db94011d3 3112 /* S Bit Fields */
sahilmgandhi 18:6a4db94011d3 3113 #define MCG_S_IRCST_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 3114 #define MCG_S_IRCST_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3115 #define MCG_S_OSCINIT0_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 3116 #define MCG_S_OSCINIT0_SHIFT 1
sahilmgandhi 18:6a4db94011d3 3117 #define MCG_S_CLKST_MASK 0xCu
sahilmgandhi 18:6a4db94011d3 3118 #define MCG_S_CLKST_SHIFT 2
sahilmgandhi 18:6a4db94011d3 3119 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
sahilmgandhi 18:6a4db94011d3 3120 #define MCG_S_IREFST_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 3121 #define MCG_S_IREFST_SHIFT 4
sahilmgandhi 18:6a4db94011d3 3122 #define MCG_S_PLLST_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 3123 #define MCG_S_PLLST_SHIFT 5
sahilmgandhi 18:6a4db94011d3 3124 #define MCG_S_LOCK0_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 3125 #define MCG_S_LOCK0_SHIFT 6
sahilmgandhi 18:6a4db94011d3 3126 #define MCG_S_LOLS0_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 3127 #define MCG_S_LOLS0_SHIFT 7
sahilmgandhi 18:6a4db94011d3 3128 /* SC Bit Fields */
sahilmgandhi 18:6a4db94011d3 3129 #define MCG_SC_LOCS0_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 3130 #define MCG_SC_LOCS0_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3131 #define MCG_SC_FCRDIV_MASK 0xEu
sahilmgandhi 18:6a4db94011d3 3132 #define MCG_SC_FCRDIV_SHIFT 1
sahilmgandhi 18:6a4db94011d3 3133 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
sahilmgandhi 18:6a4db94011d3 3134 #define MCG_SC_FLTPRSRV_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 3135 #define MCG_SC_FLTPRSRV_SHIFT 4
sahilmgandhi 18:6a4db94011d3 3136 #define MCG_SC_ATMF_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 3137 #define MCG_SC_ATMF_SHIFT 5
sahilmgandhi 18:6a4db94011d3 3138 #define MCG_SC_ATMS_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 3139 #define MCG_SC_ATMS_SHIFT 6
sahilmgandhi 18:6a4db94011d3 3140 #define MCG_SC_ATME_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 3141 #define MCG_SC_ATME_SHIFT 7
sahilmgandhi 18:6a4db94011d3 3142 /* ATCVH Bit Fields */
sahilmgandhi 18:6a4db94011d3 3143 #define MCG_ATCVH_ATCVH_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 3144 #define MCG_ATCVH_ATCVH_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3145 #define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
sahilmgandhi 18:6a4db94011d3 3146 /* ATCVL Bit Fields */
sahilmgandhi 18:6a4db94011d3 3147 #define MCG_ATCVL_ATCVL_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 3148 #define MCG_ATCVL_ATCVL_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3149 #define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
sahilmgandhi 18:6a4db94011d3 3150 /* C7 Bit Fields */
sahilmgandhi 18:6a4db94011d3 3151 #define MCG_C7_OSCSEL_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 3152 #define MCG_C7_OSCSEL_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3153 /* C8 Bit Fields */
sahilmgandhi 18:6a4db94011d3 3154 #define MCG_C8_LOCS1_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 3155 #define MCG_C8_LOCS1_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3156 #define MCG_C8_CME1_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 3157 #define MCG_C8_CME1_SHIFT 5
sahilmgandhi 18:6a4db94011d3 3158 #define MCG_C8_LOLRE_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 3159 #define MCG_C8_LOLRE_SHIFT 6
sahilmgandhi 18:6a4db94011d3 3160 #define MCG_C8_LOCRE1_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 3161 #define MCG_C8_LOCRE1_SHIFT 7
sahilmgandhi 18:6a4db94011d3 3162
sahilmgandhi 18:6a4db94011d3 3163 /**
sahilmgandhi 18:6a4db94011d3 3164 * @}
sahilmgandhi 18:6a4db94011d3 3165 */ /* end of group MCG_Register_Masks */
sahilmgandhi 18:6a4db94011d3 3166
sahilmgandhi 18:6a4db94011d3 3167
sahilmgandhi 18:6a4db94011d3 3168 /* MCG - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 3169 /** Peripheral MCG base address */
sahilmgandhi 18:6a4db94011d3 3170 #define MCG_BASE (0x40064000u)
sahilmgandhi 18:6a4db94011d3 3171 /** Peripheral MCG base pointer */
sahilmgandhi 18:6a4db94011d3 3172 #define MCG ((MCG_Type *)MCG_BASE)
sahilmgandhi 18:6a4db94011d3 3173
sahilmgandhi 18:6a4db94011d3 3174 /**
sahilmgandhi 18:6a4db94011d3 3175 * @}
sahilmgandhi 18:6a4db94011d3 3176 */ /* end of group MCG_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 3177
sahilmgandhi 18:6a4db94011d3 3178
sahilmgandhi 18:6a4db94011d3 3179 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3180 -- NV Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 3181 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 3182
sahilmgandhi 18:6a4db94011d3 3183 /**
sahilmgandhi 18:6a4db94011d3 3184 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 3185 * @{
sahilmgandhi 18:6a4db94011d3 3186 */
sahilmgandhi 18:6a4db94011d3 3187
sahilmgandhi 18:6a4db94011d3 3188 /** NV - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 3189 typedef struct {
sahilmgandhi 18:6a4db94011d3 3190 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 3191 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
sahilmgandhi 18:6a4db94011d3 3192 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
sahilmgandhi 18:6a4db94011d3 3193 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
sahilmgandhi 18:6a4db94011d3 3194 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
sahilmgandhi 18:6a4db94011d3 3195 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
sahilmgandhi 18:6a4db94011d3 3196 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
sahilmgandhi 18:6a4db94011d3 3197 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
sahilmgandhi 18:6a4db94011d3 3198 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
sahilmgandhi 18:6a4db94011d3 3199 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
sahilmgandhi 18:6a4db94011d3 3200 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
sahilmgandhi 18:6a4db94011d3 3201 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
sahilmgandhi 18:6a4db94011d3 3202 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
sahilmgandhi 18:6a4db94011d3 3203 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
sahilmgandhi 18:6a4db94011d3 3204 __I uint8_t FEPROT; /**< Non-volatile EERAM Protection Register, offset: 0xE */
sahilmgandhi 18:6a4db94011d3 3205 __I uint8_t FDPROT; /**< Non-volatile D-Flash Protection Register, offset: 0xF */
sahilmgandhi 18:6a4db94011d3 3206 } NV_Type;
sahilmgandhi 18:6a4db94011d3 3207
sahilmgandhi 18:6a4db94011d3 3208 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3209 -- NV Register Masks
sahilmgandhi 18:6a4db94011d3 3210 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 3211
sahilmgandhi 18:6a4db94011d3 3212 /**
sahilmgandhi 18:6a4db94011d3 3213 * @addtogroup NV_Register_Masks NV Register Masks
sahilmgandhi 18:6a4db94011d3 3214 * @{
sahilmgandhi 18:6a4db94011d3 3215 */
sahilmgandhi 18:6a4db94011d3 3216
sahilmgandhi 18:6a4db94011d3 3217 /* BACKKEY3 Bit Fields */
sahilmgandhi 18:6a4db94011d3 3218 #define NV_BACKKEY3_KEY_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 3219 #define NV_BACKKEY3_KEY_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3220 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
sahilmgandhi 18:6a4db94011d3 3221 /* BACKKEY2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 3222 #define NV_BACKKEY2_KEY_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 3223 #define NV_BACKKEY2_KEY_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3224 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
sahilmgandhi 18:6a4db94011d3 3225 /* BACKKEY1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 3226 #define NV_BACKKEY1_KEY_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 3227 #define NV_BACKKEY1_KEY_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3228 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
sahilmgandhi 18:6a4db94011d3 3229 /* BACKKEY0 Bit Fields */
sahilmgandhi 18:6a4db94011d3 3230 #define NV_BACKKEY0_KEY_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 3231 #define NV_BACKKEY0_KEY_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3232 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
sahilmgandhi 18:6a4db94011d3 3233 /* BACKKEY7 Bit Fields */
sahilmgandhi 18:6a4db94011d3 3234 #define NV_BACKKEY7_KEY_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 3235 #define NV_BACKKEY7_KEY_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3236 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
sahilmgandhi 18:6a4db94011d3 3237 /* BACKKEY6 Bit Fields */
sahilmgandhi 18:6a4db94011d3 3238 #define NV_BACKKEY6_KEY_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 3239 #define NV_BACKKEY6_KEY_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3240 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
sahilmgandhi 18:6a4db94011d3 3241 /* BACKKEY5 Bit Fields */
sahilmgandhi 18:6a4db94011d3 3242 #define NV_BACKKEY5_KEY_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 3243 #define NV_BACKKEY5_KEY_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3244 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
sahilmgandhi 18:6a4db94011d3 3245 /* BACKKEY4 Bit Fields */
sahilmgandhi 18:6a4db94011d3 3246 #define NV_BACKKEY4_KEY_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 3247 #define NV_BACKKEY4_KEY_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3248 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
sahilmgandhi 18:6a4db94011d3 3249 /* FPROT3 Bit Fields */
sahilmgandhi 18:6a4db94011d3 3250 #define NV_FPROT3_PROT_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 3251 #define NV_FPROT3_PROT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3252 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
sahilmgandhi 18:6a4db94011d3 3253 /* FPROT2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 3254 #define NV_FPROT2_PROT_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 3255 #define NV_FPROT2_PROT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3256 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
sahilmgandhi 18:6a4db94011d3 3257 /* FPROT1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 3258 #define NV_FPROT1_PROT_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 3259 #define NV_FPROT1_PROT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3260 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
sahilmgandhi 18:6a4db94011d3 3261 /* FPROT0 Bit Fields */
sahilmgandhi 18:6a4db94011d3 3262 #define NV_FPROT0_PROT_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 3263 #define NV_FPROT0_PROT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3264 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
sahilmgandhi 18:6a4db94011d3 3265 /* FSEC Bit Fields */
sahilmgandhi 18:6a4db94011d3 3266 #define NV_FSEC_SEC_MASK 0x3u
sahilmgandhi 18:6a4db94011d3 3267 #define NV_FSEC_SEC_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3268 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
sahilmgandhi 18:6a4db94011d3 3269 #define NV_FSEC_FSLACC_MASK 0xCu
sahilmgandhi 18:6a4db94011d3 3270 #define NV_FSEC_FSLACC_SHIFT 2
sahilmgandhi 18:6a4db94011d3 3271 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
sahilmgandhi 18:6a4db94011d3 3272 #define NV_FSEC_MEEN_MASK 0x30u
sahilmgandhi 18:6a4db94011d3 3273 #define NV_FSEC_MEEN_SHIFT 4
sahilmgandhi 18:6a4db94011d3 3274 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
sahilmgandhi 18:6a4db94011d3 3275 #define NV_FSEC_KEYEN_MASK 0xC0u
sahilmgandhi 18:6a4db94011d3 3276 #define NV_FSEC_KEYEN_SHIFT 6
sahilmgandhi 18:6a4db94011d3 3277 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
sahilmgandhi 18:6a4db94011d3 3278 /* FOPT Bit Fields */
sahilmgandhi 18:6a4db94011d3 3279 #define NV_FOPT_LPBOOT_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 3280 #define NV_FOPT_LPBOOT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3281 #define NV_FOPT_EZPORT_DIS_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 3282 #define NV_FOPT_EZPORT_DIS_SHIFT 1
sahilmgandhi 18:6a4db94011d3 3283 /* FEPROT Bit Fields */
sahilmgandhi 18:6a4db94011d3 3284 #define NV_FEPROT_EPROT_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 3285 #define NV_FEPROT_EPROT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3286 #define NV_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FEPROT_EPROT_SHIFT))&NV_FEPROT_EPROT_MASK)
sahilmgandhi 18:6a4db94011d3 3287 /* FDPROT Bit Fields */
sahilmgandhi 18:6a4db94011d3 3288 #define NV_FDPROT_DPROT_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 3289 #define NV_FDPROT_DPROT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3290 #define NV_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FDPROT_DPROT_SHIFT))&NV_FDPROT_DPROT_MASK)
sahilmgandhi 18:6a4db94011d3 3291
sahilmgandhi 18:6a4db94011d3 3292 /**
sahilmgandhi 18:6a4db94011d3 3293 * @}
sahilmgandhi 18:6a4db94011d3 3294 */ /* end of group NV_Register_Masks */
sahilmgandhi 18:6a4db94011d3 3295
sahilmgandhi 18:6a4db94011d3 3296
sahilmgandhi 18:6a4db94011d3 3297 /* NV - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 3298 /** Peripheral FTFL_FlashConfig base address */
sahilmgandhi 18:6a4db94011d3 3299 #define FTFL_FlashConfig_BASE (0x400u)
sahilmgandhi 18:6a4db94011d3 3300 /** Peripheral FTFL_FlashConfig base pointer */
sahilmgandhi 18:6a4db94011d3 3301 #define FTFL_FlashConfig ((NV_Type *)FTFL_FlashConfig_BASE)
sahilmgandhi 18:6a4db94011d3 3302
sahilmgandhi 18:6a4db94011d3 3303 /**
sahilmgandhi 18:6a4db94011d3 3304 * @}
sahilmgandhi 18:6a4db94011d3 3305 */ /* end of group NV_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 3306
sahilmgandhi 18:6a4db94011d3 3307
sahilmgandhi 18:6a4db94011d3 3308 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3309 -- OSC Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 3310 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 3311
sahilmgandhi 18:6a4db94011d3 3312 /**
sahilmgandhi 18:6a4db94011d3 3313 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 3314 * @{
sahilmgandhi 18:6a4db94011d3 3315 */
sahilmgandhi 18:6a4db94011d3 3316
sahilmgandhi 18:6a4db94011d3 3317 /** OSC - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 3318 typedef struct {
sahilmgandhi 18:6a4db94011d3 3319 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 3320 } OSC_Type;
sahilmgandhi 18:6a4db94011d3 3321
sahilmgandhi 18:6a4db94011d3 3322 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3323 -- OSC Register Masks
sahilmgandhi 18:6a4db94011d3 3324 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 3325
sahilmgandhi 18:6a4db94011d3 3326 /**
sahilmgandhi 18:6a4db94011d3 3327 * @addtogroup OSC_Register_Masks OSC Register Masks
sahilmgandhi 18:6a4db94011d3 3328 * @{
sahilmgandhi 18:6a4db94011d3 3329 */
sahilmgandhi 18:6a4db94011d3 3330
sahilmgandhi 18:6a4db94011d3 3331 /* CR Bit Fields */
sahilmgandhi 18:6a4db94011d3 3332 #define OSC_CR_SC16P_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 3333 #define OSC_CR_SC16P_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3334 #define OSC_CR_SC8P_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 3335 #define OSC_CR_SC8P_SHIFT 1
sahilmgandhi 18:6a4db94011d3 3336 #define OSC_CR_SC4P_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 3337 #define OSC_CR_SC4P_SHIFT 2
sahilmgandhi 18:6a4db94011d3 3338 #define OSC_CR_SC2P_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 3339 #define OSC_CR_SC2P_SHIFT 3
sahilmgandhi 18:6a4db94011d3 3340 #define OSC_CR_EREFSTEN_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 3341 #define OSC_CR_EREFSTEN_SHIFT 5
sahilmgandhi 18:6a4db94011d3 3342 #define OSC_CR_ERCLKEN_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 3343 #define OSC_CR_ERCLKEN_SHIFT 7
sahilmgandhi 18:6a4db94011d3 3344
sahilmgandhi 18:6a4db94011d3 3345 /**
sahilmgandhi 18:6a4db94011d3 3346 * @}
sahilmgandhi 18:6a4db94011d3 3347 */ /* end of group OSC_Register_Masks */
sahilmgandhi 18:6a4db94011d3 3348
sahilmgandhi 18:6a4db94011d3 3349
sahilmgandhi 18:6a4db94011d3 3350 /* OSC - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 3351 /** Peripheral OSC0 base address */
sahilmgandhi 18:6a4db94011d3 3352 #define OSC0_BASE (0x40065000u)
sahilmgandhi 18:6a4db94011d3 3353 /** Peripheral OSC0 base pointer */
sahilmgandhi 18:6a4db94011d3 3354 #define OSC0 ((OSC_Type *)OSC0_BASE)
sahilmgandhi 18:6a4db94011d3 3355
sahilmgandhi 18:6a4db94011d3 3356 /**
sahilmgandhi 18:6a4db94011d3 3357 * @}
sahilmgandhi 18:6a4db94011d3 3358 */ /* end of group OSC_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 3359
sahilmgandhi 18:6a4db94011d3 3360
sahilmgandhi 18:6a4db94011d3 3361 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3362 -- PDB Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 3363 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 3364
sahilmgandhi 18:6a4db94011d3 3365 /**
sahilmgandhi 18:6a4db94011d3 3366 * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 3367 * @{
sahilmgandhi 18:6a4db94011d3 3368 */
sahilmgandhi 18:6a4db94011d3 3369
sahilmgandhi 18:6a4db94011d3 3370 /** PDB - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 3371 typedef struct {
sahilmgandhi 18:6a4db94011d3 3372 __IO uint32_t SC; /**< Status and Control Register, offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 3373 __IO uint32_t MOD; /**< Modulus Register, offset: 0x4 */
sahilmgandhi 18:6a4db94011d3 3374 __I uint32_t CNT; /**< Counter Register, offset: 0x8 */
sahilmgandhi 18:6a4db94011d3 3375 __IO uint32_t IDLY; /**< Interrupt Delay Register, offset: 0xC */
sahilmgandhi 18:6a4db94011d3 3376 struct { /* offset: 0x10, array step: 0x10 */
sahilmgandhi 18:6a4db94011d3 3377 __IO uint32_t C1; /**< Channel n Control Register 1, array offset: 0x10, array step: 0x10 */
sahilmgandhi 18:6a4db94011d3 3378 __IO uint32_t S; /**< Channel n Status Register, array offset: 0x14, array step: 0x10 */
sahilmgandhi 18:6a4db94011d3 3379 __IO uint32_t DLY[2]; /**< Channel n Delay 0 Register..Channel n Delay 1 Register, array offset: 0x18, array step: index*0x10, index2*0x4 */
sahilmgandhi 18:6a4db94011d3 3380 } CH[1];
sahilmgandhi 18:6a4db94011d3 3381 uint8_t RESERVED_0[368];
sahilmgandhi 18:6a4db94011d3 3382 __IO uint32_t POEN; /**< Pulse-Out n Enable Register, offset: 0x190 */
sahilmgandhi 18:6a4db94011d3 3383 __IO uint32_t PODLY[2]; /**< Pulse-Out n Delay Register, array offset: 0x194, array step: 0x4 */
sahilmgandhi 18:6a4db94011d3 3384 } PDB_Type;
sahilmgandhi 18:6a4db94011d3 3385
sahilmgandhi 18:6a4db94011d3 3386 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3387 -- PDB Register Masks
sahilmgandhi 18:6a4db94011d3 3388 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 3389
sahilmgandhi 18:6a4db94011d3 3390 /**
sahilmgandhi 18:6a4db94011d3 3391 * @addtogroup PDB_Register_Masks PDB Register Masks
sahilmgandhi 18:6a4db94011d3 3392 * @{
sahilmgandhi 18:6a4db94011d3 3393 */
sahilmgandhi 18:6a4db94011d3 3394
sahilmgandhi 18:6a4db94011d3 3395 /* SC Bit Fields */
sahilmgandhi 18:6a4db94011d3 3396 #define PDB_SC_LDOK_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 3397 #define PDB_SC_LDOK_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3398 #define PDB_SC_CONT_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 3399 #define PDB_SC_CONT_SHIFT 1
sahilmgandhi 18:6a4db94011d3 3400 #define PDB_SC_MULT_MASK 0xCu
sahilmgandhi 18:6a4db94011d3 3401 #define PDB_SC_MULT_SHIFT 2
sahilmgandhi 18:6a4db94011d3 3402 #define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK)
sahilmgandhi 18:6a4db94011d3 3403 #define PDB_SC_PDBIE_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 3404 #define PDB_SC_PDBIE_SHIFT 5
sahilmgandhi 18:6a4db94011d3 3405 #define PDB_SC_PDBIF_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 3406 #define PDB_SC_PDBIF_SHIFT 6
sahilmgandhi 18:6a4db94011d3 3407 #define PDB_SC_PDBEN_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 3408 #define PDB_SC_PDBEN_SHIFT 7
sahilmgandhi 18:6a4db94011d3 3409 #define PDB_SC_TRGSEL_MASK 0xF00u
sahilmgandhi 18:6a4db94011d3 3410 #define PDB_SC_TRGSEL_SHIFT 8
sahilmgandhi 18:6a4db94011d3 3411 #define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK)
sahilmgandhi 18:6a4db94011d3 3412 #define PDB_SC_PRESCALER_MASK 0x7000u
sahilmgandhi 18:6a4db94011d3 3413 #define PDB_SC_PRESCALER_SHIFT 12
sahilmgandhi 18:6a4db94011d3 3414 #define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK)
sahilmgandhi 18:6a4db94011d3 3415 #define PDB_SC_DMAEN_MASK 0x8000u
sahilmgandhi 18:6a4db94011d3 3416 #define PDB_SC_DMAEN_SHIFT 15
sahilmgandhi 18:6a4db94011d3 3417 #define PDB_SC_SWTRIG_MASK 0x10000u
sahilmgandhi 18:6a4db94011d3 3418 #define PDB_SC_SWTRIG_SHIFT 16
sahilmgandhi 18:6a4db94011d3 3419 #define PDB_SC_PDBEIE_MASK 0x20000u
sahilmgandhi 18:6a4db94011d3 3420 #define PDB_SC_PDBEIE_SHIFT 17
sahilmgandhi 18:6a4db94011d3 3421 #define PDB_SC_LDMOD_MASK 0xC0000u
sahilmgandhi 18:6a4db94011d3 3422 #define PDB_SC_LDMOD_SHIFT 18
sahilmgandhi 18:6a4db94011d3 3423 #define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK)
sahilmgandhi 18:6a4db94011d3 3424 /* MOD Bit Fields */
sahilmgandhi 18:6a4db94011d3 3425 #define PDB_MOD_MOD_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 3426 #define PDB_MOD_MOD_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3427 #define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK)
sahilmgandhi 18:6a4db94011d3 3428 /* CNT Bit Fields */
sahilmgandhi 18:6a4db94011d3 3429 #define PDB_CNT_CNT_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 3430 #define PDB_CNT_CNT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3431 #define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK)
sahilmgandhi 18:6a4db94011d3 3432 /* IDLY Bit Fields */
sahilmgandhi 18:6a4db94011d3 3433 #define PDB_IDLY_IDLY_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 3434 #define PDB_IDLY_IDLY_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3435 #define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK)
sahilmgandhi 18:6a4db94011d3 3436 /* C1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 3437 #define PDB_C1_EN_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 3438 #define PDB_C1_EN_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3439 #define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK)
sahilmgandhi 18:6a4db94011d3 3440 #define PDB_C1_TOS_MASK 0xFF00u
sahilmgandhi 18:6a4db94011d3 3441 #define PDB_C1_TOS_SHIFT 8
sahilmgandhi 18:6a4db94011d3 3442 #define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK)
sahilmgandhi 18:6a4db94011d3 3443 #define PDB_C1_BB_MASK 0xFF0000u
sahilmgandhi 18:6a4db94011d3 3444 #define PDB_C1_BB_SHIFT 16
sahilmgandhi 18:6a4db94011d3 3445 #define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK)
sahilmgandhi 18:6a4db94011d3 3446 /* S Bit Fields */
sahilmgandhi 18:6a4db94011d3 3447 #define PDB_S_ERR_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 3448 #define PDB_S_ERR_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3449 #define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK)
sahilmgandhi 18:6a4db94011d3 3450 #define PDB_S_CF_MASK 0xFF0000u
sahilmgandhi 18:6a4db94011d3 3451 #define PDB_S_CF_SHIFT 16
sahilmgandhi 18:6a4db94011d3 3452 #define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK)
sahilmgandhi 18:6a4db94011d3 3453 /* DLY Bit Fields */
sahilmgandhi 18:6a4db94011d3 3454 #define PDB_DLY_DLY_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 3455 #define PDB_DLY_DLY_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3456 #define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK)
sahilmgandhi 18:6a4db94011d3 3457 /* POEN Bit Fields */
sahilmgandhi 18:6a4db94011d3 3458 #define PDB_POEN_POEN_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 3459 #define PDB_POEN_POEN_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3460 #define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_POEN_POEN_SHIFT))&PDB_POEN_POEN_MASK)
sahilmgandhi 18:6a4db94011d3 3461 /* PODLY Bit Fields */
sahilmgandhi 18:6a4db94011d3 3462 #define PDB_PODLY_DLY2_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 3463 #define PDB_PODLY_DLY2_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3464 #define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY2_SHIFT))&PDB_PODLY_DLY2_MASK)
sahilmgandhi 18:6a4db94011d3 3465 #define PDB_PODLY_DLY1_MASK 0xFFFF0000u
sahilmgandhi 18:6a4db94011d3 3466 #define PDB_PODLY_DLY1_SHIFT 16
sahilmgandhi 18:6a4db94011d3 3467 #define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY1_SHIFT))&PDB_PODLY_DLY1_MASK)
sahilmgandhi 18:6a4db94011d3 3468
sahilmgandhi 18:6a4db94011d3 3469 /**
sahilmgandhi 18:6a4db94011d3 3470 * @}
sahilmgandhi 18:6a4db94011d3 3471 */ /* end of group PDB_Register_Masks */
sahilmgandhi 18:6a4db94011d3 3472
sahilmgandhi 18:6a4db94011d3 3473
sahilmgandhi 18:6a4db94011d3 3474 /* PDB - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 3475 /** Peripheral PDB0 base address */
sahilmgandhi 18:6a4db94011d3 3476 #define PDB0_BASE (0x40036000u)
sahilmgandhi 18:6a4db94011d3 3477 /** Peripheral PDB0 base pointer */
sahilmgandhi 18:6a4db94011d3 3478 #define PDB0 ((PDB_Type *)PDB0_BASE)
sahilmgandhi 18:6a4db94011d3 3479
sahilmgandhi 18:6a4db94011d3 3480 /**
sahilmgandhi 18:6a4db94011d3 3481 * @}
sahilmgandhi 18:6a4db94011d3 3482 */ /* end of group PDB_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 3483
sahilmgandhi 18:6a4db94011d3 3484
sahilmgandhi 18:6a4db94011d3 3485 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3486 -- PIT Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 3487 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 3488
sahilmgandhi 18:6a4db94011d3 3489 /**
sahilmgandhi 18:6a4db94011d3 3490 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 3491 * @{
sahilmgandhi 18:6a4db94011d3 3492 */
sahilmgandhi 18:6a4db94011d3 3493
sahilmgandhi 18:6a4db94011d3 3494 /** PIT - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 3495 typedef struct {
sahilmgandhi 18:6a4db94011d3 3496 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 3497 uint8_t RESERVED_0[252];
sahilmgandhi 18:6a4db94011d3 3498 struct { /* offset: 0x100, array step: 0x10 */
sahilmgandhi 18:6a4db94011d3 3499 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
sahilmgandhi 18:6a4db94011d3 3500 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
sahilmgandhi 18:6a4db94011d3 3501 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
sahilmgandhi 18:6a4db94011d3 3502 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
sahilmgandhi 18:6a4db94011d3 3503 } CHANNEL[4];
sahilmgandhi 18:6a4db94011d3 3504 } PIT_Type;
sahilmgandhi 18:6a4db94011d3 3505
sahilmgandhi 18:6a4db94011d3 3506 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3507 -- PIT Register Masks
sahilmgandhi 18:6a4db94011d3 3508 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 3509
sahilmgandhi 18:6a4db94011d3 3510 /**
sahilmgandhi 18:6a4db94011d3 3511 * @addtogroup PIT_Register_Masks PIT Register Masks
sahilmgandhi 18:6a4db94011d3 3512 * @{
sahilmgandhi 18:6a4db94011d3 3513 */
sahilmgandhi 18:6a4db94011d3 3514
sahilmgandhi 18:6a4db94011d3 3515 /* MCR Bit Fields */
sahilmgandhi 18:6a4db94011d3 3516 #define PIT_MCR_FRZ_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 3517 #define PIT_MCR_FRZ_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3518 #define PIT_MCR_MDIS_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 3519 #define PIT_MCR_MDIS_SHIFT 1
sahilmgandhi 18:6a4db94011d3 3520 /* LDVAL Bit Fields */
sahilmgandhi 18:6a4db94011d3 3521 #define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 3522 #define PIT_LDVAL_TSV_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3523 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
sahilmgandhi 18:6a4db94011d3 3524 /* CVAL Bit Fields */
sahilmgandhi 18:6a4db94011d3 3525 #define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 3526 #define PIT_CVAL_TVL_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3527 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
sahilmgandhi 18:6a4db94011d3 3528 /* TCTRL Bit Fields */
sahilmgandhi 18:6a4db94011d3 3529 #define PIT_TCTRL_TEN_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 3530 #define PIT_TCTRL_TEN_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3531 #define PIT_TCTRL_TIE_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 3532 #define PIT_TCTRL_TIE_SHIFT 1
sahilmgandhi 18:6a4db94011d3 3533 #define PIT_TCTRL_CHN_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 3534 #define PIT_TCTRL_CHN_SHIFT 2
sahilmgandhi 18:6a4db94011d3 3535 /* TFLG Bit Fields */
sahilmgandhi 18:6a4db94011d3 3536 #define PIT_TFLG_TIF_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 3537 #define PIT_TFLG_TIF_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3538
sahilmgandhi 18:6a4db94011d3 3539 /**
sahilmgandhi 18:6a4db94011d3 3540 * @}
sahilmgandhi 18:6a4db94011d3 3541 */ /* end of group PIT_Register_Masks */
sahilmgandhi 18:6a4db94011d3 3542
sahilmgandhi 18:6a4db94011d3 3543
sahilmgandhi 18:6a4db94011d3 3544 /* PIT - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 3545 /** Peripheral PIT base address */
sahilmgandhi 18:6a4db94011d3 3546 #define PIT_BASE (0x40037000u)
sahilmgandhi 18:6a4db94011d3 3547 /** Peripheral PIT base pointer */
sahilmgandhi 18:6a4db94011d3 3548 #define PIT ((PIT_Type *)PIT_BASE)
sahilmgandhi 18:6a4db94011d3 3549
sahilmgandhi 18:6a4db94011d3 3550 /**
sahilmgandhi 18:6a4db94011d3 3551 * @}
sahilmgandhi 18:6a4db94011d3 3552 */ /* end of group PIT_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 3553
sahilmgandhi 18:6a4db94011d3 3554
sahilmgandhi 18:6a4db94011d3 3555 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3556 -- PMC Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 3557 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 3558
sahilmgandhi 18:6a4db94011d3 3559 /**
sahilmgandhi 18:6a4db94011d3 3560 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 3561 * @{
sahilmgandhi 18:6a4db94011d3 3562 */
sahilmgandhi 18:6a4db94011d3 3563
sahilmgandhi 18:6a4db94011d3 3564 /** PMC - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 3565 typedef struct {
sahilmgandhi 18:6a4db94011d3 3566 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status and Control 1 Register, offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 3567 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status and Control 2 Register, offset: 0x1 */
sahilmgandhi 18:6a4db94011d3 3568 __IO uint8_t REGSC; /**< Regulator Status and Control Register, offset: 0x2 */
sahilmgandhi 18:6a4db94011d3 3569 } PMC_Type;
sahilmgandhi 18:6a4db94011d3 3570
sahilmgandhi 18:6a4db94011d3 3571 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3572 -- PMC Register Masks
sahilmgandhi 18:6a4db94011d3 3573 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 3574
sahilmgandhi 18:6a4db94011d3 3575 /**
sahilmgandhi 18:6a4db94011d3 3576 * @addtogroup PMC_Register_Masks PMC Register Masks
sahilmgandhi 18:6a4db94011d3 3577 * @{
sahilmgandhi 18:6a4db94011d3 3578 */
sahilmgandhi 18:6a4db94011d3 3579
sahilmgandhi 18:6a4db94011d3 3580 /* LVDSC1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 3581 #define PMC_LVDSC1_LVDV_MASK 0x3u
sahilmgandhi 18:6a4db94011d3 3582 #define PMC_LVDSC1_LVDV_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3583 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
sahilmgandhi 18:6a4db94011d3 3584 #define PMC_LVDSC1_LVDRE_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 3585 #define PMC_LVDSC1_LVDRE_SHIFT 4
sahilmgandhi 18:6a4db94011d3 3586 #define PMC_LVDSC1_LVDIE_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 3587 #define PMC_LVDSC1_LVDIE_SHIFT 5
sahilmgandhi 18:6a4db94011d3 3588 #define PMC_LVDSC1_LVDACK_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 3589 #define PMC_LVDSC1_LVDACK_SHIFT 6
sahilmgandhi 18:6a4db94011d3 3590 #define PMC_LVDSC1_LVDF_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 3591 #define PMC_LVDSC1_LVDF_SHIFT 7
sahilmgandhi 18:6a4db94011d3 3592 /* LVDSC2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 3593 #define PMC_LVDSC2_LVWV_MASK 0x3u
sahilmgandhi 18:6a4db94011d3 3594 #define PMC_LVDSC2_LVWV_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3595 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
sahilmgandhi 18:6a4db94011d3 3596 #define PMC_LVDSC2_LVWIE_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 3597 #define PMC_LVDSC2_LVWIE_SHIFT 5
sahilmgandhi 18:6a4db94011d3 3598 #define PMC_LVDSC2_LVWACK_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 3599 #define PMC_LVDSC2_LVWACK_SHIFT 6
sahilmgandhi 18:6a4db94011d3 3600 #define PMC_LVDSC2_LVWF_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 3601 #define PMC_LVDSC2_LVWF_SHIFT 7
sahilmgandhi 18:6a4db94011d3 3602 /* REGSC Bit Fields */
sahilmgandhi 18:6a4db94011d3 3603 #define PMC_REGSC_BGBE_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 3604 #define PMC_REGSC_BGBE_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3605 #define PMC_REGSC_REGONS_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 3606 #define PMC_REGSC_REGONS_SHIFT 2
sahilmgandhi 18:6a4db94011d3 3607 #define PMC_REGSC_ACKISO_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 3608 #define PMC_REGSC_ACKISO_SHIFT 3
sahilmgandhi 18:6a4db94011d3 3609
sahilmgandhi 18:6a4db94011d3 3610 /**
sahilmgandhi 18:6a4db94011d3 3611 * @}
sahilmgandhi 18:6a4db94011d3 3612 */ /* end of group PMC_Register_Masks */
sahilmgandhi 18:6a4db94011d3 3613
sahilmgandhi 18:6a4db94011d3 3614
sahilmgandhi 18:6a4db94011d3 3615 /* PMC - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 3616 /** Peripheral PMC base address */
sahilmgandhi 18:6a4db94011d3 3617 #define PMC_BASE (0x4007D000u)
sahilmgandhi 18:6a4db94011d3 3618 /** Peripheral PMC base pointer */
sahilmgandhi 18:6a4db94011d3 3619 #define PMC ((PMC_Type *)PMC_BASE)
sahilmgandhi 18:6a4db94011d3 3620
sahilmgandhi 18:6a4db94011d3 3621 /**
sahilmgandhi 18:6a4db94011d3 3622 * @}
sahilmgandhi 18:6a4db94011d3 3623 */ /* end of group PMC_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 3624
sahilmgandhi 18:6a4db94011d3 3625
sahilmgandhi 18:6a4db94011d3 3626 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3627 -- PORT Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 3628 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 3629
sahilmgandhi 18:6a4db94011d3 3630 /**
sahilmgandhi 18:6a4db94011d3 3631 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 3632 * @{
sahilmgandhi 18:6a4db94011d3 3633 */
sahilmgandhi 18:6a4db94011d3 3634
sahilmgandhi 18:6a4db94011d3 3635 /** PORT - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 3636 typedef struct {
sahilmgandhi 18:6a4db94011d3 3637 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
sahilmgandhi 18:6a4db94011d3 3638 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
sahilmgandhi 18:6a4db94011d3 3639 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
sahilmgandhi 18:6a4db94011d3 3640 uint8_t RESERVED_0[24];
sahilmgandhi 18:6a4db94011d3 3641 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
sahilmgandhi 18:6a4db94011d3 3642 uint8_t RESERVED_1[28];
sahilmgandhi 18:6a4db94011d3 3643 __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */
sahilmgandhi 18:6a4db94011d3 3644 __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */
sahilmgandhi 18:6a4db94011d3 3645 __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */
sahilmgandhi 18:6a4db94011d3 3646 } PORT_Type;
sahilmgandhi 18:6a4db94011d3 3647
sahilmgandhi 18:6a4db94011d3 3648 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3649 -- PORT Register Masks
sahilmgandhi 18:6a4db94011d3 3650 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 3651
sahilmgandhi 18:6a4db94011d3 3652 /**
sahilmgandhi 18:6a4db94011d3 3653 * @addtogroup PORT_Register_Masks PORT Register Masks
sahilmgandhi 18:6a4db94011d3 3654 * @{
sahilmgandhi 18:6a4db94011d3 3655 */
sahilmgandhi 18:6a4db94011d3 3656
sahilmgandhi 18:6a4db94011d3 3657 /* PCR Bit Fields */
sahilmgandhi 18:6a4db94011d3 3658 #define PORT_PCR_PS_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 3659 #define PORT_PCR_PS_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3660 #define PORT_PCR_PE_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 3661 #define PORT_PCR_PE_SHIFT 1
sahilmgandhi 18:6a4db94011d3 3662 #define PORT_PCR_SRE_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 3663 #define PORT_PCR_SRE_SHIFT 2
sahilmgandhi 18:6a4db94011d3 3664 #define PORT_PCR_PFE_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 3665 #define PORT_PCR_PFE_SHIFT 4
sahilmgandhi 18:6a4db94011d3 3666 #define PORT_PCR_ODE_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 3667 #define PORT_PCR_ODE_SHIFT 5
sahilmgandhi 18:6a4db94011d3 3668 #define PORT_PCR_DSE_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 3669 #define PORT_PCR_DSE_SHIFT 6
sahilmgandhi 18:6a4db94011d3 3670 #define PORT_PCR_MUX_MASK 0x700u
sahilmgandhi 18:6a4db94011d3 3671 #define PORT_PCR_MUX_SHIFT 8
sahilmgandhi 18:6a4db94011d3 3672 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
sahilmgandhi 18:6a4db94011d3 3673 #define PORT_PCR_LK_MASK 0x8000u
sahilmgandhi 18:6a4db94011d3 3674 #define PORT_PCR_LK_SHIFT 15
sahilmgandhi 18:6a4db94011d3 3675 #define PORT_PCR_IRQC_MASK 0xF0000u
sahilmgandhi 18:6a4db94011d3 3676 #define PORT_PCR_IRQC_SHIFT 16
sahilmgandhi 18:6a4db94011d3 3677 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
sahilmgandhi 18:6a4db94011d3 3678 #define PORT_PCR_ISF_MASK 0x1000000u
sahilmgandhi 18:6a4db94011d3 3679 #define PORT_PCR_ISF_SHIFT 24
sahilmgandhi 18:6a4db94011d3 3680 /* GPCLR Bit Fields */
sahilmgandhi 18:6a4db94011d3 3681 #define PORT_GPCLR_GPWD_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 3682 #define PORT_GPCLR_GPWD_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3683 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
sahilmgandhi 18:6a4db94011d3 3684 #define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
sahilmgandhi 18:6a4db94011d3 3685 #define PORT_GPCLR_GPWE_SHIFT 16
sahilmgandhi 18:6a4db94011d3 3686 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
sahilmgandhi 18:6a4db94011d3 3687 /* GPCHR Bit Fields */
sahilmgandhi 18:6a4db94011d3 3688 #define PORT_GPCHR_GPWD_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 3689 #define PORT_GPCHR_GPWD_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3690 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
sahilmgandhi 18:6a4db94011d3 3691 #define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
sahilmgandhi 18:6a4db94011d3 3692 #define PORT_GPCHR_GPWE_SHIFT 16
sahilmgandhi 18:6a4db94011d3 3693 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
sahilmgandhi 18:6a4db94011d3 3694 /* ISFR Bit Fields */
sahilmgandhi 18:6a4db94011d3 3695 #define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 3696 #define PORT_ISFR_ISF_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3697 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
sahilmgandhi 18:6a4db94011d3 3698 /* DFER Bit Fields */
sahilmgandhi 18:6a4db94011d3 3699 #define PORT_DFER_DFE_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 3700 #define PORT_DFER_DFE_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3701 #define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)
sahilmgandhi 18:6a4db94011d3 3702 /* DFCR Bit Fields */
sahilmgandhi 18:6a4db94011d3 3703 #define PORT_DFCR_CS_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 3704 #define PORT_DFCR_CS_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3705 /* DFWR Bit Fields */
sahilmgandhi 18:6a4db94011d3 3706 #define PORT_DFWR_FILT_MASK 0x1Fu
sahilmgandhi 18:6a4db94011d3 3707 #define PORT_DFWR_FILT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3708 #define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK)
sahilmgandhi 18:6a4db94011d3 3709
sahilmgandhi 18:6a4db94011d3 3710 /**
sahilmgandhi 18:6a4db94011d3 3711 * @}
sahilmgandhi 18:6a4db94011d3 3712 */ /* end of group PORT_Register_Masks */
sahilmgandhi 18:6a4db94011d3 3713
sahilmgandhi 18:6a4db94011d3 3714
sahilmgandhi 18:6a4db94011d3 3715 /* PORT - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 3716 /** Peripheral PORTA base address */
sahilmgandhi 18:6a4db94011d3 3717 #define PORTA_BASE (0x40049000u)
sahilmgandhi 18:6a4db94011d3 3718 /** Peripheral PORTA base pointer */
sahilmgandhi 18:6a4db94011d3 3719 #define PORTA ((PORT_Type *)PORTA_BASE)
sahilmgandhi 18:6a4db94011d3 3720 /** Peripheral PORTB base address */
sahilmgandhi 18:6a4db94011d3 3721 #define PORTB_BASE (0x4004A000u)
sahilmgandhi 18:6a4db94011d3 3722 /** Peripheral PORTB base pointer */
sahilmgandhi 18:6a4db94011d3 3723 #define PORTB ((PORT_Type *)PORTB_BASE)
sahilmgandhi 18:6a4db94011d3 3724 /** Peripheral PORTC base address */
sahilmgandhi 18:6a4db94011d3 3725 #define PORTC_BASE (0x4004B000u)
sahilmgandhi 18:6a4db94011d3 3726 /** Peripheral PORTC base pointer */
sahilmgandhi 18:6a4db94011d3 3727 #define PORTC ((PORT_Type *)PORTC_BASE)
sahilmgandhi 18:6a4db94011d3 3728 /** Peripheral PORTD base address */
sahilmgandhi 18:6a4db94011d3 3729 #define PORTD_BASE (0x4004C000u)
sahilmgandhi 18:6a4db94011d3 3730 /** Peripheral PORTD base pointer */
sahilmgandhi 18:6a4db94011d3 3731 #define PORTD ((PORT_Type *)PORTD_BASE)
sahilmgandhi 18:6a4db94011d3 3732 /** Peripheral PORTE base address */
sahilmgandhi 18:6a4db94011d3 3733 #define PORTE_BASE (0x4004D000u)
sahilmgandhi 18:6a4db94011d3 3734 /** Peripheral PORTE base pointer */
sahilmgandhi 18:6a4db94011d3 3735 #define PORTE ((PORT_Type *)PORTE_BASE)
sahilmgandhi 18:6a4db94011d3 3736
sahilmgandhi 18:6a4db94011d3 3737 /**
sahilmgandhi 18:6a4db94011d3 3738 * @}
sahilmgandhi 18:6a4db94011d3 3739 */ /* end of group PORT_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 3740
sahilmgandhi 18:6a4db94011d3 3741
sahilmgandhi 18:6a4db94011d3 3742 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3743 -- RCM Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 3744 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 3745
sahilmgandhi 18:6a4db94011d3 3746 /**
sahilmgandhi 18:6a4db94011d3 3747 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 3748 * @{
sahilmgandhi 18:6a4db94011d3 3749 */
sahilmgandhi 18:6a4db94011d3 3750
sahilmgandhi 18:6a4db94011d3 3751 /** RCM - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 3752 typedef struct {
sahilmgandhi 18:6a4db94011d3 3753 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 3754 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
sahilmgandhi 18:6a4db94011d3 3755 uint8_t RESERVED_0[2];
sahilmgandhi 18:6a4db94011d3 3756 __IO uint8_t RPFC; /**< Reset Pin Filter Control Register, offset: 0x4 */
sahilmgandhi 18:6a4db94011d3 3757 __IO uint8_t RPFW; /**< Reset Pin Filter Width Register, offset: 0x5 */
sahilmgandhi 18:6a4db94011d3 3758 uint8_t RESERVED_1[1];
sahilmgandhi 18:6a4db94011d3 3759 __I uint8_t MR; /**< Mode Register, offset: 0x7 */
sahilmgandhi 18:6a4db94011d3 3760 } RCM_Type;
sahilmgandhi 18:6a4db94011d3 3761
sahilmgandhi 18:6a4db94011d3 3762 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3763 -- RCM Register Masks
sahilmgandhi 18:6a4db94011d3 3764 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 3765
sahilmgandhi 18:6a4db94011d3 3766 /**
sahilmgandhi 18:6a4db94011d3 3767 * @addtogroup RCM_Register_Masks RCM Register Masks
sahilmgandhi 18:6a4db94011d3 3768 * @{
sahilmgandhi 18:6a4db94011d3 3769 */
sahilmgandhi 18:6a4db94011d3 3770
sahilmgandhi 18:6a4db94011d3 3771 /* SRS0 Bit Fields */
sahilmgandhi 18:6a4db94011d3 3772 #define RCM_SRS0_WAKEUP_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 3773 #define RCM_SRS0_WAKEUP_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3774 #define RCM_SRS0_LVD_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 3775 #define RCM_SRS0_LVD_SHIFT 1
sahilmgandhi 18:6a4db94011d3 3776 #define RCM_SRS0_LOC_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 3777 #define RCM_SRS0_LOC_SHIFT 2
sahilmgandhi 18:6a4db94011d3 3778 #define RCM_SRS0_LOL_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 3779 #define RCM_SRS0_LOL_SHIFT 3
sahilmgandhi 18:6a4db94011d3 3780 #define RCM_SRS0_WDOG_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 3781 #define RCM_SRS0_WDOG_SHIFT 5
sahilmgandhi 18:6a4db94011d3 3782 #define RCM_SRS0_PIN_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 3783 #define RCM_SRS0_PIN_SHIFT 6
sahilmgandhi 18:6a4db94011d3 3784 #define RCM_SRS0_POR_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 3785 #define RCM_SRS0_POR_SHIFT 7
sahilmgandhi 18:6a4db94011d3 3786 /* SRS1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 3787 #define RCM_SRS1_JTAG_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 3788 #define RCM_SRS1_JTAG_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3789 #define RCM_SRS1_LOCKUP_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 3790 #define RCM_SRS1_LOCKUP_SHIFT 1
sahilmgandhi 18:6a4db94011d3 3791 #define RCM_SRS1_SW_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 3792 #define RCM_SRS1_SW_SHIFT 2
sahilmgandhi 18:6a4db94011d3 3793 #define RCM_SRS1_MDM_AP_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 3794 #define RCM_SRS1_MDM_AP_SHIFT 3
sahilmgandhi 18:6a4db94011d3 3795 #define RCM_SRS1_EZPT_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 3796 #define RCM_SRS1_EZPT_SHIFT 4
sahilmgandhi 18:6a4db94011d3 3797 #define RCM_SRS1_SACKERR_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 3798 #define RCM_SRS1_SACKERR_SHIFT 5
sahilmgandhi 18:6a4db94011d3 3799 /* RPFC Bit Fields */
sahilmgandhi 18:6a4db94011d3 3800 #define RCM_RPFC_RSTFLTSRW_MASK 0x3u
sahilmgandhi 18:6a4db94011d3 3801 #define RCM_RPFC_RSTFLTSRW_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3802 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
sahilmgandhi 18:6a4db94011d3 3803 #define RCM_RPFC_RSTFLTSS_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 3804 #define RCM_RPFC_RSTFLTSS_SHIFT 2
sahilmgandhi 18:6a4db94011d3 3805 /* RPFW Bit Fields */
sahilmgandhi 18:6a4db94011d3 3806 #define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
sahilmgandhi 18:6a4db94011d3 3807 #define RCM_RPFW_RSTFLTSEL_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3808 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
sahilmgandhi 18:6a4db94011d3 3809 /* MR Bit Fields */
sahilmgandhi 18:6a4db94011d3 3810 #define RCM_MR_EZP_MS_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 3811 #define RCM_MR_EZP_MS_SHIFT 1
sahilmgandhi 18:6a4db94011d3 3812
sahilmgandhi 18:6a4db94011d3 3813 /**
sahilmgandhi 18:6a4db94011d3 3814 * @}
sahilmgandhi 18:6a4db94011d3 3815 */ /* end of group RCM_Register_Masks */
sahilmgandhi 18:6a4db94011d3 3816
sahilmgandhi 18:6a4db94011d3 3817
sahilmgandhi 18:6a4db94011d3 3818 /* RCM - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 3819 /** Peripheral RCM base address */
sahilmgandhi 18:6a4db94011d3 3820 #define RCM_BASE (0x4007F000u)
sahilmgandhi 18:6a4db94011d3 3821 /** Peripheral RCM base pointer */
sahilmgandhi 18:6a4db94011d3 3822 #define RCM ((RCM_Type *)RCM_BASE)
sahilmgandhi 18:6a4db94011d3 3823
sahilmgandhi 18:6a4db94011d3 3824 /**
sahilmgandhi 18:6a4db94011d3 3825 * @}
sahilmgandhi 18:6a4db94011d3 3826 */ /* end of group RCM_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 3827
sahilmgandhi 18:6a4db94011d3 3828
sahilmgandhi 18:6a4db94011d3 3829 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3830 -- RFSYS Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 3831 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 3832
sahilmgandhi 18:6a4db94011d3 3833 /**
sahilmgandhi 18:6a4db94011d3 3834 * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 3835 * @{
sahilmgandhi 18:6a4db94011d3 3836 */
sahilmgandhi 18:6a4db94011d3 3837
sahilmgandhi 18:6a4db94011d3 3838 /** RFSYS - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 3839 typedef struct {
sahilmgandhi 18:6a4db94011d3 3840 __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
sahilmgandhi 18:6a4db94011d3 3841 } RFSYS_Type;
sahilmgandhi 18:6a4db94011d3 3842
sahilmgandhi 18:6a4db94011d3 3843 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3844 -- RFSYS Register Masks
sahilmgandhi 18:6a4db94011d3 3845 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 3846
sahilmgandhi 18:6a4db94011d3 3847 /**
sahilmgandhi 18:6a4db94011d3 3848 * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
sahilmgandhi 18:6a4db94011d3 3849 * @{
sahilmgandhi 18:6a4db94011d3 3850 */
sahilmgandhi 18:6a4db94011d3 3851
sahilmgandhi 18:6a4db94011d3 3852 /* REG Bit Fields */
sahilmgandhi 18:6a4db94011d3 3853 #define RFSYS_REG_LL_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 3854 #define RFSYS_REG_LL_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3855 #define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK)
sahilmgandhi 18:6a4db94011d3 3856 #define RFSYS_REG_LH_MASK 0xFF00u
sahilmgandhi 18:6a4db94011d3 3857 #define RFSYS_REG_LH_SHIFT 8
sahilmgandhi 18:6a4db94011d3 3858 #define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK)
sahilmgandhi 18:6a4db94011d3 3859 #define RFSYS_REG_HL_MASK 0xFF0000u
sahilmgandhi 18:6a4db94011d3 3860 #define RFSYS_REG_HL_SHIFT 16
sahilmgandhi 18:6a4db94011d3 3861 #define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK)
sahilmgandhi 18:6a4db94011d3 3862 #define RFSYS_REG_HH_MASK 0xFF000000u
sahilmgandhi 18:6a4db94011d3 3863 #define RFSYS_REG_HH_SHIFT 24
sahilmgandhi 18:6a4db94011d3 3864 #define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK)
sahilmgandhi 18:6a4db94011d3 3865
sahilmgandhi 18:6a4db94011d3 3866 /**
sahilmgandhi 18:6a4db94011d3 3867 * @}
sahilmgandhi 18:6a4db94011d3 3868 */ /* end of group RFSYS_Register_Masks */
sahilmgandhi 18:6a4db94011d3 3869
sahilmgandhi 18:6a4db94011d3 3870
sahilmgandhi 18:6a4db94011d3 3871 /* RFSYS - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 3872 /** Peripheral RFSYS base address */
sahilmgandhi 18:6a4db94011d3 3873 #define RFSYS_BASE (0x40041000u)
sahilmgandhi 18:6a4db94011d3 3874 /** Peripheral RFSYS base pointer */
sahilmgandhi 18:6a4db94011d3 3875 #define RFSYS ((RFSYS_Type *)RFSYS_BASE)
sahilmgandhi 18:6a4db94011d3 3876
sahilmgandhi 18:6a4db94011d3 3877 /**
sahilmgandhi 18:6a4db94011d3 3878 * @}
sahilmgandhi 18:6a4db94011d3 3879 */ /* end of group RFSYS_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 3880
sahilmgandhi 18:6a4db94011d3 3881
sahilmgandhi 18:6a4db94011d3 3882 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3883 -- RFVBAT Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 3884 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 3885
sahilmgandhi 18:6a4db94011d3 3886 /**
sahilmgandhi 18:6a4db94011d3 3887 * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 3888 * @{
sahilmgandhi 18:6a4db94011d3 3889 */
sahilmgandhi 18:6a4db94011d3 3890
sahilmgandhi 18:6a4db94011d3 3891 /** RFVBAT - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 3892 typedef struct {
sahilmgandhi 18:6a4db94011d3 3893 __IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
sahilmgandhi 18:6a4db94011d3 3894 } RFVBAT_Type;
sahilmgandhi 18:6a4db94011d3 3895
sahilmgandhi 18:6a4db94011d3 3896 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3897 -- RFVBAT Register Masks
sahilmgandhi 18:6a4db94011d3 3898 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 3899
sahilmgandhi 18:6a4db94011d3 3900 /**
sahilmgandhi 18:6a4db94011d3 3901 * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
sahilmgandhi 18:6a4db94011d3 3902 * @{
sahilmgandhi 18:6a4db94011d3 3903 */
sahilmgandhi 18:6a4db94011d3 3904
sahilmgandhi 18:6a4db94011d3 3905 /* REG Bit Fields */
sahilmgandhi 18:6a4db94011d3 3906 #define RFVBAT_REG_LL_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 3907 #define RFVBAT_REG_LL_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3908 #define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LL_SHIFT))&RFVBAT_REG_LL_MASK)
sahilmgandhi 18:6a4db94011d3 3909 #define RFVBAT_REG_LH_MASK 0xFF00u
sahilmgandhi 18:6a4db94011d3 3910 #define RFVBAT_REG_LH_SHIFT 8
sahilmgandhi 18:6a4db94011d3 3911 #define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LH_SHIFT))&RFVBAT_REG_LH_MASK)
sahilmgandhi 18:6a4db94011d3 3912 #define RFVBAT_REG_HL_MASK 0xFF0000u
sahilmgandhi 18:6a4db94011d3 3913 #define RFVBAT_REG_HL_SHIFT 16
sahilmgandhi 18:6a4db94011d3 3914 #define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HL_SHIFT))&RFVBAT_REG_HL_MASK)
sahilmgandhi 18:6a4db94011d3 3915 #define RFVBAT_REG_HH_MASK 0xFF000000u
sahilmgandhi 18:6a4db94011d3 3916 #define RFVBAT_REG_HH_SHIFT 24
sahilmgandhi 18:6a4db94011d3 3917 #define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HH_SHIFT))&RFVBAT_REG_HH_MASK)
sahilmgandhi 18:6a4db94011d3 3918
sahilmgandhi 18:6a4db94011d3 3919 /**
sahilmgandhi 18:6a4db94011d3 3920 * @}
sahilmgandhi 18:6a4db94011d3 3921 */ /* end of group RFVBAT_Register_Masks */
sahilmgandhi 18:6a4db94011d3 3922
sahilmgandhi 18:6a4db94011d3 3923
sahilmgandhi 18:6a4db94011d3 3924 /* RFVBAT - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 3925 /** Peripheral RFVBAT base address */
sahilmgandhi 18:6a4db94011d3 3926 #define RFVBAT_BASE (0x4003E000u)
sahilmgandhi 18:6a4db94011d3 3927 /** Peripheral RFVBAT base pointer */
sahilmgandhi 18:6a4db94011d3 3928 #define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE)
sahilmgandhi 18:6a4db94011d3 3929
sahilmgandhi 18:6a4db94011d3 3930 /**
sahilmgandhi 18:6a4db94011d3 3931 * @}
sahilmgandhi 18:6a4db94011d3 3932 */ /* end of group RFVBAT_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 3933
sahilmgandhi 18:6a4db94011d3 3934
sahilmgandhi 18:6a4db94011d3 3935 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3936 -- RTC Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 3937 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 3938
sahilmgandhi 18:6a4db94011d3 3939 /**
sahilmgandhi 18:6a4db94011d3 3940 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 3941 * @{
sahilmgandhi 18:6a4db94011d3 3942 */
sahilmgandhi 18:6a4db94011d3 3943
sahilmgandhi 18:6a4db94011d3 3944 /** RTC - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 3945 typedef struct {
sahilmgandhi 18:6a4db94011d3 3946 __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 3947 __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
sahilmgandhi 18:6a4db94011d3 3948 __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
sahilmgandhi 18:6a4db94011d3 3949 __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
sahilmgandhi 18:6a4db94011d3 3950 __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 3951 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 3952 __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 3953 __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 3954 uint8_t RESERVED_0[2016];
sahilmgandhi 18:6a4db94011d3 3955 __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */
sahilmgandhi 18:6a4db94011d3 3956 __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */
sahilmgandhi 18:6a4db94011d3 3957 } RTC_Type;
sahilmgandhi 18:6a4db94011d3 3958
sahilmgandhi 18:6a4db94011d3 3959 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 3960 -- RTC Register Masks
sahilmgandhi 18:6a4db94011d3 3961 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 3962
sahilmgandhi 18:6a4db94011d3 3963 /**
sahilmgandhi 18:6a4db94011d3 3964 * @addtogroup RTC_Register_Masks RTC Register Masks
sahilmgandhi 18:6a4db94011d3 3965 * @{
sahilmgandhi 18:6a4db94011d3 3966 */
sahilmgandhi 18:6a4db94011d3 3967
sahilmgandhi 18:6a4db94011d3 3968 /* TSR Bit Fields */
sahilmgandhi 18:6a4db94011d3 3969 #define RTC_TSR_TSR_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 3970 #define RTC_TSR_TSR_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3971 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
sahilmgandhi 18:6a4db94011d3 3972 /* TPR Bit Fields */
sahilmgandhi 18:6a4db94011d3 3973 #define RTC_TPR_TPR_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 3974 #define RTC_TPR_TPR_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3975 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
sahilmgandhi 18:6a4db94011d3 3976 /* TAR Bit Fields */
sahilmgandhi 18:6a4db94011d3 3977 #define RTC_TAR_TAR_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 3978 #define RTC_TAR_TAR_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3979 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
sahilmgandhi 18:6a4db94011d3 3980 /* TCR Bit Fields */
sahilmgandhi 18:6a4db94011d3 3981 #define RTC_TCR_TCR_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 3982 #define RTC_TCR_TCR_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3983 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
sahilmgandhi 18:6a4db94011d3 3984 #define RTC_TCR_CIR_MASK 0xFF00u
sahilmgandhi 18:6a4db94011d3 3985 #define RTC_TCR_CIR_SHIFT 8
sahilmgandhi 18:6a4db94011d3 3986 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
sahilmgandhi 18:6a4db94011d3 3987 #define RTC_TCR_TCV_MASK 0xFF0000u
sahilmgandhi 18:6a4db94011d3 3988 #define RTC_TCR_TCV_SHIFT 16
sahilmgandhi 18:6a4db94011d3 3989 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
sahilmgandhi 18:6a4db94011d3 3990 #define RTC_TCR_CIC_MASK 0xFF000000u
sahilmgandhi 18:6a4db94011d3 3991 #define RTC_TCR_CIC_SHIFT 24
sahilmgandhi 18:6a4db94011d3 3992 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
sahilmgandhi 18:6a4db94011d3 3993 /* CR Bit Fields */
sahilmgandhi 18:6a4db94011d3 3994 #define RTC_CR_SWR_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 3995 #define RTC_CR_SWR_SHIFT 0
sahilmgandhi 18:6a4db94011d3 3996 #define RTC_CR_WPE_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 3997 #define RTC_CR_WPE_SHIFT 1
sahilmgandhi 18:6a4db94011d3 3998 #define RTC_CR_SUP_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 3999 #define RTC_CR_SUP_SHIFT 2
sahilmgandhi 18:6a4db94011d3 4000 #define RTC_CR_UM_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 4001 #define RTC_CR_UM_SHIFT 3
sahilmgandhi 18:6a4db94011d3 4002 #define RTC_CR_OSCE_MASK 0x100u
sahilmgandhi 18:6a4db94011d3 4003 #define RTC_CR_OSCE_SHIFT 8
sahilmgandhi 18:6a4db94011d3 4004 #define RTC_CR_CLKO_MASK 0x200u
sahilmgandhi 18:6a4db94011d3 4005 #define RTC_CR_CLKO_SHIFT 9
sahilmgandhi 18:6a4db94011d3 4006 #define RTC_CR_SC16P_MASK 0x400u
sahilmgandhi 18:6a4db94011d3 4007 #define RTC_CR_SC16P_SHIFT 10
sahilmgandhi 18:6a4db94011d3 4008 #define RTC_CR_SC8P_MASK 0x800u
sahilmgandhi 18:6a4db94011d3 4009 #define RTC_CR_SC8P_SHIFT 11
sahilmgandhi 18:6a4db94011d3 4010 #define RTC_CR_SC4P_MASK 0x1000u
sahilmgandhi 18:6a4db94011d3 4011 #define RTC_CR_SC4P_SHIFT 12
sahilmgandhi 18:6a4db94011d3 4012 #define RTC_CR_SC2P_MASK 0x2000u
sahilmgandhi 18:6a4db94011d3 4013 #define RTC_CR_SC2P_SHIFT 13
sahilmgandhi 18:6a4db94011d3 4014 /* SR Bit Fields */
sahilmgandhi 18:6a4db94011d3 4015 #define RTC_SR_TIF_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 4016 #define RTC_SR_TIF_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4017 #define RTC_SR_TOF_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 4018 #define RTC_SR_TOF_SHIFT 1
sahilmgandhi 18:6a4db94011d3 4019 #define RTC_SR_TAF_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 4020 #define RTC_SR_TAF_SHIFT 2
sahilmgandhi 18:6a4db94011d3 4021 #define RTC_SR_TCE_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 4022 #define RTC_SR_TCE_SHIFT 4
sahilmgandhi 18:6a4db94011d3 4023 /* LR Bit Fields */
sahilmgandhi 18:6a4db94011d3 4024 #define RTC_LR_TCL_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 4025 #define RTC_LR_TCL_SHIFT 3
sahilmgandhi 18:6a4db94011d3 4026 #define RTC_LR_CRL_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 4027 #define RTC_LR_CRL_SHIFT 4
sahilmgandhi 18:6a4db94011d3 4028 #define RTC_LR_SRL_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 4029 #define RTC_LR_SRL_SHIFT 5
sahilmgandhi 18:6a4db94011d3 4030 #define RTC_LR_LRL_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 4031 #define RTC_LR_LRL_SHIFT 6
sahilmgandhi 18:6a4db94011d3 4032 /* IER Bit Fields */
sahilmgandhi 18:6a4db94011d3 4033 #define RTC_IER_TIIE_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 4034 #define RTC_IER_TIIE_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4035 #define RTC_IER_TOIE_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 4036 #define RTC_IER_TOIE_SHIFT 1
sahilmgandhi 18:6a4db94011d3 4037 #define RTC_IER_TAIE_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 4038 #define RTC_IER_TAIE_SHIFT 2
sahilmgandhi 18:6a4db94011d3 4039 #define RTC_IER_TSIE_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 4040 #define RTC_IER_TSIE_SHIFT 4
sahilmgandhi 18:6a4db94011d3 4041 /* WAR Bit Fields */
sahilmgandhi 18:6a4db94011d3 4042 #define RTC_WAR_TSRW_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 4043 #define RTC_WAR_TSRW_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4044 #define RTC_WAR_TPRW_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 4045 #define RTC_WAR_TPRW_SHIFT 1
sahilmgandhi 18:6a4db94011d3 4046 #define RTC_WAR_TARW_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 4047 #define RTC_WAR_TARW_SHIFT 2
sahilmgandhi 18:6a4db94011d3 4048 #define RTC_WAR_TCRW_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 4049 #define RTC_WAR_TCRW_SHIFT 3
sahilmgandhi 18:6a4db94011d3 4050 #define RTC_WAR_CRW_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 4051 #define RTC_WAR_CRW_SHIFT 4
sahilmgandhi 18:6a4db94011d3 4052 #define RTC_WAR_SRW_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 4053 #define RTC_WAR_SRW_SHIFT 5
sahilmgandhi 18:6a4db94011d3 4054 #define RTC_WAR_LRW_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 4055 #define RTC_WAR_LRW_SHIFT 6
sahilmgandhi 18:6a4db94011d3 4056 #define RTC_WAR_IERW_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 4057 #define RTC_WAR_IERW_SHIFT 7
sahilmgandhi 18:6a4db94011d3 4058 /* RAR Bit Fields */
sahilmgandhi 18:6a4db94011d3 4059 #define RTC_RAR_TSRR_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 4060 #define RTC_RAR_TSRR_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4061 #define RTC_RAR_TPRR_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 4062 #define RTC_RAR_TPRR_SHIFT 1
sahilmgandhi 18:6a4db94011d3 4063 #define RTC_RAR_TARR_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 4064 #define RTC_RAR_TARR_SHIFT 2
sahilmgandhi 18:6a4db94011d3 4065 #define RTC_RAR_TCRR_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 4066 #define RTC_RAR_TCRR_SHIFT 3
sahilmgandhi 18:6a4db94011d3 4067 #define RTC_RAR_CRR_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 4068 #define RTC_RAR_CRR_SHIFT 4
sahilmgandhi 18:6a4db94011d3 4069 #define RTC_RAR_SRR_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 4070 #define RTC_RAR_SRR_SHIFT 5
sahilmgandhi 18:6a4db94011d3 4071 #define RTC_RAR_LRR_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 4072 #define RTC_RAR_LRR_SHIFT 6
sahilmgandhi 18:6a4db94011d3 4073 #define RTC_RAR_IERR_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 4074 #define RTC_RAR_IERR_SHIFT 7
sahilmgandhi 18:6a4db94011d3 4075
sahilmgandhi 18:6a4db94011d3 4076 /**
sahilmgandhi 18:6a4db94011d3 4077 * @}
sahilmgandhi 18:6a4db94011d3 4078 */ /* end of group RTC_Register_Masks */
sahilmgandhi 18:6a4db94011d3 4079
sahilmgandhi 18:6a4db94011d3 4080
sahilmgandhi 18:6a4db94011d3 4081 /* RTC - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 4082 /** Peripheral RTC base address */
sahilmgandhi 18:6a4db94011d3 4083 #define RTC_BASE (0x4003D000u)
sahilmgandhi 18:6a4db94011d3 4084 /** Peripheral RTC base pointer */
sahilmgandhi 18:6a4db94011d3 4085 #define RTC ((RTC_Type *)RTC_BASE)
sahilmgandhi 18:6a4db94011d3 4086
sahilmgandhi 18:6a4db94011d3 4087 /**
sahilmgandhi 18:6a4db94011d3 4088 * @}
sahilmgandhi 18:6a4db94011d3 4089 */ /* end of group RTC_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 4090
sahilmgandhi 18:6a4db94011d3 4091
sahilmgandhi 18:6a4db94011d3 4092 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 4093 -- SIM Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 4094 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 4095
sahilmgandhi 18:6a4db94011d3 4096 /**
sahilmgandhi 18:6a4db94011d3 4097 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 4098 * @{
sahilmgandhi 18:6a4db94011d3 4099 */
sahilmgandhi 18:6a4db94011d3 4100
sahilmgandhi 18:6a4db94011d3 4101 /** SIM - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 4102 typedef struct {
sahilmgandhi 18:6a4db94011d3 4103 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 4104 __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
sahilmgandhi 18:6a4db94011d3 4105 uint8_t RESERVED_0[4092];
sahilmgandhi 18:6a4db94011d3 4106 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
sahilmgandhi 18:6a4db94011d3 4107 uint8_t RESERVED_1[4];
sahilmgandhi 18:6a4db94011d3 4108 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
sahilmgandhi 18:6a4db94011d3 4109 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
sahilmgandhi 18:6a4db94011d3 4110 uint8_t RESERVED_2[4];
sahilmgandhi 18:6a4db94011d3 4111 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
sahilmgandhi 18:6a4db94011d3 4112 uint8_t RESERVED_3[8];
sahilmgandhi 18:6a4db94011d3 4113 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
sahilmgandhi 18:6a4db94011d3 4114 __IO uint32_t SCGC1; /**< System Clock Gating Control Register 1, offset: 0x1028 */
sahilmgandhi 18:6a4db94011d3 4115 __IO uint32_t SCGC2; /**< System Clock Gating Control Register 2, offset: 0x102C */
sahilmgandhi 18:6a4db94011d3 4116 __IO uint32_t SCGC3; /**< System Clock Gating Control Register 3, offset: 0x1030 */
sahilmgandhi 18:6a4db94011d3 4117 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
sahilmgandhi 18:6a4db94011d3 4118 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
sahilmgandhi 18:6a4db94011d3 4119 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
sahilmgandhi 18:6a4db94011d3 4120 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
sahilmgandhi 18:6a4db94011d3 4121 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
sahilmgandhi 18:6a4db94011d3 4122 __IO uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */
sahilmgandhi 18:6a4db94011d3 4123 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
sahilmgandhi 18:6a4db94011d3 4124 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
sahilmgandhi 18:6a4db94011d3 4125 __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */
sahilmgandhi 18:6a4db94011d3 4126 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
sahilmgandhi 18:6a4db94011d3 4127 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
sahilmgandhi 18:6a4db94011d3 4128 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
sahilmgandhi 18:6a4db94011d3 4129 } SIM_Type;
sahilmgandhi 18:6a4db94011d3 4130
sahilmgandhi 18:6a4db94011d3 4131 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 4132 -- SIM Register Masks
sahilmgandhi 18:6a4db94011d3 4133 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 4134
sahilmgandhi 18:6a4db94011d3 4135 /**
sahilmgandhi 18:6a4db94011d3 4136 * @addtogroup SIM_Register_Masks SIM Register Masks
sahilmgandhi 18:6a4db94011d3 4137 * @{
sahilmgandhi 18:6a4db94011d3 4138 */
sahilmgandhi 18:6a4db94011d3 4139
sahilmgandhi 18:6a4db94011d3 4140 /* SOPT1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 4141 #define SIM_SOPT1_RAMSIZE_MASK 0xF000u
sahilmgandhi 18:6a4db94011d3 4142 #define SIM_SOPT1_RAMSIZE_SHIFT 12
sahilmgandhi 18:6a4db94011d3 4143 #define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_RAMSIZE_SHIFT))&SIM_SOPT1_RAMSIZE_MASK)
sahilmgandhi 18:6a4db94011d3 4144 #define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
sahilmgandhi 18:6a4db94011d3 4145 #define SIM_SOPT1_OSC32KSEL_SHIFT 18
sahilmgandhi 18:6a4db94011d3 4146 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
sahilmgandhi 18:6a4db94011d3 4147 #define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
sahilmgandhi 18:6a4db94011d3 4148 #define SIM_SOPT1_USBVSTBY_SHIFT 29
sahilmgandhi 18:6a4db94011d3 4149 #define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
sahilmgandhi 18:6a4db94011d3 4150 #define SIM_SOPT1_USBSSTBY_SHIFT 30
sahilmgandhi 18:6a4db94011d3 4151 #define SIM_SOPT1_USBREGEN_MASK 0x80000000u
sahilmgandhi 18:6a4db94011d3 4152 #define SIM_SOPT1_USBREGEN_SHIFT 31
sahilmgandhi 18:6a4db94011d3 4153 /* SOPT1CFG Bit Fields */
sahilmgandhi 18:6a4db94011d3 4154 #define SIM_SOPT1CFG_URWE_MASK 0x1000000u
sahilmgandhi 18:6a4db94011d3 4155 #define SIM_SOPT1CFG_URWE_SHIFT 24
sahilmgandhi 18:6a4db94011d3 4156 #define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
sahilmgandhi 18:6a4db94011d3 4157 #define SIM_SOPT1CFG_UVSWE_SHIFT 25
sahilmgandhi 18:6a4db94011d3 4158 #define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
sahilmgandhi 18:6a4db94011d3 4159 #define SIM_SOPT1CFG_USSWE_SHIFT 26
sahilmgandhi 18:6a4db94011d3 4160 /* SOPT2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 4161 #define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 4162 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
sahilmgandhi 18:6a4db94011d3 4163 #define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
sahilmgandhi 18:6a4db94011d3 4164 #define SIM_SOPT2_CLKOUTSEL_SHIFT 5
sahilmgandhi 18:6a4db94011d3 4165 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
sahilmgandhi 18:6a4db94011d3 4166 #define SIM_SOPT2_PTD7PAD_MASK 0x800u
sahilmgandhi 18:6a4db94011d3 4167 #define SIM_SOPT2_PTD7PAD_SHIFT 11
sahilmgandhi 18:6a4db94011d3 4168 #define SIM_SOPT2_TRACECLKSEL_MASK 0x1000u
sahilmgandhi 18:6a4db94011d3 4169 #define SIM_SOPT2_TRACECLKSEL_SHIFT 12
sahilmgandhi 18:6a4db94011d3 4170 #define SIM_SOPT2_PLLFLLSEL_MASK 0x10000u
sahilmgandhi 18:6a4db94011d3 4171 #define SIM_SOPT2_PLLFLLSEL_SHIFT 16
sahilmgandhi 18:6a4db94011d3 4172 #define SIM_SOPT2_USBSRC_MASK 0x40000u
sahilmgandhi 18:6a4db94011d3 4173 #define SIM_SOPT2_USBSRC_SHIFT 18
sahilmgandhi 18:6a4db94011d3 4174 /* SOPT4 Bit Fields */
sahilmgandhi 18:6a4db94011d3 4175 #define SIM_SOPT4_FTM0FLT0_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 4176 #define SIM_SOPT4_FTM0FLT0_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4177 #define SIM_SOPT4_FTM0FLT1_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 4178 #define SIM_SOPT4_FTM0FLT1_SHIFT 1
sahilmgandhi 18:6a4db94011d3 4179 #define SIM_SOPT4_FTM0FLT2_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 4180 #define SIM_SOPT4_FTM0FLT2_SHIFT 2
sahilmgandhi 18:6a4db94011d3 4181 #define SIM_SOPT4_FTM1FLT0_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 4182 #define SIM_SOPT4_FTM1FLT0_SHIFT 4
sahilmgandhi 18:6a4db94011d3 4183 #define SIM_SOPT4_FTM2FLT0_MASK 0x100u
sahilmgandhi 18:6a4db94011d3 4184 #define SIM_SOPT4_FTM2FLT0_SHIFT 8
sahilmgandhi 18:6a4db94011d3 4185 #define SIM_SOPT4_FTM1CH0SRC_MASK 0xC0000u
sahilmgandhi 18:6a4db94011d3 4186 #define SIM_SOPT4_FTM1CH0SRC_SHIFT 18
sahilmgandhi 18:6a4db94011d3 4187 #define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CH0SRC_SHIFT))&SIM_SOPT4_FTM1CH0SRC_MASK)
sahilmgandhi 18:6a4db94011d3 4188 #define SIM_SOPT4_FTM2CH0SRC_MASK 0x300000u
sahilmgandhi 18:6a4db94011d3 4189 #define SIM_SOPT4_FTM2CH0SRC_SHIFT 20
sahilmgandhi 18:6a4db94011d3 4190 #define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2CH0SRC_SHIFT))&SIM_SOPT4_FTM2CH0SRC_MASK)
sahilmgandhi 18:6a4db94011d3 4191 #define SIM_SOPT4_FTM0CLKSEL_MASK 0x1000000u
sahilmgandhi 18:6a4db94011d3 4192 #define SIM_SOPT4_FTM0CLKSEL_SHIFT 24
sahilmgandhi 18:6a4db94011d3 4193 #define SIM_SOPT4_FTM1CLKSEL_MASK 0x2000000u
sahilmgandhi 18:6a4db94011d3 4194 #define SIM_SOPT4_FTM1CLKSEL_SHIFT 25
sahilmgandhi 18:6a4db94011d3 4195 #define SIM_SOPT4_FTM2CLKSEL_MASK 0x4000000u
sahilmgandhi 18:6a4db94011d3 4196 #define SIM_SOPT4_FTM2CLKSEL_SHIFT 26
sahilmgandhi 18:6a4db94011d3 4197 #define SIM_SOPT4_FTM0TRG0SRC_MASK 0x10000000u
sahilmgandhi 18:6a4db94011d3 4198 #define SIM_SOPT4_FTM0TRG0SRC_SHIFT 28
sahilmgandhi 18:6a4db94011d3 4199 #define SIM_SOPT4_FTM0TRG1SRC_MASK 0x20000000u
sahilmgandhi 18:6a4db94011d3 4200 #define SIM_SOPT4_FTM0TRG1SRC_SHIFT 29
sahilmgandhi 18:6a4db94011d3 4201 /* SOPT5 Bit Fields */
sahilmgandhi 18:6a4db94011d3 4202 #define SIM_SOPT5_UART0TXSRC_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 4203 #define SIM_SOPT5_UART0TXSRC_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4204 #define SIM_SOPT5_UART0RXSRC_MASK 0xCu
sahilmgandhi 18:6a4db94011d3 4205 #define SIM_SOPT5_UART0RXSRC_SHIFT 2
sahilmgandhi 18:6a4db94011d3 4206 #define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0RXSRC_SHIFT))&SIM_SOPT5_UART0RXSRC_MASK)
sahilmgandhi 18:6a4db94011d3 4207 #define SIM_SOPT5_UART1TXSRC_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 4208 #define SIM_SOPT5_UART1TXSRC_SHIFT 4
sahilmgandhi 18:6a4db94011d3 4209 #define SIM_SOPT5_UART1RXSRC_MASK 0xC0u
sahilmgandhi 18:6a4db94011d3 4210 #define SIM_SOPT5_UART1RXSRC_SHIFT 6
sahilmgandhi 18:6a4db94011d3 4211 #define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1RXSRC_SHIFT))&SIM_SOPT5_UART1RXSRC_MASK)
sahilmgandhi 18:6a4db94011d3 4212 /* SOPT7 Bit Fields */
sahilmgandhi 18:6a4db94011d3 4213 #define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
sahilmgandhi 18:6a4db94011d3 4214 #define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4215 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
sahilmgandhi 18:6a4db94011d3 4216 #define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 4217 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
sahilmgandhi 18:6a4db94011d3 4218 #define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 4219 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
sahilmgandhi 18:6a4db94011d3 4220 #define SIM_SOPT7_ADC1TRGSEL_MASK 0xF00u
sahilmgandhi 18:6a4db94011d3 4221 #define SIM_SOPT7_ADC1TRGSEL_SHIFT 8
sahilmgandhi 18:6a4db94011d3 4222 #define SIM_SOPT7_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1TRGSEL_SHIFT))&SIM_SOPT7_ADC1TRGSEL_MASK)
sahilmgandhi 18:6a4db94011d3 4223 #define SIM_SOPT7_ADC1PRETRGSEL_MASK 0x1000u
sahilmgandhi 18:6a4db94011d3 4224 #define SIM_SOPT7_ADC1PRETRGSEL_SHIFT 12
sahilmgandhi 18:6a4db94011d3 4225 #define SIM_SOPT7_ADC1ALTTRGEN_MASK 0x8000u
sahilmgandhi 18:6a4db94011d3 4226 #define SIM_SOPT7_ADC1ALTTRGEN_SHIFT 15
sahilmgandhi 18:6a4db94011d3 4227 /* SDID Bit Fields */
sahilmgandhi 18:6a4db94011d3 4228 #define SIM_SDID_PINID_MASK 0xFu
sahilmgandhi 18:6a4db94011d3 4229 #define SIM_SDID_PINID_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4230 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
sahilmgandhi 18:6a4db94011d3 4231 #define SIM_SDID_FAMID_MASK 0x70u
sahilmgandhi 18:6a4db94011d3 4232 #define SIM_SDID_FAMID_SHIFT 4
sahilmgandhi 18:6a4db94011d3 4233 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
sahilmgandhi 18:6a4db94011d3 4234 #define SIM_SDID_REVID_MASK 0xF000u
sahilmgandhi 18:6a4db94011d3 4235 #define SIM_SDID_REVID_SHIFT 12
sahilmgandhi 18:6a4db94011d3 4236 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
sahilmgandhi 18:6a4db94011d3 4237 /* SCGC2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 4238 #define SIM_SCGC2_DAC0_MASK 0x1000u
sahilmgandhi 18:6a4db94011d3 4239 #define SIM_SCGC2_DAC0_SHIFT 12
sahilmgandhi 18:6a4db94011d3 4240 /* SCGC3 Bit Fields */
sahilmgandhi 18:6a4db94011d3 4241 #define SIM_SCGC3_FTM2_MASK 0x1000000u
sahilmgandhi 18:6a4db94011d3 4242 #define SIM_SCGC3_FTM2_SHIFT 24
sahilmgandhi 18:6a4db94011d3 4243 #define SIM_SCGC3_ADC1_MASK 0x8000000u
sahilmgandhi 18:6a4db94011d3 4244 #define SIM_SCGC3_ADC1_SHIFT 27
sahilmgandhi 18:6a4db94011d3 4245 /* SCGC4 Bit Fields */
sahilmgandhi 18:6a4db94011d3 4246 #define SIM_SCGC4_EWM_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 4247 #define SIM_SCGC4_EWM_SHIFT 1
sahilmgandhi 18:6a4db94011d3 4248 #define SIM_SCGC4_CMT_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 4249 #define SIM_SCGC4_CMT_SHIFT 2
sahilmgandhi 18:6a4db94011d3 4250 #define SIM_SCGC4_I2C0_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 4251 #define SIM_SCGC4_I2C0_SHIFT 6
sahilmgandhi 18:6a4db94011d3 4252 #define SIM_SCGC4_I2C1_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 4253 #define SIM_SCGC4_I2C1_SHIFT 7
sahilmgandhi 18:6a4db94011d3 4254 #define SIM_SCGC4_UART0_MASK 0x400u
sahilmgandhi 18:6a4db94011d3 4255 #define SIM_SCGC4_UART0_SHIFT 10
sahilmgandhi 18:6a4db94011d3 4256 #define SIM_SCGC4_UART1_MASK 0x800u
sahilmgandhi 18:6a4db94011d3 4257 #define SIM_SCGC4_UART1_SHIFT 11
sahilmgandhi 18:6a4db94011d3 4258 #define SIM_SCGC4_UART2_MASK 0x1000u
sahilmgandhi 18:6a4db94011d3 4259 #define SIM_SCGC4_UART2_SHIFT 12
sahilmgandhi 18:6a4db94011d3 4260 #define SIM_SCGC4_USBOTG_MASK 0x40000u
sahilmgandhi 18:6a4db94011d3 4261 #define SIM_SCGC4_USBOTG_SHIFT 18
sahilmgandhi 18:6a4db94011d3 4262 #define SIM_SCGC4_CMP_MASK 0x80000u
sahilmgandhi 18:6a4db94011d3 4263 #define SIM_SCGC4_CMP_SHIFT 19
sahilmgandhi 18:6a4db94011d3 4264 #define SIM_SCGC4_VREF_MASK 0x100000u
sahilmgandhi 18:6a4db94011d3 4265 #define SIM_SCGC4_VREF_SHIFT 20
sahilmgandhi 18:6a4db94011d3 4266 /* SCGC5 Bit Fields */
sahilmgandhi 18:6a4db94011d3 4267 #define SIM_SCGC5_LPTIMER_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 4268 #define SIM_SCGC5_LPTIMER_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4269 #define SIM_SCGC5_TSI_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 4270 #define SIM_SCGC5_TSI_SHIFT 5
sahilmgandhi 18:6a4db94011d3 4271 #define SIM_SCGC5_PORTA_MASK 0x200u
sahilmgandhi 18:6a4db94011d3 4272 #define SIM_SCGC5_PORTA_SHIFT 9
sahilmgandhi 18:6a4db94011d3 4273 #define SIM_SCGC5_PORTB_MASK 0x400u
sahilmgandhi 18:6a4db94011d3 4274 #define SIM_SCGC5_PORTB_SHIFT 10
sahilmgandhi 18:6a4db94011d3 4275 #define SIM_SCGC5_PORTC_MASK 0x800u
sahilmgandhi 18:6a4db94011d3 4276 #define SIM_SCGC5_PORTC_SHIFT 11
sahilmgandhi 18:6a4db94011d3 4277 #define SIM_SCGC5_PORTD_MASK 0x1000u
sahilmgandhi 18:6a4db94011d3 4278 #define SIM_SCGC5_PORTD_SHIFT 12
sahilmgandhi 18:6a4db94011d3 4279 #define SIM_SCGC5_PORTE_MASK 0x2000u
sahilmgandhi 18:6a4db94011d3 4280 #define SIM_SCGC5_PORTE_SHIFT 13
sahilmgandhi 18:6a4db94011d3 4281 /* SCGC6 Bit Fields */
sahilmgandhi 18:6a4db94011d3 4282 #define SIM_SCGC6_FTFL_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 4283 #define SIM_SCGC6_FTFL_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4284 #define SIM_SCGC6_DMAMUX_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 4285 #define SIM_SCGC6_DMAMUX_SHIFT 1
sahilmgandhi 18:6a4db94011d3 4286 #define SIM_SCGC6_FLEXCAN0_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 4287 #define SIM_SCGC6_FLEXCAN0_SHIFT 4
sahilmgandhi 18:6a4db94011d3 4288 #define SIM_SCGC6_SPI0_MASK 0x1000u
sahilmgandhi 18:6a4db94011d3 4289 #define SIM_SCGC6_SPI0_SHIFT 12
sahilmgandhi 18:6a4db94011d3 4290 #define SIM_SCGC6_SPI1_MASK 0x2000u
sahilmgandhi 18:6a4db94011d3 4291 #define SIM_SCGC6_SPI1_SHIFT 13
sahilmgandhi 18:6a4db94011d3 4292 #define SIM_SCGC6_I2S_MASK 0x8000u
sahilmgandhi 18:6a4db94011d3 4293 #define SIM_SCGC6_I2S_SHIFT 15
sahilmgandhi 18:6a4db94011d3 4294 #define SIM_SCGC6_CRC_MASK 0x40000u
sahilmgandhi 18:6a4db94011d3 4295 #define SIM_SCGC6_CRC_SHIFT 18
sahilmgandhi 18:6a4db94011d3 4296 #define SIM_SCGC6_USBDCD_MASK 0x200000u
sahilmgandhi 18:6a4db94011d3 4297 #define SIM_SCGC6_USBDCD_SHIFT 21
sahilmgandhi 18:6a4db94011d3 4298 #define SIM_SCGC6_PDB_MASK 0x400000u
sahilmgandhi 18:6a4db94011d3 4299 #define SIM_SCGC6_PDB_SHIFT 22
sahilmgandhi 18:6a4db94011d3 4300 #define SIM_SCGC6_PIT_MASK 0x800000u
sahilmgandhi 18:6a4db94011d3 4301 #define SIM_SCGC6_PIT_SHIFT 23
sahilmgandhi 18:6a4db94011d3 4302 #define SIM_SCGC6_FTM0_MASK 0x1000000u
sahilmgandhi 18:6a4db94011d3 4303 #define SIM_SCGC6_FTM0_SHIFT 24
sahilmgandhi 18:6a4db94011d3 4304 #define SIM_SCGC6_FTM1_MASK 0x2000000u
sahilmgandhi 18:6a4db94011d3 4305 #define SIM_SCGC6_FTM1_SHIFT 25
sahilmgandhi 18:6a4db94011d3 4306 #define SIM_SCGC6_ADC0_MASK 0x8000000u
sahilmgandhi 18:6a4db94011d3 4307 #define SIM_SCGC6_ADC0_SHIFT 27
sahilmgandhi 18:6a4db94011d3 4308 #define SIM_SCGC6_RTC_MASK 0x20000000u
sahilmgandhi 18:6a4db94011d3 4309 #define SIM_SCGC6_RTC_SHIFT 29
sahilmgandhi 18:6a4db94011d3 4310 /* SCGC7 Bit Fields */
sahilmgandhi 18:6a4db94011d3 4311 #define SIM_SCGC7_DMA_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 4312 #define SIM_SCGC7_DMA_SHIFT 1
sahilmgandhi 18:6a4db94011d3 4313 /* CLKDIV1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 4314 #define SIM_CLKDIV1_OUTDIV4_MASK 0xF0000u
sahilmgandhi 18:6a4db94011d3 4315 #define SIM_CLKDIV1_OUTDIV4_SHIFT 16
sahilmgandhi 18:6a4db94011d3 4316 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
sahilmgandhi 18:6a4db94011d3 4317 #define SIM_CLKDIV1_OUTDIV2_MASK 0xF000000u
sahilmgandhi 18:6a4db94011d3 4318 #define SIM_CLKDIV1_OUTDIV2_SHIFT 24
sahilmgandhi 18:6a4db94011d3 4319 #define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV2_SHIFT))&SIM_CLKDIV1_OUTDIV2_MASK)
sahilmgandhi 18:6a4db94011d3 4320 #define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
sahilmgandhi 18:6a4db94011d3 4321 #define SIM_CLKDIV1_OUTDIV1_SHIFT 28
sahilmgandhi 18:6a4db94011d3 4322 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
sahilmgandhi 18:6a4db94011d3 4323 /* CLKDIV2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 4324 #define SIM_CLKDIV2_USBFRAC_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 4325 #define SIM_CLKDIV2_USBFRAC_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4326 #define SIM_CLKDIV2_USBDIV_MASK 0xEu
sahilmgandhi 18:6a4db94011d3 4327 #define SIM_CLKDIV2_USBDIV_SHIFT 1
sahilmgandhi 18:6a4db94011d3 4328 #define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBDIV_SHIFT))&SIM_CLKDIV2_USBDIV_MASK)
sahilmgandhi 18:6a4db94011d3 4329 /* FCFG1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 4330 #define SIM_FCFG1_FLASHDIS_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 4331 #define SIM_FCFG1_FLASHDIS_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4332 #define SIM_FCFG1_FLASHDOZE_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 4333 #define SIM_FCFG1_FLASHDOZE_SHIFT 1
sahilmgandhi 18:6a4db94011d3 4334 #define SIM_FCFG1_DEPART_MASK 0xF00u
sahilmgandhi 18:6a4db94011d3 4335 #define SIM_FCFG1_DEPART_SHIFT 8
sahilmgandhi 18:6a4db94011d3 4336 #define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_DEPART_SHIFT))&SIM_FCFG1_DEPART_MASK)
sahilmgandhi 18:6a4db94011d3 4337 #define SIM_FCFG1_EESIZE_MASK 0xF0000u
sahilmgandhi 18:6a4db94011d3 4338 #define SIM_FCFG1_EESIZE_SHIFT 16
sahilmgandhi 18:6a4db94011d3 4339 #define SIM_FCFG1_EESIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_EESIZE_SHIFT))&SIM_FCFG1_EESIZE_MASK)
sahilmgandhi 18:6a4db94011d3 4340 #define SIM_FCFG1_PFSIZE_MASK 0xF000000u
sahilmgandhi 18:6a4db94011d3 4341 #define SIM_FCFG1_PFSIZE_SHIFT 24
sahilmgandhi 18:6a4db94011d3 4342 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
sahilmgandhi 18:6a4db94011d3 4343 #define SIM_FCFG1_NVMSIZE_MASK 0xF0000000u
sahilmgandhi 18:6a4db94011d3 4344 #define SIM_FCFG1_NVMSIZE_SHIFT 28
sahilmgandhi 18:6a4db94011d3 4345 #define SIM_FCFG1_NVMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_NVMSIZE_SHIFT))&SIM_FCFG1_NVMSIZE_MASK)
sahilmgandhi 18:6a4db94011d3 4346 /* FCFG2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 4347 #define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u
sahilmgandhi 18:6a4db94011d3 4348 #define SIM_FCFG2_MAXADDR1_SHIFT 16
sahilmgandhi 18:6a4db94011d3 4349 #define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
sahilmgandhi 18:6a4db94011d3 4350 #define SIM_FCFG2_PFLSH_MASK 0x800000u
sahilmgandhi 18:6a4db94011d3 4351 #define SIM_FCFG2_PFLSH_SHIFT 23
sahilmgandhi 18:6a4db94011d3 4352 #define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
sahilmgandhi 18:6a4db94011d3 4353 #define SIM_FCFG2_MAXADDR0_SHIFT 24
sahilmgandhi 18:6a4db94011d3 4354 #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
sahilmgandhi 18:6a4db94011d3 4355 /* UIDH Bit Fields */
sahilmgandhi 18:6a4db94011d3 4356 #define SIM_UIDH_UID_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 4357 #define SIM_UIDH_UID_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4358 #define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID_SHIFT))&SIM_UIDH_UID_MASK)
sahilmgandhi 18:6a4db94011d3 4359 /* UIDMH Bit Fields */
sahilmgandhi 18:6a4db94011d3 4360 #define SIM_UIDMH_UID_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 4361 #define SIM_UIDMH_UID_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4362 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
sahilmgandhi 18:6a4db94011d3 4363 /* UIDML Bit Fields */
sahilmgandhi 18:6a4db94011d3 4364 #define SIM_UIDML_UID_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 4365 #define SIM_UIDML_UID_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4366 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
sahilmgandhi 18:6a4db94011d3 4367 /* UIDL Bit Fields */
sahilmgandhi 18:6a4db94011d3 4368 #define SIM_UIDL_UID_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 4369 #define SIM_UIDL_UID_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4370 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
sahilmgandhi 18:6a4db94011d3 4371
sahilmgandhi 18:6a4db94011d3 4372 /**
sahilmgandhi 18:6a4db94011d3 4373 * @}
sahilmgandhi 18:6a4db94011d3 4374 */ /* end of group SIM_Register_Masks */
sahilmgandhi 18:6a4db94011d3 4375
sahilmgandhi 18:6a4db94011d3 4376
sahilmgandhi 18:6a4db94011d3 4377 /* SIM - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 4378 /** Peripheral SIM base address */
sahilmgandhi 18:6a4db94011d3 4379 #define SIM_BASE (0x40047000u)
sahilmgandhi 18:6a4db94011d3 4380 /** Peripheral SIM base pointer */
sahilmgandhi 18:6a4db94011d3 4381 #define SIM ((SIM_Type *)SIM_BASE)
sahilmgandhi 18:6a4db94011d3 4382
sahilmgandhi 18:6a4db94011d3 4383 /**
sahilmgandhi 18:6a4db94011d3 4384 * @}
sahilmgandhi 18:6a4db94011d3 4385 */ /* end of group SIM_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 4386
sahilmgandhi 18:6a4db94011d3 4387
sahilmgandhi 18:6a4db94011d3 4388 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 4389 -- SMC Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 4390 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 4391
sahilmgandhi 18:6a4db94011d3 4392 /**
sahilmgandhi 18:6a4db94011d3 4393 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 4394 * @{
sahilmgandhi 18:6a4db94011d3 4395 */
sahilmgandhi 18:6a4db94011d3 4396
sahilmgandhi 18:6a4db94011d3 4397 /** SMC - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 4398 typedef struct {
sahilmgandhi 18:6a4db94011d3 4399 __IO uint8_t PMPROT; /**< Power Mode Protection Register, offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 4400 __IO uint8_t PMCTRL; /**< Power Mode Control Register, offset: 0x1 */
sahilmgandhi 18:6a4db94011d3 4401 __IO uint8_t VLLSCTRL; /**< VLLS Control Register, offset: 0x2 */
sahilmgandhi 18:6a4db94011d3 4402 __I uint8_t PMSTAT; /**< Power Mode Status Register, offset: 0x3 */
sahilmgandhi 18:6a4db94011d3 4403 } SMC_Type;
sahilmgandhi 18:6a4db94011d3 4404
sahilmgandhi 18:6a4db94011d3 4405 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 4406 -- SMC Register Masks
sahilmgandhi 18:6a4db94011d3 4407 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 4408
sahilmgandhi 18:6a4db94011d3 4409 /**
sahilmgandhi 18:6a4db94011d3 4410 * @addtogroup SMC_Register_Masks SMC Register Masks
sahilmgandhi 18:6a4db94011d3 4411 * @{
sahilmgandhi 18:6a4db94011d3 4412 */
sahilmgandhi 18:6a4db94011d3 4413
sahilmgandhi 18:6a4db94011d3 4414 /* PMPROT Bit Fields */
sahilmgandhi 18:6a4db94011d3 4415 #define SMC_PMPROT_AVLLS_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 4416 #define SMC_PMPROT_AVLLS_SHIFT 1
sahilmgandhi 18:6a4db94011d3 4417 #define SMC_PMPROT_ALLS_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 4418 #define SMC_PMPROT_ALLS_SHIFT 3
sahilmgandhi 18:6a4db94011d3 4419 #define SMC_PMPROT_AVLP_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 4420 #define SMC_PMPROT_AVLP_SHIFT 5
sahilmgandhi 18:6a4db94011d3 4421 /* PMCTRL Bit Fields */
sahilmgandhi 18:6a4db94011d3 4422 #define SMC_PMCTRL_STOPM_MASK 0x7u
sahilmgandhi 18:6a4db94011d3 4423 #define SMC_PMCTRL_STOPM_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4424 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
sahilmgandhi 18:6a4db94011d3 4425 #define SMC_PMCTRL_STOPA_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 4426 #define SMC_PMCTRL_STOPA_SHIFT 3
sahilmgandhi 18:6a4db94011d3 4427 #define SMC_PMCTRL_RUNM_MASK 0x60u
sahilmgandhi 18:6a4db94011d3 4428 #define SMC_PMCTRL_RUNM_SHIFT 5
sahilmgandhi 18:6a4db94011d3 4429 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
sahilmgandhi 18:6a4db94011d3 4430 #define SMC_PMCTRL_LPWUI_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 4431 #define SMC_PMCTRL_LPWUI_SHIFT 7
sahilmgandhi 18:6a4db94011d3 4432 /* VLLSCTRL Bit Fields */
sahilmgandhi 18:6a4db94011d3 4433 #define SMC_VLLSCTRL_VLLSM_MASK 0x7u
sahilmgandhi 18:6a4db94011d3 4434 #define SMC_VLLSCTRL_VLLSM_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4435 #define SMC_VLLSCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_VLLSCTRL_VLLSM_SHIFT))&SMC_VLLSCTRL_VLLSM_MASK)
sahilmgandhi 18:6a4db94011d3 4436 #define SMC_VLLSCTRL_PORPO_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 4437 #define SMC_VLLSCTRL_PORPO_SHIFT 5
sahilmgandhi 18:6a4db94011d3 4438 /* PMSTAT Bit Fields */
sahilmgandhi 18:6a4db94011d3 4439 #define SMC_PMSTAT_PMSTAT_MASK 0x7Fu
sahilmgandhi 18:6a4db94011d3 4440 #define SMC_PMSTAT_PMSTAT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4441 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
sahilmgandhi 18:6a4db94011d3 4442
sahilmgandhi 18:6a4db94011d3 4443 /**
sahilmgandhi 18:6a4db94011d3 4444 * @}
sahilmgandhi 18:6a4db94011d3 4445 */ /* end of group SMC_Register_Masks */
sahilmgandhi 18:6a4db94011d3 4446
sahilmgandhi 18:6a4db94011d3 4447
sahilmgandhi 18:6a4db94011d3 4448 /* SMC - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 4449 /** Peripheral SMC base address */
sahilmgandhi 18:6a4db94011d3 4450 #define SMC_BASE (0x4007E000u)
sahilmgandhi 18:6a4db94011d3 4451 /** Peripheral SMC base pointer */
sahilmgandhi 18:6a4db94011d3 4452 #define SMC ((SMC_Type *)SMC_BASE)
sahilmgandhi 18:6a4db94011d3 4453
sahilmgandhi 18:6a4db94011d3 4454 /**
sahilmgandhi 18:6a4db94011d3 4455 * @}
sahilmgandhi 18:6a4db94011d3 4456 */ /* end of group SMC_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 4457
sahilmgandhi 18:6a4db94011d3 4458
sahilmgandhi 18:6a4db94011d3 4459 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 4460 -- SPI Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 4461 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 4462
sahilmgandhi 18:6a4db94011d3 4463 /**
sahilmgandhi 18:6a4db94011d3 4464 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 4465 * @{
sahilmgandhi 18:6a4db94011d3 4466 */
sahilmgandhi 18:6a4db94011d3 4467
sahilmgandhi 18:6a4db94011d3 4468 /** SPI - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 4469 typedef struct {
sahilmgandhi 18:6a4db94011d3 4470 __IO uint32_t MCR; /**< DSPI Module Configuration Register, offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 4471 uint8_t RESERVED_0[4];
sahilmgandhi 18:6a4db94011d3 4472 __IO uint32_t TCR; /**< DSPI Transfer Count Register, offset: 0x8 */
sahilmgandhi 18:6a4db94011d3 4473 union { /* offset: 0xC */
sahilmgandhi 18:6a4db94011d3 4474 __IO uint32_t CTAR[2]; /**< DSPI Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
sahilmgandhi 18:6a4db94011d3 4475 __IO uint32_t CTAR_SLAVE[1]; /**< DSPI Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
sahilmgandhi 18:6a4db94011d3 4476 };
sahilmgandhi 18:6a4db94011d3 4477 uint8_t RESERVED_1[24];
sahilmgandhi 18:6a4db94011d3 4478 __IO uint32_t SR; /**< DSPI Status Register, offset: 0x2C */
sahilmgandhi 18:6a4db94011d3 4479 __IO uint32_t RSER; /**< DSPI DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
sahilmgandhi 18:6a4db94011d3 4480 union { /* offset: 0x34 */
sahilmgandhi 18:6a4db94011d3 4481 __IO uint32_t PUSHR; /**< DSPI PUSH TX FIFO Register In Master Mode, offset: 0x34 */
sahilmgandhi 18:6a4db94011d3 4482 __IO uint32_t PUSHR_SLAVE; /**< DSPI PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
sahilmgandhi 18:6a4db94011d3 4483 };
sahilmgandhi 18:6a4db94011d3 4484 __I uint32_t POPR; /**< DSPI POP RX FIFO Register, offset: 0x38 */
sahilmgandhi 18:6a4db94011d3 4485 __I uint32_t TXFR0; /**< DSPI Transmit FIFO Registers, offset: 0x3C */
sahilmgandhi 18:6a4db94011d3 4486 __I uint32_t TXFR1; /**< DSPI Transmit FIFO Registers, offset: 0x40 */
sahilmgandhi 18:6a4db94011d3 4487 __I uint32_t TXFR2; /**< DSPI Transmit FIFO Registers, offset: 0x44 */
sahilmgandhi 18:6a4db94011d3 4488 __I uint32_t TXFR3; /**< DSPI Transmit FIFO Registers, offset: 0x48 */
sahilmgandhi 18:6a4db94011d3 4489 uint8_t RESERVED_2[48];
sahilmgandhi 18:6a4db94011d3 4490 __I uint32_t RXFR0; /**< DSPI Receive FIFO Registers, offset: 0x7C */
sahilmgandhi 18:6a4db94011d3 4491 __I uint32_t RXFR1; /**< DSPI Receive FIFO Registers, offset: 0x80 */
sahilmgandhi 18:6a4db94011d3 4492 __I uint32_t RXFR2; /**< DSPI Receive FIFO Registers, offset: 0x84 */
sahilmgandhi 18:6a4db94011d3 4493 __I uint32_t RXFR3; /**< DSPI Receive FIFO Registers, offset: 0x88 */
sahilmgandhi 18:6a4db94011d3 4494 } SPI_Type;
sahilmgandhi 18:6a4db94011d3 4495
sahilmgandhi 18:6a4db94011d3 4496 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 4497 -- SPI Register Masks
sahilmgandhi 18:6a4db94011d3 4498 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 4499
sahilmgandhi 18:6a4db94011d3 4500 /**
sahilmgandhi 18:6a4db94011d3 4501 * @addtogroup SPI_Register_Masks SPI Register Masks
sahilmgandhi 18:6a4db94011d3 4502 * @{
sahilmgandhi 18:6a4db94011d3 4503 */
sahilmgandhi 18:6a4db94011d3 4504
sahilmgandhi 18:6a4db94011d3 4505 /* MCR Bit Fields */
sahilmgandhi 18:6a4db94011d3 4506 #define SPI_MCR_HALT_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 4507 #define SPI_MCR_HALT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4508 #define SPI_MCR_SMPL_PT_MASK 0x300u
sahilmgandhi 18:6a4db94011d3 4509 #define SPI_MCR_SMPL_PT_SHIFT 8
sahilmgandhi 18:6a4db94011d3 4510 #define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK)
sahilmgandhi 18:6a4db94011d3 4511 #define SPI_MCR_CLR_RXF_MASK 0x400u
sahilmgandhi 18:6a4db94011d3 4512 #define SPI_MCR_CLR_RXF_SHIFT 10
sahilmgandhi 18:6a4db94011d3 4513 #define SPI_MCR_CLR_TXF_MASK 0x800u
sahilmgandhi 18:6a4db94011d3 4514 #define SPI_MCR_CLR_TXF_SHIFT 11
sahilmgandhi 18:6a4db94011d3 4515 #define SPI_MCR_DIS_RXF_MASK 0x1000u
sahilmgandhi 18:6a4db94011d3 4516 #define SPI_MCR_DIS_RXF_SHIFT 12
sahilmgandhi 18:6a4db94011d3 4517 #define SPI_MCR_DIS_TXF_MASK 0x2000u
sahilmgandhi 18:6a4db94011d3 4518 #define SPI_MCR_DIS_TXF_SHIFT 13
sahilmgandhi 18:6a4db94011d3 4519 #define SPI_MCR_MDIS_MASK 0x4000u
sahilmgandhi 18:6a4db94011d3 4520 #define SPI_MCR_MDIS_SHIFT 14
sahilmgandhi 18:6a4db94011d3 4521 #define SPI_MCR_DOZE_MASK 0x8000u
sahilmgandhi 18:6a4db94011d3 4522 #define SPI_MCR_DOZE_SHIFT 15
sahilmgandhi 18:6a4db94011d3 4523 #define SPI_MCR_PCSIS_MASK 0x3F0000u
sahilmgandhi 18:6a4db94011d3 4524 #define SPI_MCR_PCSIS_SHIFT 16
sahilmgandhi 18:6a4db94011d3 4525 #define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK)
sahilmgandhi 18:6a4db94011d3 4526 #define SPI_MCR_ROOE_MASK 0x1000000u
sahilmgandhi 18:6a4db94011d3 4527 #define SPI_MCR_ROOE_SHIFT 24
sahilmgandhi 18:6a4db94011d3 4528 #define SPI_MCR_PCSSE_MASK 0x2000000u
sahilmgandhi 18:6a4db94011d3 4529 #define SPI_MCR_PCSSE_SHIFT 25
sahilmgandhi 18:6a4db94011d3 4530 #define SPI_MCR_MTFE_MASK 0x4000000u
sahilmgandhi 18:6a4db94011d3 4531 #define SPI_MCR_MTFE_SHIFT 26
sahilmgandhi 18:6a4db94011d3 4532 #define SPI_MCR_FRZ_MASK 0x8000000u
sahilmgandhi 18:6a4db94011d3 4533 #define SPI_MCR_FRZ_SHIFT 27
sahilmgandhi 18:6a4db94011d3 4534 #define SPI_MCR_DCONF_MASK 0x30000000u
sahilmgandhi 18:6a4db94011d3 4535 #define SPI_MCR_DCONF_SHIFT 28
sahilmgandhi 18:6a4db94011d3 4536 #define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK)
sahilmgandhi 18:6a4db94011d3 4537 #define SPI_MCR_CONT_SCKE_MASK 0x40000000u
sahilmgandhi 18:6a4db94011d3 4538 #define SPI_MCR_CONT_SCKE_SHIFT 30
sahilmgandhi 18:6a4db94011d3 4539 #define SPI_MCR_MSTR_MASK 0x80000000u
sahilmgandhi 18:6a4db94011d3 4540 #define SPI_MCR_MSTR_SHIFT 31
sahilmgandhi 18:6a4db94011d3 4541 /* TCR Bit Fields */
sahilmgandhi 18:6a4db94011d3 4542 #define SPI_TCR_SPI_TCNT_MASK 0xFFFF0000u
sahilmgandhi 18:6a4db94011d3 4543 #define SPI_TCR_SPI_TCNT_SHIFT 16
sahilmgandhi 18:6a4db94011d3 4544 #define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x))<<SPI_TCR_SPI_TCNT_SHIFT))&SPI_TCR_SPI_TCNT_MASK)
sahilmgandhi 18:6a4db94011d3 4545 /* CTAR Bit Fields */
sahilmgandhi 18:6a4db94011d3 4546 #define SPI_CTAR_BR_MASK 0xFu
sahilmgandhi 18:6a4db94011d3 4547 #define SPI_CTAR_BR_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4548 #define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_BR_SHIFT))&SPI_CTAR_BR_MASK)
sahilmgandhi 18:6a4db94011d3 4549 #define SPI_CTAR_DT_MASK 0xF0u
sahilmgandhi 18:6a4db94011d3 4550 #define SPI_CTAR_DT_SHIFT 4
sahilmgandhi 18:6a4db94011d3 4551 #define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DT_SHIFT))&SPI_CTAR_DT_MASK)
sahilmgandhi 18:6a4db94011d3 4552 #define SPI_CTAR_ASC_MASK 0xF00u
sahilmgandhi 18:6a4db94011d3 4553 #define SPI_CTAR_ASC_SHIFT 8
sahilmgandhi 18:6a4db94011d3 4554 #define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_ASC_SHIFT))&SPI_CTAR_ASC_MASK)
sahilmgandhi 18:6a4db94011d3 4555 #define SPI_CTAR_CSSCK_MASK 0xF000u
sahilmgandhi 18:6a4db94011d3 4556 #define SPI_CTAR_CSSCK_SHIFT 12
sahilmgandhi 18:6a4db94011d3 4557 #define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CSSCK_SHIFT))&SPI_CTAR_CSSCK_MASK)
sahilmgandhi 18:6a4db94011d3 4558 #define SPI_CTAR_PBR_MASK 0x30000u
sahilmgandhi 18:6a4db94011d3 4559 #define SPI_CTAR_PBR_SHIFT 16
sahilmgandhi 18:6a4db94011d3 4560 #define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PBR_SHIFT))&SPI_CTAR_PBR_MASK)
sahilmgandhi 18:6a4db94011d3 4561 #define SPI_CTAR_PDT_MASK 0xC0000u
sahilmgandhi 18:6a4db94011d3 4562 #define SPI_CTAR_PDT_SHIFT 18
sahilmgandhi 18:6a4db94011d3 4563 #define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PDT_SHIFT))&SPI_CTAR_PDT_MASK)
sahilmgandhi 18:6a4db94011d3 4564 #define SPI_CTAR_PASC_MASK 0x300000u
sahilmgandhi 18:6a4db94011d3 4565 #define SPI_CTAR_PASC_SHIFT 20
sahilmgandhi 18:6a4db94011d3 4566 #define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PASC_SHIFT))&SPI_CTAR_PASC_MASK)
sahilmgandhi 18:6a4db94011d3 4567 #define SPI_CTAR_PCSSCK_MASK 0xC00000u
sahilmgandhi 18:6a4db94011d3 4568 #define SPI_CTAR_PCSSCK_SHIFT 22
sahilmgandhi 18:6a4db94011d3 4569 #define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK)
sahilmgandhi 18:6a4db94011d3 4570 #define SPI_CTAR_LSBFE_MASK 0x1000000u
sahilmgandhi 18:6a4db94011d3 4571 #define SPI_CTAR_LSBFE_SHIFT 24
sahilmgandhi 18:6a4db94011d3 4572 #define SPI_CTAR_CPHA_MASK 0x2000000u
sahilmgandhi 18:6a4db94011d3 4573 #define SPI_CTAR_CPHA_SHIFT 25
sahilmgandhi 18:6a4db94011d3 4574 #define SPI_CTAR_CPOL_MASK 0x4000000u
sahilmgandhi 18:6a4db94011d3 4575 #define SPI_CTAR_CPOL_SHIFT 26
sahilmgandhi 18:6a4db94011d3 4576 #define SPI_CTAR_FMSZ_MASK 0x78000000u
sahilmgandhi 18:6a4db94011d3 4577 #define SPI_CTAR_FMSZ_SHIFT 27
sahilmgandhi 18:6a4db94011d3 4578 #define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_FMSZ_SHIFT))&SPI_CTAR_FMSZ_MASK)
sahilmgandhi 18:6a4db94011d3 4579 #define SPI_CTAR_DBR_MASK 0x80000000u
sahilmgandhi 18:6a4db94011d3 4580 #define SPI_CTAR_DBR_SHIFT 31
sahilmgandhi 18:6a4db94011d3 4581 /* CTAR_SLAVE Bit Fields */
sahilmgandhi 18:6a4db94011d3 4582 #define SPI_CTAR_SLAVE_CPHA_MASK 0x2000000u
sahilmgandhi 18:6a4db94011d3 4583 #define SPI_CTAR_SLAVE_CPHA_SHIFT 25
sahilmgandhi 18:6a4db94011d3 4584 #define SPI_CTAR_SLAVE_CPOL_MASK 0x4000000u
sahilmgandhi 18:6a4db94011d3 4585 #define SPI_CTAR_SLAVE_CPOL_SHIFT 26
sahilmgandhi 18:6a4db94011d3 4586 #define SPI_CTAR_SLAVE_FMSZ_MASK 0xF8000000u
sahilmgandhi 18:6a4db94011d3 4587 #define SPI_CTAR_SLAVE_FMSZ_SHIFT 27
sahilmgandhi 18:6a4db94011d3 4588 #define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_FMSZ_SHIFT))&SPI_CTAR_SLAVE_FMSZ_MASK)
sahilmgandhi 18:6a4db94011d3 4589 /* SR Bit Fields */
sahilmgandhi 18:6a4db94011d3 4590 #define SPI_SR_POPNXTPTR_MASK 0xFu
sahilmgandhi 18:6a4db94011d3 4591 #define SPI_SR_POPNXTPTR_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4592 #define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_POPNXTPTR_SHIFT))&SPI_SR_POPNXTPTR_MASK)
sahilmgandhi 18:6a4db94011d3 4593 #define SPI_SR_RXCTR_MASK 0xF0u
sahilmgandhi 18:6a4db94011d3 4594 #define SPI_SR_RXCTR_SHIFT 4
sahilmgandhi 18:6a4db94011d3 4595 #define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_RXCTR_SHIFT))&SPI_SR_RXCTR_MASK)
sahilmgandhi 18:6a4db94011d3 4596 #define SPI_SR_TXNXTPTR_MASK 0xF00u
sahilmgandhi 18:6a4db94011d3 4597 #define SPI_SR_TXNXTPTR_SHIFT 8
sahilmgandhi 18:6a4db94011d3 4598 #define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXNXTPTR_SHIFT))&SPI_SR_TXNXTPTR_MASK)
sahilmgandhi 18:6a4db94011d3 4599 #define SPI_SR_TXCTR_MASK 0xF000u
sahilmgandhi 18:6a4db94011d3 4600 #define SPI_SR_TXCTR_SHIFT 12
sahilmgandhi 18:6a4db94011d3 4601 #define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXCTR_SHIFT))&SPI_SR_TXCTR_MASK)
sahilmgandhi 18:6a4db94011d3 4602 #define SPI_SR_RFDF_MASK 0x20000u
sahilmgandhi 18:6a4db94011d3 4603 #define SPI_SR_RFDF_SHIFT 17
sahilmgandhi 18:6a4db94011d3 4604 #define SPI_SR_RFOF_MASK 0x80000u
sahilmgandhi 18:6a4db94011d3 4605 #define SPI_SR_RFOF_SHIFT 19
sahilmgandhi 18:6a4db94011d3 4606 #define SPI_SR_TFFF_MASK 0x2000000u
sahilmgandhi 18:6a4db94011d3 4607 #define SPI_SR_TFFF_SHIFT 25
sahilmgandhi 18:6a4db94011d3 4608 #define SPI_SR_TFUF_MASK 0x8000000u
sahilmgandhi 18:6a4db94011d3 4609 #define SPI_SR_TFUF_SHIFT 27
sahilmgandhi 18:6a4db94011d3 4610 #define SPI_SR_EOQF_MASK 0x10000000u
sahilmgandhi 18:6a4db94011d3 4611 #define SPI_SR_EOQF_SHIFT 28
sahilmgandhi 18:6a4db94011d3 4612 #define SPI_SR_TXRXS_MASK 0x40000000u
sahilmgandhi 18:6a4db94011d3 4613 #define SPI_SR_TXRXS_SHIFT 30
sahilmgandhi 18:6a4db94011d3 4614 #define SPI_SR_TCF_MASK 0x80000000u
sahilmgandhi 18:6a4db94011d3 4615 #define SPI_SR_TCF_SHIFT 31
sahilmgandhi 18:6a4db94011d3 4616 /* RSER Bit Fields */
sahilmgandhi 18:6a4db94011d3 4617 #define SPI_RSER_RFDF_DIRS_MASK 0x10000u
sahilmgandhi 18:6a4db94011d3 4618 #define SPI_RSER_RFDF_DIRS_SHIFT 16
sahilmgandhi 18:6a4db94011d3 4619 #define SPI_RSER_RFDF_RE_MASK 0x20000u
sahilmgandhi 18:6a4db94011d3 4620 #define SPI_RSER_RFDF_RE_SHIFT 17
sahilmgandhi 18:6a4db94011d3 4621 #define SPI_RSER_RFOF_RE_MASK 0x80000u
sahilmgandhi 18:6a4db94011d3 4622 #define SPI_RSER_RFOF_RE_SHIFT 19
sahilmgandhi 18:6a4db94011d3 4623 #define SPI_RSER_TFFF_DIRS_MASK 0x1000000u
sahilmgandhi 18:6a4db94011d3 4624 #define SPI_RSER_TFFF_DIRS_SHIFT 24
sahilmgandhi 18:6a4db94011d3 4625 #define SPI_RSER_TFFF_RE_MASK 0x2000000u
sahilmgandhi 18:6a4db94011d3 4626 #define SPI_RSER_TFFF_RE_SHIFT 25
sahilmgandhi 18:6a4db94011d3 4627 #define SPI_RSER_TFUF_RE_MASK 0x8000000u
sahilmgandhi 18:6a4db94011d3 4628 #define SPI_RSER_TFUF_RE_SHIFT 27
sahilmgandhi 18:6a4db94011d3 4629 #define SPI_RSER_EOQF_RE_MASK 0x10000000u
sahilmgandhi 18:6a4db94011d3 4630 #define SPI_RSER_EOQF_RE_SHIFT 28
sahilmgandhi 18:6a4db94011d3 4631 #define SPI_RSER_TCF_RE_MASK 0x80000000u
sahilmgandhi 18:6a4db94011d3 4632 #define SPI_RSER_TCF_RE_SHIFT 31
sahilmgandhi 18:6a4db94011d3 4633 /* PUSHR Bit Fields */
sahilmgandhi 18:6a4db94011d3 4634 #define SPI_PUSHR_TXDATA_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 4635 #define SPI_PUSHR_TXDATA_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4636 #define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_TXDATA_SHIFT))&SPI_PUSHR_TXDATA_MASK)
sahilmgandhi 18:6a4db94011d3 4637 #define SPI_PUSHR_PCS_MASK 0x3F0000u
sahilmgandhi 18:6a4db94011d3 4638 #define SPI_PUSHR_PCS_SHIFT 16
sahilmgandhi 18:6a4db94011d3 4639 #define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_PCS_SHIFT))&SPI_PUSHR_PCS_MASK)
sahilmgandhi 18:6a4db94011d3 4640 #define SPI_PUSHR_CTCNT_MASK 0x4000000u
sahilmgandhi 18:6a4db94011d3 4641 #define SPI_PUSHR_CTCNT_SHIFT 26
sahilmgandhi 18:6a4db94011d3 4642 #define SPI_PUSHR_EOQ_MASK 0x8000000u
sahilmgandhi 18:6a4db94011d3 4643 #define SPI_PUSHR_EOQ_SHIFT 27
sahilmgandhi 18:6a4db94011d3 4644 #define SPI_PUSHR_CTAS_MASK 0x70000000u
sahilmgandhi 18:6a4db94011d3 4645 #define SPI_PUSHR_CTAS_SHIFT 28
sahilmgandhi 18:6a4db94011d3 4646 #define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTAS_SHIFT))&SPI_PUSHR_CTAS_MASK)
sahilmgandhi 18:6a4db94011d3 4647 #define SPI_PUSHR_CONT_MASK 0x80000000u
sahilmgandhi 18:6a4db94011d3 4648 #define SPI_PUSHR_CONT_SHIFT 31
sahilmgandhi 18:6a4db94011d3 4649 /* PUSHR_SLAVE Bit Fields */
sahilmgandhi 18:6a4db94011d3 4650 #define SPI_PUSHR_SLAVE_TXDATA_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 4651 #define SPI_PUSHR_SLAVE_TXDATA_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4652 #define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_SLAVE_TXDATA_SHIFT))&SPI_PUSHR_SLAVE_TXDATA_MASK)
sahilmgandhi 18:6a4db94011d3 4653 /* POPR Bit Fields */
sahilmgandhi 18:6a4db94011d3 4654 #define SPI_POPR_RXDATA_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 4655 #define SPI_POPR_RXDATA_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4656 #define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_POPR_RXDATA_SHIFT))&SPI_POPR_RXDATA_MASK)
sahilmgandhi 18:6a4db94011d3 4657 /* TXFR0 Bit Fields */
sahilmgandhi 18:6a4db94011d3 4658 #define SPI_TXFR0_TXDATA_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 4659 #define SPI_TXFR0_TXDATA_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4660 #define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXDATA_SHIFT))&SPI_TXFR0_TXDATA_MASK)
sahilmgandhi 18:6a4db94011d3 4661 #define SPI_TXFR0_TXCMD_TXDATA_MASK 0xFFFF0000u
sahilmgandhi 18:6a4db94011d3 4662 #define SPI_TXFR0_TXCMD_TXDATA_SHIFT 16
sahilmgandhi 18:6a4db94011d3 4663 #define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXCMD_TXDATA_SHIFT))&SPI_TXFR0_TXCMD_TXDATA_MASK)
sahilmgandhi 18:6a4db94011d3 4664 /* TXFR1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 4665 #define SPI_TXFR1_TXDATA_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 4666 #define SPI_TXFR1_TXDATA_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4667 #define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXDATA_SHIFT))&SPI_TXFR1_TXDATA_MASK)
sahilmgandhi 18:6a4db94011d3 4668 #define SPI_TXFR1_TXCMD_TXDATA_MASK 0xFFFF0000u
sahilmgandhi 18:6a4db94011d3 4669 #define SPI_TXFR1_TXCMD_TXDATA_SHIFT 16
sahilmgandhi 18:6a4db94011d3 4670 #define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXCMD_TXDATA_SHIFT))&SPI_TXFR1_TXCMD_TXDATA_MASK)
sahilmgandhi 18:6a4db94011d3 4671 /* TXFR2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 4672 #define SPI_TXFR2_TXDATA_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 4673 #define SPI_TXFR2_TXDATA_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4674 #define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXDATA_SHIFT))&SPI_TXFR2_TXDATA_MASK)
sahilmgandhi 18:6a4db94011d3 4675 #define SPI_TXFR2_TXCMD_TXDATA_MASK 0xFFFF0000u
sahilmgandhi 18:6a4db94011d3 4676 #define SPI_TXFR2_TXCMD_TXDATA_SHIFT 16
sahilmgandhi 18:6a4db94011d3 4677 #define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXCMD_TXDATA_SHIFT))&SPI_TXFR2_TXCMD_TXDATA_MASK)
sahilmgandhi 18:6a4db94011d3 4678 /* TXFR3 Bit Fields */
sahilmgandhi 18:6a4db94011d3 4679 #define SPI_TXFR3_TXDATA_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 4680 #define SPI_TXFR3_TXDATA_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4681 #define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXDATA_SHIFT))&SPI_TXFR3_TXDATA_MASK)
sahilmgandhi 18:6a4db94011d3 4682 #define SPI_TXFR3_TXCMD_TXDATA_MASK 0xFFFF0000u
sahilmgandhi 18:6a4db94011d3 4683 #define SPI_TXFR3_TXCMD_TXDATA_SHIFT 16
sahilmgandhi 18:6a4db94011d3 4684 #define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXCMD_TXDATA_SHIFT))&SPI_TXFR3_TXCMD_TXDATA_MASK)
sahilmgandhi 18:6a4db94011d3 4685 /* RXFR0 Bit Fields */
sahilmgandhi 18:6a4db94011d3 4686 #define SPI_RXFR0_RXDATA_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 4687 #define SPI_RXFR0_RXDATA_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4688 #define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR0_RXDATA_SHIFT))&SPI_RXFR0_RXDATA_MASK)
sahilmgandhi 18:6a4db94011d3 4689 /* RXFR1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 4690 #define SPI_RXFR1_RXDATA_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 4691 #define SPI_RXFR1_RXDATA_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4692 #define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR1_RXDATA_SHIFT))&SPI_RXFR1_RXDATA_MASK)
sahilmgandhi 18:6a4db94011d3 4693 /* RXFR2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 4694 #define SPI_RXFR2_RXDATA_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 4695 #define SPI_RXFR2_RXDATA_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4696 #define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR2_RXDATA_SHIFT))&SPI_RXFR2_RXDATA_MASK)
sahilmgandhi 18:6a4db94011d3 4697 /* RXFR3 Bit Fields */
sahilmgandhi 18:6a4db94011d3 4698 #define SPI_RXFR3_RXDATA_MASK 0xFFFFFFFFu
sahilmgandhi 18:6a4db94011d3 4699 #define SPI_RXFR3_RXDATA_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4700 #define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR3_RXDATA_SHIFT))&SPI_RXFR3_RXDATA_MASK)
sahilmgandhi 18:6a4db94011d3 4701
sahilmgandhi 18:6a4db94011d3 4702 /**
sahilmgandhi 18:6a4db94011d3 4703 * @}
sahilmgandhi 18:6a4db94011d3 4704 */ /* end of group SPI_Register_Masks */
sahilmgandhi 18:6a4db94011d3 4705
sahilmgandhi 18:6a4db94011d3 4706
sahilmgandhi 18:6a4db94011d3 4707 /* SPI - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 4708 /** Peripheral SPI0 base address */
sahilmgandhi 18:6a4db94011d3 4709 #define SPI0_BASE (0x4002C000u)
sahilmgandhi 18:6a4db94011d3 4710 /** Peripheral SPI0 base pointer */
sahilmgandhi 18:6a4db94011d3 4711 #define SPI0 ((SPI_Type *)SPI0_BASE)
sahilmgandhi 18:6a4db94011d3 4712
sahilmgandhi 18:6a4db94011d3 4713 /**
sahilmgandhi 18:6a4db94011d3 4714 * @}
sahilmgandhi 18:6a4db94011d3 4715 */ /* end of group SPI_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 4716
sahilmgandhi 18:6a4db94011d3 4717
sahilmgandhi 18:6a4db94011d3 4718 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 4719 -- TSI Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 4720 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 4721
sahilmgandhi 18:6a4db94011d3 4722 /**
sahilmgandhi 18:6a4db94011d3 4723 * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 4724 * @{
sahilmgandhi 18:6a4db94011d3 4725 */
sahilmgandhi 18:6a4db94011d3 4726
sahilmgandhi 18:6a4db94011d3 4727 /** TSI - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 4728 typedef struct {
sahilmgandhi 18:6a4db94011d3 4729 __IO uint32_t GENCS; /**< General Control and Status Register, offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 4730 __IO uint32_t SCANC; /**< SCAN Control Register, offset: 0x4 */
sahilmgandhi 18:6a4db94011d3 4731 __IO uint32_t PEN; /**< Pin Enable Register, offset: 0x8 */
sahilmgandhi 18:6a4db94011d3 4732 __I uint32_t WUCNTR; /**< Wake-Up Channel Counter Register, offset: 0xC */
sahilmgandhi 18:6a4db94011d3 4733 uint8_t RESERVED_0[240];
sahilmgandhi 18:6a4db94011d3 4734 __I uint32_t CNTR1; /**< Counter Register, offset: 0x100 */
sahilmgandhi 18:6a4db94011d3 4735 __I uint32_t CNTR3; /**< Counter Register, offset: 0x104 */
sahilmgandhi 18:6a4db94011d3 4736 __I uint32_t CNTR5; /**< Counter Register, offset: 0x108 */
sahilmgandhi 18:6a4db94011d3 4737 __I uint32_t CNTR7; /**< Counter Register, offset: 0x10C */
sahilmgandhi 18:6a4db94011d3 4738 __I uint32_t CNTR9; /**< Counter Register, offset: 0x110 */
sahilmgandhi 18:6a4db94011d3 4739 __I uint32_t CNTR11; /**< Counter Register, offset: 0x114 */
sahilmgandhi 18:6a4db94011d3 4740 __I uint32_t CNTR13; /**< Counter Register, offset: 0x118 */
sahilmgandhi 18:6a4db94011d3 4741 __I uint32_t CNTR15; /**< Counter Register, offset: 0x11C */
sahilmgandhi 18:6a4db94011d3 4742 __IO uint32_t THRESHOLD; /**< Low Power Channel Threshold Register, offset: 0x120 */
sahilmgandhi 18:6a4db94011d3 4743 } TSI_Type;
sahilmgandhi 18:6a4db94011d3 4744
sahilmgandhi 18:6a4db94011d3 4745 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 4746 -- TSI Register Masks
sahilmgandhi 18:6a4db94011d3 4747 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 4748
sahilmgandhi 18:6a4db94011d3 4749 /**
sahilmgandhi 18:6a4db94011d3 4750 * @addtogroup TSI_Register_Masks TSI Register Masks
sahilmgandhi 18:6a4db94011d3 4751 * @{
sahilmgandhi 18:6a4db94011d3 4752 */
sahilmgandhi 18:6a4db94011d3 4753
sahilmgandhi 18:6a4db94011d3 4754 /* GENCS Bit Fields */
sahilmgandhi 18:6a4db94011d3 4755 #define TSI_GENCS_STPE_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 4756 #define TSI_GENCS_STPE_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4757 #define TSI_GENCS_STM_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 4758 #define TSI_GENCS_STM_SHIFT 1
sahilmgandhi 18:6a4db94011d3 4759 #define TSI_GENCS_ESOR_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 4760 #define TSI_GENCS_ESOR_SHIFT 4
sahilmgandhi 18:6a4db94011d3 4761 #define TSI_GENCS_ERIE_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 4762 #define TSI_GENCS_ERIE_SHIFT 5
sahilmgandhi 18:6a4db94011d3 4763 #define TSI_GENCS_TSIIE_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 4764 #define TSI_GENCS_TSIIE_SHIFT 6
sahilmgandhi 18:6a4db94011d3 4765 #define TSI_GENCS_TSIEN_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 4766 #define TSI_GENCS_TSIEN_SHIFT 7
sahilmgandhi 18:6a4db94011d3 4767 #define TSI_GENCS_SWTS_MASK 0x100u
sahilmgandhi 18:6a4db94011d3 4768 #define TSI_GENCS_SWTS_SHIFT 8
sahilmgandhi 18:6a4db94011d3 4769 #define TSI_GENCS_SCNIP_MASK 0x200u
sahilmgandhi 18:6a4db94011d3 4770 #define TSI_GENCS_SCNIP_SHIFT 9
sahilmgandhi 18:6a4db94011d3 4771 #define TSI_GENCS_OVRF_MASK 0x1000u
sahilmgandhi 18:6a4db94011d3 4772 #define TSI_GENCS_OVRF_SHIFT 12
sahilmgandhi 18:6a4db94011d3 4773 #define TSI_GENCS_EXTERF_MASK 0x2000u
sahilmgandhi 18:6a4db94011d3 4774 #define TSI_GENCS_EXTERF_SHIFT 13
sahilmgandhi 18:6a4db94011d3 4775 #define TSI_GENCS_OUTRGF_MASK 0x4000u
sahilmgandhi 18:6a4db94011d3 4776 #define TSI_GENCS_OUTRGF_SHIFT 14
sahilmgandhi 18:6a4db94011d3 4777 #define TSI_GENCS_EOSF_MASK 0x8000u
sahilmgandhi 18:6a4db94011d3 4778 #define TSI_GENCS_EOSF_SHIFT 15
sahilmgandhi 18:6a4db94011d3 4779 #define TSI_GENCS_PS_MASK 0x70000u
sahilmgandhi 18:6a4db94011d3 4780 #define TSI_GENCS_PS_SHIFT 16
sahilmgandhi 18:6a4db94011d3 4781 #define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK)
sahilmgandhi 18:6a4db94011d3 4782 #define TSI_GENCS_NSCN_MASK 0xF80000u
sahilmgandhi 18:6a4db94011d3 4783 #define TSI_GENCS_NSCN_SHIFT 19
sahilmgandhi 18:6a4db94011d3 4784 #define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK)
sahilmgandhi 18:6a4db94011d3 4785 #define TSI_GENCS_LPSCNITV_MASK 0xF000000u
sahilmgandhi 18:6a4db94011d3 4786 #define TSI_GENCS_LPSCNITV_SHIFT 24
sahilmgandhi 18:6a4db94011d3 4787 #define TSI_GENCS_LPSCNITV(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_LPSCNITV_SHIFT))&TSI_GENCS_LPSCNITV_MASK)
sahilmgandhi 18:6a4db94011d3 4788 #define TSI_GENCS_LPCLKS_MASK 0x10000000u
sahilmgandhi 18:6a4db94011d3 4789 #define TSI_GENCS_LPCLKS_SHIFT 28
sahilmgandhi 18:6a4db94011d3 4790 /* SCANC Bit Fields */
sahilmgandhi 18:6a4db94011d3 4791 #define TSI_SCANC_AMPSC_MASK 0x7u
sahilmgandhi 18:6a4db94011d3 4792 #define TSI_SCANC_AMPSC_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4793 #define TSI_SCANC_AMPSC(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_AMPSC_SHIFT))&TSI_SCANC_AMPSC_MASK)
sahilmgandhi 18:6a4db94011d3 4794 #define TSI_SCANC_AMCLKS_MASK 0x18u
sahilmgandhi 18:6a4db94011d3 4795 #define TSI_SCANC_AMCLKS_SHIFT 3
sahilmgandhi 18:6a4db94011d3 4796 #define TSI_SCANC_AMCLKS(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_AMCLKS_SHIFT))&TSI_SCANC_AMCLKS_MASK)
sahilmgandhi 18:6a4db94011d3 4797 #define TSI_SCANC_SMOD_MASK 0xFF00u
sahilmgandhi 18:6a4db94011d3 4798 #define TSI_SCANC_SMOD_SHIFT 8
sahilmgandhi 18:6a4db94011d3 4799 #define TSI_SCANC_SMOD(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_SMOD_SHIFT))&TSI_SCANC_SMOD_MASK)
sahilmgandhi 18:6a4db94011d3 4800 #define TSI_SCANC_EXTCHRG_MASK 0xF0000u
sahilmgandhi 18:6a4db94011d3 4801 #define TSI_SCANC_EXTCHRG_SHIFT 16
sahilmgandhi 18:6a4db94011d3 4802 #define TSI_SCANC_EXTCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_EXTCHRG_SHIFT))&TSI_SCANC_EXTCHRG_MASK)
sahilmgandhi 18:6a4db94011d3 4803 #define TSI_SCANC_REFCHRG_MASK 0xF000000u
sahilmgandhi 18:6a4db94011d3 4804 #define TSI_SCANC_REFCHRG_SHIFT 24
sahilmgandhi 18:6a4db94011d3 4805 #define TSI_SCANC_REFCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_REFCHRG_SHIFT))&TSI_SCANC_REFCHRG_MASK)
sahilmgandhi 18:6a4db94011d3 4806 /* PEN Bit Fields */
sahilmgandhi 18:6a4db94011d3 4807 #define TSI_PEN_PEN0_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 4808 #define TSI_PEN_PEN0_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4809 #define TSI_PEN_PEN1_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 4810 #define TSI_PEN_PEN1_SHIFT 1
sahilmgandhi 18:6a4db94011d3 4811 #define TSI_PEN_PEN2_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 4812 #define TSI_PEN_PEN2_SHIFT 2
sahilmgandhi 18:6a4db94011d3 4813 #define TSI_PEN_PEN3_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 4814 #define TSI_PEN_PEN3_SHIFT 3
sahilmgandhi 18:6a4db94011d3 4815 #define TSI_PEN_PEN4_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 4816 #define TSI_PEN_PEN4_SHIFT 4
sahilmgandhi 18:6a4db94011d3 4817 #define TSI_PEN_PEN5_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 4818 #define TSI_PEN_PEN5_SHIFT 5
sahilmgandhi 18:6a4db94011d3 4819 #define TSI_PEN_PEN6_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 4820 #define TSI_PEN_PEN6_SHIFT 6
sahilmgandhi 18:6a4db94011d3 4821 #define TSI_PEN_PEN7_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 4822 #define TSI_PEN_PEN7_SHIFT 7
sahilmgandhi 18:6a4db94011d3 4823 #define TSI_PEN_PEN8_MASK 0x100u
sahilmgandhi 18:6a4db94011d3 4824 #define TSI_PEN_PEN8_SHIFT 8
sahilmgandhi 18:6a4db94011d3 4825 #define TSI_PEN_PEN9_MASK 0x200u
sahilmgandhi 18:6a4db94011d3 4826 #define TSI_PEN_PEN9_SHIFT 9
sahilmgandhi 18:6a4db94011d3 4827 #define TSI_PEN_PEN10_MASK 0x400u
sahilmgandhi 18:6a4db94011d3 4828 #define TSI_PEN_PEN10_SHIFT 10
sahilmgandhi 18:6a4db94011d3 4829 #define TSI_PEN_PEN11_MASK 0x800u
sahilmgandhi 18:6a4db94011d3 4830 #define TSI_PEN_PEN11_SHIFT 11
sahilmgandhi 18:6a4db94011d3 4831 #define TSI_PEN_PEN12_MASK 0x1000u
sahilmgandhi 18:6a4db94011d3 4832 #define TSI_PEN_PEN12_SHIFT 12
sahilmgandhi 18:6a4db94011d3 4833 #define TSI_PEN_PEN13_MASK 0x2000u
sahilmgandhi 18:6a4db94011d3 4834 #define TSI_PEN_PEN13_SHIFT 13
sahilmgandhi 18:6a4db94011d3 4835 #define TSI_PEN_PEN14_MASK 0x4000u
sahilmgandhi 18:6a4db94011d3 4836 #define TSI_PEN_PEN14_SHIFT 14
sahilmgandhi 18:6a4db94011d3 4837 #define TSI_PEN_PEN15_MASK 0x8000u
sahilmgandhi 18:6a4db94011d3 4838 #define TSI_PEN_PEN15_SHIFT 15
sahilmgandhi 18:6a4db94011d3 4839 #define TSI_PEN_LPSP_MASK 0xF0000u
sahilmgandhi 18:6a4db94011d3 4840 #define TSI_PEN_LPSP_SHIFT 16
sahilmgandhi 18:6a4db94011d3 4841 #define TSI_PEN_LPSP(x) (((uint32_t)(((uint32_t)(x))<<TSI_PEN_LPSP_SHIFT))&TSI_PEN_LPSP_MASK)
sahilmgandhi 18:6a4db94011d3 4842 /* WUCNTR Bit Fields */
sahilmgandhi 18:6a4db94011d3 4843 #define TSI_WUCNTR_WUCNT_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 4844 #define TSI_WUCNTR_WUCNT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4845 #define TSI_WUCNTR_WUCNT(x) (((uint32_t)(((uint32_t)(x))<<TSI_WUCNTR_WUCNT_SHIFT))&TSI_WUCNTR_WUCNT_MASK)
sahilmgandhi 18:6a4db94011d3 4846 /* CNTR1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 4847 #define TSI_CNTR1_CTN1_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 4848 #define TSI_CNTR1_CTN1_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4849 #define TSI_CNTR1_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR1_CTN1_SHIFT))&TSI_CNTR1_CTN1_MASK)
sahilmgandhi 18:6a4db94011d3 4850 #define TSI_CNTR1_CTN_MASK 0xFFFF0000u
sahilmgandhi 18:6a4db94011d3 4851 #define TSI_CNTR1_CTN_SHIFT 16
sahilmgandhi 18:6a4db94011d3 4852 #define TSI_CNTR1_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR1_CTN_SHIFT))&TSI_CNTR1_CTN_MASK)
sahilmgandhi 18:6a4db94011d3 4853 /* CNTR3 Bit Fields */
sahilmgandhi 18:6a4db94011d3 4854 #define TSI_CNTR3_CTN1_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 4855 #define TSI_CNTR3_CTN1_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4856 #define TSI_CNTR3_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR3_CTN1_SHIFT))&TSI_CNTR3_CTN1_MASK)
sahilmgandhi 18:6a4db94011d3 4857 #define TSI_CNTR3_CTN_MASK 0xFFFF0000u
sahilmgandhi 18:6a4db94011d3 4858 #define TSI_CNTR3_CTN_SHIFT 16
sahilmgandhi 18:6a4db94011d3 4859 #define TSI_CNTR3_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR3_CTN_SHIFT))&TSI_CNTR3_CTN_MASK)
sahilmgandhi 18:6a4db94011d3 4860 /* CNTR5 Bit Fields */
sahilmgandhi 18:6a4db94011d3 4861 #define TSI_CNTR5_CTN1_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 4862 #define TSI_CNTR5_CTN1_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4863 #define TSI_CNTR5_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR5_CTN1_SHIFT))&TSI_CNTR5_CTN1_MASK)
sahilmgandhi 18:6a4db94011d3 4864 #define TSI_CNTR5_CTN_MASK 0xFFFF0000u
sahilmgandhi 18:6a4db94011d3 4865 #define TSI_CNTR5_CTN_SHIFT 16
sahilmgandhi 18:6a4db94011d3 4866 #define TSI_CNTR5_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR5_CTN_SHIFT))&TSI_CNTR5_CTN_MASK)
sahilmgandhi 18:6a4db94011d3 4867 /* CNTR7 Bit Fields */
sahilmgandhi 18:6a4db94011d3 4868 #define TSI_CNTR7_CTN1_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 4869 #define TSI_CNTR7_CTN1_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4870 #define TSI_CNTR7_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR7_CTN1_SHIFT))&TSI_CNTR7_CTN1_MASK)
sahilmgandhi 18:6a4db94011d3 4871 #define TSI_CNTR7_CTN_MASK 0xFFFF0000u
sahilmgandhi 18:6a4db94011d3 4872 #define TSI_CNTR7_CTN_SHIFT 16
sahilmgandhi 18:6a4db94011d3 4873 #define TSI_CNTR7_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR7_CTN_SHIFT))&TSI_CNTR7_CTN_MASK)
sahilmgandhi 18:6a4db94011d3 4874 /* CNTR9 Bit Fields */
sahilmgandhi 18:6a4db94011d3 4875 #define TSI_CNTR9_CTN1_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 4876 #define TSI_CNTR9_CTN1_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4877 #define TSI_CNTR9_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR9_CTN1_SHIFT))&TSI_CNTR9_CTN1_MASK)
sahilmgandhi 18:6a4db94011d3 4878 #define TSI_CNTR9_CTN_MASK 0xFFFF0000u
sahilmgandhi 18:6a4db94011d3 4879 #define TSI_CNTR9_CTN_SHIFT 16
sahilmgandhi 18:6a4db94011d3 4880 #define TSI_CNTR9_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR9_CTN_SHIFT))&TSI_CNTR9_CTN_MASK)
sahilmgandhi 18:6a4db94011d3 4881 /* CNTR11 Bit Fields */
sahilmgandhi 18:6a4db94011d3 4882 #define TSI_CNTR11_CTN1_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 4883 #define TSI_CNTR11_CTN1_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4884 #define TSI_CNTR11_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR11_CTN1_SHIFT))&TSI_CNTR11_CTN1_MASK)
sahilmgandhi 18:6a4db94011d3 4885 #define TSI_CNTR11_CTN_MASK 0xFFFF0000u
sahilmgandhi 18:6a4db94011d3 4886 #define TSI_CNTR11_CTN_SHIFT 16
sahilmgandhi 18:6a4db94011d3 4887 #define TSI_CNTR11_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR11_CTN_SHIFT))&TSI_CNTR11_CTN_MASK)
sahilmgandhi 18:6a4db94011d3 4888 /* CNTR13 Bit Fields */
sahilmgandhi 18:6a4db94011d3 4889 #define TSI_CNTR13_CTN1_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 4890 #define TSI_CNTR13_CTN1_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4891 #define TSI_CNTR13_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR13_CTN1_SHIFT))&TSI_CNTR13_CTN1_MASK)
sahilmgandhi 18:6a4db94011d3 4892 #define TSI_CNTR13_CTN_MASK 0xFFFF0000u
sahilmgandhi 18:6a4db94011d3 4893 #define TSI_CNTR13_CTN_SHIFT 16
sahilmgandhi 18:6a4db94011d3 4894 #define TSI_CNTR13_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR13_CTN_SHIFT))&TSI_CNTR13_CTN_MASK)
sahilmgandhi 18:6a4db94011d3 4895 /* CNTR15 Bit Fields */
sahilmgandhi 18:6a4db94011d3 4896 #define TSI_CNTR15_CTN1_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 4897 #define TSI_CNTR15_CTN1_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4898 #define TSI_CNTR15_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR15_CTN1_SHIFT))&TSI_CNTR15_CTN1_MASK)
sahilmgandhi 18:6a4db94011d3 4899 #define TSI_CNTR15_CTN_MASK 0xFFFF0000u
sahilmgandhi 18:6a4db94011d3 4900 #define TSI_CNTR15_CTN_SHIFT 16
sahilmgandhi 18:6a4db94011d3 4901 #define TSI_CNTR15_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR15_CTN_SHIFT))&TSI_CNTR15_CTN_MASK)
sahilmgandhi 18:6a4db94011d3 4902 /* THRESHOLD Bit Fields */
sahilmgandhi 18:6a4db94011d3 4903 #define TSI_THRESHOLD_HTHH_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 4904 #define TSI_THRESHOLD_HTHH_SHIFT 0
sahilmgandhi 18:6a4db94011d3 4905 #define TSI_THRESHOLD_HTHH(x) (((uint32_t)(((uint32_t)(x))<<TSI_THRESHOLD_HTHH_SHIFT))&TSI_THRESHOLD_HTHH_MASK)
sahilmgandhi 18:6a4db94011d3 4906 #define TSI_THRESHOLD_LTHH_MASK 0xFFFF0000u
sahilmgandhi 18:6a4db94011d3 4907 #define TSI_THRESHOLD_LTHH_SHIFT 16
sahilmgandhi 18:6a4db94011d3 4908 #define TSI_THRESHOLD_LTHH(x) (((uint32_t)(((uint32_t)(x))<<TSI_THRESHOLD_LTHH_SHIFT))&TSI_THRESHOLD_LTHH_MASK)
sahilmgandhi 18:6a4db94011d3 4909
sahilmgandhi 18:6a4db94011d3 4910 /**
sahilmgandhi 18:6a4db94011d3 4911 * @}
sahilmgandhi 18:6a4db94011d3 4912 */ /* end of group TSI_Register_Masks */
sahilmgandhi 18:6a4db94011d3 4913
sahilmgandhi 18:6a4db94011d3 4914
sahilmgandhi 18:6a4db94011d3 4915 /* TSI - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 4916 /** Peripheral TSI0 base address */
sahilmgandhi 18:6a4db94011d3 4917 #define TSI0_BASE (0x40045000u)
sahilmgandhi 18:6a4db94011d3 4918 /** Peripheral TSI0 base pointer */
sahilmgandhi 18:6a4db94011d3 4919 #define TSI0 ((TSI_Type *)TSI0_BASE)
sahilmgandhi 18:6a4db94011d3 4920
sahilmgandhi 18:6a4db94011d3 4921 /**
sahilmgandhi 18:6a4db94011d3 4922 * @}
sahilmgandhi 18:6a4db94011d3 4923 */ /* end of group TSI_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 4924
sahilmgandhi 18:6a4db94011d3 4925
sahilmgandhi 18:6a4db94011d3 4926 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 4927 -- UART Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 4928 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 4929
sahilmgandhi 18:6a4db94011d3 4930 /**
sahilmgandhi 18:6a4db94011d3 4931 * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 4932 * @{
sahilmgandhi 18:6a4db94011d3 4933 */
sahilmgandhi 18:6a4db94011d3 4934
sahilmgandhi 18:6a4db94011d3 4935 /** UART - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 4936 typedef struct {
sahilmgandhi 18:6a4db94011d3 4937 __IO uint8_t BDH; /**< UART Baud Rate Registers:High, offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 4938 __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */
sahilmgandhi 18:6a4db94011d3 4939 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
sahilmgandhi 18:6a4db94011d3 4940 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
sahilmgandhi 18:6a4db94011d3 4941 __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
sahilmgandhi 18:6a4db94011d3 4942 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
sahilmgandhi 18:6a4db94011d3 4943 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
sahilmgandhi 18:6a4db94011d3 4944 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
sahilmgandhi 18:6a4db94011d3 4945 __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
sahilmgandhi 18:6a4db94011d3 4946 __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
sahilmgandhi 18:6a4db94011d3 4947 __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
sahilmgandhi 18:6a4db94011d3 4948 __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
sahilmgandhi 18:6a4db94011d3 4949 __I uint8_t ED; /**< UART Extended Data Register, offset: 0xC */
sahilmgandhi 18:6a4db94011d3 4950 __IO uint8_t MODEM; /**< UART Modem Register, offset: 0xD */
sahilmgandhi 18:6a4db94011d3 4951 __IO uint8_t IR; /**< UART Infrared Register, offset: 0xE */
sahilmgandhi 18:6a4db94011d3 4952 uint8_t RESERVED_0[1];
sahilmgandhi 18:6a4db94011d3 4953 __IO uint8_t PFIFO; /**< UART FIFO Parameters, offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 4954 __IO uint8_t CFIFO; /**< UART FIFO Control Register, offset: 0x11 */
sahilmgandhi 18:6a4db94011d3 4955 __IO uint8_t SFIFO; /**< UART FIFO Status Register, offset: 0x12 */
sahilmgandhi 18:6a4db94011d3 4956 __IO uint8_t TWFIFO; /**< UART FIFO Transmit Watermark, offset: 0x13 */
sahilmgandhi 18:6a4db94011d3 4957 __I uint8_t TCFIFO; /**< UART FIFO Transmit Count, offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 4958 __IO uint8_t RWFIFO; /**< UART FIFO Receive Watermark, offset: 0x15 */
sahilmgandhi 18:6a4db94011d3 4959 __I uint8_t RCFIFO; /**< UART FIFO Receive Count, offset: 0x16 */
sahilmgandhi 18:6a4db94011d3 4960 uint8_t RESERVED_1[1];
sahilmgandhi 18:6a4db94011d3 4961 __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 4962 __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
sahilmgandhi 18:6a4db94011d3 4963 __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */
sahilmgandhi 18:6a4db94011d3 4964 union { /* offset: 0x1B */
sahilmgandhi 18:6a4db94011d3 4965 __IO uint8_t WP7816_T_TYPE0; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
sahilmgandhi 18:6a4db94011d3 4966 __IO uint8_t WP7816_T_TYPE1; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
sahilmgandhi 18:6a4db94011d3 4967 };
sahilmgandhi 18:6a4db94011d3 4968 __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 4969 __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */
sahilmgandhi 18:6a4db94011d3 4970 __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */
sahilmgandhi 18:6a4db94011d3 4971 __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */
sahilmgandhi 18:6a4db94011d3 4972 uint8_t RESERVED_2[1];
sahilmgandhi 18:6a4db94011d3 4973 __IO uint8_t C6; /**< UART CEA709.1-B Control Register 6, offset: 0x21 */
sahilmgandhi 18:6a4db94011d3 4974 __IO uint8_t PCTH; /**< UART CEA709.1-B Packet Cycle Time Counter High, offset: 0x22 */
sahilmgandhi 18:6a4db94011d3 4975 __IO uint8_t PCTL; /**< UART CEA709.1-B Packet Cycle Time Counter Low, offset: 0x23 */
sahilmgandhi 18:6a4db94011d3 4976 __IO uint8_t B1T; /**< UART CEA709.1-B Beta1 Timer, offset: 0x24 */
sahilmgandhi 18:6a4db94011d3 4977 __IO uint8_t SDTH; /**< UART CEA709.1-B Secondary Delay Timer High, offset: 0x25 */
sahilmgandhi 18:6a4db94011d3 4978 __IO uint8_t SDTL; /**< UART CEA709.1-B Secondary Delay Timer Low, offset: 0x26 */
sahilmgandhi 18:6a4db94011d3 4979 __IO uint8_t PRE; /**< UART CEA709.1-B Preamble, offset: 0x27 */
sahilmgandhi 18:6a4db94011d3 4980 __IO uint8_t TPL; /**< UART CEA709.1-B Transmit Packet Length, offset: 0x28 */
sahilmgandhi 18:6a4db94011d3 4981 __IO uint8_t IE; /**< UART CEA709.1-B Interrupt Enable Register, offset: 0x29 */
sahilmgandhi 18:6a4db94011d3 4982 __IO uint8_t WB; /**< UART CEA709.1-B WBASE, offset: 0x2A */
sahilmgandhi 18:6a4db94011d3 4983 __IO uint8_t S3; /**< UART CEA709.1-B Status Register, offset: 0x2B */
sahilmgandhi 18:6a4db94011d3 4984 __IO uint8_t S4; /**< UART CEA709.1-B Status Register, offset: 0x2C */
sahilmgandhi 18:6a4db94011d3 4985 __I uint8_t RPL; /**< UART CEA709.1-B Received Packet Length, offset: 0x2D */
sahilmgandhi 18:6a4db94011d3 4986 __I uint8_t RPREL; /**< UART CEA709.1-B Received Preamble Length, offset: 0x2E */
sahilmgandhi 18:6a4db94011d3 4987 __IO uint8_t CPW; /**< UART CEA709.1-B Collision Pulse Width, offset: 0x2F */
sahilmgandhi 18:6a4db94011d3 4988 __IO uint8_t RIDT; /**< UART CEA709.1-B Receive Indeterminate Time, offset: 0x30 */
sahilmgandhi 18:6a4db94011d3 4989 __IO uint8_t TIDT; /**< UART CEA709.1-B Transmit Indeterminate Time, offset: 0x31 */
sahilmgandhi 18:6a4db94011d3 4990 } UART_Type;
sahilmgandhi 18:6a4db94011d3 4991
sahilmgandhi 18:6a4db94011d3 4992 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 4993 -- UART Register Masks
sahilmgandhi 18:6a4db94011d3 4994 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 4995
sahilmgandhi 18:6a4db94011d3 4996 /**
sahilmgandhi 18:6a4db94011d3 4997 * @addtogroup UART_Register_Masks UART Register Masks
sahilmgandhi 18:6a4db94011d3 4998 * @{
sahilmgandhi 18:6a4db94011d3 4999 */
sahilmgandhi 18:6a4db94011d3 5000
sahilmgandhi 18:6a4db94011d3 5001 /* BDH Bit Fields */
sahilmgandhi 18:6a4db94011d3 5002 #define UART_BDH_SBR_MASK 0x1Fu
sahilmgandhi 18:6a4db94011d3 5003 #define UART_BDH_SBR_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5004 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
sahilmgandhi 18:6a4db94011d3 5005 #define UART_BDH_RXEDGIE_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 5006 #define UART_BDH_RXEDGIE_SHIFT 6
sahilmgandhi 18:6a4db94011d3 5007 #define UART_BDH_LBKDIE_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 5008 #define UART_BDH_LBKDIE_SHIFT 7
sahilmgandhi 18:6a4db94011d3 5009 /* BDL Bit Fields */
sahilmgandhi 18:6a4db94011d3 5010 #define UART_BDL_SBR_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 5011 #define UART_BDL_SBR_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5012 #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
sahilmgandhi 18:6a4db94011d3 5013 /* C1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 5014 #define UART_C1_PT_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 5015 #define UART_C1_PT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5016 #define UART_C1_PE_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 5017 #define UART_C1_PE_SHIFT 1
sahilmgandhi 18:6a4db94011d3 5018 #define UART_C1_ILT_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 5019 #define UART_C1_ILT_SHIFT 2
sahilmgandhi 18:6a4db94011d3 5020 #define UART_C1_WAKE_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 5021 #define UART_C1_WAKE_SHIFT 3
sahilmgandhi 18:6a4db94011d3 5022 #define UART_C1_M_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 5023 #define UART_C1_M_SHIFT 4
sahilmgandhi 18:6a4db94011d3 5024 #define UART_C1_RSRC_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 5025 #define UART_C1_RSRC_SHIFT 5
sahilmgandhi 18:6a4db94011d3 5026 #define UART_C1_UARTSWAI_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 5027 #define UART_C1_UARTSWAI_SHIFT 6
sahilmgandhi 18:6a4db94011d3 5028 #define UART_C1_LOOPS_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 5029 #define UART_C1_LOOPS_SHIFT 7
sahilmgandhi 18:6a4db94011d3 5030 /* C2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 5031 #define UART_C2_SBK_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 5032 #define UART_C2_SBK_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5033 #define UART_C2_RWU_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 5034 #define UART_C2_RWU_SHIFT 1
sahilmgandhi 18:6a4db94011d3 5035 #define UART_C2_RE_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 5036 #define UART_C2_RE_SHIFT 2
sahilmgandhi 18:6a4db94011d3 5037 #define UART_C2_TE_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 5038 #define UART_C2_TE_SHIFT 3
sahilmgandhi 18:6a4db94011d3 5039 #define UART_C2_ILIE_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 5040 #define UART_C2_ILIE_SHIFT 4
sahilmgandhi 18:6a4db94011d3 5041 #define UART_C2_RIE_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 5042 #define UART_C2_RIE_SHIFT 5
sahilmgandhi 18:6a4db94011d3 5043 #define UART_C2_TCIE_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 5044 #define UART_C2_TCIE_SHIFT 6
sahilmgandhi 18:6a4db94011d3 5045 #define UART_C2_TIE_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 5046 #define UART_C2_TIE_SHIFT 7
sahilmgandhi 18:6a4db94011d3 5047 /* S1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 5048 #define UART_S1_PF_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 5049 #define UART_S1_PF_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5050 #define UART_S1_FE_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 5051 #define UART_S1_FE_SHIFT 1
sahilmgandhi 18:6a4db94011d3 5052 #define UART_S1_NF_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 5053 #define UART_S1_NF_SHIFT 2
sahilmgandhi 18:6a4db94011d3 5054 #define UART_S1_OR_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 5055 #define UART_S1_OR_SHIFT 3
sahilmgandhi 18:6a4db94011d3 5056 #define UART_S1_IDLE_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 5057 #define UART_S1_IDLE_SHIFT 4
sahilmgandhi 18:6a4db94011d3 5058 #define UART_S1_RDRF_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 5059 #define UART_S1_RDRF_SHIFT 5
sahilmgandhi 18:6a4db94011d3 5060 #define UART_S1_TC_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 5061 #define UART_S1_TC_SHIFT 6
sahilmgandhi 18:6a4db94011d3 5062 #define UART_S1_TDRE_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 5063 #define UART_S1_TDRE_SHIFT 7
sahilmgandhi 18:6a4db94011d3 5064 /* S2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 5065 #define UART_S2_RAF_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 5066 #define UART_S2_RAF_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5067 #define UART_S2_LBKDE_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 5068 #define UART_S2_LBKDE_SHIFT 1
sahilmgandhi 18:6a4db94011d3 5069 #define UART_S2_BRK13_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 5070 #define UART_S2_BRK13_SHIFT 2
sahilmgandhi 18:6a4db94011d3 5071 #define UART_S2_RWUID_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 5072 #define UART_S2_RWUID_SHIFT 3
sahilmgandhi 18:6a4db94011d3 5073 #define UART_S2_RXINV_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 5074 #define UART_S2_RXINV_SHIFT 4
sahilmgandhi 18:6a4db94011d3 5075 #define UART_S2_MSBF_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 5076 #define UART_S2_MSBF_SHIFT 5
sahilmgandhi 18:6a4db94011d3 5077 #define UART_S2_RXEDGIF_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 5078 #define UART_S2_RXEDGIF_SHIFT 6
sahilmgandhi 18:6a4db94011d3 5079 #define UART_S2_LBKDIF_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 5080 #define UART_S2_LBKDIF_SHIFT 7
sahilmgandhi 18:6a4db94011d3 5081 /* C3 Bit Fields */
sahilmgandhi 18:6a4db94011d3 5082 #define UART_C3_PEIE_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 5083 #define UART_C3_PEIE_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5084 #define UART_C3_FEIE_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 5085 #define UART_C3_FEIE_SHIFT 1
sahilmgandhi 18:6a4db94011d3 5086 #define UART_C3_NEIE_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 5087 #define UART_C3_NEIE_SHIFT 2
sahilmgandhi 18:6a4db94011d3 5088 #define UART_C3_ORIE_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 5089 #define UART_C3_ORIE_SHIFT 3
sahilmgandhi 18:6a4db94011d3 5090 #define UART_C3_TXINV_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 5091 #define UART_C3_TXINV_SHIFT 4
sahilmgandhi 18:6a4db94011d3 5092 #define UART_C3_TXDIR_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 5093 #define UART_C3_TXDIR_SHIFT 5
sahilmgandhi 18:6a4db94011d3 5094 #define UART_C3_T8_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 5095 #define UART_C3_T8_SHIFT 6
sahilmgandhi 18:6a4db94011d3 5096 #define UART_C3_R8_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 5097 #define UART_C3_R8_SHIFT 7
sahilmgandhi 18:6a4db94011d3 5098 /* D Bit Fields */
sahilmgandhi 18:6a4db94011d3 5099 #define UART_D_RT_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 5100 #define UART_D_RT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5101 #define UART_D_RT(x) (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK)
sahilmgandhi 18:6a4db94011d3 5102 /* MA1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 5103 #define UART_MA1_MA_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 5104 #define UART_MA1_MA_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5105 #define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK)
sahilmgandhi 18:6a4db94011d3 5106 /* MA2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 5107 #define UART_MA2_MA_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 5108 #define UART_MA2_MA_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5109 #define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK)
sahilmgandhi 18:6a4db94011d3 5110 /* C4 Bit Fields */
sahilmgandhi 18:6a4db94011d3 5111 #define UART_C4_BRFA_MASK 0x1Fu
sahilmgandhi 18:6a4db94011d3 5112 #define UART_C4_BRFA_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5113 #define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK)
sahilmgandhi 18:6a4db94011d3 5114 #define UART_C4_M10_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 5115 #define UART_C4_M10_SHIFT 5
sahilmgandhi 18:6a4db94011d3 5116 #define UART_C4_MAEN2_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 5117 #define UART_C4_MAEN2_SHIFT 6
sahilmgandhi 18:6a4db94011d3 5118 #define UART_C4_MAEN1_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 5119 #define UART_C4_MAEN1_SHIFT 7
sahilmgandhi 18:6a4db94011d3 5120 /* C5 Bit Fields */
sahilmgandhi 18:6a4db94011d3 5121 #define UART_C5_RDMAS_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 5122 #define UART_C5_RDMAS_SHIFT 5
sahilmgandhi 18:6a4db94011d3 5123 #define UART_C5_TDMAS_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 5124 #define UART_C5_TDMAS_SHIFT 7
sahilmgandhi 18:6a4db94011d3 5125 /* ED Bit Fields */
sahilmgandhi 18:6a4db94011d3 5126 #define UART_ED_PARITYE_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 5127 #define UART_ED_PARITYE_SHIFT 6
sahilmgandhi 18:6a4db94011d3 5128 #define UART_ED_NOISY_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 5129 #define UART_ED_NOISY_SHIFT 7
sahilmgandhi 18:6a4db94011d3 5130 /* MODEM Bit Fields */
sahilmgandhi 18:6a4db94011d3 5131 #define UART_MODEM_TXCTSE_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 5132 #define UART_MODEM_TXCTSE_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5133 #define UART_MODEM_TXRTSE_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 5134 #define UART_MODEM_TXRTSE_SHIFT 1
sahilmgandhi 18:6a4db94011d3 5135 #define UART_MODEM_TXRTSPOL_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 5136 #define UART_MODEM_TXRTSPOL_SHIFT 2
sahilmgandhi 18:6a4db94011d3 5137 #define UART_MODEM_RXRTSE_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 5138 #define UART_MODEM_RXRTSE_SHIFT 3
sahilmgandhi 18:6a4db94011d3 5139 /* IR Bit Fields */
sahilmgandhi 18:6a4db94011d3 5140 #define UART_IR_TNP_MASK 0x3u
sahilmgandhi 18:6a4db94011d3 5141 #define UART_IR_TNP_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5142 #define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x))<<UART_IR_TNP_SHIFT))&UART_IR_TNP_MASK)
sahilmgandhi 18:6a4db94011d3 5143 #define UART_IR_IREN_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 5144 #define UART_IR_IREN_SHIFT 2
sahilmgandhi 18:6a4db94011d3 5145 /* PFIFO Bit Fields */
sahilmgandhi 18:6a4db94011d3 5146 #define UART_PFIFO_RXFIFOSIZE_MASK 0x7u
sahilmgandhi 18:6a4db94011d3 5147 #define UART_PFIFO_RXFIFOSIZE_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5148 #define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFIFOSIZE_SHIFT))&UART_PFIFO_RXFIFOSIZE_MASK)
sahilmgandhi 18:6a4db94011d3 5149 #define UART_PFIFO_RXFE_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 5150 #define UART_PFIFO_RXFE_SHIFT 3
sahilmgandhi 18:6a4db94011d3 5151 #define UART_PFIFO_TXFIFOSIZE_MASK 0x70u
sahilmgandhi 18:6a4db94011d3 5152 #define UART_PFIFO_TXFIFOSIZE_SHIFT 4
sahilmgandhi 18:6a4db94011d3 5153 #define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFIFOSIZE_SHIFT))&UART_PFIFO_TXFIFOSIZE_MASK)
sahilmgandhi 18:6a4db94011d3 5154 #define UART_PFIFO_TXFE_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 5155 #define UART_PFIFO_TXFE_SHIFT 7
sahilmgandhi 18:6a4db94011d3 5156 /* CFIFO Bit Fields */
sahilmgandhi 18:6a4db94011d3 5157 #define UART_CFIFO_RXUFE_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 5158 #define UART_CFIFO_RXUFE_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5159 #define UART_CFIFO_TXOFE_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 5160 #define UART_CFIFO_TXOFE_SHIFT 1
sahilmgandhi 18:6a4db94011d3 5161 #define UART_CFIFO_RXFLUSH_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 5162 #define UART_CFIFO_RXFLUSH_SHIFT 6
sahilmgandhi 18:6a4db94011d3 5163 #define UART_CFIFO_TXFLUSH_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 5164 #define UART_CFIFO_TXFLUSH_SHIFT 7
sahilmgandhi 18:6a4db94011d3 5165 /* SFIFO Bit Fields */
sahilmgandhi 18:6a4db94011d3 5166 #define UART_SFIFO_RXUF_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 5167 #define UART_SFIFO_RXUF_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5168 #define UART_SFIFO_TXOF_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 5169 #define UART_SFIFO_TXOF_SHIFT 1
sahilmgandhi 18:6a4db94011d3 5170 #define UART_SFIFO_RXEMPT_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 5171 #define UART_SFIFO_RXEMPT_SHIFT 6
sahilmgandhi 18:6a4db94011d3 5172 #define UART_SFIFO_TXEMPT_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 5173 #define UART_SFIFO_TXEMPT_SHIFT 7
sahilmgandhi 18:6a4db94011d3 5174 /* TWFIFO Bit Fields */
sahilmgandhi 18:6a4db94011d3 5175 #define UART_TWFIFO_TXWATER_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 5176 #define UART_TWFIFO_TXWATER_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5177 #define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_TWFIFO_TXWATER_SHIFT))&UART_TWFIFO_TXWATER_MASK)
sahilmgandhi 18:6a4db94011d3 5178 /* TCFIFO Bit Fields */
sahilmgandhi 18:6a4db94011d3 5179 #define UART_TCFIFO_TXCOUNT_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 5180 #define UART_TCFIFO_TXCOUNT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5181 #define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_TCFIFO_TXCOUNT_SHIFT))&UART_TCFIFO_TXCOUNT_MASK)
sahilmgandhi 18:6a4db94011d3 5182 /* RWFIFO Bit Fields */
sahilmgandhi 18:6a4db94011d3 5183 #define UART_RWFIFO_RXWATER_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 5184 #define UART_RWFIFO_RXWATER_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5185 #define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_RWFIFO_RXWATER_SHIFT))&UART_RWFIFO_RXWATER_MASK)
sahilmgandhi 18:6a4db94011d3 5186 /* RCFIFO Bit Fields */
sahilmgandhi 18:6a4db94011d3 5187 #define UART_RCFIFO_RXCOUNT_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 5188 #define UART_RCFIFO_RXCOUNT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5189 #define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_RCFIFO_RXCOUNT_SHIFT))&UART_RCFIFO_RXCOUNT_MASK)
sahilmgandhi 18:6a4db94011d3 5190 /* C7816 Bit Fields */
sahilmgandhi 18:6a4db94011d3 5191 #define UART_C7816_ISO_7816E_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 5192 #define UART_C7816_ISO_7816E_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5193 #define UART_C7816_TTYPE_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 5194 #define UART_C7816_TTYPE_SHIFT 1
sahilmgandhi 18:6a4db94011d3 5195 #define UART_C7816_INIT_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 5196 #define UART_C7816_INIT_SHIFT 2
sahilmgandhi 18:6a4db94011d3 5197 #define UART_C7816_ANACK_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 5198 #define UART_C7816_ANACK_SHIFT 3
sahilmgandhi 18:6a4db94011d3 5199 #define UART_C7816_ONACK_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 5200 #define UART_C7816_ONACK_SHIFT 4
sahilmgandhi 18:6a4db94011d3 5201 /* IE7816 Bit Fields */
sahilmgandhi 18:6a4db94011d3 5202 #define UART_IE7816_RXTE_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 5203 #define UART_IE7816_RXTE_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5204 #define UART_IE7816_TXTE_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 5205 #define UART_IE7816_TXTE_SHIFT 1
sahilmgandhi 18:6a4db94011d3 5206 #define UART_IE7816_GTVE_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 5207 #define UART_IE7816_GTVE_SHIFT 2
sahilmgandhi 18:6a4db94011d3 5208 #define UART_IE7816_INITDE_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 5209 #define UART_IE7816_INITDE_SHIFT 4
sahilmgandhi 18:6a4db94011d3 5210 #define UART_IE7816_BWTE_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 5211 #define UART_IE7816_BWTE_SHIFT 5
sahilmgandhi 18:6a4db94011d3 5212 #define UART_IE7816_CWTE_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 5213 #define UART_IE7816_CWTE_SHIFT 6
sahilmgandhi 18:6a4db94011d3 5214 #define UART_IE7816_WTE_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 5215 #define UART_IE7816_WTE_SHIFT 7
sahilmgandhi 18:6a4db94011d3 5216 /* IS7816 Bit Fields */
sahilmgandhi 18:6a4db94011d3 5217 #define UART_IS7816_RXT_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 5218 #define UART_IS7816_RXT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5219 #define UART_IS7816_TXT_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 5220 #define UART_IS7816_TXT_SHIFT 1
sahilmgandhi 18:6a4db94011d3 5221 #define UART_IS7816_GTV_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 5222 #define UART_IS7816_GTV_SHIFT 2
sahilmgandhi 18:6a4db94011d3 5223 #define UART_IS7816_INITD_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 5224 #define UART_IS7816_INITD_SHIFT 4
sahilmgandhi 18:6a4db94011d3 5225 #define UART_IS7816_BWT_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 5226 #define UART_IS7816_BWT_SHIFT 5
sahilmgandhi 18:6a4db94011d3 5227 #define UART_IS7816_CWT_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 5228 #define UART_IS7816_CWT_SHIFT 6
sahilmgandhi 18:6a4db94011d3 5229 #define UART_IS7816_WT_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 5230 #define UART_IS7816_WT_SHIFT 7
sahilmgandhi 18:6a4db94011d3 5231 /* WP7816_T_TYPE0 Bit Fields */
sahilmgandhi 18:6a4db94011d3 5232 #define UART_WP7816_T_TYPE0_WI_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 5233 #define UART_WP7816_T_TYPE0_WI_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5234 #define UART_WP7816_T_TYPE0_WI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE0_WI_SHIFT))&UART_WP7816_T_TYPE0_WI_MASK)
sahilmgandhi 18:6a4db94011d3 5235 /* WP7816_T_TYPE1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 5236 #define UART_WP7816_T_TYPE1_BWI_MASK 0xFu
sahilmgandhi 18:6a4db94011d3 5237 #define UART_WP7816_T_TYPE1_BWI_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5238 #define UART_WP7816_T_TYPE1_BWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE1_BWI_SHIFT))&UART_WP7816_T_TYPE1_BWI_MASK)
sahilmgandhi 18:6a4db94011d3 5239 #define UART_WP7816_T_TYPE1_CWI_MASK 0xF0u
sahilmgandhi 18:6a4db94011d3 5240 #define UART_WP7816_T_TYPE1_CWI_SHIFT 4
sahilmgandhi 18:6a4db94011d3 5241 #define UART_WP7816_T_TYPE1_CWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE1_CWI_SHIFT))&UART_WP7816_T_TYPE1_CWI_MASK)
sahilmgandhi 18:6a4db94011d3 5242 /* WN7816 Bit Fields */
sahilmgandhi 18:6a4db94011d3 5243 #define UART_WN7816_GTN_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 5244 #define UART_WN7816_GTN_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5245 #define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK)
sahilmgandhi 18:6a4db94011d3 5246 /* WF7816 Bit Fields */
sahilmgandhi 18:6a4db94011d3 5247 #define UART_WF7816_GTFD_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 5248 #define UART_WF7816_GTFD_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5249 #define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK)
sahilmgandhi 18:6a4db94011d3 5250 /* ET7816 Bit Fields */
sahilmgandhi 18:6a4db94011d3 5251 #define UART_ET7816_RXTHRESHOLD_MASK 0xFu
sahilmgandhi 18:6a4db94011d3 5252 #define UART_ET7816_RXTHRESHOLD_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5253 #define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK)
sahilmgandhi 18:6a4db94011d3 5254 #define UART_ET7816_TXTHRESHOLD_MASK 0xF0u
sahilmgandhi 18:6a4db94011d3 5255 #define UART_ET7816_TXTHRESHOLD_SHIFT 4
sahilmgandhi 18:6a4db94011d3 5256 #define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK)
sahilmgandhi 18:6a4db94011d3 5257 /* TL7816 Bit Fields */
sahilmgandhi 18:6a4db94011d3 5258 #define UART_TL7816_TLEN_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 5259 #define UART_TL7816_TLEN_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5260 #define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK)
sahilmgandhi 18:6a4db94011d3 5261 /* C6 Bit Fields */
sahilmgandhi 18:6a4db94011d3 5262 #define UART_C6_CP_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 5263 #define UART_C6_CP_SHIFT 4
sahilmgandhi 18:6a4db94011d3 5264 #define UART_C6_CE_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 5265 #define UART_C6_CE_SHIFT 5
sahilmgandhi 18:6a4db94011d3 5266 #define UART_C6_TX709_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 5267 #define UART_C6_TX709_SHIFT 6
sahilmgandhi 18:6a4db94011d3 5268 #define UART_C6_EN709_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 5269 #define UART_C6_EN709_SHIFT 7
sahilmgandhi 18:6a4db94011d3 5270 /* PCTH Bit Fields */
sahilmgandhi 18:6a4db94011d3 5271 #define UART_PCTH_PCTH_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 5272 #define UART_PCTH_PCTH_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5273 #define UART_PCTH_PCTH(x) (((uint8_t)(((uint8_t)(x))<<UART_PCTH_PCTH_SHIFT))&UART_PCTH_PCTH_MASK)
sahilmgandhi 18:6a4db94011d3 5274 /* PCTL Bit Fields */
sahilmgandhi 18:6a4db94011d3 5275 #define UART_PCTL_PCTL_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 5276 #define UART_PCTL_PCTL_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5277 #define UART_PCTL_PCTL(x) (((uint8_t)(((uint8_t)(x))<<UART_PCTL_PCTL_SHIFT))&UART_PCTL_PCTL_MASK)
sahilmgandhi 18:6a4db94011d3 5278 /* B1T Bit Fields */
sahilmgandhi 18:6a4db94011d3 5279 #define UART_B1T_B1T_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 5280 #define UART_B1T_B1T_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5281 #define UART_B1T_B1T(x) (((uint8_t)(((uint8_t)(x))<<UART_B1T_B1T_SHIFT))&UART_B1T_B1T_MASK)
sahilmgandhi 18:6a4db94011d3 5282 /* SDTH Bit Fields */
sahilmgandhi 18:6a4db94011d3 5283 #define UART_SDTH_SDTH_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 5284 #define UART_SDTH_SDTH_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5285 #define UART_SDTH_SDTH(x) (((uint8_t)(((uint8_t)(x))<<UART_SDTH_SDTH_SHIFT))&UART_SDTH_SDTH_MASK)
sahilmgandhi 18:6a4db94011d3 5286 /* SDTL Bit Fields */
sahilmgandhi 18:6a4db94011d3 5287 #define UART_SDTL_SDTL_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 5288 #define UART_SDTL_SDTL_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5289 #define UART_SDTL_SDTL(x) (((uint8_t)(((uint8_t)(x))<<UART_SDTL_SDTL_SHIFT))&UART_SDTL_SDTL_MASK)
sahilmgandhi 18:6a4db94011d3 5290 /* PRE Bit Fields */
sahilmgandhi 18:6a4db94011d3 5291 #define UART_PRE_PREAMBLE_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 5292 #define UART_PRE_PREAMBLE_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5293 #define UART_PRE_PREAMBLE(x) (((uint8_t)(((uint8_t)(x))<<UART_PRE_PREAMBLE_SHIFT))&UART_PRE_PREAMBLE_MASK)
sahilmgandhi 18:6a4db94011d3 5294 /* TPL Bit Fields */
sahilmgandhi 18:6a4db94011d3 5295 #define UART_TPL_TPL_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 5296 #define UART_TPL_TPL_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5297 #define UART_TPL_TPL(x) (((uint8_t)(((uint8_t)(x))<<UART_TPL_TPL_SHIFT))&UART_TPL_TPL_MASK)
sahilmgandhi 18:6a4db94011d3 5298 /* IE Bit Fields */
sahilmgandhi 18:6a4db94011d3 5299 #define UART_IE_TXFIE_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 5300 #define UART_IE_TXFIE_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5301 #define UART_IE_PSIE_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 5302 #define UART_IE_PSIE_SHIFT 1
sahilmgandhi 18:6a4db94011d3 5303 #define UART_IE_PCTEIE_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 5304 #define UART_IE_PCTEIE_SHIFT 2
sahilmgandhi 18:6a4db94011d3 5305 #define UART_IE_PTXIE_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 5306 #define UART_IE_PTXIE_SHIFT 3
sahilmgandhi 18:6a4db94011d3 5307 #define UART_IE_PRXIE_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 5308 #define UART_IE_PRXIE_SHIFT 4
sahilmgandhi 18:6a4db94011d3 5309 #define UART_IE_ISDIE_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 5310 #define UART_IE_ISDIE_SHIFT 5
sahilmgandhi 18:6a4db94011d3 5311 #define UART_IE_WBEIE_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 5312 #define UART_IE_WBEIE_SHIFT 6
sahilmgandhi 18:6a4db94011d3 5313 /* WB Bit Fields */
sahilmgandhi 18:6a4db94011d3 5314 #define UART_WB_WBASE_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 5315 #define UART_WB_WBASE_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5316 #define UART_WB_WBASE(x) (((uint8_t)(((uint8_t)(x))<<UART_WB_WBASE_SHIFT))&UART_WB_WBASE_MASK)
sahilmgandhi 18:6a4db94011d3 5317 /* S3 Bit Fields */
sahilmgandhi 18:6a4db94011d3 5318 #define UART_S3_TXFF_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 5319 #define UART_S3_TXFF_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5320 #define UART_S3_PSF_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 5321 #define UART_S3_PSF_SHIFT 1
sahilmgandhi 18:6a4db94011d3 5322 #define UART_S3_PCTEF_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 5323 #define UART_S3_PCTEF_SHIFT 2
sahilmgandhi 18:6a4db94011d3 5324 #define UART_S3_PTXF_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 5325 #define UART_S3_PTXF_SHIFT 3
sahilmgandhi 18:6a4db94011d3 5326 #define UART_S3_PRXF_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 5327 #define UART_S3_PRXF_SHIFT 4
sahilmgandhi 18:6a4db94011d3 5328 #define UART_S3_ISD_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 5329 #define UART_S3_ISD_SHIFT 5
sahilmgandhi 18:6a4db94011d3 5330 #define UART_S3_WBEF_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 5331 #define UART_S3_WBEF_SHIFT 6
sahilmgandhi 18:6a4db94011d3 5332 #define UART_S3_PEF_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 5333 #define UART_S3_PEF_SHIFT 7
sahilmgandhi 18:6a4db94011d3 5334 /* S4 Bit Fields */
sahilmgandhi 18:6a4db94011d3 5335 #define UART_S4_FE_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 5336 #define UART_S4_FE_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5337 #define UART_S4_ILCV_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 5338 #define UART_S4_ILCV_SHIFT 1
sahilmgandhi 18:6a4db94011d3 5339 #define UART_S4_CDET_MASK 0xCu
sahilmgandhi 18:6a4db94011d3 5340 #define UART_S4_CDET_SHIFT 2
sahilmgandhi 18:6a4db94011d3 5341 #define UART_S4_CDET(x) (((uint8_t)(((uint8_t)(x))<<UART_S4_CDET_SHIFT))&UART_S4_CDET_MASK)
sahilmgandhi 18:6a4db94011d3 5342 #define UART_S4_INITF_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 5343 #define UART_S4_INITF_SHIFT 4
sahilmgandhi 18:6a4db94011d3 5344 /* RPL Bit Fields */
sahilmgandhi 18:6a4db94011d3 5345 #define UART_RPL_RPL_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 5346 #define UART_RPL_RPL_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5347 #define UART_RPL_RPL(x) (((uint8_t)(((uint8_t)(x))<<UART_RPL_RPL_SHIFT))&UART_RPL_RPL_MASK)
sahilmgandhi 18:6a4db94011d3 5348 /* RPREL Bit Fields */
sahilmgandhi 18:6a4db94011d3 5349 #define UART_RPREL_RPREL_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 5350 #define UART_RPREL_RPREL_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5351 #define UART_RPREL_RPREL(x) (((uint8_t)(((uint8_t)(x))<<UART_RPREL_RPREL_SHIFT))&UART_RPREL_RPREL_MASK)
sahilmgandhi 18:6a4db94011d3 5352 /* CPW Bit Fields */
sahilmgandhi 18:6a4db94011d3 5353 #define UART_CPW_CPW_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 5354 #define UART_CPW_CPW_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5355 #define UART_CPW_CPW(x) (((uint8_t)(((uint8_t)(x))<<UART_CPW_CPW_SHIFT))&UART_CPW_CPW_MASK)
sahilmgandhi 18:6a4db94011d3 5356 /* RIDT Bit Fields */
sahilmgandhi 18:6a4db94011d3 5357 #define UART_RIDT_RIDT_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 5358 #define UART_RIDT_RIDT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5359 #define UART_RIDT_RIDT(x) (((uint8_t)(((uint8_t)(x))<<UART_RIDT_RIDT_SHIFT))&UART_RIDT_RIDT_MASK)
sahilmgandhi 18:6a4db94011d3 5360 /* TIDT Bit Fields */
sahilmgandhi 18:6a4db94011d3 5361 #define UART_TIDT_TIDT_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 5362 #define UART_TIDT_TIDT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5363 #define UART_TIDT_TIDT(x) (((uint8_t)(((uint8_t)(x))<<UART_TIDT_TIDT_SHIFT))&UART_TIDT_TIDT_MASK)
sahilmgandhi 18:6a4db94011d3 5364
sahilmgandhi 18:6a4db94011d3 5365 /**
sahilmgandhi 18:6a4db94011d3 5366 * @}
sahilmgandhi 18:6a4db94011d3 5367 */ /* end of group UART_Register_Masks */
sahilmgandhi 18:6a4db94011d3 5368
sahilmgandhi 18:6a4db94011d3 5369
sahilmgandhi 18:6a4db94011d3 5370 /* UART - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 5371 /** Peripheral UART0 base address */
sahilmgandhi 18:6a4db94011d3 5372 #define UART0_BASE (0x4006A000u)
sahilmgandhi 18:6a4db94011d3 5373 /** Peripheral UART0 base pointer */
sahilmgandhi 18:6a4db94011d3 5374 #define UART0 ((UART_Type *)UART0_BASE)
sahilmgandhi 18:6a4db94011d3 5375 /** Peripheral UART1 base address */
sahilmgandhi 18:6a4db94011d3 5376 #define UART1_BASE (0x4006B000u)
sahilmgandhi 18:6a4db94011d3 5377 /** Peripheral UART1 base pointer */
sahilmgandhi 18:6a4db94011d3 5378 #define UART1 ((UART_Type *)UART1_BASE)
sahilmgandhi 18:6a4db94011d3 5379 /** Peripheral UART2 base address */
sahilmgandhi 18:6a4db94011d3 5380 #define UART2_BASE (0x4006C000u)
sahilmgandhi 18:6a4db94011d3 5381 /** Peripheral UART2 base pointer */
sahilmgandhi 18:6a4db94011d3 5382 #define UART2 ((UART_Type *)UART2_BASE)
sahilmgandhi 18:6a4db94011d3 5383
sahilmgandhi 18:6a4db94011d3 5384 /**
sahilmgandhi 18:6a4db94011d3 5385 * @}
sahilmgandhi 18:6a4db94011d3 5386 */ /* end of group UART_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 5387
sahilmgandhi 18:6a4db94011d3 5388
sahilmgandhi 18:6a4db94011d3 5389 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 5390 -- USB Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 5391 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 5392
sahilmgandhi 18:6a4db94011d3 5393 /**
sahilmgandhi 18:6a4db94011d3 5394 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 5395 * @{
sahilmgandhi 18:6a4db94011d3 5396 */
sahilmgandhi 18:6a4db94011d3 5397
sahilmgandhi 18:6a4db94011d3 5398 /** USB - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 5399 typedef struct {
sahilmgandhi 18:6a4db94011d3 5400 __I uint8_t PERID; /**< Peripheral ID Register, offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 5401 uint8_t RESERVED_0[3];
sahilmgandhi 18:6a4db94011d3 5402 __I uint8_t IDCOMP; /**< Peripheral ID Complement Register, offset: 0x4 */
sahilmgandhi 18:6a4db94011d3 5403 uint8_t RESERVED_1[3];
sahilmgandhi 18:6a4db94011d3 5404 __I uint8_t REV; /**< Peripheral Revision Register, offset: 0x8 */
sahilmgandhi 18:6a4db94011d3 5405 uint8_t RESERVED_2[3];
sahilmgandhi 18:6a4db94011d3 5406 __I uint8_t ADDINFO; /**< Peripheral Additional Info Register, offset: 0xC */
sahilmgandhi 18:6a4db94011d3 5407 uint8_t RESERVED_3[3];
sahilmgandhi 18:6a4db94011d3 5408 __IO uint8_t OTGISTAT; /**< OTG Interrupt Status Register, offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 5409 uint8_t RESERVED_4[3];
sahilmgandhi 18:6a4db94011d3 5410 __IO uint8_t OTGICR; /**< OTG Interrupt Control Register, offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 5411 uint8_t RESERVED_5[3];
sahilmgandhi 18:6a4db94011d3 5412 __IO uint8_t OTGSTAT; /**< OTG Status Register, offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 5413 uint8_t RESERVED_6[3];
sahilmgandhi 18:6a4db94011d3 5414 __IO uint8_t OTGCTL; /**< OTG Control Register, offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 5415 uint8_t RESERVED_7[99];
sahilmgandhi 18:6a4db94011d3 5416 __IO uint8_t ISTAT; /**< Interrupt Status Register, offset: 0x80 */
sahilmgandhi 18:6a4db94011d3 5417 uint8_t RESERVED_8[3];
sahilmgandhi 18:6a4db94011d3 5418 __IO uint8_t INTEN; /**< Interrupt Enable Register, offset: 0x84 */
sahilmgandhi 18:6a4db94011d3 5419 uint8_t RESERVED_9[3];
sahilmgandhi 18:6a4db94011d3 5420 __IO uint8_t ERRSTAT; /**< Error Interrupt Status Register, offset: 0x88 */
sahilmgandhi 18:6a4db94011d3 5421 uint8_t RESERVED_10[3];
sahilmgandhi 18:6a4db94011d3 5422 __IO uint8_t ERREN; /**< Error Interrupt Enable Register, offset: 0x8C */
sahilmgandhi 18:6a4db94011d3 5423 uint8_t RESERVED_11[3];
sahilmgandhi 18:6a4db94011d3 5424 __I uint8_t STAT; /**< Status Register, offset: 0x90 */
sahilmgandhi 18:6a4db94011d3 5425 uint8_t RESERVED_12[3];
sahilmgandhi 18:6a4db94011d3 5426 __IO uint8_t CTL; /**< Control Register, offset: 0x94 */
sahilmgandhi 18:6a4db94011d3 5427 uint8_t RESERVED_13[3];
sahilmgandhi 18:6a4db94011d3 5428 __IO uint8_t ADDR; /**< Address Register, offset: 0x98 */
sahilmgandhi 18:6a4db94011d3 5429 uint8_t RESERVED_14[3];
sahilmgandhi 18:6a4db94011d3 5430 __IO uint8_t BDTPAGE1; /**< BDT Page Register 1, offset: 0x9C */
sahilmgandhi 18:6a4db94011d3 5431 uint8_t RESERVED_15[3];
sahilmgandhi 18:6a4db94011d3 5432 __IO uint8_t FRMNUML; /**< Frame Number Register Low, offset: 0xA0 */
sahilmgandhi 18:6a4db94011d3 5433 uint8_t RESERVED_16[3];
sahilmgandhi 18:6a4db94011d3 5434 __IO uint8_t FRMNUMH; /**< Frame Number Register High, offset: 0xA4 */
sahilmgandhi 18:6a4db94011d3 5435 uint8_t RESERVED_17[3];
sahilmgandhi 18:6a4db94011d3 5436 __IO uint8_t TOKEN; /**< Token Register, offset: 0xA8 */
sahilmgandhi 18:6a4db94011d3 5437 uint8_t RESERVED_18[3];
sahilmgandhi 18:6a4db94011d3 5438 __IO uint8_t SOFTHLD; /**< SOF Threshold Register, offset: 0xAC */
sahilmgandhi 18:6a4db94011d3 5439 uint8_t RESERVED_19[3];
sahilmgandhi 18:6a4db94011d3 5440 __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
sahilmgandhi 18:6a4db94011d3 5441 uint8_t RESERVED_20[3];
sahilmgandhi 18:6a4db94011d3 5442 __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
sahilmgandhi 18:6a4db94011d3 5443 uint8_t RESERVED_21[11];
sahilmgandhi 18:6a4db94011d3 5444 struct { /* offset: 0xC0, array step: 0x4 */
sahilmgandhi 18:6a4db94011d3 5445 __IO uint8_t ENDPT; /**< Endpoint Control Register, array offset: 0xC0, array step: 0x4 */
sahilmgandhi 18:6a4db94011d3 5446 uint8_t RESERVED_0[3];
sahilmgandhi 18:6a4db94011d3 5447 } ENDPOINT[16];
sahilmgandhi 18:6a4db94011d3 5448 __IO uint8_t USBCTRL; /**< USB Control Register, offset: 0x100 */
sahilmgandhi 18:6a4db94011d3 5449 uint8_t RESERVED_22[3];
sahilmgandhi 18:6a4db94011d3 5450 __I uint8_t OBSERVE; /**< USB OTG Observe Register, offset: 0x104 */
sahilmgandhi 18:6a4db94011d3 5451 uint8_t RESERVED_23[3];
sahilmgandhi 18:6a4db94011d3 5452 __IO uint8_t CONTROL; /**< USB OTG Control Register, offset: 0x108 */
sahilmgandhi 18:6a4db94011d3 5453 uint8_t RESERVED_24[3];
sahilmgandhi 18:6a4db94011d3 5454 __IO uint8_t USBTRC0; /**< USB Transceiver Control Register 0, offset: 0x10C */
sahilmgandhi 18:6a4db94011d3 5455 uint8_t RESERVED_25[7];
sahilmgandhi 18:6a4db94011d3 5456 __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
sahilmgandhi 18:6a4db94011d3 5457 } USB_Type;
sahilmgandhi 18:6a4db94011d3 5458
sahilmgandhi 18:6a4db94011d3 5459 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 5460 -- USB Register Masks
sahilmgandhi 18:6a4db94011d3 5461 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 5462
sahilmgandhi 18:6a4db94011d3 5463 /**
sahilmgandhi 18:6a4db94011d3 5464 * @addtogroup USB_Register_Masks USB Register Masks
sahilmgandhi 18:6a4db94011d3 5465 * @{
sahilmgandhi 18:6a4db94011d3 5466 */
sahilmgandhi 18:6a4db94011d3 5467
sahilmgandhi 18:6a4db94011d3 5468 /* PERID Bit Fields */
sahilmgandhi 18:6a4db94011d3 5469 #define USB_PERID_ID_MASK 0x3Fu
sahilmgandhi 18:6a4db94011d3 5470 #define USB_PERID_ID_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5471 #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
sahilmgandhi 18:6a4db94011d3 5472 /* IDCOMP Bit Fields */
sahilmgandhi 18:6a4db94011d3 5473 #define USB_IDCOMP_NID_MASK 0x3Fu
sahilmgandhi 18:6a4db94011d3 5474 #define USB_IDCOMP_NID_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5475 #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
sahilmgandhi 18:6a4db94011d3 5476 /* REV Bit Fields */
sahilmgandhi 18:6a4db94011d3 5477 #define USB_REV_REV_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 5478 #define USB_REV_REV_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5479 #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
sahilmgandhi 18:6a4db94011d3 5480 /* ADDINFO Bit Fields */
sahilmgandhi 18:6a4db94011d3 5481 #define USB_ADDINFO_IEHOST_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 5482 #define USB_ADDINFO_IEHOST_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5483 #define USB_ADDINFO_IRQNUM_MASK 0xF8u
sahilmgandhi 18:6a4db94011d3 5484 #define USB_ADDINFO_IRQNUM_SHIFT 3
sahilmgandhi 18:6a4db94011d3 5485 #define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
sahilmgandhi 18:6a4db94011d3 5486 /* OTGISTAT Bit Fields */
sahilmgandhi 18:6a4db94011d3 5487 #define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 5488 #define USB_OTGISTAT_AVBUSCHG_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5489 #define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 5490 #define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
sahilmgandhi 18:6a4db94011d3 5491 #define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 5492 #define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
sahilmgandhi 18:6a4db94011d3 5493 #define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 5494 #define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
sahilmgandhi 18:6a4db94011d3 5495 #define USB_OTGISTAT_ONEMSEC_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 5496 #define USB_OTGISTAT_ONEMSEC_SHIFT 6
sahilmgandhi 18:6a4db94011d3 5497 #define USB_OTGISTAT_IDCHG_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 5498 #define USB_OTGISTAT_IDCHG_SHIFT 7
sahilmgandhi 18:6a4db94011d3 5499 /* OTGICR Bit Fields */
sahilmgandhi 18:6a4db94011d3 5500 #define USB_OTGICR_AVBUSEN_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 5501 #define USB_OTGICR_AVBUSEN_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5502 #define USB_OTGICR_BSESSEN_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 5503 #define USB_OTGICR_BSESSEN_SHIFT 2
sahilmgandhi 18:6a4db94011d3 5504 #define USB_OTGICR_SESSVLDEN_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 5505 #define USB_OTGICR_SESSVLDEN_SHIFT 3
sahilmgandhi 18:6a4db94011d3 5506 #define USB_OTGICR_LINESTATEEN_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 5507 #define USB_OTGICR_LINESTATEEN_SHIFT 5
sahilmgandhi 18:6a4db94011d3 5508 #define USB_OTGICR_ONEMSECEN_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 5509 #define USB_OTGICR_ONEMSECEN_SHIFT 6
sahilmgandhi 18:6a4db94011d3 5510 #define USB_OTGICR_IDEN_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 5511 #define USB_OTGICR_IDEN_SHIFT 7
sahilmgandhi 18:6a4db94011d3 5512 /* OTGSTAT Bit Fields */
sahilmgandhi 18:6a4db94011d3 5513 #define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 5514 #define USB_OTGSTAT_AVBUSVLD_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5515 #define USB_OTGSTAT_BSESSEND_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 5516 #define USB_OTGSTAT_BSESSEND_SHIFT 2
sahilmgandhi 18:6a4db94011d3 5517 #define USB_OTGSTAT_SESS_VLD_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 5518 #define USB_OTGSTAT_SESS_VLD_SHIFT 3
sahilmgandhi 18:6a4db94011d3 5519 #define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 5520 #define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
sahilmgandhi 18:6a4db94011d3 5521 #define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 5522 #define USB_OTGSTAT_ONEMSECEN_SHIFT 6
sahilmgandhi 18:6a4db94011d3 5523 #define USB_OTGSTAT_ID_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 5524 #define USB_OTGSTAT_ID_SHIFT 7
sahilmgandhi 18:6a4db94011d3 5525 /* OTGCTL Bit Fields */
sahilmgandhi 18:6a4db94011d3 5526 #define USB_OTGCTL_OTGEN_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 5527 #define USB_OTGCTL_OTGEN_SHIFT 2
sahilmgandhi 18:6a4db94011d3 5528 #define USB_OTGCTL_DMLOW_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 5529 #define USB_OTGCTL_DMLOW_SHIFT 4
sahilmgandhi 18:6a4db94011d3 5530 #define USB_OTGCTL_DPLOW_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 5531 #define USB_OTGCTL_DPLOW_SHIFT 5
sahilmgandhi 18:6a4db94011d3 5532 #define USB_OTGCTL_DPHIGH_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 5533 #define USB_OTGCTL_DPHIGH_SHIFT 7
sahilmgandhi 18:6a4db94011d3 5534 /* ISTAT Bit Fields */
sahilmgandhi 18:6a4db94011d3 5535 #define USB_ISTAT_USBRST_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 5536 #define USB_ISTAT_USBRST_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5537 #define USB_ISTAT_ERROR_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 5538 #define USB_ISTAT_ERROR_SHIFT 1
sahilmgandhi 18:6a4db94011d3 5539 #define USB_ISTAT_SOFTOK_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 5540 #define USB_ISTAT_SOFTOK_SHIFT 2
sahilmgandhi 18:6a4db94011d3 5541 #define USB_ISTAT_TOKDNE_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 5542 #define USB_ISTAT_TOKDNE_SHIFT 3
sahilmgandhi 18:6a4db94011d3 5543 #define USB_ISTAT_SLEEP_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 5544 #define USB_ISTAT_SLEEP_SHIFT 4
sahilmgandhi 18:6a4db94011d3 5545 #define USB_ISTAT_RESUME_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 5546 #define USB_ISTAT_RESUME_SHIFT 5
sahilmgandhi 18:6a4db94011d3 5547 #define USB_ISTAT_ATTACH_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 5548 #define USB_ISTAT_ATTACH_SHIFT 6
sahilmgandhi 18:6a4db94011d3 5549 #define USB_ISTAT_STALL_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 5550 #define USB_ISTAT_STALL_SHIFT 7
sahilmgandhi 18:6a4db94011d3 5551 /* INTEN Bit Fields */
sahilmgandhi 18:6a4db94011d3 5552 #define USB_INTEN_USBRSTEN_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 5553 #define USB_INTEN_USBRSTEN_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5554 #define USB_INTEN_ERROREN_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 5555 #define USB_INTEN_ERROREN_SHIFT 1
sahilmgandhi 18:6a4db94011d3 5556 #define USB_INTEN_SOFTOKEN_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 5557 #define USB_INTEN_SOFTOKEN_SHIFT 2
sahilmgandhi 18:6a4db94011d3 5558 #define USB_INTEN_TOKDNEEN_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 5559 #define USB_INTEN_TOKDNEEN_SHIFT 3
sahilmgandhi 18:6a4db94011d3 5560 #define USB_INTEN_SLEEPEN_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 5561 #define USB_INTEN_SLEEPEN_SHIFT 4
sahilmgandhi 18:6a4db94011d3 5562 #define USB_INTEN_RESUMEEN_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 5563 #define USB_INTEN_RESUMEEN_SHIFT 5
sahilmgandhi 18:6a4db94011d3 5564 #define USB_INTEN_ATTACHEN_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 5565 #define USB_INTEN_ATTACHEN_SHIFT 6
sahilmgandhi 18:6a4db94011d3 5566 #define USB_INTEN_STALLEN_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 5567 #define USB_INTEN_STALLEN_SHIFT 7
sahilmgandhi 18:6a4db94011d3 5568 /* ERRSTAT Bit Fields */
sahilmgandhi 18:6a4db94011d3 5569 #define USB_ERRSTAT_PIDERR_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 5570 #define USB_ERRSTAT_PIDERR_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5571 #define USB_ERRSTAT_CRC5EOF_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 5572 #define USB_ERRSTAT_CRC5EOF_SHIFT 1
sahilmgandhi 18:6a4db94011d3 5573 #define USB_ERRSTAT_CRC16_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 5574 #define USB_ERRSTAT_CRC16_SHIFT 2
sahilmgandhi 18:6a4db94011d3 5575 #define USB_ERRSTAT_DFN8_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 5576 #define USB_ERRSTAT_DFN8_SHIFT 3
sahilmgandhi 18:6a4db94011d3 5577 #define USB_ERRSTAT_BTOERR_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 5578 #define USB_ERRSTAT_BTOERR_SHIFT 4
sahilmgandhi 18:6a4db94011d3 5579 #define USB_ERRSTAT_DMAERR_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 5580 #define USB_ERRSTAT_DMAERR_SHIFT 5
sahilmgandhi 18:6a4db94011d3 5581 #define USB_ERRSTAT_BTSERR_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 5582 #define USB_ERRSTAT_BTSERR_SHIFT 7
sahilmgandhi 18:6a4db94011d3 5583 /* ERREN Bit Fields */
sahilmgandhi 18:6a4db94011d3 5584 #define USB_ERREN_PIDERREN_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 5585 #define USB_ERREN_PIDERREN_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5586 #define USB_ERREN_CRC5EOFEN_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 5587 #define USB_ERREN_CRC5EOFEN_SHIFT 1
sahilmgandhi 18:6a4db94011d3 5588 #define USB_ERREN_CRC16EN_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 5589 #define USB_ERREN_CRC16EN_SHIFT 2
sahilmgandhi 18:6a4db94011d3 5590 #define USB_ERREN_DFN8EN_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 5591 #define USB_ERREN_DFN8EN_SHIFT 3
sahilmgandhi 18:6a4db94011d3 5592 #define USB_ERREN_BTOERREN_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 5593 #define USB_ERREN_BTOERREN_SHIFT 4
sahilmgandhi 18:6a4db94011d3 5594 #define USB_ERREN_DMAERREN_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 5595 #define USB_ERREN_DMAERREN_SHIFT 5
sahilmgandhi 18:6a4db94011d3 5596 #define USB_ERREN_BTSERREN_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 5597 #define USB_ERREN_BTSERREN_SHIFT 7
sahilmgandhi 18:6a4db94011d3 5598 /* STAT Bit Fields */
sahilmgandhi 18:6a4db94011d3 5599 #define USB_STAT_ODD_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 5600 #define USB_STAT_ODD_SHIFT 2
sahilmgandhi 18:6a4db94011d3 5601 #define USB_STAT_TX_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 5602 #define USB_STAT_TX_SHIFT 3
sahilmgandhi 18:6a4db94011d3 5603 #define USB_STAT_ENDP_MASK 0xF0u
sahilmgandhi 18:6a4db94011d3 5604 #define USB_STAT_ENDP_SHIFT 4
sahilmgandhi 18:6a4db94011d3 5605 #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
sahilmgandhi 18:6a4db94011d3 5606 /* CTL Bit Fields */
sahilmgandhi 18:6a4db94011d3 5607 #define USB_CTL_USBENSOFEN_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 5608 #define USB_CTL_USBENSOFEN_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5609 #define USB_CTL_ODDRST_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 5610 #define USB_CTL_ODDRST_SHIFT 1
sahilmgandhi 18:6a4db94011d3 5611 #define USB_CTL_RESUME_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 5612 #define USB_CTL_RESUME_SHIFT 2
sahilmgandhi 18:6a4db94011d3 5613 #define USB_CTL_HOSTMODEEN_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 5614 #define USB_CTL_HOSTMODEEN_SHIFT 3
sahilmgandhi 18:6a4db94011d3 5615 #define USB_CTL_RESET_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 5616 #define USB_CTL_RESET_SHIFT 4
sahilmgandhi 18:6a4db94011d3 5617 #define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 5618 #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
sahilmgandhi 18:6a4db94011d3 5619 #define USB_CTL_SE0_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 5620 #define USB_CTL_SE0_SHIFT 6
sahilmgandhi 18:6a4db94011d3 5621 #define USB_CTL_JSTATE_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 5622 #define USB_CTL_JSTATE_SHIFT 7
sahilmgandhi 18:6a4db94011d3 5623 /* ADDR Bit Fields */
sahilmgandhi 18:6a4db94011d3 5624 #define USB_ADDR_ADDR_MASK 0x7Fu
sahilmgandhi 18:6a4db94011d3 5625 #define USB_ADDR_ADDR_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5626 #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
sahilmgandhi 18:6a4db94011d3 5627 #define USB_ADDR_LSEN_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 5628 #define USB_ADDR_LSEN_SHIFT 7
sahilmgandhi 18:6a4db94011d3 5629 /* BDTPAGE1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 5630 #define USB_BDTPAGE1_BDTBA_MASK 0xFEu
sahilmgandhi 18:6a4db94011d3 5631 #define USB_BDTPAGE1_BDTBA_SHIFT 1
sahilmgandhi 18:6a4db94011d3 5632 #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
sahilmgandhi 18:6a4db94011d3 5633 /* FRMNUML Bit Fields */
sahilmgandhi 18:6a4db94011d3 5634 #define USB_FRMNUML_FRM_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 5635 #define USB_FRMNUML_FRM_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5636 #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
sahilmgandhi 18:6a4db94011d3 5637 /* FRMNUMH Bit Fields */
sahilmgandhi 18:6a4db94011d3 5638 #define USB_FRMNUMH_FRM_MASK 0x7u
sahilmgandhi 18:6a4db94011d3 5639 #define USB_FRMNUMH_FRM_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5640 #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
sahilmgandhi 18:6a4db94011d3 5641 /* TOKEN Bit Fields */
sahilmgandhi 18:6a4db94011d3 5642 #define USB_TOKEN_TOKENENDPT_MASK 0xFu
sahilmgandhi 18:6a4db94011d3 5643 #define USB_TOKEN_TOKENENDPT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5644 #define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
sahilmgandhi 18:6a4db94011d3 5645 #define USB_TOKEN_TOKENPID_MASK 0xF0u
sahilmgandhi 18:6a4db94011d3 5646 #define USB_TOKEN_TOKENPID_SHIFT 4
sahilmgandhi 18:6a4db94011d3 5647 #define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
sahilmgandhi 18:6a4db94011d3 5648 /* SOFTHLD Bit Fields */
sahilmgandhi 18:6a4db94011d3 5649 #define USB_SOFTHLD_CNT_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 5650 #define USB_SOFTHLD_CNT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5651 #define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
sahilmgandhi 18:6a4db94011d3 5652 /* BDTPAGE2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 5653 #define USB_BDTPAGE2_BDTBA_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 5654 #define USB_BDTPAGE2_BDTBA_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5655 #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
sahilmgandhi 18:6a4db94011d3 5656 /* BDTPAGE3 Bit Fields */
sahilmgandhi 18:6a4db94011d3 5657 #define USB_BDTPAGE3_BDTBA_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 5658 #define USB_BDTPAGE3_BDTBA_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5659 #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
sahilmgandhi 18:6a4db94011d3 5660 /* ENDPT Bit Fields */
sahilmgandhi 18:6a4db94011d3 5661 #define USB_ENDPT_EPHSHK_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 5662 #define USB_ENDPT_EPHSHK_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5663 #define USB_ENDPT_EPSTALL_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 5664 #define USB_ENDPT_EPSTALL_SHIFT 1
sahilmgandhi 18:6a4db94011d3 5665 #define USB_ENDPT_EPTXEN_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 5666 #define USB_ENDPT_EPTXEN_SHIFT 2
sahilmgandhi 18:6a4db94011d3 5667 #define USB_ENDPT_EPRXEN_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 5668 #define USB_ENDPT_EPRXEN_SHIFT 3
sahilmgandhi 18:6a4db94011d3 5669 #define USB_ENDPT_EPCTLDIS_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 5670 #define USB_ENDPT_EPCTLDIS_SHIFT 4
sahilmgandhi 18:6a4db94011d3 5671 #define USB_ENDPT_RETRYDIS_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 5672 #define USB_ENDPT_RETRYDIS_SHIFT 6
sahilmgandhi 18:6a4db94011d3 5673 #define USB_ENDPT_HOSTWOHUB_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 5674 #define USB_ENDPT_HOSTWOHUB_SHIFT 7
sahilmgandhi 18:6a4db94011d3 5675 /* USBCTRL Bit Fields */
sahilmgandhi 18:6a4db94011d3 5676 #define USB_USBCTRL_PDE_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 5677 #define USB_USBCTRL_PDE_SHIFT 6
sahilmgandhi 18:6a4db94011d3 5678 #define USB_USBCTRL_SUSP_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 5679 #define USB_USBCTRL_SUSP_SHIFT 7
sahilmgandhi 18:6a4db94011d3 5680 /* OBSERVE Bit Fields */
sahilmgandhi 18:6a4db94011d3 5681 #define USB_OBSERVE_DMPD_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 5682 #define USB_OBSERVE_DMPD_SHIFT 4
sahilmgandhi 18:6a4db94011d3 5683 #define USB_OBSERVE_DPPD_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 5684 #define USB_OBSERVE_DPPD_SHIFT 6
sahilmgandhi 18:6a4db94011d3 5685 #define USB_OBSERVE_DPPU_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 5686 #define USB_OBSERVE_DPPU_SHIFT 7
sahilmgandhi 18:6a4db94011d3 5687 /* CONTROL Bit Fields */
sahilmgandhi 18:6a4db94011d3 5688 #define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 5689 #define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
sahilmgandhi 18:6a4db94011d3 5690 /* USBTRC0 Bit Fields */
sahilmgandhi 18:6a4db94011d3 5691 #define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 5692 #define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5693 #define USB_USBTRC0_SYNC_DET_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 5694 #define USB_USBTRC0_SYNC_DET_SHIFT 1
sahilmgandhi 18:6a4db94011d3 5695 #define USB_USBTRC0_USBRESMEN_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 5696 #define USB_USBTRC0_USBRESMEN_SHIFT 5
sahilmgandhi 18:6a4db94011d3 5697 #define USB_USBTRC0_USBRESET_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 5698 #define USB_USBTRC0_USBRESET_SHIFT 7
sahilmgandhi 18:6a4db94011d3 5699 /* USBFRMADJUST Bit Fields */
sahilmgandhi 18:6a4db94011d3 5700 #define USB_USBFRMADJUST_ADJ_MASK 0xFFu
sahilmgandhi 18:6a4db94011d3 5701 #define USB_USBFRMADJUST_ADJ_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5702 #define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
sahilmgandhi 18:6a4db94011d3 5703
sahilmgandhi 18:6a4db94011d3 5704 /**
sahilmgandhi 18:6a4db94011d3 5705 * @}
sahilmgandhi 18:6a4db94011d3 5706 */ /* end of group USB_Register_Masks */
sahilmgandhi 18:6a4db94011d3 5707
sahilmgandhi 18:6a4db94011d3 5708
sahilmgandhi 18:6a4db94011d3 5709 /* USB - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 5710 /** Peripheral USB0 base address */
sahilmgandhi 18:6a4db94011d3 5711 #define USB0_BASE (0x40072000u)
sahilmgandhi 18:6a4db94011d3 5712 /** Peripheral USB0 base pointer */
sahilmgandhi 18:6a4db94011d3 5713 #define USB0 ((USB_Type *)USB0_BASE)
sahilmgandhi 18:6a4db94011d3 5714
sahilmgandhi 18:6a4db94011d3 5715 /**
sahilmgandhi 18:6a4db94011d3 5716 * @}
sahilmgandhi 18:6a4db94011d3 5717 */ /* end of group USB_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 5718
sahilmgandhi 18:6a4db94011d3 5719
sahilmgandhi 18:6a4db94011d3 5720 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 5721 -- USBDCD Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 5722 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 5723
sahilmgandhi 18:6a4db94011d3 5724 /**
sahilmgandhi 18:6a4db94011d3 5725 * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 5726 * @{
sahilmgandhi 18:6a4db94011d3 5727 */
sahilmgandhi 18:6a4db94011d3 5728
sahilmgandhi 18:6a4db94011d3 5729 /** USBDCD - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 5730 typedef struct {
sahilmgandhi 18:6a4db94011d3 5731 __IO uint32_t CONTROL; /**< Control Register, offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 5732 __IO uint32_t CLOCK; /**< Clock Register, offset: 0x4 */
sahilmgandhi 18:6a4db94011d3 5733 __I uint32_t STATUS; /**< Status Register, offset: 0x8 */
sahilmgandhi 18:6a4db94011d3 5734 uint8_t RESERVED_0[4];
sahilmgandhi 18:6a4db94011d3 5735 __IO uint32_t TIMER0; /**< TIMER0 Register, offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 5736 __IO uint32_t TIMER1; /**< , offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 5737 __IO uint32_t TIMER2; /**< , offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 5738 } USBDCD_Type;
sahilmgandhi 18:6a4db94011d3 5739
sahilmgandhi 18:6a4db94011d3 5740 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 5741 -- USBDCD Register Masks
sahilmgandhi 18:6a4db94011d3 5742 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 5743
sahilmgandhi 18:6a4db94011d3 5744 /**
sahilmgandhi 18:6a4db94011d3 5745 * @addtogroup USBDCD_Register_Masks USBDCD Register Masks
sahilmgandhi 18:6a4db94011d3 5746 * @{
sahilmgandhi 18:6a4db94011d3 5747 */
sahilmgandhi 18:6a4db94011d3 5748
sahilmgandhi 18:6a4db94011d3 5749 /* CONTROL Bit Fields */
sahilmgandhi 18:6a4db94011d3 5750 #define USBDCD_CONTROL_IACK_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 5751 #define USBDCD_CONTROL_IACK_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5752 #define USBDCD_CONTROL_IF_MASK 0x100u
sahilmgandhi 18:6a4db94011d3 5753 #define USBDCD_CONTROL_IF_SHIFT 8
sahilmgandhi 18:6a4db94011d3 5754 #define USBDCD_CONTROL_IE_MASK 0x10000u
sahilmgandhi 18:6a4db94011d3 5755 #define USBDCD_CONTROL_IE_SHIFT 16
sahilmgandhi 18:6a4db94011d3 5756 #define USBDCD_CONTROL_START_MASK 0x1000000u
sahilmgandhi 18:6a4db94011d3 5757 #define USBDCD_CONTROL_START_SHIFT 24
sahilmgandhi 18:6a4db94011d3 5758 #define USBDCD_CONTROL_SR_MASK 0x2000000u
sahilmgandhi 18:6a4db94011d3 5759 #define USBDCD_CONTROL_SR_SHIFT 25
sahilmgandhi 18:6a4db94011d3 5760 /* CLOCK Bit Fields */
sahilmgandhi 18:6a4db94011d3 5761 #define USBDCD_CLOCK_CLOCK_UNIT_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 5762 #define USBDCD_CLOCK_CLOCK_UNIT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5763 #define USBDCD_CLOCK_CLOCK_SPEED_MASK 0xFFCu
sahilmgandhi 18:6a4db94011d3 5764 #define USBDCD_CLOCK_CLOCK_SPEED_SHIFT 2
sahilmgandhi 18:6a4db94011d3 5765 #define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_CLOCK_CLOCK_SPEED_SHIFT))&USBDCD_CLOCK_CLOCK_SPEED_MASK)
sahilmgandhi 18:6a4db94011d3 5766 /* STATUS Bit Fields */
sahilmgandhi 18:6a4db94011d3 5767 #define USBDCD_STATUS_SEQ_RES_MASK 0x30000u
sahilmgandhi 18:6a4db94011d3 5768 #define USBDCD_STATUS_SEQ_RES_SHIFT 16
sahilmgandhi 18:6a4db94011d3 5769 #define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_RES_SHIFT))&USBDCD_STATUS_SEQ_RES_MASK)
sahilmgandhi 18:6a4db94011d3 5770 #define USBDCD_STATUS_SEQ_STAT_MASK 0xC0000u
sahilmgandhi 18:6a4db94011d3 5771 #define USBDCD_STATUS_SEQ_STAT_SHIFT 18
sahilmgandhi 18:6a4db94011d3 5772 #define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_STAT_SHIFT))&USBDCD_STATUS_SEQ_STAT_MASK)
sahilmgandhi 18:6a4db94011d3 5773 #define USBDCD_STATUS_ERR_MASK 0x100000u
sahilmgandhi 18:6a4db94011d3 5774 #define USBDCD_STATUS_ERR_SHIFT 20
sahilmgandhi 18:6a4db94011d3 5775 #define USBDCD_STATUS_TO_MASK 0x200000u
sahilmgandhi 18:6a4db94011d3 5776 #define USBDCD_STATUS_TO_SHIFT 21
sahilmgandhi 18:6a4db94011d3 5777 #define USBDCD_STATUS_ACTIVE_MASK 0x400000u
sahilmgandhi 18:6a4db94011d3 5778 #define USBDCD_STATUS_ACTIVE_SHIFT 22
sahilmgandhi 18:6a4db94011d3 5779 /* TIMER0 Bit Fields */
sahilmgandhi 18:6a4db94011d3 5780 #define USBDCD_TIMER0_TUNITCON_MASK 0xFFFu
sahilmgandhi 18:6a4db94011d3 5781 #define USBDCD_TIMER0_TUNITCON_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5782 #define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TUNITCON_SHIFT))&USBDCD_TIMER0_TUNITCON_MASK)
sahilmgandhi 18:6a4db94011d3 5783 #define USBDCD_TIMER0_TSEQ_INIT_MASK 0x3FF0000u
sahilmgandhi 18:6a4db94011d3 5784 #define USBDCD_TIMER0_TSEQ_INIT_SHIFT 16
sahilmgandhi 18:6a4db94011d3 5785 #define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TSEQ_INIT_SHIFT))&USBDCD_TIMER0_TSEQ_INIT_MASK)
sahilmgandhi 18:6a4db94011d3 5786 /* TIMER1 Bit Fields */
sahilmgandhi 18:6a4db94011d3 5787 #define USBDCD_TIMER1_TVDPSRC_ON_MASK 0x3FFu
sahilmgandhi 18:6a4db94011d3 5788 #define USBDCD_TIMER1_TVDPSRC_ON_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5789 #define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TVDPSRC_ON_SHIFT))&USBDCD_TIMER1_TVDPSRC_ON_MASK)
sahilmgandhi 18:6a4db94011d3 5790 #define USBDCD_TIMER1_TDCD_DBNC_MASK 0x3FF0000u
sahilmgandhi 18:6a4db94011d3 5791 #define USBDCD_TIMER1_TDCD_DBNC_SHIFT 16
sahilmgandhi 18:6a4db94011d3 5792 #define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TDCD_DBNC_SHIFT))&USBDCD_TIMER1_TDCD_DBNC_MASK)
sahilmgandhi 18:6a4db94011d3 5793 /* TIMER2 Bit Fields */
sahilmgandhi 18:6a4db94011d3 5794 #define USBDCD_TIMER2_CHECK_DM_MASK 0xFu
sahilmgandhi 18:6a4db94011d3 5795 #define USBDCD_TIMER2_CHECK_DM_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5796 #define USBDCD_TIMER2_CHECK_DM(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_CHECK_DM_SHIFT))&USBDCD_TIMER2_CHECK_DM_MASK)
sahilmgandhi 18:6a4db94011d3 5797 #define USBDCD_TIMER2_TVDPSRC_CON_MASK 0x3FF0000u
sahilmgandhi 18:6a4db94011d3 5798 #define USBDCD_TIMER2_TVDPSRC_CON_SHIFT 16
sahilmgandhi 18:6a4db94011d3 5799 #define USBDCD_TIMER2_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_TVDPSRC_CON_SHIFT))&USBDCD_TIMER2_TVDPSRC_CON_MASK)
sahilmgandhi 18:6a4db94011d3 5800
sahilmgandhi 18:6a4db94011d3 5801 /**
sahilmgandhi 18:6a4db94011d3 5802 * @}
sahilmgandhi 18:6a4db94011d3 5803 */ /* end of group USBDCD_Register_Masks */
sahilmgandhi 18:6a4db94011d3 5804
sahilmgandhi 18:6a4db94011d3 5805
sahilmgandhi 18:6a4db94011d3 5806 /* USBDCD - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 5807 /** Peripheral USBDCD base address */
sahilmgandhi 18:6a4db94011d3 5808 #define USBDCD_BASE (0x40035000u)
sahilmgandhi 18:6a4db94011d3 5809 /** Peripheral USBDCD base pointer */
sahilmgandhi 18:6a4db94011d3 5810 #define USBDCD ((USBDCD_Type *)USBDCD_BASE)
sahilmgandhi 18:6a4db94011d3 5811
sahilmgandhi 18:6a4db94011d3 5812 /**
sahilmgandhi 18:6a4db94011d3 5813 * @}
sahilmgandhi 18:6a4db94011d3 5814 */ /* end of group USBDCD_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 5815
sahilmgandhi 18:6a4db94011d3 5816
sahilmgandhi 18:6a4db94011d3 5817 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 5818 -- VREF Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 5819 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 5820
sahilmgandhi 18:6a4db94011d3 5821 /**
sahilmgandhi 18:6a4db94011d3 5822 * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 5823 * @{
sahilmgandhi 18:6a4db94011d3 5824 */
sahilmgandhi 18:6a4db94011d3 5825
sahilmgandhi 18:6a4db94011d3 5826 /** VREF - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 5827 typedef struct {
sahilmgandhi 18:6a4db94011d3 5828 __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 5829 __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
sahilmgandhi 18:6a4db94011d3 5830 } VREF_Type;
sahilmgandhi 18:6a4db94011d3 5831
sahilmgandhi 18:6a4db94011d3 5832 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 5833 -- VREF Register Masks
sahilmgandhi 18:6a4db94011d3 5834 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 5835
sahilmgandhi 18:6a4db94011d3 5836 /**
sahilmgandhi 18:6a4db94011d3 5837 * @addtogroup VREF_Register_Masks VREF Register Masks
sahilmgandhi 18:6a4db94011d3 5838 * @{
sahilmgandhi 18:6a4db94011d3 5839 */
sahilmgandhi 18:6a4db94011d3 5840
sahilmgandhi 18:6a4db94011d3 5841 /* TRM Bit Fields */
sahilmgandhi 18:6a4db94011d3 5842 #define VREF_TRM_TRIM_MASK 0x3Fu
sahilmgandhi 18:6a4db94011d3 5843 #define VREF_TRM_TRIM_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5844 #define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK)
sahilmgandhi 18:6a4db94011d3 5845 #define VREF_TRM_CHOPEN_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 5846 #define VREF_TRM_CHOPEN_SHIFT 6
sahilmgandhi 18:6a4db94011d3 5847 /* SC Bit Fields */
sahilmgandhi 18:6a4db94011d3 5848 #define VREF_SC_MODE_LV_MASK 0x3u
sahilmgandhi 18:6a4db94011d3 5849 #define VREF_SC_MODE_LV_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5850 #define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK)
sahilmgandhi 18:6a4db94011d3 5851 #define VREF_SC_VREFST_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 5852 #define VREF_SC_VREFST_SHIFT 2
sahilmgandhi 18:6a4db94011d3 5853 #define VREF_SC_REGEN_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 5854 #define VREF_SC_REGEN_SHIFT 6
sahilmgandhi 18:6a4db94011d3 5855 #define VREF_SC_VREFEN_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 5856 #define VREF_SC_VREFEN_SHIFT 7
sahilmgandhi 18:6a4db94011d3 5857
sahilmgandhi 18:6a4db94011d3 5858 /**
sahilmgandhi 18:6a4db94011d3 5859 * @}
sahilmgandhi 18:6a4db94011d3 5860 */ /* end of group VREF_Register_Masks */
sahilmgandhi 18:6a4db94011d3 5861
sahilmgandhi 18:6a4db94011d3 5862
sahilmgandhi 18:6a4db94011d3 5863 /* VREF - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 5864 /** Peripheral VREF base address */
sahilmgandhi 18:6a4db94011d3 5865 #define VREF_BASE (0x40074000u)
sahilmgandhi 18:6a4db94011d3 5866 /** Peripheral VREF base pointer */
sahilmgandhi 18:6a4db94011d3 5867 #define VREF ((VREF_Type *)VREF_BASE)
sahilmgandhi 18:6a4db94011d3 5868
sahilmgandhi 18:6a4db94011d3 5869 /**
sahilmgandhi 18:6a4db94011d3 5870 * @}
sahilmgandhi 18:6a4db94011d3 5871 */ /* end of group VREF_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 5872
sahilmgandhi 18:6a4db94011d3 5873
sahilmgandhi 18:6a4db94011d3 5874 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 5875 -- WDOG Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 5876 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 5877
sahilmgandhi 18:6a4db94011d3 5878 /**
sahilmgandhi 18:6a4db94011d3 5879 * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
sahilmgandhi 18:6a4db94011d3 5880 * @{
sahilmgandhi 18:6a4db94011d3 5881 */
sahilmgandhi 18:6a4db94011d3 5882
sahilmgandhi 18:6a4db94011d3 5883 /** WDOG - Register Layout Typedef */
sahilmgandhi 18:6a4db94011d3 5884 typedef struct {
sahilmgandhi 18:6a4db94011d3 5885 __IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */
sahilmgandhi 18:6a4db94011d3 5886 __IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */
sahilmgandhi 18:6a4db94011d3 5887 __IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */
sahilmgandhi 18:6a4db94011d3 5888 __IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */
sahilmgandhi 18:6a4db94011d3 5889 __IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */
sahilmgandhi 18:6a4db94011d3 5890 __IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */
sahilmgandhi 18:6a4db94011d3 5891 __IO uint16_t REFRESH; /**< Watchdog Refresh Register, offset: 0xC */
sahilmgandhi 18:6a4db94011d3 5892 __IO uint16_t UNLOCK; /**< Watchdog Unlock Register, offset: 0xE */
sahilmgandhi 18:6a4db94011d3 5893 __IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 5894 __IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */
sahilmgandhi 18:6a4db94011d3 5895 __IO uint16_t RSTCNT; /**< Watchdog Reset Count Register, offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 5896 __IO uint16_t PRESC; /**< Watchdog Prescaler Register, offset: 0x16 */
sahilmgandhi 18:6a4db94011d3 5897 } WDOG_Type;
sahilmgandhi 18:6a4db94011d3 5898
sahilmgandhi 18:6a4db94011d3 5899 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 5900 -- WDOG Register Masks
sahilmgandhi 18:6a4db94011d3 5901 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 5902
sahilmgandhi 18:6a4db94011d3 5903 /**
sahilmgandhi 18:6a4db94011d3 5904 * @addtogroup WDOG_Register_Masks WDOG Register Masks
sahilmgandhi 18:6a4db94011d3 5905 * @{
sahilmgandhi 18:6a4db94011d3 5906 */
sahilmgandhi 18:6a4db94011d3 5907
sahilmgandhi 18:6a4db94011d3 5908 /* STCTRLH Bit Fields */
sahilmgandhi 18:6a4db94011d3 5909 #define WDOG_STCTRLH_WDOGEN_MASK 0x1u
sahilmgandhi 18:6a4db94011d3 5910 #define WDOG_STCTRLH_WDOGEN_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5911 #define WDOG_STCTRLH_CLKSRC_MASK 0x2u
sahilmgandhi 18:6a4db94011d3 5912 #define WDOG_STCTRLH_CLKSRC_SHIFT 1
sahilmgandhi 18:6a4db94011d3 5913 #define WDOG_STCTRLH_IRQRSTEN_MASK 0x4u
sahilmgandhi 18:6a4db94011d3 5914 #define WDOG_STCTRLH_IRQRSTEN_SHIFT 2
sahilmgandhi 18:6a4db94011d3 5915 #define WDOG_STCTRLH_WINEN_MASK 0x8u
sahilmgandhi 18:6a4db94011d3 5916 #define WDOG_STCTRLH_WINEN_SHIFT 3
sahilmgandhi 18:6a4db94011d3 5917 #define WDOG_STCTRLH_ALLOWUPDATE_MASK 0x10u
sahilmgandhi 18:6a4db94011d3 5918 #define WDOG_STCTRLH_ALLOWUPDATE_SHIFT 4
sahilmgandhi 18:6a4db94011d3 5919 #define WDOG_STCTRLH_DBGEN_MASK 0x20u
sahilmgandhi 18:6a4db94011d3 5920 #define WDOG_STCTRLH_DBGEN_SHIFT 5
sahilmgandhi 18:6a4db94011d3 5921 #define WDOG_STCTRLH_STOPEN_MASK 0x40u
sahilmgandhi 18:6a4db94011d3 5922 #define WDOG_STCTRLH_STOPEN_SHIFT 6
sahilmgandhi 18:6a4db94011d3 5923 #define WDOG_STCTRLH_WAITEN_MASK 0x80u
sahilmgandhi 18:6a4db94011d3 5924 #define WDOG_STCTRLH_WAITEN_SHIFT 7
sahilmgandhi 18:6a4db94011d3 5925 #define WDOG_STCTRLH_TESTWDOG_MASK 0x400u
sahilmgandhi 18:6a4db94011d3 5926 #define WDOG_STCTRLH_TESTWDOG_SHIFT 10
sahilmgandhi 18:6a4db94011d3 5927 #define WDOG_STCTRLH_TESTSEL_MASK 0x800u
sahilmgandhi 18:6a4db94011d3 5928 #define WDOG_STCTRLH_TESTSEL_SHIFT 11
sahilmgandhi 18:6a4db94011d3 5929 #define WDOG_STCTRLH_BYTESEL_MASK 0x3000u
sahilmgandhi 18:6a4db94011d3 5930 #define WDOG_STCTRLH_BYTESEL_SHIFT 12
sahilmgandhi 18:6a4db94011d3 5931 #define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_BYTESEL_SHIFT))&WDOG_STCTRLH_BYTESEL_MASK)
sahilmgandhi 18:6a4db94011d3 5932 #define WDOG_STCTRLH_DISTESTWDOG_MASK 0x4000u
sahilmgandhi 18:6a4db94011d3 5933 #define WDOG_STCTRLH_DISTESTWDOG_SHIFT 14
sahilmgandhi 18:6a4db94011d3 5934 /* STCTRLL Bit Fields */
sahilmgandhi 18:6a4db94011d3 5935 #define WDOG_STCTRLL_INTFLG_MASK 0x8000u
sahilmgandhi 18:6a4db94011d3 5936 #define WDOG_STCTRLL_INTFLG_SHIFT 15
sahilmgandhi 18:6a4db94011d3 5937 /* TOVALH Bit Fields */
sahilmgandhi 18:6a4db94011d3 5938 #define WDOG_TOVALH_TOVALHIGH_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 5939 #define WDOG_TOVALH_TOVALHIGH_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5940 #define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALH_TOVALHIGH_SHIFT))&WDOG_TOVALH_TOVALHIGH_MASK)
sahilmgandhi 18:6a4db94011d3 5941 /* TOVALL Bit Fields */
sahilmgandhi 18:6a4db94011d3 5942 #define WDOG_TOVALL_TOVALLOW_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 5943 #define WDOG_TOVALL_TOVALLOW_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5944 #define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALL_TOVALLOW_SHIFT))&WDOG_TOVALL_TOVALLOW_MASK)
sahilmgandhi 18:6a4db94011d3 5945 /* WINH Bit Fields */
sahilmgandhi 18:6a4db94011d3 5946 #define WDOG_WINH_WINHIGH_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 5947 #define WDOG_WINH_WINHIGH_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5948 #define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINH_WINHIGH_SHIFT))&WDOG_WINH_WINHIGH_MASK)
sahilmgandhi 18:6a4db94011d3 5949 /* WINL Bit Fields */
sahilmgandhi 18:6a4db94011d3 5950 #define WDOG_WINL_WINLOW_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 5951 #define WDOG_WINL_WINLOW_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5952 #define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINL_WINLOW_SHIFT))&WDOG_WINL_WINLOW_MASK)
sahilmgandhi 18:6a4db94011d3 5953 /* REFRESH Bit Fields */
sahilmgandhi 18:6a4db94011d3 5954 #define WDOG_REFRESH_WDOGREFRESH_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 5955 #define WDOG_REFRESH_WDOGREFRESH_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5956 #define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_REFRESH_WDOGREFRESH_SHIFT))&WDOG_REFRESH_WDOGREFRESH_MASK)
sahilmgandhi 18:6a4db94011d3 5957 /* UNLOCK Bit Fields */
sahilmgandhi 18:6a4db94011d3 5958 #define WDOG_UNLOCK_WDOGUNLOCK_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 5959 #define WDOG_UNLOCK_WDOGUNLOCK_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5960 #define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x))<<WDOG_UNLOCK_WDOGUNLOCK_SHIFT))&WDOG_UNLOCK_WDOGUNLOCK_MASK)
sahilmgandhi 18:6a4db94011d3 5961 /* TMROUTH Bit Fields */
sahilmgandhi 18:6a4db94011d3 5962 #define WDOG_TMROUTH_TIMEROUTHIGH_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 5963 #define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5964 #define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTH_TIMEROUTHIGH_SHIFT))&WDOG_TMROUTH_TIMEROUTHIGH_MASK)
sahilmgandhi 18:6a4db94011d3 5965 /* TMROUTL Bit Fields */
sahilmgandhi 18:6a4db94011d3 5966 #define WDOG_TMROUTL_TIMEROUTLOW_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 5967 #define WDOG_TMROUTL_TIMEROUTLOW_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5968 #define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTL_TIMEROUTLOW_SHIFT))&WDOG_TMROUTL_TIMEROUTLOW_MASK)
sahilmgandhi 18:6a4db94011d3 5969 /* RSTCNT Bit Fields */
sahilmgandhi 18:6a4db94011d3 5970 #define WDOG_RSTCNT_RSTCNT_MASK 0xFFFFu
sahilmgandhi 18:6a4db94011d3 5971 #define WDOG_RSTCNT_RSTCNT_SHIFT 0
sahilmgandhi 18:6a4db94011d3 5972 #define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x))<<WDOG_RSTCNT_RSTCNT_SHIFT))&WDOG_RSTCNT_RSTCNT_MASK)
sahilmgandhi 18:6a4db94011d3 5973 /* PRESC Bit Fields */
sahilmgandhi 18:6a4db94011d3 5974 #define WDOG_PRESC_PRESCVAL_MASK 0x700u
sahilmgandhi 18:6a4db94011d3 5975 #define WDOG_PRESC_PRESCVAL_SHIFT 8
sahilmgandhi 18:6a4db94011d3 5976 #define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_PRESC_PRESCVAL_SHIFT))&WDOG_PRESC_PRESCVAL_MASK)
sahilmgandhi 18:6a4db94011d3 5977
sahilmgandhi 18:6a4db94011d3 5978 /**
sahilmgandhi 18:6a4db94011d3 5979 * @}
sahilmgandhi 18:6a4db94011d3 5980 */ /* end of group WDOG_Register_Masks */
sahilmgandhi 18:6a4db94011d3 5981
sahilmgandhi 18:6a4db94011d3 5982
sahilmgandhi 18:6a4db94011d3 5983 /* WDOG - Peripheral instance base addresses */
sahilmgandhi 18:6a4db94011d3 5984 /** Peripheral WDOG base address */
sahilmgandhi 18:6a4db94011d3 5985 #define WDOG_BASE (0x40052000u)
sahilmgandhi 18:6a4db94011d3 5986 /** Peripheral WDOG base pointer */
sahilmgandhi 18:6a4db94011d3 5987 #define WDOG ((WDOG_Type *)WDOG_BASE)
sahilmgandhi 18:6a4db94011d3 5988
sahilmgandhi 18:6a4db94011d3 5989 /**
sahilmgandhi 18:6a4db94011d3 5990 * @}
sahilmgandhi 18:6a4db94011d3 5991 */ /* end of group WDOG_Peripheral_Access_Layer */
sahilmgandhi 18:6a4db94011d3 5992
sahilmgandhi 18:6a4db94011d3 5993
sahilmgandhi 18:6a4db94011d3 5994 /*
sahilmgandhi 18:6a4db94011d3 5995 ** End of section using anonymous unions
sahilmgandhi 18:6a4db94011d3 5996 */
sahilmgandhi 18:6a4db94011d3 5997
sahilmgandhi 18:6a4db94011d3 5998 #if defined(__ARMCC_VERSION)
sahilmgandhi 18:6a4db94011d3 5999 #pragma pop
sahilmgandhi 18:6a4db94011d3 6000 #elif defined(__CWCC__)
sahilmgandhi 18:6a4db94011d3 6001 #pragma pop
sahilmgandhi 18:6a4db94011d3 6002 #elif defined(__GNUC__)
sahilmgandhi 18:6a4db94011d3 6003 /* leave anonymous unions enabled */
sahilmgandhi 18:6a4db94011d3 6004 #elif defined(__IAR_SYSTEMS_ICC__)
sahilmgandhi 18:6a4db94011d3 6005 #pragma language=default
sahilmgandhi 18:6a4db94011d3 6006 #else
sahilmgandhi 18:6a4db94011d3 6007 #error Not supported compiler type
sahilmgandhi 18:6a4db94011d3 6008 #endif
sahilmgandhi 18:6a4db94011d3 6009
sahilmgandhi 18:6a4db94011d3 6010 /**
sahilmgandhi 18:6a4db94011d3 6011 * @}
sahilmgandhi 18:6a4db94011d3 6012 */ /* end of group Peripheral_access_layer */
sahilmgandhi 18:6a4db94011d3 6013
sahilmgandhi 18:6a4db94011d3 6014
sahilmgandhi 18:6a4db94011d3 6015 /* ----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 6016 -- Backward Compatibility
sahilmgandhi 18:6a4db94011d3 6017 ---------------------------------------------------------------------------- */
sahilmgandhi 18:6a4db94011d3 6018
sahilmgandhi 18:6a4db94011d3 6019 /**
sahilmgandhi 18:6a4db94011d3 6020 * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
sahilmgandhi 18:6a4db94011d3 6021 * @{
sahilmgandhi 18:6a4db94011d3 6022 */
sahilmgandhi 18:6a4db94011d3 6023
sahilmgandhi 18:6a4db94011d3 6024 /* No backward compatibility issues. */
sahilmgandhi 18:6a4db94011d3 6025
sahilmgandhi 18:6a4db94011d3 6026 /**
sahilmgandhi 18:6a4db94011d3 6027 * @}
sahilmgandhi 18:6a4db94011d3 6028 */ /* end of group Backward_Compatibility_Symbols */
sahilmgandhi 18:6a4db94011d3 6029
sahilmgandhi 18:6a4db94011d3 6030
sahilmgandhi 18:6a4db94011d3 6031 #endif /* #if !defined(MK20D5_H_) */
sahilmgandhi 18:6a4db94011d3 6032
sahilmgandhi 18:6a4db94011d3 6033 /* MK20D5.h, eof. */
sahilmgandhi 18:6a4db94011d3 6034