MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/PeripheralNames.h@34:69342782fb68, 2017-05-26 (annotated)

Committer:
sahilmgandhi
Date:
Fri May 26 17:21:04 2017 +0000
Revision:
34:69342782fb68
Parent:
18:6a4db94011d3 
Added small reverse turns before the break so that we can stop faster.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2006-2015 ARM Limited
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 */
sahilmgandhi 18:6a4db94011d3 16 #ifndef MBED_PERIPHERALNAMES_H
sahilmgandhi 18:6a4db94011d3 17 #define MBED_PERIPHERALNAMES_H
sahilmgandhi 18:6a4db94011d3 18
sahilmgandhi 18:6a4db94011d3 19 #include "cmsis.h"
sahilmgandhi 18:6a4db94011d3 20
sahilmgandhi 18:6a4db94011d3 21 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 22 extern "C" {
sahilmgandhi 18:6a4db94011d3 23 #endif
sahilmgandhi 18:6a4db94011d3 24
sahilmgandhi 18:6a4db94011d3 25 typedef enum {
sahilmgandhi 18:6a4db94011d3 26 UART_0 = (int)UART0_BASE,
sahilmgandhi 18:6a4db94011d3 27 UART_1 = (int)UART1_BASE,
sahilmgandhi 18:6a4db94011d3 28 UART_2 = (int)UART2_BASE
sahilmgandhi 18:6a4db94011d3 29 } UARTName;
sahilmgandhi 18:6a4db94011d3 30 #define STDIO_UART_TX USBTX
sahilmgandhi 18:6a4db94011d3 31 #define STDIO_UART_RX USBRX
sahilmgandhi 18:6a4db94011d3 32 #define STDIO_UART UART_0
sahilmgandhi 18:6a4db94011d3 33
sahilmgandhi 18:6a4db94011d3 34 typedef enum {
sahilmgandhi 18:6a4db94011d3 35 I2C_0 = (int)I2C0_BASE,
sahilmgandhi 18:6a4db94011d3 36 I2C_1 = (int)I2C1_BASE,
sahilmgandhi 18:6a4db94011d3 37 } I2CName;
sahilmgandhi 18:6a4db94011d3 38
sahilmgandhi 18:6a4db94011d3 39 #define TPM_SHIFT 8
sahilmgandhi 18:6a4db94011d3 40 typedef enum {
sahilmgandhi 18:6a4db94011d3 41 PWM_1 = (0 << TPM_SHIFT) | (0), // FTM0 CH0
sahilmgandhi 18:6a4db94011d3 42 PWM_2 = (0 << TPM_SHIFT) | (1), // FTM0 CH1
sahilmgandhi 18:6a4db94011d3 43 PWM_3 = (0 << TPM_SHIFT) | (2), // FTM0 CH2
sahilmgandhi 18:6a4db94011d3 44 PWM_4 = (0 << TPM_SHIFT) | (3), // FTM0 CH3
sahilmgandhi 18:6a4db94011d3 45 PWM_5 = (0 << TPM_SHIFT) | (4), // FTM0 CH4
sahilmgandhi 18:6a4db94011d3 46 PWM_6 = (0 << TPM_SHIFT) | (5), // FTM0 CH5
sahilmgandhi 18:6a4db94011d3 47 PWM_7 = (0 << TPM_SHIFT) | (6), // FTM0 CH6
sahilmgandhi 18:6a4db94011d3 48 PWM_8 = (0 << TPM_SHIFT) | (7), // FTM0 CH7
sahilmgandhi 18:6a4db94011d3 49 PWM_9 = (1 << TPM_SHIFT) | (0), // FTM1 CH0
sahilmgandhi 18:6a4db94011d3 50 PWM_10 = (1 << TPM_SHIFT) | (1), // FTM1 CH1
sahilmgandhi 18:6a4db94011d3 51 } PWMName;
sahilmgandhi 18:6a4db94011d3 52
sahilmgandhi 18:6a4db94011d3 53 typedef enum {
sahilmgandhi 18:6a4db94011d3 54 ADC0_SE4b = 4,
sahilmgandhi 18:6a4db94011d3 55 ADC0_SE5b = 5,
sahilmgandhi 18:6a4db94011d3 56 ADC0_SE6b = 6,
sahilmgandhi 18:6a4db94011d3 57 ADC0_SE7b = 7,
sahilmgandhi 18:6a4db94011d3 58 ADC0_SE8 = 8,
sahilmgandhi 18:6a4db94011d3 59 ADC0_SE9 = 9,
sahilmgandhi 18:6a4db94011d3 60 ADC0_SE12 = 12,
sahilmgandhi 18:6a4db94011d3 61 ADC0_SE13 = 13,
sahilmgandhi 18:6a4db94011d3 62 ADC0_SE14 = 14,
sahilmgandhi 18:6a4db94011d3 63 ADC0_SE15 = 15,
sahilmgandhi 18:6a4db94011d3 64 ADC1_SE4b = 16,
sahilmgandhi 18:6a4db94011d3 65 ADC1_SE5b = 17,
sahilmgandhi 18:6a4db94011d3 66 ADC1_SE6b = 18,
sahilmgandhi 18:6a4db94011d3 67 ADC1_SE7b = 19,
sahilmgandhi 18:6a4db94011d3 68 } ADCName;
sahilmgandhi 18:6a4db94011d3 69
sahilmgandhi 18:6a4db94011d3 70 typedef enum {
sahilmgandhi 18:6a4db94011d3 71 DAC_0 = 0
sahilmgandhi 18:6a4db94011d3 72 } DACName;
sahilmgandhi 18:6a4db94011d3 73
sahilmgandhi 18:6a4db94011d3 74 typedef enum {
sahilmgandhi 18:6a4db94011d3 75 SPI_0 = (int)SPI0_BASE,
sahilmgandhi 18:6a4db94011d3 76 SPI_1 = (int)SPI0_BASE,
sahilmgandhi 18:6a4db94011d3 77 SPI_2 = (int)SPI0_BASE,
sahilmgandhi 18:6a4db94011d3 78 SPI_3 = (int)SPI0_BASE,
sahilmgandhi 18:6a4db94011d3 79 SPI_4 = (int)SPI0_BASE,
sahilmgandhi 18:6a4db94011d3 80 } SPIName;
sahilmgandhi 18:6a4db94011d3 81
sahilmgandhi 18:6a4db94011d3 82 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 83 }
sahilmgandhi 18:6a4db94011d3 84 #endif
sahilmgandhi 18:6a4db94011d3 85
sahilmgandhi 18:6a4db94011d3 86 #endif