MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/cmsis/core_ca9.h@23:690b0ca34ee9, 2017-05-20 (annotated)

Committer:
christine222
Date:
Sat May 20 09:11:08 2017 +0000
Revision:
23:690b0ca34ee9
Parent:
18:6a4db94011d3 
ncellencoderirwall function working for all walls (both, 1 side, no sides) need to tune detecting the sides though, there's a very precise threshold that we need to find

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 2 * @file core_ca9.h
sahilmgandhi 18:6a4db94011d3 3 * @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File
sahilmgandhi 18:6a4db94011d3 4 * @version
sahilmgandhi 18:6a4db94011d3 5 * @date 25 March 2013
sahilmgandhi 18:6a4db94011d3 6 *
sahilmgandhi 18:6a4db94011d3 7 * @note
sahilmgandhi 18:6a4db94011d3 8 *
sahilmgandhi 18:6a4db94011d3 9 ******************************************************************************/
sahilmgandhi 18:6a4db94011d3 10 /* Copyright (c) 2009 - 2012 ARM LIMITED
sahilmgandhi 18:6a4db94011d3 11
sahilmgandhi 18:6a4db94011d3 12 All rights reserved.
sahilmgandhi 18:6a4db94011d3 13 Redistribution and use in source and binary forms, with or without
sahilmgandhi 18:6a4db94011d3 14 modification, are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 15 - Redistributions of source code must retain the above copyright
sahilmgandhi 18:6a4db94011d3 16 notice, this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 17 - Redistributions in binary form must reproduce the above copyright
sahilmgandhi 18:6a4db94011d3 18 notice, this list of conditions and the following disclaimer in the
sahilmgandhi 18:6a4db94011d3 19 documentation and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 20 - Neither the name of ARM nor the names of its contributors may be used
sahilmgandhi 18:6a4db94011d3 21 to endorse or promote products derived from this software without
sahilmgandhi 18:6a4db94011d3 22 specific prior written permission.
sahilmgandhi 18:6a4db94011d3 23 *
sahilmgandhi 18:6a4db94011d3 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
sahilmgandhi 18:6a4db94011d3 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
sahilmgandhi 18:6a4db94011d3 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
sahilmgandhi 18:6a4db94011d3 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
sahilmgandhi 18:6a4db94011d3 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
sahilmgandhi 18:6a4db94011d3 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
sahilmgandhi 18:6a4db94011d3 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
sahilmgandhi 18:6a4db94011d3 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
sahilmgandhi 18:6a4db94011d3 34 POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 35 ---------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 36
sahilmgandhi 18:6a4db94011d3 37
sahilmgandhi 18:6a4db94011d3 38 #if defined ( __ICCARM__ )
sahilmgandhi 18:6a4db94011d3 39 #pragma system_include /* treat file as system include file for MISRA check */
sahilmgandhi 18:6a4db94011d3 40 #endif
sahilmgandhi 18:6a4db94011d3 41
sahilmgandhi 18:6a4db94011d3 42 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 43 extern "C" {
sahilmgandhi 18:6a4db94011d3 44 #endif
sahilmgandhi 18:6a4db94011d3 45
sahilmgandhi 18:6a4db94011d3 46 #ifndef __CORE_CA9_H_GENERIC
sahilmgandhi 18:6a4db94011d3 47 #define __CORE_CA9_H_GENERIC
sahilmgandhi 18:6a4db94011d3 48
sahilmgandhi 18:6a4db94011d3 49
sahilmgandhi 18:6a4db94011d3 50 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
sahilmgandhi 18:6a4db94011d3 51 CMSIS violates the following MISRA-C:2004 rules:
sahilmgandhi 18:6a4db94011d3 52
sahilmgandhi 18:6a4db94011d3 53 \li Required Rule 8.5, object/function definition in header file.<br>
sahilmgandhi 18:6a4db94011d3 54 Function definitions in header files are used to allow 'inlining'.
sahilmgandhi 18:6a4db94011d3 55
sahilmgandhi 18:6a4db94011d3 56 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
sahilmgandhi 18:6a4db94011d3 57 Unions are used for effective representation of core registers.
sahilmgandhi 18:6a4db94011d3 58
sahilmgandhi 18:6a4db94011d3 59 \li Advisory Rule 19.7, Function-like macro defined.<br>
sahilmgandhi 18:6a4db94011d3 60 Function-like macros are used to allow more efficient code.
sahilmgandhi 18:6a4db94011d3 61 */
sahilmgandhi 18:6a4db94011d3 62
sahilmgandhi 18:6a4db94011d3 63
sahilmgandhi 18:6a4db94011d3 64 /*******************************************************************************
sahilmgandhi 18:6a4db94011d3 65 * CMSIS definitions
sahilmgandhi 18:6a4db94011d3 66 ******************************************************************************/
sahilmgandhi 18:6a4db94011d3 67 /** \ingroup Cortex_A9
sahilmgandhi 18:6a4db94011d3 68 @{
sahilmgandhi 18:6a4db94011d3 69 */
sahilmgandhi 18:6a4db94011d3 70
sahilmgandhi 18:6a4db94011d3 71 /* CMSIS CA9 definitions */
sahilmgandhi 18:6a4db94011d3 72 #define __CA9_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
sahilmgandhi 18:6a4db94011d3 73 #define __CA9_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */
sahilmgandhi 18:6a4db94011d3 74 #define __CA9_CMSIS_VERSION ((__CA9_CMSIS_VERSION_MAIN << 16) | \
sahilmgandhi 18:6a4db94011d3 75 __CA9_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
sahilmgandhi 18:6a4db94011d3 76
sahilmgandhi 18:6a4db94011d3 77 #define __CORTEX_A (0x09) /*!< Cortex-A Core */
sahilmgandhi 18:6a4db94011d3 78
sahilmgandhi 18:6a4db94011d3 79
sahilmgandhi 18:6a4db94011d3 80 #if defined ( __CC_ARM )
sahilmgandhi 18:6a4db94011d3 81 #define __ASM __asm /*!< asm keyword for ARM Compiler */
sahilmgandhi 18:6a4db94011d3 82 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
sahilmgandhi 18:6a4db94011d3 83 #define __STATIC_INLINE static __inline
sahilmgandhi 18:6a4db94011d3 84 #define __STATIC_ASM static __asm
sahilmgandhi 18:6a4db94011d3 85
sahilmgandhi 18:6a4db94011d3 86 #elif defined ( __ICCARM__ )
sahilmgandhi 18:6a4db94011d3 87 #define __ASM __asm /*!< asm keyword for IAR Compiler */
sahilmgandhi 18:6a4db94011d3 88 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
sahilmgandhi 18:6a4db94011d3 89 #define __STATIC_INLINE static inline
sahilmgandhi 18:6a4db94011d3 90 #define __STATIC_ASM static __asm
sahilmgandhi 18:6a4db94011d3 91
sahilmgandhi 18:6a4db94011d3 92 #include <stdint.h>
sahilmgandhi 18:6a4db94011d3 93 inline uint32_t __get_PSR(void) {
sahilmgandhi 18:6a4db94011d3 94 __ASM("mrs r0, cpsr");
sahilmgandhi 18:6a4db94011d3 95 }
sahilmgandhi 18:6a4db94011d3 96
sahilmgandhi 18:6a4db94011d3 97 #elif defined ( __TMS470__ )
sahilmgandhi 18:6a4db94011d3 98 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
sahilmgandhi 18:6a4db94011d3 99 #define __STATIC_INLINE static inline
sahilmgandhi 18:6a4db94011d3 100 #define __STATIC_ASM static __asm
sahilmgandhi 18:6a4db94011d3 101
sahilmgandhi 18:6a4db94011d3 102 #elif defined ( __GNUC__ )
sahilmgandhi 18:6a4db94011d3 103 #define __ASM __asm /*!< asm keyword for GNU Compiler */
sahilmgandhi 18:6a4db94011d3 104 #define __INLINE inline /*!< inline keyword for GNU Compiler */
sahilmgandhi 18:6a4db94011d3 105 #define __STATIC_INLINE static inline
sahilmgandhi 18:6a4db94011d3 106 #define __STATIC_ASM static __asm
sahilmgandhi 18:6a4db94011d3 107
sahilmgandhi 18:6a4db94011d3 108 #elif defined ( __TASKING__ )
sahilmgandhi 18:6a4db94011d3 109 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
sahilmgandhi 18:6a4db94011d3 110 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
sahilmgandhi 18:6a4db94011d3 111 #define __STATIC_INLINE static inline
sahilmgandhi 18:6a4db94011d3 112 #define __STATIC_ASM static __asm
sahilmgandhi 18:6a4db94011d3 113
sahilmgandhi 18:6a4db94011d3 114 #endif
sahilmgandhi 18:6a4db94011d3 115
sahilmgandhi 18:6a4db94011d3 116 /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
sahilmgandhi 18:6a4db94011d3 117 */
sahilmgandhi 18:6a4db94011d3 118 #if defined ( __CC_ARM )
sahilmgandhi 18:6a4db94011d3 119 #if defined __TARGET_FPU_VFP
sahilmgandhi 18:6a4db94011d3 120 #if (__FPU_PRESENT == 1)
sahilmgandhi 18:6a4db94011d3 121 #define __FPU_USED 1
sahilmgandhi 18:6a4db94011d3 122 #else
sahilmgandhi 18:6a4db94011d3 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
sahilmgandhi 18:6a4db94011d3 124 #define __FPU_USED 0
sahilmgandhi 18:6a4db94011d3 125 #endif
sahilmgandhi 18:6a4db94011d3 126 #else
sahilmgandhi 18:6a4db94011d3 127 #define __FPU_USED 0
sahilmgandhi 18:6a4db94011d3 128 #endif
sahilmgandhi 18:6a4db94011d3 129
sahilmgandhi 18:6a4db94011d3 130 #elif defined ( __ICCARM__ )
sahilmgandhi 18:6a4db94011d3 131 #if defined __ARMVFP__
sahilmgandhi 18:6a4db94011d3 132 #if (__FPU_PRESENT == 1)
sahilmgandhi 18:6a4db94011d3 133 #define __FPU_USED 1
sahilmgandhi 18:6a4db94011d3 134 #else
sahilmgandhi 18:6a4db94011d3 135 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
sahilmgandhi 18:6a4db94011d3 136 #define __FPU_USED 0
sahilmgandhi 18:6a4db94011d3 137 #endif
sahilmgandhi 18:6a4db94011d3 138 #else
sahilmgandhi 18:6a4db94011d3 139 #define __FPU_USED 0
sahilmgandhi 18:6a4db94011d3 140 #endif
sahilmgandhi 18:6a4db94011d3 141
sahilmgandhi 18:6a4db94011d3 142 #elif defined ( __TMS470__ )
sahilmgandhi 18:6a4db94011d3 143 #if defined __TI_VFP_SUPPORT__
sahilmgandhi 18:6a4db94011d3 144 #if (__FPU_PRESENT == 1)
sahilmgandhi 18:6a4db94011d3 145 #define __FPU_USED 1
sahilmgandhi 18:6a4db94011d3 146 #else
sahilmgandhi 18:6a4db94011d3 147 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
sahilmgandhi 18:6a4db94011d3 148 #define __FPU_USED 0
sahilmgandhi 18:6a4db94011d3 149 #endif
sahilmgandhi 18:6a4db94011d3 150 #else
sahilmgandhi 18:6a4db94011d3 151 #define __FPU_USED 0
sahilmgandhi 18:6a4db94011d3 152 #endif
sahilmgandhi 18:6a4db94011d3 153
sahilmgandhi 18:6a4db94011d3 154 #elif defined ( __GNUC__ )
sahilmgandhi 18:6a4db94011d3 155 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
sahilmgandhi 18:6a4db94011d3 156 #if (__FPU_PRESENT == 1)
sahilmgandhi 18:6a4db94011d3 157 #define __FPU_USED 1
sahilmgandhi 18:6a4db94011d3 158 #else
sahilmgandhi 18:6a4db94011d3 159 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
sahilmgandhi 18:6a4db94011d3 160 #define __FPU_USED 0
sahilmgandhi 18:6a4db94011d3 161 #endif
sahilmgandhi 18:6a4db94011d3 162 #else
sahilmgandhi 18:6a4db94011d3 163 #define __FPU_USED 0
sahilmgandhi 18:6a4db94011d3 164 #endif
sahilmgandhi 18:6a4db94011d3 165
sahilmgandhi 18:6a4db94011d3 166 #elif defined ( __TASKING__ )
sahilmgandhi 18:6a4db94011d3 167 #if defined __FPU_VFP__
sahilmgandhi 18:6a4db94011d3 168 #if (__FPU_PRESENT == 1)
sahilmgandhi 18:6a4db94011d3 169 #define __FPU_USED 1
sahilmgandhi 18:6a4db94011d3 170 #else
sahilmgandhi 18:6a4db94011d3 171 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
sahilmgandhi 18:6a4db94011d3 172 #define __FPU_USED 0
sahilmgandhi 18:6a4db94011d3 173 #endif
sahilmgandhi 18:6a4db94011d3 174 #else
sahilmgandhi 18:6a4db94011d3 175 #define __FPU_USED 0
sahilmgandhi 18:6a4db94011d3 176 #endif
sahilmgandhi 18:6a4db94011d3 177 #endif
sahilmgandhi 18:6a4db94011d3 178
sahilmgandhi 18:6a4db94011d3 179 #include <stdint.h> /*!< standard types definitions */
sahilmgandhi 18:6a4db94011d3 180 #include "core_caInstr.h" /*!< Core Instruction Access */
sahilmgandhi 18:6a4db94011d3 181 #include "core_caFunc.h" /*!< Core Function Access */
sahilmgandhi 18:6a4db94011d3 182 #include "core_cm4_simd.h" /*!< Compiler specific SIMD Intrinsics */
sahilmgandhi 18:6a4db94011d3 183
sahilmgandhi 18:6a4db94011d3 184 #endif /* __CORE_CA9_H_GENERIC */
sahilmgandhi 18:6a4db94011d3 185
sahilmgandhi 18:6a4db94011d3 186 #ifndef __CMSIS_GENERIC
sahilmgandhi 18:6a4db94011d3 187
sahilmgandhi 18:6a4db94011d3 188 #ifndef __CORE_CA9_H_DEPENDANT
sahilmgandhi 18:6a4db94011d3 189 #define __CORE_CA9_H_DEPENDANT
sahilmgandhi 18:6a4db94011d3 190
sahilmgandhi 18:6a4db94011d3 191 /* check device defines and use defaults */
sahilmgandhi 18:6a4db94011d3 192 #if defined __CHECK_DEVICE_DEFINES
sahilmgandhi 18:6a4db94011d3 193 #ifndef __CA9_REV
sahilmgandhi 18:6a4db94011d3 194 #define __CA9_REV 0x0000
sahilmgandhi 18:6a4db94011d3 195 #warning "__CA9_REV not defined in device header file; using default!"
sahilmgandhi 18:6a4db94011d3 196 #endif
sahilmgandhi 18:6a4db94011d3 197
sahilmgandhi 18:6a4db94011d3 198 #ifndef __FPU_PRESENT
sahilmgandhi 18:6a4db94011d3 199 #define __FPU_PRESENT 1
sahilmgandhi 18:6a4db94011d3 200 #warning "__FPU_PRESENT not defined in device header file; using default!"
sahilmgandhi 18:6a4db94011d3 201 #endif
sahilmgandhi 18:6a4db94011d3 202
sahilmgandhi 18:6a4db94011d3 203 #ifndef __Vendor_SysTickConfig
sahilmgandhi 18:6a4db94011d3 204 #define __Vendor_SysTickConfig 1
sahilmgandhi 18:6a4db94011d3 205 #endif
sahilmgandhi 18:6a4db94011d3 206
sahilmgandhi 18:6a4db94011d3 207 #if __Vendor_SysTickConfig == 0
sahilmgandhi 18:6a4db94011d3 208 #error "__Vendor_SysTickConfig set to 0, but vendor systick timer must be supplied for Cortex-A9"
sahilmgandhi 18:6a4db94011d3 209 #endif
sahilmgandhi 18:6a4db94011d3 210 #endif
sahilmgandhi 18:6a4db94011d3 211
sahilmgandhi 18:6a4db94011d3 212 /* IO definitions (access restrictions to peripheral registers) */
sahilmgandhi 18:6a4db94011d3 213 /**
sahilmgandhi 18:6a4db94011d3 214 \defgroup CMSIS_glob_defs CMSIS Global Defines
sahilmgandhi 18:6a4db94011d3 215
sahilmgandhi 18:6a4db94011d3 216 <strong>IO Type Qualifiers</strong> are used
sahilmgandhi 18:6a4db94011d3 217 \li to specify the access to peripheral variables.
sahilmgandhi 18:6a4db94011d3 218 \li for automatic generation of peripheral register debug information.
sahilmgandhi 18:6a4db94011d3 219 */
sahilmgandhi 18:6a4db94011d3 220 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 221 #define __I volatile /*!< Defines 'read only' permissions */
sahilmgandhi 18:6a4db94011d3 222 #else
sahilmgandhi 18:6a4db94011d3 223 #define __I volatile const /*!< Defines 'read only' permissions */
sahilmgandhi 18:6a4db94011d3 224 #endif
sahilmgandhi 18:6a4db94011d3 225 #define __O volatile /*!< Defines 'write only' permissions */
sahilmgandhi 18:6a4db94011d3 226 #define __IO volatile /*!< Defines 'read / write' permissions */
sahilmgandhi 18:6a4db94011d3 227
sahilmgandhi 18:6a4db94011d3 228 /*@} end of group Cortex_A9 */
sahilmgandhi 18:6a4db94011d3 229
sahilmgandhi 18:6a4db94011d3 230
sahilmgandhi 18:6a4db94011d3 231 /*******************************************************************************
sahilmgandhi 18:6a4db94011d3 232 * Register Abstraction
sahilmgandhi 18:6a4db94011d3 233 ******************************************************************************/
sahilmgandhi 18:6a4db94011d3 234 /** \defgroup CMSIS_core_register Defines and Type Definitions
sahilmgandhi 18:6a4db94011d3 235 \brief Type definitions and defines for Cortex-A processor based devices.
sahilmgandhi 18:6a4db94011d3 236 */
sahilmgandhi 18:6a4db94011d3 237
sahilmgandhi 18:6a4db94011d3 238 /** \ingroup CMSIS_core_register
sahilmgandhi 18:6a4db94011d3 239 \defgroup CMSIS_CORE Status and Control Registers
sahilmgandhi 18:6a4db94011d3 240 \brief Core Register type definitions.
sahilmgandhi 18:6a4db94011d3 241 @{
sahilmgandhi 18:6a4db94011d3 242 */
sahilmgandhi 18:6a4db94011d3 243
sahilmgandhi 18:6a4db94011d3 244 /** \brief Union type to access the Application Program Status Register (APSR).
sahilmgandhi 18:6a4db94011d3 245 */
sahilmgandhi 18:6a4db94011d3 246 typedef union
sahilmgandhi 18:6a4db94011d3 247 {
sahilmgandhi 18:6a4db94011d3 248 struct
sahilmgandhi 18:6a4db94011d3 249 {
sahilmgandhi 18:6a4db94011d3 250 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
sahilmgandhi 18:6a4db94011d3 251 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
sahilmgandhi 18:6a4db94011d3 252 uint32_t reserved1:7; /*!< bit: 20..23 Reserved */
sahilmgandhi 18:6a4db94011d3 253 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
sahilmgandhi 18:6a4db94011d3 254 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
sahilmgandhi 18:6a4db94011d3 255 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
sahilmgandhi 18:6a4db94011d3 256 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
sahilmgandhi 18:6a4db94011d3 257 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
sahilmgandhi 18:6a4db94011d3 258 } b; /*!< Structure used for bit access */
sahilmgandhi 18:6a4db94011d3 259 uint32_t w; /*!< Type used for word access */
sahilmgandhi 18:6a4db94011d3 260 } APSR_Type;
sahilmgandhi 18:6a4db94011d3 261
sahilmgandhi 18:6a4db94011d3 262
sahilmgandhi 18:6a4db94011d3 263 /*@} end of group CMSIS_CORE */
sahilmgandhi 18:6a4db94011d3 264
sahilmgandhi 18:6a4db94011d3 265 /*@} end of CMSIS_Core_FPUFunctions */
sahilmgandhi 18:6a4db94011d3 266
sahilmgandhi 18:6a4db94011d3 267
sahilmgandhi 18:6a4db94011d3 268 #endif /* __CORE_CA9_H_GENERIC */
sahilmgandhi 18:6a4db94011d3 269
sahilmgandhi 18:6a4db94011d3 270 #endif /* __CMSIS_GENERIC */
sahilmgandhi 18:6a4db94011d3 271
sahilmgandhi 18:6a4db94011d3 272 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 273 }
sahilmgandhi 18:6a4db94011d3 274
sahilmgandhi 18:6a4db94011d3 275
sahilmgandhi 18:6a4db94011d3 276 #endif