mbed_f401re

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targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_tim.c@0:7e2bd16f80af, 2015-01-17 (annotated)

Committer:: elessair
Date:: Sat Jan 17 18:03:58 2015 +0000
Revision:: 0:7e2bd16f80af

nucleo f401re internal temperature added

Who changed what in which revision?

User	Revision	Line number	New contents of line
elessair	0:7e2bd16f80af	1	/**
elessair	0:7e2bd16f80af	2	******************************************************************************
elessair	0:7e2bd16f80af	3	* @file stm32l1xx_hal_tim.c
elessair	0:7e2bd16f80af	4	* @author MCD Application Team
elessair	0:7e2bd16f80af	5	* @version V1.0.0
elessair	0:7e2bd16f80af	6	* @date 5-September-2014
elessair	0:7e2bd16f80af	7	* @brief TIM HAL module driver.
elessair	0:7e2bd16f80af	8	* This file provides firmware functions to manage the following
elessair	0:7e2bd16f80af	9	* functionalities of the Timer (TIM) peripheral:
elessair	0:7e2bd16f80af	10	* + Time Base Initialization
elessair	0:7e2bd16f80af	11	* + Time Base Start
elessair	0:7e2bd16f80af	12	* + Time Base Start Interruption
elessair	0:7e2bd16f80af	13	* + Time Base Start DMA
elessair	0:7e2bd16f80af	14	* + Time Output Compare/PWM Initialization
elessair	0:7e2bd16f80af	15	* + Time Output Compare/PWM Channel Configuration
elessair	0:7e2bd16f80af	16	* + Time Output Compare/PWM Start
elessair	0:7e2bd16f80af	17	* + Time Output Compare/PWM Start Interruption
elessair	0:7e2bd16f80af	18	* + Time Output Compare/PWM Start DMA
elessair	0:7e2bd16f80af	19	* + Time Input Capture Initialization
elessair	0:7e2bd16f80af	20	* + Time Input Capture Channel Configuration
elessair	0:7e2bd16f80af	21	* + Time Input Capture Start
elessair	0:7e2bd16f80af	22	* + Time Input Capture Start Interruption
elessair	0:7e2bd16f80af	23	* + Time Input Capture Start DMA
elessair	0:7e2bd16f80af	24	* + Time One Pulse Initialization
elessair	0:7e2bd16f80af	25	* + Time One Pulse Channel Configuration
elessair	0:7e2bd16f80af	26	* + Time One Pulse Start
elessair	0:7e2bd16f80af	27	* + Time Encoder Interface Initialization
elessair	0:7e2bd16f80af	28	* + Time Encoder Interface Start
elessair	0:7e2bd16f80af	29	* + Time Encoder Interface Start Interruption
elessair	0:7e2bd16f80af	30	* + Time Encoder Interface Start DMA
elessair	0:7e2bd16f80af	31	* + Commutation Event configuration with Interruption and DMA
elessair	0:7e2bd16f80af	32	* + Time OCRef clear configuration
elessair	0:7e2bd16f80af	33	* + Time External Clock configuration
elessair	0:7e2bd16f80af	34	* + Time Master and Slave synchronization configuration
elessair	0:7e2bd16f80af	35	@verbatim
elessair	0:7e2bd16f80af	36	==============================================================================
elessair	0:7e2bd16f80af	37	##### TIMER Generic features #####
elessair	0:7e2bd16f80af	38	==============================================================================
elessair	0:7e2bd16f80af	39	[..] The Timer features include:
elessair	0:7e2bd16f80af	40	(#) 16-bit up, down, up/down auto-reload counter.
elessair	0:7e2bd16f80af	41	(#) 16-bit programmable prescaler allowing dividing (also on the fly) the
elessair	0:7e2bd16f80af	42	counter clock frequency either by any factor between 1 and 65536.
elessair	0:7e2bd16f80af	43	(#) Up to 4 independent channels for:
elessair	0:7e2bd16f80af	44	(++) Input Capture
elessair	0:7e2bd16f80af	45	(++) Output Compare
elessair	0:7e2bd16f80af	46	(++) PWM generation (Edge and Center-aligned Mode)
elessair	0:7e2bd16f80af	47	(++) One-pulse mode output
elessair	0:7e2bd16f80af	48	(#) Synchronization circuit to control the timer with external signals and to interconnect
elessair	0:7e2bd16f80af	49	several timers together.
elessair	0:7e2bd16f80af	50	(#) Supports incremental (quadrature) encoder
elessair	0:7e2bd16f80af	51
elessair	0:7e2bd16f80af	52	##### How to use this driver #####
elessair	0:7e2bd16f80af	53	================================================================================
elessair	0:7e2bd16f80af	54	[..]
elessair	0:7e2bd16f80af	55	(#) Initialize the TIM low level resources by implementing the following functions
elessair	0:7e2bd16f80af	56	depending from feature used :
elessair	0:7e2bd16f80af	57	(++) Time Base : HAL_TIM_Base_MspInit()
elessair	0:7e2bd16f80af	58	(++) Input Capture : HAL_TIM_IC_MspInit()
elessair	0:7e2bd16f80af	59	(++) Output Compare : HAL_TIM_OC_MspInit()
elessair	0:7e2bd16f80af	60	(++) PWM generation : HAL_TIM_PWM_MspInit()
elessair	0:7e2bd16f80af	61	(++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
elessair	0:7e2bd16f80af	62	(++) Encoder mode output : HAL_TIM_Encoder_MspInit()
elessair	0:7e2bd16f80af	63
elessair	0:7e2bd16f80af	64	(#) Initialize the TIM low level resources :
elessair	0:7e2bd16f80af	65	(##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
elessair	0:7e2bd16f80af	66	(##) TIM pins configuration
elessair	0:7e2bd16f80af	67	(+++) Enable the clock for the TIM GPIOs using the following function:
elessair	0:7e2bd16f80af	68	__GPIOx_CLK_ENABLE();
elessair	0:7e2bd16f80af	69	(+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
elessair	0:7e2bd16f80af	70
elessair	0:7e2bd16f80af	71	(#) The external Clock can be configured, if needed (the default clock is the
elessair	0:7e2bd16f80af	72	internal clock from the APBx), using the following function:
elessair	0:7e2bd16f80af	73	HAL_TIM_ConfigClockSource, the clock configuration should be done before
elessair	0:7e2bd16f80af	74	any start function.
elessair	0:7e2bd16f80af	75
elessair	0:7e2bd16f80af	76	(#) Configure the TIM in the desired functioning mode using one of the
elessair	0:7e2bd16f80af	77	Initialization function of this driver:
elessair	0:7e2bd16f80af	78	(++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
elessair	0:7e2bd16f80af	79	(++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
elessair	0:7e2bd16f80af	80	Output Compare signal.
elessair	0:7e2bd16f80af	81	(++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
elessair	0:7e2bd16f80af	82	PWM signal.
elessair	0:7e2bd16f80af	83	(++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
elessair	0:7e2bd16f80af	84	external signal.
elessair	0:7e2bd16f80af	85	(++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
elessair	0:7e2bd16f80af	86	in One Pulse Mode.
elessair	0:7e2bd16f80af	87	(++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
elessair	0:7e2bd16f80af	88
elessair	0:7e2bd16f80af	89	(#) Activate the TIM peripheral using one of the start functions depending from the feature used:
elessair	0:7e2bd16f80af	90	(++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
elessair	0:7e2bd16f80af	91	(++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
elessair	0:7e2bd16f80af	92	(++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
elessair	0:7e2bd16f80af	93	(++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
elessair	0:7e2bd16f80af	94	(++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
elessair	0:7e2bd16f80af	95	(++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
elessair	0:7e2bd16f80af	96
elessair	0:7e2bd16f80af	97	(#) The DMA Burst is managed with the two following functions:
elessair	0:7e2bd16f80af	98	HAL_TIM_DMABurst_WriteStart()
elessair	0:7e2bd16f80af	99	HAL_TIM_DMABurst_ReadStart()
elessair	0:7e2bd16f80af	100
elessair	0:7e2bd16f80af	101	@endverbatim
elessair	0:7e2bd16f80af	102	******************************************************************************
elessair	0:7e2bd16f80af	103	* @attention
elessair	0:7e2bd16f80af	104	*
elessair	0:7e2bd16f80af	105	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
elessair	0:7e2bd16f80af	106	*
elessair	0:7e2bd16f80af	107	* Redistribution and use in source and binary forms, with or without modification,
elessair	0:7e2bd16f80af	108	* are permitted provided that the following conditions are met:
elessair	0:7e2bd16f80af	109	* 1. Redistributions of source code must retain the above copyright notice,
elessair	0:7e2bd16f80af	110	* this list of conditions and the following disclaimer.
elessair	0:7e2bd16f80af	111	* 2. Redistributions in binary form must reproduce the above copyright notice,
elessair	0:7e2bd16f80af	112	* this list of conditions and the following disclaimer in the documentation
elessair	0:7e2bd16f80af	113	* and/or other materials provided with the distribution.
elessair	0:7e2bd16f80af	114	* 3. Neither the name of STMicroelectronics nor the names of its contributors
elessair	0:7e2bd16f80af	115	* may be used to endorse or promote products derived from this software
elessair	0:7e2bd16f80af	116	* without specific prior written permission.
elessair	0:7e2bd16f80af	117	*
elessair	0:7e2bd16f80af	118	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
elessair	0:7e2bd16f80af	119	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
elessair	0:7e2bd16f80af	120	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
elessair	0:7e2bd16f80af	121	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
elessair	0:7e2bd16f80af	122	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
elessair	0:7e2bd16f80af	123	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
elessair	0:7e2bd16f80af	124	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
elessair	0:7e2bd16f80af	125	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
elessair	0:7e2bd16f80af	126	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
elessair	0:7e2bd16f80af	127	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
elessair	0:7e2bd16f80af	128	*
elessair	0:7e2bd16f80af	129	******************************************************************************
elessair	0:7e2bd16f80af	130	*/
elessair	0:7e2bd16f80af	131
elessair	0:7e2bd16f80af	132	/* Includes ------------------------------------------------------------------*/
elessair	0:7e2bd16f80af	133	#include "stm32l1xx_hal.h"
elessair	0:7e2bd16f80af	134
elessair	0:7e2bd16f80af	135	/** @addtogroup STM32L1xx_HAL_Driver
elessair	0:7e2bd16f80af	136	* @{
elessair	0:7e2bd16f80af	137	*/
elessair	0:7e2bd16f80af	138
elessair	0:7e2bd16f80af	139	/** @defgroup TIM TIM
elessair	0:7e2bd16f80af	140	* @brief TIM HAL module driver
elessair	0:7e2bd16f80af	141	* @{
elessair	0:7e2bd16f80af	142	*/
elessair	0:7e2bd16f80af	143
elessair	0:7e2bd16f80af	144	#ifdef HAL_TIM_MODULE_ENABLED
elessair	0:7e2bd16f80af	145
elessair	0:7e2bd16f80af	146	/* Private typedef -----------------------------------------------------------*/
elessair	0:7e2bd16f80af	147	/* Private define ------------------------------------------------------------*/
elessair	0:7e2bd16f80af	148	/* Private macro -------------------------------------------------------------*/
elessair	0:7e2bd16f80af	149	/* Private variables ---------------------------------------------------------*/
elessair	0:7e2bd16f80af	150	/* Private function prototypes -----------------------------------------------*/
elessair	0:7e2bd16f80af	151	/** @defgroup TIM_Private_Functions TIM Private Functions
elessair	0:7e2bd16f80af	152	* @{
elessair	0:7e2bd16f80af	153	*/
elessair	0:7e2bd16f80af	154	static void TIM_OC1_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
elessair	0:7e2bd16f80af	155	static void TIM_OC3_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
elessair	0:7e2bd16f80af	156	static void TIM_OC4_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
elessair	0:7e2bd16f80af	157
elessair	0:7e2bd16f80af	158	static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
elessair	0:7e2bd16f80af	159	static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
elessair	0:7e2bd16f80af	160	uint32_t TIM_ICFilter);
elessair	0:7e2bd16f80af	161	static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
elessair	0:7e2bd16f80af	162	static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
elessair	0:7e2bd16f80af	163	uint32_t TIM_ICFilter);
elessair	0:7e2bd16f80af	164	static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
elessair	0:7e2bd16f80af	165	uint32_t TIM_ICFilter);
elessair	0:7e2bd16f80af	166
elessair	0:7e2bd16f80af	167	static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
elessair	0:7e2bd16f80af	168	uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
elessair	0:7e2bd16f80af	169
elessair	0:7e2bd16f80af	170	static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource);
elessair	0:7e2bd16f80af	171	static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
elessair	0:7e2bd16f80af	172	static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
elessair	0:7e2bd16f80af	173	static void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure);
elessair	0:7e2bd16f80af	174	static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
elessair	0:7e2bd16f80af	175	static void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
elessair	0:7e2bd16f80af	176	static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
elessair	0:7e2bd16f80af	177	static void TIM_DMAError(DMA_HandleTypeDef *hdma);
elessair	0:7e2bd16f80af	178	static void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
elessair	0:7e2bd16f80af	179	static void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
elessair	0:7e2bd16f80af	180
elessair	0:7e2bd16f80af	181	/**
elessair	0:7e2bd16f80af	182	* @}
elessair	0:7e2bd16f80af	183	*/
elessair	0:7e2bd16f80af	184
elessair	0:7e2bd16f80af	185	/* External functions ---------------------------------------------------------*/
elessair	0:7e2bd16f80af	186
elessair	0:7e2bd16f80af	187	/** @defgroup TIM_Exported_Functions TIM Exported Functions
elessair	0:7e2bd16f80af	188	* @{
elessair	0:7e2bd16f80af	189	*/
elessair	0:7e2bd16f80af	190
elessair	0:7e2bd16f80af	191	/** @defgroup TIM_Exported_Functions_Group1 Time Base functions
elessair	0:7e2bd16f80af	192	* @brief Time Base functions
elessair	0:7e2bd16f80af	193	*
elessair	0:7e2bd16f80af	194	@verbatim
elessair	0:7e2bd16f80af	195	==============================================================================
elessair	0:7e2bd16f80af	196	##### Time Base functions #####
elessair	0:7e2bd16f80af	197	==============================================================================
elessair	0:7e2bd16f80af	198	[..]
elessair	0:7e2bd16f80af	199	This section provides functions allowing to:
elessair	0:7e2bd16f80af	200	(+) Initialize and configure the TIM base.
elessair	0:7e2bd16f80af	201	(+) De-initialize the TIM base.
elessair	0:7e2bd16f80af	202	(+) Start the Time Base.
elessair	0:7e2bd16f80af	203	(+) Stop the Time Base.
elessair	0:7e2bd16f80af	204	(+) Start the Time Base and enable interrupt.
elessair	0:7e2bd16f80af	205	(+) Stop the Time Base and disable interrupt.
elessair	0:7e2bd16f80af	206	(+) Start the Time Base and enable DMA transfer.
elessair	0:7e2bd16f80af	207	(+) Stop the Time Base and disable DMA transfer.
elessair	0:7e2bd16f80af	208
elessair	0:7e2bd16f80af	209	@endverbatim
elessair	0:7e2bd16f80af	210	* @{
elessair	0:7e2bd16f80af	211	*/
elessair	0:7e2bd16f80af	212	/**
elessair	0:7e2bd16f80af	213	* @brief Initializes the TIM Time base Unit according to the specified
elessair	0:7e2bd16f80af	214	* parameters in the TIM_HandleTypeDef and create the associated handle.
elessair	0:7e2bd16f80af	215	* @param htim: TIM Base handle
elessair	0:7e2bd16f80af	216	* @retval HAL status
elessair	0:7e2bd16f80af	217	*/
elessair	0:7e2bd16f80af	218	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
elessair	0:7e2bd16f80af	219	{
elessair	0:7e2bd16f80af	220	/* Check the TIM handle allocation */
elessair	0:7e2bd16f80af	221	if(htim == HAL_NULL)
elessair	0:7e2bd16f80af	222	{
elessair	0:7e2bd16f80af	223	return HAL_ERROR;
elessair	0:7e2bd16f80af	224	}
elessair	0:7e2bd16f80af	225
elessair	0:7e2bd16f80af	226	/* Check the parameters */
elessair	0:7e2bd16f80af	227	assert_param(IS_TIM_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	228	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
elessair	0:7e2bd16f80af	229	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
elessair	0:7e2bd16f80af	230
elessair	0:7e2bd16f80af	231	if(htim->State == HAL_TIM_STATE_RESET)
elessair	0:7e2bd16f80af	232	{
elessair	0:7e2bd16f80af	233	/* Init the low level hardware : GPIO, CLOCK, NVIC */
elessair	0:7e2bd16f80af	234	HAL_TIM_Base_MspInit(htim);
elessair	0:7e2bd16f80af	235	}
elessair	0:7e2bd16f80af	236
elessair	0:7e2bd16f80af	237	/* Set the TIM state */
elessair	0:7e2bd16f80af	238	htim->State= HAL_TIM_STATE_BUSY;
elessair	0:7e2bd16f80af	239
elessair	0:7e2bd16f80af	240	/* Set the Time Base configuration */
elessair	0:7e2bd16f80af	241	TIM_Base_SetConfig(htim->Instance, &htim->Init);
elessair	0:7e2bd16f80af	242
elessair	0:7e2bd16f80af	243	/* Initialize the TIM state*/
elessair	0:7e2bd16f80af	244	htim->State= HAL_TIM_STATE_READY;
elessair	0:7e2bd16f80af	245
elessair	0:7e2bd16f80af	246	return HAL_OK;
elessair	0:7e2bd16f80af	247	}
elessair	0:7e2bd16f80af	248
elessair	0:7e2bd16f80af	249	/**
elessair	0:7e2bd16f80af	250	* @brief DeInitializes the TIM Base peripheral
elessair	0:7e2bd16f80af	251	* @param htim: TIM Base handle
elessair	0:7e2bd16f80af	252	* @retval HAL status
elessair	0:7e2bd16f80af	253	*/
elessair	0:7e2bd16f80af	254	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
elessair	0:7e2bd16f80af	255	{
elessair	0:7e2bd16f80af	256	/* Check the parameters */
elessair	0:7e2bd16f80af	257	assert_param(IS_TIM_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	258
elessair	0:7e2bd16f80af	259	htim->State = HAL_TIM_STATE_BUSY;
elessair	0:7e2bd16f80af	260
elessair	0:7e2bd16f80af	261	/* Disable the TIM Peripheral Clock */
elessair	0:7e2bd16f80af	262	__HAL_TIM_DISABLE(htim);
elessair	0:7e2bd16f80af	263
elessair	0:7e2bd16f80af	264	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
elessair	0:7e2bd16f80af	265	HAL_TIM_Base_MspDeInit(htim);
elessair	0:7e2bd16f80af	266
elessair	0:7e2bd16f80af	267	/* Change TIM state */
elessair	0:7e2bd16f80af	268	htim->State = HAL_TIM_STATE_RESET;
elessair	0:7e2bd16f80af	269
elessair	0:7e2bd16f80af	270	/* Release Lock */
elessair	0:7e2bd16f80af	271	__HAL_UNLOCK(htim);
elessair	0:7e2bd16f80af	272
elessair	0:7e2bd16f80af	273	return HAL_OK;
elessair	0:7e2bd16f80af	274	}
elessair	0:7e2bd16f80af	275
elessair	0:7e2bd16f80af	276	/**
elessair	0:7e2bd16f80af	277	* @brief Initializes the TIM Base MSP.
elessair	0:7e2bd16f80af	278	* @param htim: TIM handle
elessair	0:7e2bd16f80af	279	* @retval None
elessair	0:7e2bd16f80af	280	*/
elessair	0:7e2bd16f80af	281	__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
elessair	0:7e2bd16f80af	282	{
elessair	0:7e2bd16f80af	283	/* NOTE : This function Should not be modified, when the callback is needed,
elessair	0:7e2bd16f80af	284	the HAL_TIM_Base_MspInit could be implemented in the user file
elessair	0:7e2bd16f80af	285	*/
elessair	0:7e2bd16f80af	286	}
elessair	0:7e2bd16f80af	287
elessair	0:7e2bd16f80af	288	/**
elessair	0:7e2bd16f80af	289	* @brief DeInitializes TIM Base MSP.
elessair	0:7e2bd16f80af	290	* @param htim: TIM handle
elessair	0:7e2bd16f80af	291	* @retval None
elessair	0:7e2bd16f80af	292	*/
elessair	0:7e2bd16f80af	293	__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
elessair	0:7e2bd16f80af	294	{
elessair	0:7e2bd16f80af	295	/* NOTE : This function Should not be modified, when the callback is needed,
elessair	0:7e2bd16f80af	296	the HAL_TIM_Base_MspDeInit could be implemented in the user file
elessair	0:7e2bd16f80af	297	*/
elessair	0:7e2bd16f80af	298	}
elessair	0:7e2bd16f80af	299
elessair	0:7e2bd16f80af	300
elessair	0:7e2bd16f80af	301	/**
elessair	0:7e2bd16f80af	302	* @brief Starts the TIM Base generation.
elessair	0:7e2bd16f80af	303	* @param htim : TIM handle
elessair	0:7e2bd16f80af	304	* @retval HAL status
elessair	0:7e2bd16f80af	305	*/
elessair	0:7e2bd16f80af	306	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
elessair	0:7e2bd16f80af	307	{
elessair	0:7e2bd16f80af	308	/* Check the parameters */
elessair	0:7e2bd16f80af	309	assert_param(IS_TIM_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	310
elessair	0:7e2bd16f80af	311	/* Set the TIM state */
elessair	0:7e2bd16f80af	312	htim->State= HAL_TIM_STATE_BUSY;
elessair	0:7e2bd16f80af	313
elessair	0:7e2bd16f80af	314	/* Enable the Peripheral */
elessair	0:7e2bd16f80af	315	__HAL_TIM_ENABLE(htim);
elessair	0:7e2bd16f80af	316
elessair	0:7e2bd16f80af	317	/* Change the TIM state*/
elessair	0:7e2bd16f80af	318	htim->State= HAL_TIM_STATE_READY;
elessair	0:7e2bd16f80af	319
elessair	0:7e2bd16f80af	320	/* Return function status */
elessair	0:7e2bd16f80af	321	return HAL_OK;
elessair	0:7e2bd16f80af	322	}
elessair	0:7e2bd16f80af	323
elessair	0:7e2bd16f80af	324	/**
elessair	0:7e2bd16f80af	325	* @brief Stops the TIM Base generation.
elessair	0:7e2bd16f80af	326	* @param htim : TIM handle
elessair	0:7e2bd16f80af	327	* @retval HAL status
elessair	0:7e2bd16f80af	328	*/
elessair	0:7e2bd16f80af	329	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
elessair	0:7e2bd16f80af	330	{
elessair	0:7e2bd16f80af	331	/* Check the parameters */
elessair	0:7e2bd16f80af	332	assert_param(IS_TIM_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	333
elessair	0:7e2bd16f80af	334	/* Set the TIM state */
elessair	0:7e2bd16f80af	335	htim->State= HAL_TIM_STATE_BUSY;
elessair	0:7e2bd16f80af	336
elessair	0:7e2bd16f80af	337	/* Disable the Peripheral */
elessair	0:7e2bd16f80af	338	__HAL_TIM_DISABLE(htim);
elessair	0:7e2bd16f80af	339
elessair	0:7e2bd16f80af	340	/* Change the TIM state*/
elessair	0:7e2bd16f80af	341	htim->State= HAL_TIM_STATE_READY;
elessair	0:7e2bd16f80af	342
elessair	0:7e2bd16f80af	343	/* Return function status */
elessair	0:7e2bd16f80af	344	return HAL_OK;
elessair	0:7e2bd16f80af	345	}
elessair	0:7e2bd16f80af	346
elessair	0:7e2bd16f80af	347	/**
elessair	0:7e2bd16f80af	348	* @brief Starts the TIM Base generation in interrupt mode.
elessair	0:7e2bd16f80af	349	* @param htim : TIM handle
elessair	0:7e2bd16f80af	350	* @retval HAL status
elessair	0:7e2bd16f80af	351	*/
elessair	0:7e2bd16f80af	352	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
elessair	0:7e2bd16f80af	353	{
elessair	0:7e2bd16f80af	354	/* Check the parameters */
elessair	0:7e2bd16f80af	355	assert_param(IS_TIM_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	356
elessair	0:7e2bd16f80af	357	/* Enable the TIM Update interrupt */
elessair	0:7e2bd16f80af	358	__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
elessair	0:7e2bd16f80af	359
elessair	0:7e2bd16f80af	360	/* Enable the Peripheral */
elessair	0:7e2bd16f80af	361	__HAL_TIM_ENABLE(htim);
elessair	0:7e2bd16f80af	362
elessair	0:7e2bd16f80af	363	/* Return function status */
elessair	0:7e2bd16f80af	364	return HAL_OK;
elessair	0:7e2bd16f80af	365	}
elessair	0:7e2bd16f80af	366
elessair	0:7e2bd16f80af	367	/**
elessair	0:7e2bd16f80af	368	* @brief Stops the TIM Base generation in interrupt mode.
elessair	0:7e2bd16f80af	369	* @param htim : TIM handle
elessair	0:7e2bd16f80af	370	* @retval HAL status
elessair	0:7e2bd16f80af	371	*/
elessair	0:7e2bd16f80af	372	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
elessair	0:7e2bd16f80af	373	{
elessair	0:7e2bd16f80af	374	/* Check the parameters */
elessair	0:7e2bd16f80af	375	assert_param(IS_TIM_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	376	/* Disable the TIM Update interrupt */
elessair	0:7e2bd16f80af	377	__HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
elessair	0:7e2bd16f80af	378
elessair	0:7e2bd16f80af	379	/* Disable the Peripheral */
elessair	0:7e2bd16f80af	380	__HAL_TIM_DISABLE(htim);
elessair	0:7e2bd16f80af	381
elessair	0:7e2bd16f80af	382	/* Return function status */
elessair	0:7e2bd16f80af	383	return HAL_OK;
elessair	0:7e2bd16f80af	384	}
elessair	0:7e2bd16f80af	385
elessair	0:7e2bd16f80af	386	/**
elessair	0:7e2bd16f80af	387	* @brief Starts the TIM Base generation in DMA mode.
elessair	0:7e2bd16f80af	388	* @param htim : TIM handle
elessair	0:7e2bd16f80af	389	* @param pData: The source Buffer address.
elessair	0:7e2bd16f80af	390	* @param Length: The length of data to be transferred from memory to peripheral.
elessair	0:7e2bd16f80af	391	* @retval HAL status
elessair	0:7e2bd16f80af	392	*/
elessair	0:7e2bd16f80af	393	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length)
elessair	0:7e2bd16f80af	394	{
elessair	0:7e2bd16f80af	395	/* Check the parameters */
elessair	0:7e2bd16f80af	396	assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	397
elessair	0:7e2bd16f80af	398	if((htim->State == HAL_TIM_STATE_BUSY))
elessair	0:7e2bd16f80af	399	{
elessair	0:7e2bd16f80af	400	return HAL_BUSY;
elessair	0:7e2bd16f80af	401	}
elessair	0:7e2bd16f80af	402	else if((htim->State == HAL_TIM_STATE_READY))
elessair	0:7e2bd16f80af	403	{
elessair	0:7e2bd16f80af	404	if((pData == 0 ) && (Length > 0))
elessair	0:7e2bd16f80af	405	{
elessair	0:7e2bd16f80af	406	return HAL_ERROR;
elessair	0:7e2bd16f80af	407	}
elessair	0:7e2bd16f80af	408	else
elessair	0:7e2bd16f80af	409	{
elessair	0:7e2bd16f80af	410	htim->State = HAL_TIM_STATE_BUSY;
elessair	0:7e2bd16f80af	411	}
elessair	0:7e2bd16f80af	412	}
elessair	0:7e2bd16f80af	413	else
elessair	0:7e2bd16f80af	414	{
elessair	0:7e2bd16f80af	415	return HAL_ERROR;
elessair	0:7e2bd16f80af	416	}
elessair	0:7e2bd16f80af	417
elessair	0:7e2bd16f80af	418	/* Set the DMA Period elapsed callback */
elessair	0:7e2bd16f80af	419	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
elessair	0:7e2bd16f80af	420
elessair	0:7e2bd16f80af	421	/* Set the DMA error callback */
elessair	0:7e2bd16f80af	422	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
elessair	0:7e2bd16f80af	423
elessair	0:7e2bd16f80af	424	/* Enable the DMA channel */
elessair	0:7e2bd16f80af	425	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
elessair	0:7e2bd16f80af	426
elessair	0:7e2bd16f80af	427	/* Enable the TIM Update DMA request */
elessair	0:7e2bd16f80af	428	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
elessair	0:7e2bd16f80af	429
elessair	0:7e2bd16f80af	430	/* Enable the Peripheral */
elessair	0:7e2bd16f80af	431	__HAL_TIM_ENABLE(htim);
elessair	0:7e2bd16f80af	432
elessair	0:7e2bd16f80af	433	/* Return function status */
elessair	0:7e2bd16f80af	434	return HAL_OK;
elessair	0:7e2bd16f80af	435	}
elessair	0:7e2bd16f80af	436
elessair	0:7e2bd16f80af	437	/**
elessair	0:7e2bd16f80af	438	* @brief Stops the TIM Base generation in DMA mode.
elessair	0:7e2bd16f80af	439	* @param htim : TIM handle
elessair	0:7e2bd16f80af	440	* @retval HAL status
elessair	0:7e2bd16f80af	441	*/
elessair	0:7e2bd16f80af	442	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
elessair	0:7e2bd16f80af	443	{
elessair	0:7e2bd16f80af	444	/* Check the parameters */
elessair	0:7e2bd16f80af	445	assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	446
elessair	0:7e2bd16f80af	447	/* Disable the TIM Update DMA request */
elessair	0:7e2bd16f80af	448	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
elessair	0:7e2bd16f80af	449
elessair	0:7e2bd16f80af	450	/* Disable the Peripheral */
elessair	0:7e2bd16f80af	451	__HAL_TIM_DISABLE(htim);
elessair	0:7e2bd16f80af	452
elessair	0:7e2bd16f80af	453	/* Change the htim state */
elessair	0:7e2bd16f80af	454	htim->State = HAL_TIM_STATE_READY;
elessair	0:7e2bd16f80af	455
elessair	0:7e2bd16f80af	456	/* Return function status */
elessair	0:7e2bd16f80af	457	return HAL_OK;
elessair	0:7e2bd16f80af	458	}
elessair	0:7e2bd16f80af	459
elessair	0:7e2bd16f80af	460	/**
elessair	0:7e2bd16f80af	461	* @}
elessair	0:7e2bd16f80af	462	*/
elessair	0:7e2bd16f80af	463
elessair	0:7e2bd16f80af	464	/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
elessair	0:7e2bd16f80af	465	* @brief Time Output Compare functions
elessair	0:7e2bd16f80af	466	*
elessair	0:7e2bd16f80af	467	@verbatim
elessair	0:7e2bd16f80af	468	==============================================================================
elessair	0:7e2bd16f80af	469	##### Time Output Compare functions #####
elessair	0:7e2bd16f80af	470	==============================================================================
elessair	0:7e2bd16f80af	471	[..]
elessair	0:7e2bd16f80af	472	This section provides functions allowing to:
elessair	0:7e2bd16f80af	473	(+) Initialize and configure the TIM Output Compare.
elessair	0:7e2bd16f80af	474	(+) De-initialize the TIM Output Compare.
elessair	0:7e2bd16f80af	475	(+) Start the Time Output Compare.
elessair	0:7e2bd16f80af	476	(+) Stop the Time Output Compare.
elessair	0:7e2bd16f80af	477	(+) Start the Time Output Compare and enable interrupt.
elessair	0:7e2bd16f80af	478	(+) Stop the Time Output Compare and disable interrupt.
elessair	0:7e2bd16f80af	479	(+) Start the Time Output Compare and enable DMA transfer.
elessair	0:7e2bd16f80af	480	(+) Stop the Time Output Compare and disable DMA transfer.
elessair	0:7e2bd16f80af	481
elessair	0:7e2bd16f80af	482	@endverbatim
elessair	0:7e2bd16f80af	483	* @{
elessair	0:7e2bd16f80af	484	*/
elessair	0:7e2bd16f80af	485	/**
elessair	0:7e2bd16f80af	486	* @brief Initializes the TIM Output Compare according to the specified
elessair	0:7e2bd16f80af	487	* parameters in the TIM_HandleTypeDef and create the associated handle.
elessair	0:7e2bd16f80af	488	* @param htim: TIM Output Compare handle
elessair	0:7e2bd16f80af	489	* @retval HAL status
elessair	0:7e2bd16f80af	490	*/
elessair	0:7e2bd16f80af	491	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
elessair	0:7e2bd16f80af	492	{
elessair	0:7e2bd16f80af	493	/* Check the TIM handle allocation */
elessair	0:7e2bd16f80af	494	if(htim == HAL_NULL)
elessair	0:7e2bd16f80af	495	{
elessair	0:7e2bd16f80af	496	return HAL_ERROR;
elessair	0:7e2bd16f80af	497	}
elessair	0:7e2bd16f80af	498
elessair	0:7e2bd16f80af	499	/* Check the parameters */
elessair	0:7e2bd16f80af	500	assert_param(IS_TIM_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	501	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
elessair	0:7e2bd16f80af	502	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
elessair	0:7e2bd16f80af	503
elessair	0:7e2bd16f80af	504	if(htim->State == HAL_TIM_STATE_RESET)
elessair	0:7e2bd16f80af	505	{
elessair	0:7e2bd16f80af	506	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
elessair	0:7e2bd16f80af	507	HAL_TIM_OC_MspInit(htim);
elessair	0:7e2bd16f80af	508	}
elessair	0:7e2bd16f80af	509
elessair	0:7e2bd16f80af	510	/* Set the TIM state */
elessair	0:7e2bd16f80af	511	htim->State= HAL_TIM_STATE_BUSY;
elessair	0:7e2bd16f80af	512
elessair	0:7e2bd16f80af	513	/* Init the base time for the Output Compare */
elessair	0:7e2bd16f80af	514	TIM_Base_SetConfig(htim->Instance, &htim->Init);
elessair	0:7e2bd16f80af	515
elessair	0:7e2bd16f80af	516	/* Initialize the TIM state*/
elessair	0:7e2bd16f80af	517	htim->State= HAL_TIM_STATE_READY;
elessair	0:7e2bd16f80af	518
elessair	0:7e2bd16f80af	519	return HAL_OK;
elessair	0:7e2bd16f80af	520	}
elessair	0:7e2bd16f80af	521
elessair	0:7e2bd16f80af	522	/**
elessair	0:7e2bd16f80af	523	* @brief DeInitializes the TIM peripheral
elessair	0:7e2bd16f80af	524	* @param htim: TIM Output Compare handle
elessair	0:7e2bd16f80af	525	* @retval HAL status
elessair	0:7e2bd16f80af	526	*/
elessair	0:7e2bd16f80af	527	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
elessair	0:7e2bd16f80af	528	{
elessair	0:7e2bd16f80af	529	/* Check the parameters */
elessair	0:7e2bd16f80af	530	assert_param(IS_TIM_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	531
elessair	0:7e2bd16f80af	532	htim->State = HAL_TIM_STATE_BUSY;
elessair	0:7e2bd16f80af	533
elessair	0:7e2bd16f80af	534	/* Disable the TIM Peripheral Clock */
elessair	0:7e2bd16f80af	535	__HAL_TIM_DISABLE(htim);
elessair	0:7e2bd16f80af	536
elessair	0:7e2bd16f80af	537	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
elessair	0:7e2bd16f80af	538	HAL_TIM_OC_MspDeInit(htim);
elessair	0:7e2bd16f80af	539
elessair	0:7e2bd16f80af	540	/* Change TIM state */
elessair	0:7e2bd16f80af	541	htim->State = HAL_TIM_STATE_RESET;
elessair	0:7e2bd16f80af	542
elessair	0:7e2bd16f80af	543	/* Release Lock */
elessair	0:7e2bd16f80af	544	__HAL_UNLOCK(htim);
elessair	0:7e2bd16f80af	545
elessair	0:7e2bd16f80af	546	return HAL_OK;
elessair	0:7e2bd16f80af	547	}
elessair	0:7e2bd16f80af	548
elessair	0:7e2bd16f80af	549	/**
elessair	0:7e2bd16f80af	550	* @brief Initializes the TIM Output Compare MSP.
elessair	0:7e2bd16f80af	551	* @param htim: TIM handle
elessair	0:7e2bd16f80af	552	* @retval None
elessair	0:7e2bd16f80af	553	*/
elessair	0:7e2bd16f80af	554	__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
elessair	0:7e2bd16f80af	555	{
elessair	0:7e2bd16f80af	556	/* NOTE : This function Should not be modified, when the callback is needed,
elessair	0:7e2bd16f80af	557	the HAL_TIM_OC_MspInit could be implemented in the user file
elessair	0:7e2bd16f80af	558	*/
elessair	0:7e2bd16f80af	559	}
elessair	0:7e2bd16f80af	560
elessair	0:7e2bd16f80af	561	/**
elessair	0:7e2bd16f80af	562	* @brief DeInitializes TIM Output Compare MSP.
elessair	0:7e2bd16f80af	563	* @param htim: TIM handle
elessair	0:7e2bd16f80af	564	* @retval None
elessair	0:7e2bd16f80af	565	*/
elessair	0:7e2bd16f80af	566	__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
elessair	0:7e2bd16f80af	567	{
elessair	0:7e2bd16f80af	568	/* NOTE : This function Should not be modified, when the callback is needed,
elessair	0:7e2bd16f80af	569	the HAL_TIM_OC_MspDeInit could be implemented in the user file
elessair	0:7e2bd16f80af	570	*/
elessair	0:7e2bd16f80af	571	}
elessair	0:7e2bd16f80af	572
elessair	0:7e2bd16f80af	573	/**
elessair	0:7e2bd16f80af	574	* @brief Starts the TIM Output Compare signal generation.
elessair	0:7e2bd16f80af	575	* @param htim : TIM Output Compare handle
elessair	0:7e2bd16f80af	576	* @param Channel : TIM Channel to be enabled
elessair	0:7e2bd16f80af	577	* This parameter can be one of the following values:
elessair	0:7e2bd16f80af	578	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
elessair	0:7e2bd16f80af	579	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
elessair	0:7e2bd16f80af	580	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
elessair	0:7e2bd16f80af	581	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
elessair	0:7e2bd16f80af	582	* @retval HAL status
elessair	0:7e2bd16f80af	583	*/
elessair	0:7e2bd16f80af	584	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
elessair	0:7e2bd16f80af	585	{
elessair	0:7e2bd16f80af	586	/* Check the parameters */
elessair	0:7e2bd16f80af	587	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
elessair	0:7e2bd16f80af	588
elessair	0:7e2bd16f80af	589	/* Enable the Output compare channel */
elessair	0:7e2bd16f80af	590	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
elessair	0:7e2bd16f80af	591
elessair	0:7e2bd16f80af	592	/* Enable the Peripheral */
elessair	0:7e2bd16f80af	593	__HAL_TIM_ENABLE(htim);
elessair	0:7e2bd16f80af	594
elessair	0:7e2bd16f80af	595	/* Return function status */
elessair	0:7e2bd16f80af	596	return HAL_OK;
elessair	0:7e2bd16f80af	597	}
elessair	0:7e2bd16f80af	598
elessair	0:7e2bd16f80af	599	/**
elessair	0:7e2bd16f80af	600	* @brief Stops the TIM Output Compare signal generation.
elessair	0:7e2bd16f80af	601	* @param htim : TIM handle
elessair	0:7e2bd16f80af	602	* @param Channel : TIM Channel to be disabled
elessair	0:7e2bd16f80af	603	* This parameter can be one of the following values:
elessair	0:7e2bd16f80af	604	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
elessair	0:7e2bd16f80af	605	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
elessair	0:7e2bd16f80af	606	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
elessair	0:7e2bd16f80af	607	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
elessair	0:7e2bd16f80af	608	* @retval HAL status
elessair	0:7e2bd16f80af	609	*/
elessair	0:7e2bd16f80af	610	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
elessair	0:7e2bd16f80af	611	{
elessair	0:7e2bd16f80af	612	/* Check the parameters */
elessair	0:7e2bd16f80af	613	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
elessair	0:7e2bd16f80af	614
elessair	0:7e2bd16f80af	615	/* Disable the Output compare channel */
elessair	0:7e2bd16f80af	616	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
elessair	0:7e2bd16f80af	617
elessair	0:7e2bd16f80af	618	/* Disable the Peripheral */
elessair	0:7e2bd16f80af	619	__HAL_TIM_DISABLE(htim);
elessair	0:7e2bd16f80af	620
elessair	0:7e2bd16f80af	621	/* Return function status */
elessair	0:7e2bd16f80af	622	return HAL_OK;
elessair	0:7e2bd16f80af	623	}
elessair	0:7e2bd16f80af	624
elessair	0:7e2bd16f80af	625	/**
elessair	0:7e2bd16f80af	626	* @brief Starts the TIM Output Compare signal generation in interrupt mode.
elessair	0:7e2bd16f80af	627	* @param htim : TIM OC handle
elessair	0:7e2bd16f80af	628	* @param Channel : TIM Channel to be enabled
elessair	0:7e2bd16f80af	629	* This parameter can be one of the following values:
elessair	0:7e2bd16f80af	630	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
elessair	0:7e2bd16f80af	631	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
elessair	0:7e2bd16f80af	632	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
elessair	0:7e2bd16f80af	633	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
elessair	0:7e2bd16f80af	634	* @retval HAL status
elessair	0:7e2bd16f80af	635	*/
elessair	0:7e2bd16f80af	636	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
elessair	0:7e2bd16f80af	637	{
elessair	0:7e2bd16f80af	638	/* Check the parameters */
elessair	0:7e2bd16f80af	639	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
elessair	0:7e2bd16f80af	640
elessair	0:7e2bd16f80af	641	switch (Channel)
elessair	0:7e2bd16f80af	642	{
elessair	0:7e2bd16f80af	643	case TIM_CHANNEL_1:
elessair	0:7e2bd16f80af	644	{
elessair	0:7e2bd16f80af	645	/* Enable the TIM Capture/Compare 1 interrupt */
elessair	0:7e2bd16f80af	646	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
elessair	0:7e2bd16f80af	647	}
elessair	0:7e2bd16f80af	648	break;
elessair	0:7e2bd16f80af	649
elessair	0:7e2bd16f80af	650	case TIM_CHANNEL_2:
elessair	0:7e2bd16f80af	651	{
elessair	0:7e2bd16f80af	652	/* Enable the TIM Capture/Compare 2 interrupt */
elessair	0:7e2bd16f80af	653	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
elessair	0:7e2bd16f80af	654	}
elessair	0:7e2bd16f80af	655	break;
elessair	0:7e2bd16f80af	656
elessair	0:7e2bd16f80af	657	case TIM_CHANNEL_3:
elessair	0:7e2bd16f80af	658	{
elessair	0:7e2bd16f80af	659	/* Enable the TIM Capture/Compare 3 interrupt */
elessair	0:7e2bd16f80af	660	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
elessair	0:7e2bd16f80af	661	}
elessair	0:7e2bd16f80af	662	break;
elessair	0:7e2bd16f80af	663
elessair	0:7e2bd16f80af	664	case TIM_CHANNEL_4:
elessair	0:7e2bd16f80af	665	{
elessair	0:7e2bd16f80af	666	/* Enable the TIM Capture/Compare 4 interrupt */
elessair	0:7e2bd16f80af	667	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
elessair	0:7e2bd16f80af	668	}
elessair	0:7e2bd16f80af	669	break;
elessair	0:7e2bd16f80af	670
elessair	0:7e2bd16f80af	671	default:
elessair	0:7e2bd16f80af	672	break;
elessair	0:7e2bd16f80af	673	}
elessair	0:7e2bd16f80af	674
elessair	0:7e2bd16f80af	675	/* Enable the Output compare channel */
elessair	0:7e2bd16f80af	676	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
elessair	0:7e2bd16f80af	677
elessair	0:7e2bd16f80af	678	/* Enable the Peripheral */
elessair	0:7e2bd16f80af	679	__HAL_TIM_ENABLE(htim);
elessair	0:7e2bd16f80af	680
elessair	0:7e2bd16f80af	681	/* Return function status */
elessair	0:7e2bd16f80af	682	return HAL_OK;
elessair	0:7e2bd16f80af	683	}
elessair	0:7e2bd16f80af	684
elessair	0:7e2bd16f80af	685	/**
elessair	0:7e2bd16f80af	686	* @brief Stops the TIM Output Compare signal generation in interrupt mode.
elessair	0:7e2bd16f80af	687	* @param htim : TIM Output Compare handle
elessair	0:7e2bd16f80af	688	* @param Channel : TIM Channel to be disabled
elessair	0:7e2bd16f80af	689	* This parameter can be one of the following values:
elessair	0:7e2bd16f80af	690	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
elessair	0:7e2bd16f80af	691	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
elessair	0:7e2bd16f80af	692	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
elessair	0:7e2bd16f80af	693	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
elessair	0:7e2bd16f80af	694	* @retval HAL status
elessair	0:7e2bd16f80af	695	*/
elessair	0:7e2bd16f80af	696	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
elessair	0:7e2bd16f80af	697	{
elessair	0:7e2bd16f80af	698	/* Check the parameters */
elessair	0:7e2bd16f80af	699	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
elessair	0:7e2bd16f80af	700
elessair	0:7e2bd16f80af	701	switch (Channel)
elessair	0:7e2bd16f80af	702	{
elessair	0:7e2bd16f80af	703	case TIM_CHANNEL_1:
elessair	0:7e2bd16f80af	704	{
elessair	0:7e2bd16f80af	705	/* Disable the TIM Capture/Compare 1 interrupt */
elessair	0:7e2bd16f80af	706	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
elessair	0:7e2bd16f80af	707	}
elessair	0:7e2bd16f80af	708	break;
elessair	0:7e2bd16f80af	709
elessair	0:7e2bd16f80af	710	case TIM_CHANNEL_2:
elessair	0:7e2bd16f80af	711	{
elessair	0:7e2bd16f80af	712	/* Disable the TIM Capture/Compare 2 interrupt */
elessair	0:7e2bd16f80af	713	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
elessair	0:7e2bd16f80af	714	}
elessair	0:7e2bd16f80af	715	break;
elessair	0:7e2bd16f80af	716
elessair	0:7e2bd16f80af	717	case TIM_CHANNEL_3:
elessair	0:7e2bd16f80af	718	{
elessair	0:7e2bd16f80af	719	/* Disable the TIM Capture/Compare 3 interrupt */
elessair	0:7e2bd16f80af	720	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
elessair	0:7e2bd16f80af	721	}
elessair	0:7e2bd16f80af	722	break;
elessair	0:7e2bd16f80af	723
elessair	0:7e2bd16f80af	724	case TIM_CHANNEL_4:
elessair	0:7e2bd16f80af	725	{
elessair	0:7e2bd16f80af	726	/* Disable the TIM Capture/Compare 4 interrupt */
elessair	0:7e2bd16f80af	727	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
elessair	0:7e2bd16f80af	728	}
elessair	0:7e2bd16f80af	729	break;
elessair	0:7e2bd16f80af	730
elessair	0:7e2bd16f80af	731	default:
elessair	0:7e2bd16f80af	732	break;
elessair	0:7e2bd16f80af	733	}
elessair	0:7e2bd16f80af	734
elessair	0:7e2bd16f80af	735	/* Disable the Output compare channel */
elessair	0:7e2bd16f80af	736	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
elessair	0:7e2bd16f80af	737
elessair	0:7e2bd16f80af	738	/* Disable the Peripheral */
elessair	0:7e2bd16f80af	739	__HAL_TIM_DISABLE(htim);
elessair	0:7e2bd16f80af	740
elessair	0:7e2bd16f80af	741	/* Return function status */
elessair	0:7e2bd16f80af	742	return HAL_OK;
elessair	0:7e2bd16f80af	743	}
elessair	0:7e2bd16f80af	744
elessair	0:7e2bd16f80af	745	/**
elessair	0:7e2bd16f80af	746	* @brief Starts the TIM Output Compare signal generation in DMA mode.
elessair	0:7e2bd16f80af	747	* @param htim : TIM Output Compare handle
elessair	0:7e2bd16f80af	748	* @param Channel : TIM Channel to be enabled
elessair	0:7e2bd16f80af	749	* This parameter can be one of the following values:
elessair	0:7e2bd16f80af	750	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
elessair	0:7e2bd16f80af	751	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
elessair	0:7e2bd16f80af	752	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
elessair	0:7e2bd16f80af	753	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
elessair	0:7e2bd16f80af	754	* @param pData: The source Buffer address.
elessair	0:7e2bd16f80af	755	* @param Length: The length of data to be transferred from memory to TIM peripheral
elessair	0:7e2bd16f80af	756	* @retval HAL status
elessair	0:7e2bd16f80af	757	*/
elessair	0:7e2bd16f80af	758	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
elessair	0:7e2bd16f80af	759	{
elessair	0:7e2bd16f80af	760	/* Check the parameters */
elessair	0:7e2bd16f80af	761	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
elessair	0:7e2bd16f80af	762
elessair	0:7e2bd16f80af	763	if((htim->State == HAL_TIM_STATE_BUSY))
elessair	0:7e2bd16f80af	764	{
elessair	0:7e2bd16f80af	765	return HAL_BUSY;
elessair	0:7e2bd16f80af	766	}
elessair	0:7e2bd16f80af	767	else if((htim->State == HAL_TIM_STATE_READY))
elessair	0:7e2bd16f80af	768	{
elessair	0:7e2bd16f80af	769	if(((uint32_t)pData == 0 ) && (Length > 0))
elessair	0:7e2bd16f80af	770	{
elessair	0:7e2bd16f80af	771	return HAL_ERROR;
elessair	0:7e2bd16f80af	772	}
elessair	0:7e2bd16f80af	773	else
elessair	0:7e2bd16f80af	774	{
elessair	0:7e2bd16f80af	775	htim->State = HAL_TIM_STATE_BUSY;
elessair	0:7e2bd16f80af	776	}
elessair	0:7e2bd16f80af	777	}
elessair	0:7e2bd16f80af	778	else
elessair	0:7e2bd16f80af	779	{
elessair	0:7e2bd16f80af	780	return HAL_ERROR;
elessair	0:7e2bd16f80af	781	}
elessair	0:7e2bd16f80af	782
elessair	0:7e2bd16f80af	783	switch (Channel)
elessair	0:7e2bd16f80af	784	{
elessair	0:7e2bd16f80af	785	case TIM_CHANNEL_1:
elessair	0:7e2bd16f80af	786	{
elessair	0:7e2bd16f80af	787	/* Set the DMA Period elapsed callback */
elessair	0:7e2bd16f80af	788	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
elessair	0:7e2bd16f80af	789
elessair	0:7e2bd16f80af	790	/* Set the DMA error callback */
elessair	0:7e2bd16f80af	791	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
elessair	0:7e2bd16f80af	792
elessair	0:7e2bd16f80af	793	/* Enable the DMA channel */
elessair	0:7e2bd16f80af	794	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
elessair	0:7e2bd16f80af	795
elessair	0:7e2bd16f80af	796	/* Enable the TIM Capture/Compare 1 DMA request */
elessair	0:7e2bd16f80af	797	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
elessair	0:7e2bd16f80af	798	}
elessair	0:7e2bd16f80af	799	break;
elessair	0:7e2bd16f80af	800
elessair	0:7e2bd16f80af	801	case TIM_CHANNEL_2:
elessair	0:7e2bd16f80af	802	{
elessair	0:7e2bd16f80af	803	/* Set the DMA Period elapsed callback */
elessair	0:7e2bd16f80af	804	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
elessair	0:7e2bd16f80af	805
elessair	0:7e2bd16f80af	806	/* Set the DMA error callback */
elessair	0:7e2bd16f80af	807	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
elessair	0:7e2bd16f80af	808
elessair	0:7e2bd16f80af	809	/* Enable the DMA channel */
elessair	0:7e2bd16f80af	810	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
elessair	0:7e2bd16f80af	811
elessair	0:7e2bd16f80af	812	/* Enable the TIM Capture/Compare 2 DMA request */
elessair	0:7e2bd16f80af	813	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
elessair	0:7e2bd16f80af	814	}
elessair	0:7e2bd16f80af	815	break;
elessair	0:7e2bd16f80af	816
elessair	0:7e2bd16f80af	817	case TIM_CHANNEL_3:
elessair	0:7e2bd16f80af	818	{
elessair	0:7e2bd16f80af	819	/* Set the DMA Period elapsed callback */
elessair	0:7e2bd16f80af	820	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
elessair	0:7e2bd16f80af	821
elessair	0:7e2bd16f80af	822	/* Set the DMA error callback */
elessair	0:7e2bd16f80af	823	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
elessair	0:7e2bd16f80af	824
elessair	0:7e2bd16f80af	825	/* Enable the DMA channel */
elessair	0:7e2bd16f80af	826	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
elessair	0:7e2bd16f80af	827
elessair	0:7e2bd16f80af	828	/* Enable the TIM Capture/Compare 3 DMA request */
elessair	0:7e2bd16f80af	829	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
elessair	0:7e2bd16f80af	830	}
elessair	0:7e2bd16f80af	831	break;
elessair	0:7e2bd16f80af	832
elessair	0:7e2bd16f80af	833	case TIM_CHANNEL_4:
elessair	0:7e2bd16f80af	834	{
elessair	0:7e2bd16f80af	835	/* Set the DMA Period elapsed callback */
elessair	0:7e2bd16f80af	836	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
elessair	0:7e2bd16f80af	837
elessair	0:7e2bd16f80af	838	/* Set the DMA error callback */
elessair	0:7e2bd16f80af	839	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
elessair	0:7e2bd16f80af	840
elessair	0:7e2bd16f80af	841	/* Enable the DMA channel */
elessair	0:7e2bd16f80af	842	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
elessair	0:7e2bd16f80af	843
elessair	0:7e2bd16f80af	844	/* Enable the TIM Capture/Compare 4 DMA request */
elessair	0:7e2bd16f80af	845	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
elessair	0:7e2bd16f80af	846	}
elessair	0:7e2bd16f80af	847	break;
elessair	0:7e2bd16f80af	848
elessair	0:7e2bd16f80af	849	default:
elessair	0:7e2bd16f80af	850	break;
elessair	0:7e2bd16f80af	851	}
elessair	0:7e2bd16f80af	852
elessair	0:7e2bd16f80af	853	/* Enable the Output compare channel */
elessair	0:7e2bd16f80af	854	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
elessair	0:7e2bd16f80af	855
elessair	0:7e2bd16f80af	856	/* Enable the Peripheral */
elessair	0:7e2bd16f80af	857	__HAL_TIM_ENABLE(htim);
elessair	0:7e2bd16f80af	858
elessair	0:7e2bd16f80af	859	/* Return function status */
elessair	0:7e2bd16f80af	860	return HAL_OK;
elessair	0:7e2bd16f80af	861	}
elessair	0:7e2bd16f80af	862
elessair	0:7e2bd16f80af	863	/**
elessair	0:7e2bd16f80af	864	* @brief Stops the TIM Output Compare signal generation in DMA mode.
elessair	0:7e2bd16f80af	865	* @param htim : TIM Output Compare handle
elessair	0:7e2bd16f80af	866	* @param Channel : TIM Channel to be disabled
elessair	0:7e2bd16f80af	867	* This parameter can be one of the following values:
elessair	0:7e2bd16f80af	868	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
elessair	0:7e2bd16f80af	869	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
elessair	0:7e2bd16f80af	870	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
elessair	0:7e2bd16f80af	871	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
elessair	0:7e2bd16f80af	872	* @retval HAL status
elessair	0:7e2bd16f80af	873	*/
elessair	0:7e2bd16f80af	874	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
elessair	0:7e2bd16f80af	875	{
elessair	0:7e2bd16f80af	876	/* Check the parameters */
elessair	0:7e2bd16f80af	877	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
elessair	0:7e2bd16f80af	878
elessair	0:7e2bd16f80af	879	switch (Channel)
elessair	0:7e2bd16f80af	880	{
elessair	0:7e2bd16f80af	881	case TIM_CHANNEL_1:
elessair	0:7e2bd16f80af	882	{
elessair	0:7e2bd16f80af	883	/* Disable the TIM Capture/Compare 1 DMA request */
elessair	0:7e2bd16f80af	884	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
elessair	0:7e2bd16f80af	885	}
elessair	0:7e2bd16f80af	886	break;
elessair	0:7e2bd16f80af	887
elessair	0:7e2bd16f80af	888	case TIM_CHANNEL_2:
elessair	0:7e2bd16f80af	889	{
elessair	0:7e2bd16f80af	890	/* Disable the TIM Capture/Compare 2 DMA request */
elessair	0:7e2bd16f80af	891	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
elessair	0:7e2bd16f80af	892	}
elessair	0:7e2bd16f80af	893	break;
elessair	0:7e2bd16f80af	894
elessair	0:7e2bd16f80af	895	case TIM_CHANNEL_3:
elessair	0:7e2bd16f80af	896	{
elessair	0:7e2bd16f80af	897	/* Disable the TIM Capture/Compare 3 DMA request */
elessair	0:7e2bd16f80af	898	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
elessair	0:7e2bd16f80af	899	}
elessair	0:7e2bd16f80af	900	break;
elessair	0:7e2bd16f80af	901
elessair	0:7e2bd16f80af	902	case TIM_CHANNEL_4:
elessair	0:7e2bd16f80af	903	{
elessair	0:7e2bd16f80af	904	/* Disable the TIM Capture/Compare 4 interrupt */
elessair	0:7e2bd16f80af	905	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
elessair	0:7e2bd16f80af	906	}
elessair	0:7e2bd16f80af	907	break;
elessair	0:7e2bd16f80af	908
elessair	0:7e2bd16f80af	909	default:
elessair	0:7e2bd16f80af	910	break;
elessair	0:7e2bd16f80af	911	}
elessair	0:7e2bd16f80af	912
elessair	0:7e2bd16f80af	913	/* Disable the Output compare channel */
elessair	0:7e2bd16f80af	914	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
elessair	0:7e2bd16f80af	915
elessair	0:7e2bd16f80af	916	/* Disable the Peripheral */
elessair	0:7e2bd16f80af	917	__HAL_TIM_DISABLE(htim);
elessair	0:7e2bd16f80af	918
elessair	0:7e2bd16f80af	919	/* Change the htim state */
elessair	0:7e2bd16f80af	920	htim->State = HAL_TIM_STATE_READY;
elessair	0:7e2bd16f80af	921
elessair	0:7e2bd16f80af	922	/* Return function status */
elessair	0:7e2bd16f80af	923	return HAL_OK;
elessair	0:7e2bd16f80af	924	}
elessair	0:7e2bd16f80af	925
elessair	0:7e2bd16f80af	926	/**
elessair	0:7e2bd16f80af	927	* @}
elessair	0:7e2bd16f80af	928	*/
elessair	0:7e2bd16f80af	929
elessair	0:7e2bd16f80af	930	/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
elessair	0:7e2bd16f80af	931	* @brief Time PWM functions
elessair	0:7e2bd16f80af	932	*
elessair	0:7e2bd16f80af	933	@verbatim
elessair	0:7e2bd16f80af	934	==============================================================================
elessair	0:7e2bd16f80af	935	##### Time PWM functions #####
elessair	0:7e2bd16f80af	936	==============================================================================
elessair	0:7e2bd16f80af	937	[..]
elessair	0:7e2bd16f80af	938	This section provides functions allowing to:
elessair	0:7e2bd16f80af	939	(+) Initialize and configure the TIM OPWM.
elessair	0:7e2bd16f80af	940	(+) De-initialize the TIM PWM.
elessair	0:7e2bd16f80af	941	(+) Start the Time PWM.
elessair	0:7e2bd16f80af	942	(+) Stop the Time PWM.
elessair	0:7e2bd16f80af	943	(+) Start the Time PWM and enable interrupt.
elessair	0:7e2bd16f80af	944	(+) Stop the Time PWM and disable interrupt.
elessair	0:7e2bd16f80af	945	(+) Start the Time PWM and enable DMA transfer.
elessair	0:7e2bd16f80af	946	(+) Stop the Time PWM and disable DMA transfer.
elessair	0:7e2bd16f80af	947
elessair	0:7e2bd16f80af	948	@endverbatim
elessair	0:7e2bd16f80af	949	* @{
elessair	0:7e2bd16f80af	950	*/
elessair	0:7e2bd16f80af	951	/**
elessair	0:7e2bd16f80af	952	* @brief Initializes the TIM PWM Time Base according to the specified
elessair	0:7e2bd16f80af	953	* parameters in the TIM_HandleTypeDef and create the associated handle.
elessair	0:7e2bd16f80af	954	* @param htim: TIM handle
elessair	0:7e2bd16f80af	955	* @retval HAL status
elessair	0:7e2bd16f80af	956	*/
elessair	0:7e2bd16f80af	957	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
elessair	0:7e2bd16f80af	958	{
elessair	0:7e2bd16f80af	959	/* Check the TIM handle allocation */
elessair	0:7e2bd16f80af	960	if(htim == HAL_NULL)
elessair	0:7e2bd16f80af	961	{
elessair	0:7e2bd16f80af	962	return HAL_ERROR;
elessair	0:7e2bd16f80af	963	}
elessair	0:7e2bd16f80af	964
elessair	0:7e2bd16f80af	965	/* Check the parameters */
elessair	0:7e2bd16f80af	966	assert_param(IS_TIM_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	967	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
elessair	0:7e2bd16f80af	968	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
elessair	0:7e2bd16f80af	969
elessair	0:7e2bd16f80af	970	if(htim->State == HAL_TIM_STATE_RESET)
elessair	0:7e2bd16f80af	971	{
elessair	0:7e2bd16f80af	972	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
elessair	0:7e2bd16f80af	973	HAL_TIM_PWM_MspInit(htim);
elessair	0:7e2bd16f80af	974	}
elessair	0:7e2bd16f80af	975
elessair	0:7e2bd16f80af	976	/* Set the TIM state */
elessair	0:7e2bd16f80af	977	htim->State= HAL_TIM_STATE_BUSY;
elessair	0:7e2bd16f80af	978
elessair	0:7e2bd16f80af	979	/* Init the base time for the PWM */
elessair	0:7e2bd16f80af	980	TIM_Base_SetConfig(htim->Instance, &htim->Init);
elessair	0:7e2bd16f80af	981
elessair	0:7e2bd16f80af	982	/* Initialize the TIM state*/
elessair	0:7e2bd16f80af	983	htim->State= HAL_TIM_STATE_READY;
elessair	0:7e2bd16f80af	984
elessair	0:7e2bd16f80af	985	return HAL_OK;
elessair	0:7e2bd16f80af	986	}
elessair	0:7e2bd16f80af	987
elessair	0:7e2bd16f80af	988	/**
elessair	0:7e2bd16f80af	989	* @brief DeInitializes the TIM peripheral
elessair	0:7e2bd16f80af	990	* @param htim: TIM handle
elessair	0:7e2bd16f80af	991	* @retval HAL status
elessair	0:7e2bd16f80af	992	*/
elessair	0:7e2bd16f80af	993	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
elessair	0:7e2bd16f80af	994	{
elessair	0:7e2bd16f80af	995	/* Check the parameters */
elessair	0:7e2bd16f80af	996	assert_param(IS_TIM_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	997
elessair	0:7e2bd16f80af	998	htim->State = HAL_TIM_STATE_BUSY;
elessair	0:7e2bd16f80af	999
elessair	0:7e2bd16f80af	1000	/* Disable the TIM Peripheral Clock */
elessair	0:7e2bd16f80af	1001	__HAL_TIM_DISABLE(htim);
elessair	0:7e2bd16f80af	1002
elessair	0:7e2bd16f80af	1003	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
elessair	0:7e2bd16f80af	1004	HAL_TIM_PWM_MspDeInit(htim);
elessair	0:7e2bd16f80af	1005
elessair	0:7e2bd16f80af	1006	/* Change TIM state */
elessair	0:7e2bd16f80af	1007	htim->State = HAL_TIM_STATE_RESET;
elessair	0:7e2bd16f80af	1008
elessair	0:7e2bd16f80af	1009	/* Release Lock */
elessair	0:7e2bd16f80af	1010	__HAL_UNLOCK(htim);
elessair	0:7e2bd16f80af	1011
elessair	0:7e2bd16f80af	1012	return HAL_OK;
elessair	0:7e2bd16f80af	1013	}
elessair	0:7e2bd16f80af	1014
elessair	0:7e2bd16f80af	1015	/**
elessair	0:7e2bd16f80af	1016	* @brief Initializes the TIM PWM MSP.
elessair	0:7e2bd16f80af	1017	* @param htim: TIM handle
elessair	0:7e2bd16f80af	1018	* @retval None
elessair	0:7e2bd16f80af	1019	*/
elessair	0:7e2bd16f80af	1020	__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
elessair	0:7e2bd16f80af	1021	{
elessair	0:7e2bd16f80af	1022	/* NOTE : This function Should not be modified, when the callback is needed,
elessair	0:7e2bd16f80af	1023	the HAL_TIM_PWM_MspInit could be implemented in the user file
elessair	0:7e2bd16f80af	1024	*/
elessair	0:7e2bd16f80af	1025	}
elessair	0:7e2bd16f80af	1026
elessair	0:7e2bd16f80af	1027	/**
elessair	0:7e2bd16f80af	1028	* @brief DeInitializes TIM PWM MSP.
elessair	0:7e2bd16f80af	1029	* @param htim: TIM handle
elessair	0:7e2bd16f80af	1030	* @retval None
elessair	0:7e2bd16f80af	1031	*/
elessair	0:7e2bd16f80af	1032	__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
elessair	0:7e2bd16f80af	1033	{
elessair	0:7e2bd16f80af	1034	/* NOTE : This function Should not be modified, when the callback is needed,
elessair	0:7e2bd16f80af	1035	the HAL_TIM_PWM_MspDeInit could be implemented in the user file
elessair	0:7e2bd16f80af	1036	*/
elessair	0:7e2bd16f80af	1037	}
elessair	0:7e2bd16f80af	1038
elessair	0:7e2bd16f80af	1039	/**
elessair	0:7e2bd16f80af	1040	* @brief Starts the PWM signal generation.
elessair	0:7e2bd16f80af	1041	* @param htim : TIM handle
elessair	0:7e2bd16f80af	1042	* @param Channel : TIM Channels to be enabled
elessair	0:7e2bd16f80af	1043	* This parameter can be one of the following values:
elessair	0:7e2bd16f80af	1044	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
elessair	0:7e2bd16f80af	1045	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
elessair	0:7e2bd16f80af	1046	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
elessair	0:7e2bd16f80af	1047	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
elessair	0:7e2bd16f80af	1048	* @retval HAL status
elessair	0:7e2bd16f80af	1049	*/
elessair	0:7e2bd16f80af	1050	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
elessair	0:7e2bd16f80af	1051	{
elessair	0:7e2bd16f80af	1052	/* Check the parameters */
elessair	0:7e2bd16f80af	1053	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
elessair	0:7e2bd16f80af	1054
elessair	0:7e2bd16f80af	1055	/* Enable the Capture compare channel */
elessair	0:7e2bd16f80af	1056	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
elessair	0:7e2bd16f80af	1057
elessair	0:7e2bd16f80af	1058	/* Enable the Peripheral */
elessair	0:7e2bd16f80af	1059	__HAL_TIM_ENABLE(htim);
elessair	0:7e2bd16f80af	1060
elessair	0:7e2bd16f80af	1061	/* Return function status */
elessair	0:7e2bd16f80af	1062	return HAL_OK;
elessair	0:7e2bd16f80af	1063	}
elessair	0:7e2bd16f80af	1064
elessair	0:7e2bd16f80af	1065	/**
elessair	0:7e2bd16f80af	1066	* @brief Stops the PWM signal generation.
elessair	0:7e2bd16f80af	1067	* @param htim : TIM handle
elessair	0:7e2bd16f80af	1068	* @param Channel : TIM Channels to be disabled
elessair	0:7e2bd16f80af	1069	* This parameter can be one of the following values:
elessair	0:7e2bd16f80af	1070	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
elessair	0:7e2bd16f80af	1071	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
elessair	0:7e2bd16f80af	1072	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
elessair	0:7e2bd16f80af	1073	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
elessair	0:7e2bd16f80af	1074	* @retval HAL status
elessair	0:7e2bd16f80af	1075	*/
elessair	0:7e2bd16f80af	1076	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
elessair	0:7e2bd16f80af	1077	{
elessair	0:7e2bd16f80af	1078	/* Check the parameters */
elessair	0:7e2bd16f80af	1079	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
elessair	0:7e2bd16f80af	1080
elessair	0:7e2bd16f80af	1081	/* Disable the Capture compare channel */
elessair	0:7e2bd16f80af	1082	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
elessair	0:7e2bd16f80af	1083
elessair	0:7e2bd16f80af	1084	/* Disable the Peripheral */
elessair	0:7e2bd16f80af	1085	__HAL_TIM_DISABLE(htim);
elessair	0:7e2bd16f80af	1086
elessair	0:7e2bd16f80af	1087	/* Change the htim state */
elessair	0:7e2bd16f80af	1088	htim->State = HAL_TIM_STATE_READY;
elessair	0:7e2bd16f80af	1089
elessair	0:7e2bd16f80af	1090	/* Return function status */
elessair	0:7e2bd16f80af	1091	return HAL_OK;
elessair	0:7e2bd16f80af	1092	}
elessair	0:7e2bd16f80af	1093
elessair	0:7e2bd16f80af	1094	/**
elessair	0:7e2bd16f80af	1095	* @brief Starts the PWM signal generation in interrupt mode.
elessair	0:7e2bd16f80af	1096	* @param htim : TIM handle
elessair	0:7e2bd16f80af	1097	* @param Channel : TIM Channel to be disabled
elessair	0:7e2bd16f80af	1098	* This parameter can be one of the following values:
elessair	0:7e2bd16f80af	1099	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
elessair	0:7e2bd16f80af	1100	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
elessair	0:7e2bd16f80af	1101	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
elessair	0:7e2bd16f80af	1102	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
elessair	0:7e2bd16f80af	1103	* @retval HAL status
elessair	0:7e2bd16f80af	1104	*/
elessair	0:7e2bd16f80af	1105	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
elessair	0:7e2bd16f80af	1106	{
elessair	0:7e2bd16f80af	1107	/* Check the parameters */
elessair	0:7e2bd16f80af	1108	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
elessair	0:7e2bd16f80af	1109
elessair	0:7e2bd16f80af	1110	switch (Channel)
elessair	0:7e2bd16f80af	1111	{
elessair	0:7e2bd16f80af	1112	case TIM_CHANNEL_1:
elessair	0:7e2bd16f80af	1113	{
elessair	0:7e2bd16f80af	1114	/* Enable the TIM Capture/Compare 1 interrupt */
elessair	0:7e2bd16f80af	1115	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
elessair	0:7e2bd16f80af	1116	}
elessair	0:7e2bd16f80af	1117	break;
elessair	0:7e2bd16f80af	1118
elessair	0:7e2bd16f80af	1119	case TIM_CHANNEL_2:
elessair	0:7e2bd16f80af	1120	{
elessair	0:7e2bd16f80af	1121	/* Enable the TIM Capture/Compare 2 interrupt */
elessair	0:7e2bd16f80af	1122	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
elessair	0:7e2bd16f80af	1123	}
elessair	0:7e2bd16f80af	1124	break;
elessair	0:7e2bd16f80af	1125
elessair	0:7e2bd16f80af	1126	case TIM_CHANNEL_3:
elessair	0:7e2bd16f80af	1127	{
elessair	0:7e2bd16f80af	1128	/* Enable the TIM Capture/Compare 3 interrupt */
elessair	0:7e2bd16f80af	1129	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
elessair	0:7e2bd16f80af	1130	}
elessair	0:7e2bd16f80af	1131	break;
elessair	0:7e2bd16f80af	1132
elessair	0:7e2bd16f80af	1133	case TIM_CHANNEL_4:
elessair	0:7e2bd16f80af	1134	{
elessair	0:7e2bd16f80af	1135	/* Enable the TIM Capture/Compare 4 interrupt */
elessair	0:7e2bd16f80af	1136	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
elessair	0:7e2bd16f80af	1137	}
elessair	0:7e2bd16f80af	1138	break;
elessair	0:7e2bd16f80af	1139
elessair	0:7e2bd16f80af	1140	default:
elessair	0:7e2bd16f80af	1141	break;
elessair	0:7e2bd16f80af	1142	}
elessair	0:7e2bd16f80af	1143
elessair	0:7e2bd16f80af	1144	/* Enable the Capture compare channel */
elessair	0:7e2bd16f80af	1145	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
elessair	0:7e2bd16f80af	1146
elessair	0:7e2bd16f80af	1147	/* Enable the Peripheral */
elessair	0:7e2bd16f80af	1148	__HAL_TIM_ENABLE(htim);
elessair	0:7e2bd16f80af	1149
elessair	0:7e2bd16f80af	1150	/* Return function status */
elessair	0:7e2bd16f80af	1151	return HAL_OK;
elessair	0:7e2bd16f80af	1152	}
elessair	0:7e2bd16f80af	1153
elessair	0:7e2bd16f80af	1154	/**
elessair	0:7e2bd16f80af	1155	* @brief Stops the PWM signal generation in interrupt mode.
elessair	0:7e2bd16f80af	1156	* @param htim : TIM handle
elessair	0:7e2bd16f80af	1157	* @param Channel : TIM Channels to be disabled
elessair	0:7e2bd16f80af	1158	* This parameter can be one of the following values:
elessair	0:7e2bd16f80af	1159	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
elessair	0:7e2bd16f80af	1160	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
elessair	0:7e2bd16f80af	1161	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
elessair	0:7e2bd16f80af	1162	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
elessair	0:7e2bd16f80af	1163	* @retval HAL status
elessair	0:7e2bd16f80af	1164	*/
elessair	0:7e2bd16f80af	1165	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
elessair	0:7e2bd16f80af	1166	{
elessair	0:7e2bd16f80af	1167	/* Check the parameters */
elessair	0:7e2bd16f80af	1168	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
elessair	0:7e2bd16f80af	1169
elessair	0:7e2bd16f80af	1170	switch (Channel)
elessair	0:7e2bd16f80af	1171	{
elessair	0:7e2bd16f80af	1172	case TIM_CHANNEL_1:
elessair	0:7e2bd16f80af	1173	{
elessair	0:7e2bd16f80af	1174	/* Disable the TIM Capture/Compare 1 interrupt */
elessair	0:7e2bd16f80af	1175	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
elessair	0:7e2bd16f80af	1176	}
elessair	0:7e2bd16f80af	1177	break;
elessair	0:7e2bd16f80af	1178
elessair	0:7e2bd16f80af	1179	case TIM_CHANNEL_2:
elessair	0:7e2bd16f80af	1180	{
elessair	0:7e2bd16f80af	1181	/* Disable the TIM Capture/Compare 2 interrupt */
elessair	0:7e2bd16f80af	1182	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
elessair	0:7e2bd16f80af	1183	}
elessair	0:7e2bd16f80af	1184	break;
elessair	0:7e2bd16f80af	1185
elessair	0:7e2bd16f80af	1186	case TIM_CHANNEL_3:
elessair	0:7e2bd16f80af	1187	{
elessair	0:7e2bd16f80af	1188	/* Disable the TIM Capture/Compare 3 interrupt */
elessair	0:7e2bd16f80af	1189	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
elessair	0:7e2bd16f80af	1190	}
elessair	0:7e2bd16f80af	1191	break;
elessair	0:7e2bd16f80af	1192
elessair	0:7e2bd16f80af	1193	case TIM_CHANNEL_4:
elessair	0:7e2bd16f80af	1194	{
elessair	0:7e2bd16f80af	1195	/* Disable the TIM Capture/Compare 4 interrupt */
elessair	0:7e2bd16f80af	1196	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
elessair	0:7e2bd16f80af	1197	}
elessair	0:7e2bd16f80af	1198	break;
elessair	0:7e2bd16f80af	1199
elessair	0:7e2bd16f80af	1200	default:
elessair	0:7e2bd16f80af	1201	break;
elessair	0:7e2bd16f80af	1202	}
elessair	0:7e2bd16f80af	1203
elessair	0:7e2bd16f80af	1204	/* Disable the Capture compare channel */
elessair	0:7e2bd16f80af	1205	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
elessair	0:7e2bd16f80af	1206
elessair	0:7e2bd16f80af	1207
elessair	0:7e2bd16f80af	1208	/* Disable the Peripheral */
elessair	0:7e2bd16f80af	1209	__HAL_TIM_DISABLE(htim);
elessair	0:7e2bd16f80af	1210
elessair	0:7e2bd16f80af	1211	/* Return function status */
elessair	0:7e2bd16f80af	1212	return HAL_OK;
elessair	0:7e2bd16f80af	1213	}
elessair	0:7e2bd16f80af	1214
elessair	0:7e2bd16f80af	1215	/**
elessair	0:7e2bd16f80af	1216	* @brief Starts the TIM PWM signal generation in DMA mode.
elessair	0:7e2bd16f80af	1217	* @param htim : TIM handle
elessair	0:7e2bd16f80af	1218	* @param Channel : TIM Channels to be enabled
elessair	0:7e2bd16f80af	1219	* This parameter can be one of the following values:
elessair	0:7e2bd16f80af	1220	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
elessair	0:7e2bd16f80af	1221	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
elessair	0:7e2bd16f80af	1222	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
elessair	0:7e2bd16f80af	1223	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
elessair	0:7e2bd16f80af	1224	* @param pData: The source Buffer address.
elessair	0:7e2bd16f80af	1225	* @param Length: The length of data to be transferred from memory to TIM peripheral
elessair	0:7e2bd16f80af	1226	* @retval HAL status
elessair	0:7e2bd16f80af	1227	*/
elessair	0:7e2bd16f80af	1228	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
elessair	0:7e2bd16f80af	1229	{
elessair	0:7e2bd16f80af	1230	/* Check the parameters */
elessair	0:7e2bd16f80af	1231	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
elessair	0:7e2bd16f80af	1232
elessair	0:7e2bd16f80af	1233	if((htim->State == HAL_TIM_STATE_BUSY))
elessair	0:7e2bd16f80af	1234	{
elessair	0:7e2bd16f80af	1235	return HAL_BUSY;
elessair	0:7e2bd16f80af	1236	}
elessair	0:7e2bd16f80af	1237	else if((htim->State == HAL_TIM_STATE_READY))
elessair	0:7e2bd16f80af	1238	{
elessair	0:7e2bd16f80af	1239	if(((uint32_t)pData == 0 ) && (Length > 0))
elessair	0:7e2bd16f80af	1240	{
elessair	0:7e2bd16f80af	1241	return HAL_ERROR;
elessair	0:7e2bd16f80af	1242	}
elessair	0:7e2bd16f80af	1243	else
elessair	0:7e2bd16f80af	1244	{
elessair	0:7e2bd16f80af	1245	htim->State = HAL_TIM_STATE_BUSY;
elessair	0:7e2bd16f80af	1246	}
elessair	0:7e2bd16f80af	1247	}
elessair	0:7e2bd16f80af	1248	else
elessair	0:7e2bd16f80af	1249	{
elessair	0:7e2bd16f80af	1250	return HAL_ERROR;
elessair	0:7e2bd16f80af	1251	}
elessair	0:7e2bd16f80af	1252
elessair	0:7e2bd16f80af	1253	switch (Channel)
elessair	0:7e2bd16f80af	1254	{
elessair	0:7e2bd16f80af	1255	case TIM_CHANNEL_1:
elessair	0:7e2bd16f80af	1256	{
elessair	0:7e2bd16f80af	1257	/* Set the DMA Period elapsed callback */
elessair	0:7e2bd16f80af	1258	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
elessair	0:7e2bd16f80af	1259
elessair	0:7e2bd16f80af	1260	/* Set the DMA error callback */
elessair	0:7e2bd16f80af	1261	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
elessair	0:7e2bd16f80af	1262
elessair	0:7e2bd16f80af	1263	/* Enable the DMA channel */
elessair	0:7e2bd16f80af	1264	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
elessair	0:7e2bd16f80af	1265
elessair	0:7e2bd16f80af	1266	/* Enable the TIM Capture/Compare 1 DMA request */
elessair	0:7e2bd16f80af	1267	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
elessair	0:7e2bd16f80af	1268	}
elessair	0:7e2bd16f80af	1269	break;
elessair	0:7e2bd16f80af	1270
elessair	0:7e2bd16f80af	1271	case TIM_CHANNEL_2:
elessair	0:7e2bd16f80af	1272	{
elessair	0:7e2bd16f80af	1273	/* Set the DMA Period elapsed callback */
elessair	0:7e2bd16f80af	1274	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
elessair	0:7e2bd16f80af	1275
elessair	0:7e2bd16f80af	1276	/* Set the DMA error callback */
elessair	0:7e2bd16f80af	1277	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
elessair	0:7e2bd16f80af	1278
elessair	0:7e2bd16f80af	1279	/* Enable the DMA channel */
elessair	0:7e2bd16f80af	1280	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
elessair	0:7e2bd16f80af	1281
elessair	0:7e2bd16f80af	1282	/* Enable the TIM Capture/Compare 2 DMA request */
elessair	0:7e2bd16f80af	1283	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
elessair	0:7e2bd16f80af	1284	}
elessair	0:7e2bd16f80af	1285	break;
elessair	0:7e2bd16f80af	1286
elessair	0:7e2bd16f80af	1287	case TIM_CHANNEL_3:
elessair	0:7e2bd16f80af	1288	{
elessair	0:7e2bd16f80af	1289	/* Set the DMA Period elapsed callback */
elessair	0:7e2bd16f80af	1290	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
elessair	0:7e2bd16f80af	1291
elessair	0:7e2bd16f80af	1292	/* Set the DMA error callback */
elessair	0:7e2bd16f80af	1293	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
elessair	0:7e2bd16f80af	1294
elessair	0:7e2bd16f80af	1295	/* Enable the DMA channel */
elessair	0:7e2bd16f80af	1296	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
elessair	0:7e2bd16f80af	1297
elessair	0:7e2bd16f80af	1298	/* Enable the TIM Output Capture/Compare 3 request */
elessair	0:7e2bd16f80af	1299	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
elessair	0:7e2bd16f80af	1300	}
elessair	0:7e2bd16f80af	1301	break;
elessair	0:7e2bd16f80af	1302
elessair	0:7e2bd16f80af	1303	case TIM_CHANNEL_4:
elessair	0:7e2bd16f80af	1304	{
elessair	0:7e2bd16f80af	1305	/* Set the DMA Period elapsed callback */
elessair	0:7e2bd16f80af	1306	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
elessair	0:7e2bd16f80af	1307
elessair	0:7e2bd16f80af	1308	/* Set the DMA error callback */
elessair	0:7e2bd16f80af	1309	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
elessair	0:7e2bd16f80af	1310
elessair	0:7e2bd16f80af	1311	/* Enable the DMA channel */
elessair	0:7e2bd16f80af	1312	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
elessair	0:7e2bd16f80af	1313
elessair	0:7e2bd16f80af	1314	/* Enable the TIM Capture/Compare 4 DMA request */
elessair	0:7e2bd16f80af	1315	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
elessair	0:7e2bd16f80af	1316	}
elessair	0:7e2bd16f80af	1317	break;
elessair	0:7e2bd16f80af	1318
elessair	0:7e2bd16f80af	1319	default:
elessair	0:7e2bd16f80af	1320	break;
elessair	0:7e2bd16f80af	1321	}
elessair	0:7e2bd16f80af	1322
elessair	0:7e2bd16f80af	1323	/* Enable the Capture compare channel */
elessair	0:7e2bd16f80af	1324	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
elessair	0:7e2bd16f80af	1325
elessair	0:7e2bd16f80af	1326	/* Enable the Peripheral */
elessair	0:7e2bd16f80af	1327	__HAL_TIM_ENABLE(htim);
elessair	0:7e2bd16f80af	1328
elessair	0:7e2bd16f80af	1329	/* Return function status */
elessair	0:7e2bd16f80af	1330	return HAL_OK;
elessair	0:7e2bd16f80af	1331	}
elessair	0:7e2bd16f80af	1332
elessair	0:7e2bd16f80af	1333	/**
elessair	0:7e2bd16f80af	1334	* @brief Stops the TIM PWM signal generation in DMA mode.
elessair	0:7e2bd16f80af	1335	* @param htim : TIM handle
elessair	0:7e2bd16f80af	1336	* @param Channel : TIM Channels to be disabled
elessair	0:7e2bd16f80af	1337	* This parameter can be one of the following values:
elessair	0:7e2bd16f80af	1338	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
elessair	0:7e2bd16f80af	1339	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
elessair	0:7e2bd16f80af	1340	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
elessair	0:7e2bd16f80af	1341	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
elessair	0:7e2bd16f80af	1342	* @retval HAL status
elessair	0:7e2bd16f80af	1343	*/
elessair	0:7e2bd16f80af	1344	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
elessair	0:7e2bd16f80af	1345	{
elessair	0:7e2bd16f80af	1346	/* Check the parameters */
elessair	0:7e2bd16f80af	1347	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
elessair	0:7e2bd16f80af	1348
elessair	0:7e2bd16f80af	1349	switch (Channel)
elessair	0:7e2bd16f80af	1350	{
elessair	0:7e2bd16f80af	1351	case TIM_CHANNEL_1:
elessair	0:7e2bd16f80af	1352	{
elessair	0:7e2bd16f80af	1353	/* Disable the TIM Capture/Compare 1 DMA request */
elessair	0:7e2bd16f80af	1354	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
elessair	0:7e2bd16f80af	1355	}
elessair	0:7e2bd16f80af	1356	break;
elessair	0:7e2bd16f80af	1357
elessair	0:7e2bd16f80af	1358	case TIM_CHANNEL_2:
elessair	0:7e2bd16f80af	1359	{
elessair	0:7e2bd16f80af	1360	/* Disable the TIM Capture/Compare 2 DMA request */
elessair	0:7e2bd16f80af	1361	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
elessair	0:7e2bd16f80af	1362	}
elessair	0:7e2bd16f80af	1363	break;
elessair	0:7e2bd16f80af	1364
elessair	0:7e2bd16f80af	1365	case TIM_CHANNEL_3:
elessair	0:7e2bd16f80af	1366	{
elessair	0:7e2bd16f80af	1367	/* Disable the TIM Capture/Compare 3 DMA request */
elessair	0:7e2bd16f80af	1368	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
elessair	0:7e2bd16f80af	1369	}
elessair	0:7e2bd16f80af	1370	break;
elessair	0:7e2bd16f80af	1371
elessair	0:7e2bd16f80af	1372	case TIM_CHANNEL_4:
elessair	0:7e2bd16f80af	1373	{
elessair	0:7e2bd16f80af	1374	/* Disable the TIM Capture/Compare 4 interrupt */
elessair	0:7e2bd16f80af	1375	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
elessair	0:7e2bd16f80af	1376	}
elessair	0:7e2bd16f80af	1377	break;
elessair	0:7e2bd16f80af	1378
elessair	0:7e2bd16f80af	1379	default:
elessair	0:7e2bd16f80af	1380	break;
elessair	0:7e2bd16f80af	1381	}
elessair	0:7e2bd16f80af	1382
elessair	0:7e2bd16f80af	1383	/* Disable the Capture compare channel */
elessair	0:7e2bd16f80af	1384	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
elessair	0:7e2bd16f80af	1385
elessair	0:7e2bd16f80af	1386	/* Disable the Peripheral */
elessair	0:7e2bd16f80af	1387	__HAL_TIM_DISABLE(htim);
elessair	0:7e2bd16f80af	1388
elessair	0:7e2bd16f80af	1389	/* Change the htim state */
elessair	0:7e2bd16f80af	1390	htim->State = HAL_TIM_STATE_READY;
elessair	0:7e2bd16f80af	1391
elessair	0:7e2bd16f80af	1392	/* Return function status */
elessair	0:7e2bd16f80af	1393	return HAL_OK;
elessair	0:7e2bd16f80af	1394	}
elessair	0:7e2bd16f80af	1395
elessair	0:7e2bd16f80af	1396	/**
elessair	0:7e2bd16f80af	1397	* @}
elessair	0:7e2bd16f80af	1398	*/
elessair	0:7e2bd16f80af	1399
elessair	0:7e2bd16f80af	1400	/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
elessair	0:7e2bd16f80af	1401	* @brief Time Input Capture functions
elessair	0:7e2bd16f80af	1402	*
elessair	0:7e2bd16f80af	1403	@verbatim
elessair	0:7e2bd16f80af	1404	==============================================================================
elessair	0:7e2bd16f80af	1405	##### Time Input Capture functions #####
elessair	0:7e2bd16f80af	1406	==============================================================================
elessair	0:7e2bd16f80af	1407	[..]
elessair	0:7e2bd16f80af	1408	This section provides functions allowing to:
elessair	0:7e2bd16f80af	1409	(+) Initialize and configure the TIM Input Capture.
elessair	0:7e2bd16f80af	1410	(+) De-initialize the TIM Input Capture.
elessair	0:7e2bd16f80af	1411	(+) Start the Time Input Capture.
elessair	0:7e2bd16f80af	1412	(+) Stop the Time Input Capture.
elessair	0:7e2bd16f80af	1413	(+) Start the Time Input Capture and enable interrupt.
elessair	0:7e2bd16f80af	1414	(+) Stop the Time Input Capture and disable interrupt.
elessair	0:7e2bd16f80af	1415	(+) Start the Time Input Capture and enable DMA transfer.
elessair	0:7e2bd16f80af	1416	(+) Stop the Time Input Capture and disable DMA transfer.
elessair	0:7e2bd16f80af	1417
elessair	0:7e2bd16f80af	1418	@endverbatim
elessair	0:7e2bd16f80af	1419	* @{
elessair	0:7e2bd16f80af	1420	*/
elessair	0:7e2bd16f80af	1421	/**
elessair	0:7e2bd16f80af	1422	* @brief Initializes the TIM Input Capture Time base according to the specified
elessair	0:7e2bd16f80af	1423	* parameters in the TIM_HandleTypeDef and create the associated handle.
elessair	0:7e2bd16f80af	1424	* @param htim: TIM Input Capture handle
elessair	0:7e2bd16f80af	1425	* @retval HAL status
elessair	0:7e2bd16f80af	1426	*/
elessair	0:7e2bd16f80af	1427	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
elessair	0:7e2bd16f80af	1428	{
elessair	0:7e2bd16f80af	1429	/* Check the TIM handle allocation */
elessair	0:7e2bd16f80af	1430	if(htim == HAL_NULL)
elessair	0:7e2bd16f80af	1431	{
elessair	0:7e2bd16f80af	1432	return HAL_ERROR;
elessair	0:7e2bd16f80af	1433	}
elessair	0:7e2bd16f80af	1434
elessair	0:7e2bd16f80af	1435	/* Check the parameters */
elessair	0:7e2bd16f80af	1436	assert_param(IS_TIM_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	1437	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
elessair	0:7e2bd16f80af	1438	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
elessair	0:7e2bd16f80af	1439
elessair	0:7e2bd16f80af	1440	if(htim->State == HAL_TIM_STATE_RESET)
elessair	0:7e2bd16f80af	1441	{
elessair	0:7e2bd16f80af	1442	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
elessair	0:7e2bd16f80af	1443	HAL_TIM_IC_MspInit(htim);
elessair	0:7e2bd16f80af	1444	}
elessair	0:7e2bd16f80af	1445
elessair	0:7e2bd16f80af	1446	/* Set the TIM state */
elessair	0:7e2bd16f80af	1447	htim->State= HAL_TIM_STATE_BUSY;
elessair	0:7e2bd16f80af	1448
elessair	0:7e2bd16f80af	1449	/* Init the base time for the input capture */
elessair	0:7e2bd16f80af	1450	TIM_Base_SetConfig(htim->Instance, &htim->Init);
elessair	0:7e2bd16f80af	1451
elessair	0:7e2bd16f80af	1452	/* Initialize the TIM state*/
elessair	0:7e2bd16f80af	1453	htim->State= HAL_TIM_STATE_READY;
elessair	0:7e2bd16f80af	1454
elessair	0:7e2bd16f80af	1455	return HAL_OK;
elessair	0:7e2bd16f80af	1456	}
elessair	0:7e2bd16f80af	1457
elessair	0:7e2bd16f80af	1458	/**
elessair	0:7e2bd16f80af	1459	* @brief DeInitializes the TIM peripheral
elessair	0:7e2bd16f80af	1460	* @param htim: TIM Input Capture handle
elessair	0:7e2bd16f80af	1461	* @retval HAL status
elessair	0:7e2bd16f80af	1462	*/
elessair	0:7e2bd16f80af	1463	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
elessair	0:7e2bd16f80af	1464	{
elessair	0:7e2bd16f80af	1465	/* Check the parameters */
elessair	0:7e2bd16f80af	1466	assert_param(IS_TIM_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	1467
elessair	0:7e2bd16f80af	1468	htim->State = HAL_TIM_STATE_BUSY;
elessair	0:7e2bd16f80af	1469
elessair	0:7e2bd16f80af	1470	/* Disable the TIM Peripheral Clock */
elessair	0:7e2bd16f80af	1471	__HAL_TIM_DISABLE(htim);
elessair	0:7e2bd16f80af	1472
elessair	0:7e2bd16f80af	1473	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
elessair	0:7e2bd16f80af	1474	HAL_TIM_IC_MspDeInit(htim);
elessair	0:7e2bd16f80af	1475
elessair	0:7e2bd16f80af	1476	/* Change TIM state */
elessair	0:7e2bd16f80af	1477	htim->State = HAL_TIM_STATE_RESET;
elessair	0:7e2bd16f80af	1478
elessair	0:7e2bd16f80af	1479	/* Release Lock */
elessair	0:7e2bd16f80af	1480	__HAL_UNLOCK(htim);
elessair	0:7e2bd16f80af	1481
elessair	0:7e2bd16f80af	1482	return HAL_OK;
elessair	0:7e2bd16f80af	1483	}
elessair	0:7e2bd16f80af	1484
elessair	0:7e2bd16f80af	1485	/**
elessair	0:7e2bd16f80af	1486	* @brief Initializes the TIM INput Capture MSP.
elessair	0:7e2bd16f80af	1487	* @param htim: TIM handle
elessair	0:7e2bd16f80af	1488	* @retval None
elessair	0:7e2bd16f80af	1489	*/
elessair	0:7e2bd16f80af	1490	__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
elessair	0:7e2bd16f80af	1491	{
elessair	0:7e2bd16f80af	1492	/* NOTE : This function Should not be modified, when the callback is needed,
elessair	0:7e2bd16f80af	1493	the HAL_TIM_IC_MspInit could be implemented in the user file
elessair	0:7e2bd16f80af	1494	*/
elessair	0:7e2bd16f80af	1495	}
elessair	0:7e2bd16f80af	1496
elessair	0:7e2bd16f80af	1497	/**
elessair	0:7e2bd16f80af	1498	* @brief DeInitializes TIM Input Capture MSP.
elessair	0:7e2bd16f80af	1499	* @param htim: TIM handle
elessair	0:7e2bd16f80af	1500	* @retval None
elessair	0:7e2bd16f80af	1501	*/
elessair	0:7e2bd16f80af	1502	__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
elessair	0:7e2bd16f80af	1503	{
elessair	0:7e2bd16f80af	1504	/* NOTE : This function Should not be modified, when the callback is needed,
elessair	0:7e2bd16f80af	1505	the HAL_TIM_IC_MspDeInit could be implemented in the user file
elessair	0:7e2bd16f80af	1506	*/
elessair	0:7e2bd16f80af	1507	}
elessair	0:7e2bd16f80af	1508
elessair	0:7e2bd16f80af	1509	/**
elessair	0:7e2bd16f80af	1510	* @brief Starts the TIM Input Capture measurement.
elessair	0:7e2bd16f80af	1511	* @param htim : TIM Input Capture handle
elessair	0:7e2bd16f80af	1512	* @param Channel : TIM Channels to be enabled
elessair	0:7e2bd16f80af	1513	* This parameter can be one of the following values:
elessair	0:7e2bd16f80af	1514	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
elessair	0:7e2bd16f80af	1515	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
elessair	0:7e2bd16f80af	1516	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
elessair	0:7e2bd16f80af	1517	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
elessair	0:7e2bd16f80af	1518	* @retval HAL status
elessair	0:7e2bd16f80af	1519	*/
elessair	0:7e2bd16f80af	1520	HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
elessair	0:7e2bd16f80af	1521	{
elessair	0:7e2bd16f80af	1522	/* Check the parameters */
elessair	0:7e2bd16f80af	1523	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
elessair	0:7e2bd16f80af	1524
elessair	0:7e2bd16f80af	1525	/* Enable the Input Capture channel */
elessair	0:7e2bd16f80af	1526	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
elessair	0:7e2bd16f80af	1527
elessair	0:7e2bd16f80af	1528	/* Enable the Peripheral */
elessair	0:7e2bd16f80af	1529	__HAL_TIM_ENABLE(htim);
elessair	0:7e2bd16f80af	1530
elessair	0:7e2bd16f80af	1531	/* Return function status */
elessair	0:7e2bd16f80af	1532	return HAL_OK;
elessair	0:7e2bd16f80af	1533	}
elessair	0:7e2bd16f80af	1534
elessair	0:7e2bd16f80af	1535	/**
elessair	0:7e2bd16f80af	1536	* @brief Stops the TIM Input Capture measurement.
elessair	0:7e2bd16f80af	1537	* @param htim : TIM handle
elessair	0:7e2bd16f80af	1538	* @param Channel : TIM Channels to be disabled
elessair	0:7e2bd16f80af	1539	* This parameter can be one of the following values:
elessair	0:7e2bd16f80af	1540	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
elessair	0:7e2bd16f80af	1541	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
elessair	0:7e2bd16f80af	1542	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
elessair	0:7e2bd16f80af	1543	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
elessair	0:7e2bd16f80af	1544	* @retval HAL status
elessair	0:7e2bd16f80af	1545	*/
elessair	0:7e2bd16f80af	1546	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
elessair	0:7e2bd16f80af	1547	{
elessair	0:7e2bd16f80af	1548	/* Check the parameters */
elessair	0:7e2bd16f80af	1549	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
elessair	0:7e2bd16f80af	1550
elessair	0:7e2bd16f80af	1551	/* Disable the Input Capture channel */
elessair	0:7e2bd16f80af	1552	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
elessair	0:7e2bd16f80af	1553
elessair	0:7e2bd16f80af	1554	/* Disable the Peripheral */
elessair	0:7e2bd16f80af	1555	__HAL_TIM_DISABLE(htim);
elessair	0:7e2bd16f80af	1556
elessair	0:7e2bd16f80af	1557	/* Return function status */
elessair	0:7e2bd16f80af	1558	return HAL_OK;
elessair	0:7e2bd16f80af	1559	}
elessair	0:7e2bd16f80af	1560
elessair	0:7e2bd16f80af	1561	/**
elessair	0:7e2bd16f80af	1562	* @brief Starts the TIM Input Capture measurement in interrupt mode.
elessair	0:7e2bd16f80af	1563	* @param htim : TIM Input Capture handle
elessair	0:7e2bd16f80af	1564	* @param Channel : TIM Channels to be enabled
elessair	0:7e2bd16f80af	1565	* This parameter can be one of the following values:
elessair	0:7e2bd16f80af	1566	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
elessair	0:7e2bd16f80af	1567	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
elessair	0:7e2bd16f80af	1568	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
elessair	0:7e2bd16f80af	1569	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
elessair	0:7e2bd16f80af	1570	* @retval HAL status
elessair	0:7e2bd16f80af	1571	*/
elessair	0:7e2bd16f80af	1572	HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
elessair	0:7e2bd16f80af	1573	{
elessair	0:7e2bd16f80af	1574	/* Check the parameters */
elessair	0:7e2bd16f80af	1575	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
elessair	0:7e2bd16f80af	1576
elessair	0:7e2bd16f80af	1577	switch (Channel)
elessair	0:7e2bd16f80af	1578	{
elessair	0:7e2bd16f80af	1579	case TIM_CHANNEL_1:
elessair	0:7e2bd16f80af	1580	{
elessair	0:7e2bd16f80af	1581	/* Enable the TIM Capture/Compare 1 interrupt */
elessair	0:7e2bd16f80af	1582	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
elessair	0:7e2bd16f80af	1583	}
elessair	0:7e2bd16f80af	1584	break;
elessair	0:7e2bd16f80af	1585
elessair	0:7e2bd16f80af	1586	case TIM_CHANNEL_2:
elessair	0:7e2bd16f80af	1587	{
elessair	0:7e2bd16f80af	1588	/* Enable the TIM Capture/Compare 2 interrupt */
elessair	0:7e2bd16f80af	1589	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
elessair	0:7e2bd16f80af	1590	}
elessair	0:7e2bd16f80af	1591	break;
elessair	0:7e2bd16f80af	1592
elessair	0:7e2bd16f80af	1593	case TIM_CHANNEL_3:
elessair	0:7e2bd16f80af	1594	{
elessair	0:7e2bd16f80af	1595	/* Enable the TIM Capture/Compare 3 interrupt */
elessair	0:7e2bd16f80af	1596	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
elessair	0:7e2bd16f80af	1597	}
elessair	0:7e2bd16f80af	1598	break;
elessair	0:7e2bd16f80af	1599
elessair	0:7e2bd16f80af	1600	case TIM_CHANNEL_4:
elessair	0:7e2bd16f80af	1601	{
elessair	0:7e2bd16f80af	1602	/* Enable the TIM Capture/Compare 4 interrupt */
elessair	0:7e2bd16f80af	1603	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
elessair	0:7e2bd16f80af	1604	}
elessair	0:7e2bd16f80af	1605	break;
elessair	0:7e2bd16f80af	1606
elessair	0:7e2bd16f80af	1607	default:
elessair	0:7e2bd16f80af	1608	break;
elessair	0:7e2bd16f80af	1609	}
elessair	0:7e2bd16f80af	1610	/* Enable the Input Capture channel */
elessair	0:7e2bd16f80af	1611	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
elessair	0:7e2bd16f80af	1612
elessair	0:7e2bd16f80af	1613	/* Enable the Peripheral */
elessair	0:7e2bd16f80af	1614	__HAL_TIM_ENABLE(htim);
elessair	0:7e2bd16f80af	1615
elessair	0:7e2bd16f80af	1616	/* Return function status */
elessair	0:7e2bd16f80af	1617	return HAL_OK;
elessair	0:7e2bd16f80af	1618	}
elessair	0:7e2bd16f80af	1619
elessair	0:7e2bd16f80af	1620	/**
elessair	0:7e2bd16f80af	1621	* @brief Stops the TIM Input Capture measurement in interrupt mode.
elessair	0:7e2bd16f80af	1622	* @param htim : TIM handle
elessair	0:7e2bd16f80af	1623	* @param Channel : TIM Channels to be disabled
elessair	0:7e2bd16f80af	1624	* This parameter can be one of the following values:
elessair	0:7e2bd16f80af	1625	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
elessair	0:7e2bd16f80af	1626	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
elessair	0:7e2bd16f80af	1627	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
elessair	0:7e2bd16f80af	1628	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
elessair	0:7e2bd16f80af	1629	* @retval HAL status
elessair	0:7e2bd16f80af	1630	*/
elessair	0:7e2bd16f80af	1631	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
elessair	0:7e2bd16f80af	1632	{
elessair	0:7e2bd16f80af	1633	/* Check the parameters */
elessair	0:7e2bd16f80af	1634	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
elessair	0:7e2bd16f80af	1635
elessair	0:7e2bd16f80af	1636	switch (Channel)
elessair	0:7e2bd16f80af	1637	{
elessair	0:7e2bd16f80af	1638	case TIM_CHANNEL_1:
elessair	0:7e2bd16f80af	1639	{
elessair	0:7e2bd16f80af	1640	/* Disable the TIM Capture/Compare 1 interrupt */
elessair	0:7e2bd16f80af	1641	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
elessair	0:7e2bd16f80af	1642	}
elessair	0:7e2bd16f80af	1643	break;
elessair	0:7e2bd16f80af	1644
elessair	0:7e2bd16f80af	1645	case TIM_CHANNEL_2:
elessair	0:7e2bd16f80af	1646	{
elessair	0:7e2bd16f80af	1647	/* Disable the TIM Capture/Compare 2 interrupt */
elessair	0:7e2bd16f80af	1648	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
elessair	0:7e2bd16f80af	1649	}
elessair	0:7e2bd16f80af	1650	break;
elessair	0:7e2bd16f80af	1651
elessair	0:7e2bd16f80af	1652	case TIM_CHANNEL_3:
elessair	0:7e2bd16f80af	1653	{
elessair	0:7e2bd16f80af	1654	/* Disable the TIM Capture/Compare 3 interrupt */
elessair	0:7e2bd16f80af	1655	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
elessair	0:7e2bd16f80af	1656	}
elessair	0:7e2bd16f80af	1657	break;
elessair	0:7e2bd16f80af	1658
elessair	0:7e2bd16f80af	1659	case TIM_CHANNEL_4:
elessair	0:7e2bd16f80af	1660	{
elessair	0:7e2bd16f80af	1661	/* Disable the TIM Capture/Compare 4 interrupt */
elessair	0:7e2bd16f80af	1662	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
elessair	0:7e2bd16f80af	1663	}
elessair	0:7e2bd16f80af	1664	break;
elessair	0:7e2bd16f80af	1665
elessair	0:7e2bd16f80af	1666	default:
elessair	0:7e2bd16f80af	1667	break;
elessair	0:7e2bd16f80af	1668	}
elessair	0:7e2bd16f80af	1669
elessair	0:7e2bd16f80af	1670	/* Disable the Input Capture channel */
elessair	0:7e2bd16f80af	1671	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
elessair	0:7e2bd16f80af	1672
elessair	0:7e2bd16f80af	1673	/* Disable the Peripheral */
elessair	0:7e2bd16f80af	1674	__HAL_TIM_DISABLE(htim);
elessair	0:7e2bd16f80af	1675
elessair	0:7e2bd16f80af	1676	/* Return function status */
elessair	0:7e2bd16f80af	1677	return HAL_OK;
elessair	0:7e2bd16f80af	1678	}
elessair	0:7e2bd16f80af	1679
elessair	0:7e2bd16f80af	1680	/**
elessair	0:7e2bd16f80af	1681	* @brief Starts the TIM Input Capture measurement on in DMA mode.
elessair	0:7e2bd16f80af	1682	* @param htim : TIM Input Capture handle
elessair	0:7e2bd16f80af	1683	* @param Channel : TIM Channels to be enabled
elessair	0:7e2bd16f80af	1684	* This parameter can be one of the following values:
elessair	0:7e2bd16f80af	1685	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
elessair	0:7e2bd16f80af	1686	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
elessair	0:7e2bd16f80af	1687	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
elessair	0:7e2bd16f80af	1688	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
elessair	0:7e2bd16f80af	1689	* @param pData: The destination Buffer address.
elessair	0:7e2bd16f80af	1690	* @param Length: The length of data to be transferred from TIM peripheral to memory.
elessair	0:7e2bd16f80af	1691	* @retval HAL status
elessair	0:7e2bd16f80af	1692	*/
elessair	0:7e2bd16f80af	1693	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
elessair	0:7e2bd16f80af	1694	{
elessair	0:7e2bd16f80af	1695	/* Check the parameters */
elessair	0:7e2bd16f80af	1696	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
elessair	0:7e2bd16f80af	1697	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	1698
elessair	0:7e2bd16f80af	1699	if((htim->State == HAL_TIM_STATE_BUSY))
elessair	0:7e2bd16f80af	1700	{
elessair	0:7e2bd16f80af	1701	return HAL_BUSY;
elessair	0:7e2bd16f80af	1702	}
elessair	0:7e2bd16f80af	1703	else if((htim->State == HAL_TIM_STATE_READY))
elessair	0:7e2bd16f80af	1704	{
elessair	0:7e2bd16f80af	1705	if((pData == 0 ) && (Length > 0))
elessair	0:7e2bd16f80af	1706	{
elessair	0:7e2bd16f80af	1707	return HAL_ERROR;
elessair	0:7e2bd16f80af	1708	}
elessair	0:7e2bd16f80af	1709	else
elessair	0:7e2bd16f80af	1710	{
elessair	0:7e2bd16f80af	1711	htim->State = HAL_TIM_STATE_BUSY;
elessair	0:7e2bd16f80af	1712	}
elessair	0:7e2bd16f80af	1713	}
elessair	0:7e2bd16f80af	1714	else
elessair	0:7e2bd16f80af	1715	{
elessair	0:7e2bd16f80af	1716	return HAL_ERROR;
elessair	0:7e2bd16f80af	1717	}
elessair	0:7e2bd16f80af	1718
elessair	0:7e2bd16f80af	1719	switch (Channel)
elessair	0:7e2bd16f80af	1720	{
elessair	0:7e2bd16f80af	1721	case TIM_CHANNEL_1:
elessair	0:7e2bd16f80af	1722	{
elessair	0:7e2bd16f80af	1723	/* Set the DMA Period elapsed callback */
elessair	0:7e2bd16f80af	1724	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
elessair	0:7e2bd16f80af	1725
elessair	0:7e2bd16f80af	1726	/* Set the DMA error callback */
elessair	0:7e2bd16f80af	1727	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
elessair	0:7e2bd16f80af	1728
elessair	0:7e2bd16f80af	1729	/* Enable the DMA channel */
elessair	0:7e2bd16f80af	1730	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
elessair	0:7e2bd16f80af	1731
elessair	0:7e2bd16f80af	1732	/* Enable the TIM Capture/Compare 1 DMA request */
elessair	0:7e2bd16f80af	1733	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
elessair	0:7e2bd16f80af	1734	}
elessair	0:7e2bd16f80af	1735	break;
elessair	0:7e2bd16f80af	1736
elessair	0:7e2bd16f80af	1737	case TIM_CHANNEL_2:
elessair	0:7e2bd16f80af	1738	{
elessair	0:7e2bd16f80af	1739	/* Set the DMA Period elapsed callback */
elessair	0:7e2bd16f80af	1740	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
elessair	0:7e2bd16f80af	1741
elessair	0:7e2bd16f80af	1742	/* Set the DMA error callback */
elessair	0:7e2bd16f80af	1743	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
elessair	0:7e2bd16f80af	1744
elessair	0:7e2bd16f80af	1745	/* Enable the DMA channel */
elessair	0:7e2bd16f80af	1746	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
elessair	0:7e2bd16f80af	1747
elessair	0:7e2bd16f80af	1748	/* Enable the TIM Capture/Compare 2 DMA request */
elessair	0:7e2bd16f80af	1749	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
elessair	0:7e2bd16f80af	1750	}
elessair	0:7e2bd16f80af	1751	break;
elessair	0:7e2bd16f80af	1752
elessair	0:7e2bd16f80af	1753	case TIM_CHANNEL_3:
elessair	0:7e2bd16f80af	1754	{
elessair	0:7e2bd16f80af	1755	/* Set the DMA Period elapsed callback */
elessair	0:7e2bd16f80af	1756	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
elessair	0:7e2bd16f80af	1757
elessair	0:7e2bd16f80af	1758	/* Set the DMA error callback */
elessair	0:7e2bd16f80af	1759	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
elessair	0:7e2bd16f80af	1760
elessair	0:7e2bd16f80af	1761	/* Enable the DMA channel */
elessair	0:7e2bd16f80af	1762	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
elessair	0:7e2bd16f80af	1763
elessair	0:7e2bd16f80af	1764	/* Enable the TIM Capture/Compare 3 DMA request */
elessair	0:7e2bd16f80af	1765	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
elessair	0:7e2bd16f80af	1766	}
elessair	0:7e2bd16f80af	1767	break;
elessair	0:7e2bd16f80af	1768
elessair	0:7e2bd16f80af	1769	case TIM_CHANNEL_4:
elessair	0:7e2bd16f80af	1770	{
elessair	0:7e2bd16f80af	1771	/* Set the DMA Period elapsed callback */
elessair	0:7e2bd16f80af	1772	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
elessair	0:7e2bd16f80af	1773
elessair	0:7e2bd16f80af	1774	/* Set the DMA error callback */
elessair	0:7e2bd16f80af	1775	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
elessair	0:7e2bd16f80af	1776
elessair	0:7e2bd16f80af	1777	/* Enable the DMA channel */
elessair	0:7e2bd16f80af	1778	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
elessair	0:7e2bd16f80af	1779
elessair	0:7e2bd16f80af	1780	/* Enable the TIM Capture/Compare 4 DMA request */
elessair	0:7e2bd16f80af	1781	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
elessair	0:7e2bd16f80af	1782	}
elessair	0:7e2bd16f80af	1783	break;
elessair	0:7e2bd16f80af	1784
elessair	0:7e2bd16f80af	1785	default:
elessair	0:7e2bd16f80af	1786	break;
elessair	0:7e2bd16f80af	1787	}
elessair	0:7e2bd16f80af	1788
elessair	0:7e2bd16f80af	1789	/* Enable the Input Capture channel */
elessair	0:7e2bd16f80af	1790	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
elessair	0:7e2bd16f80af	1791
elessair	0:7e2bd16f80af	1792	/* Enable the Peripheral */
elessair	0:7e2bd16f80af	1793	__HAL_TIM_ENABLE(htim);
elessair	0:7e2bd16f80af	1794
elessair	0:7e2bd16f80af	1795	/* Return function status */
elessair	0:7e2bd16f80af	1796	return HAL_OK;
elessair	0:7e2bd16f80af	1797	}
elessair	0:7e2bd16f80af	1798
elessair	0:7e2bd16f80af	1799	/**
elessair	0:7e2bd16f80af	1800	* @brief Stops the TIM Input Capture measurement on in DMA mode.
elessair	0:7e2bd16f80af	1801	* @param htim : TIM Input Capture handle
elessair	0:7e2bd16f80af	1802	* @param Channel : TIM Channels to be disabled
elessair	0:7e2bd16f80af	1803	* This parameter can be one of the following values:
elessair	0:7e2bd16f80af	1804	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
elessair	0:7e2bd16f80af	1805	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
elessair	0:7e2bd16f80af	1806	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
elessair	0:7e2bd16f80af	1807	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
elessair	0:7e2bd16f80af	1808	* @retval HAL status
elessair	0:7e2bd16f80af	1809	*/
elessair	0:7e2bd16f80af	1810	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
elessair	0:7e2bd16f80af	1811	{
elessair	0:7e2bd16f80af	1812	/* Check the parameters */
elessair	0:7e2bd16f80af	1813	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
elessair	0:7e2bd16f80af	1814	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	1815
elessair	0:7e2bd16f80af	1816	switch (Channel)
elessair	0:7e2bd16f80af	1817	{
elessair	0:7e2bd16f80af	1818	case TIM_CHANNEL_1:
elessair	0:7e2bd16f80af	1819	{
elessair	0:7e2bd16f80af	1820	/* Disable the TIM Capture/Compare 1 DMA request */
elessair	0:7e2bd16f80af	1821	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
elessair	0:7e2bd16f80af	1822	}
elessair	0:7e2bd16f80af	1823	break;
elessair	0:7e2bd16f80af	1824
elessair	0:7e2bd16f80af	1825	case TIM_CHANNEL_2:
elessair	0:7e2bd16f80af	1826	{
elessair	0:7e2bd16f80af	1827	/* Disable the TIM Capture/Compare 2 DMA request */
elessair	0:7e2bd16f80af	1828	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
elessair	0:7e2bd16f80af	1829	}
elessair	0:7e2bd16f80af	1830	break;
elessair	0:7e2bd16f80af	1831
elessair	0:7e2bd16f80af	1832	case TIM_CHANNEL_3:
elessair	0:7e2bd16f80af	1833	{
elessair	0:7e2bd16f80af	1834	/* Disable the TIM Capture/Compare 3 DMA request */
elessair	0:7e2bd16f80af	1835	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
elessair	0:7e2bd16f80af	1836	}
elessair	0:7e2bd16f80af	1837	break;
elessair	0:7e2bd16f80af	1838
elessair	0:7e2bd16f80af	1839	case TIM_CHANNEL_4:
elessair	0:7e2bd16f80af	1840	{
elessair	0:7e2bd16f80af	1841	/* Disable the TIM Capture/Compare 4 DMA request */
elessair	0:7e2bd16f80af	1842	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
elessair	0:7e2bd16f80af	1843	}
elessair	0:7e2bd16f80af	1844	break;
elessair	0:7e2bd16f80af	1845
elessair	0:7e2bd16f80af	1846	default:
elessair	0:7e2bd16f80af	1847	break;
elessair	0:7e2bd16f80af	1848	}
elessair	0:7e2bd16f80af	1849
elessair	0:7e2bd16f80af	1850	/* Disable the Input Capture channel */
elessair	0:7e2bd16f80af	1851	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
elessair	0:7e2bd16f80af	1852
elessair	0:7e2bd16f80af	1853	/* Disable the Peripheral */
elessair	0:7e2bd16f80af	1854	__HAL_TIM_DISABLE(htim);
elessair	0:7e2bd16f80af	1855
elessair	0:7e2bd16f80af	1856	/* Change the htim state */
elessair	0:7e2bd16f80af	1857	htim->State = HAL_TIM_STATE_READY;
elessair	0:7e2bd16f80af	1858
elessair	0:7e2bd16f80af	1859	/* Return function status */
elessair	0:7e2bd16f80af	1860	return HAL_OK;
elessair	0:7e2bd16f80af	1861	}
elessair	0:7e2bd16f80af	1862	/**
elessair	0:7e2bd16f80af	1863	* @}
elessair	0:7e2bd16f80af	1864	*/
elessair	0:7e2bd16f80af	1865
elessair	0:7e2bd16f80af	1866	/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
elessair	0:7e2bd16f80af	1867	* @brief Time One Pulse functions
elessair	0:7e2bd16f80af	1868	*
elessair	0:7e2bd16f80af	1869	@verbatim
elessair	0:7e2bd16f80af	1870	==============================================================================
elessair	0:7e2bd16f80af	1871	##### Time One Pulse functions #####
elessair	0:7e2bd16f80af	1872	==============================================================================
elessair	0:7e2bd16f80af	1873	[..]
elessair	0:7e2bd16f80af	1874	This section provides functions allowing to:
elessair	0:7e2bd16f80af	1875	(+) Initialize and configure the TIM One Pulse.
elessair	0:7e2bd16f80af	1876	(+) De-initialize the TIM One Pulse.
elessair	0:7e2bd16f80af	1877	(+) Start the Time One Pulse.
elessair	0:7e2bd16f80af	1878	(+) Stop the Time One Pulse.
elessair	0:7e2bd16f80af	1879	(+) Start the Time One Pulse and enable interrupt.
elessair	0:7e2bd16f80af	1880	(+) Stop the Time One Pulse and disable interrupt.
elessair	0:7e2bd16f80af	1881	(+) Start the Time One Pulse and enable DMA transfer.
elessair	0:7e2bd16f80af	1882	(+) Stop the Time One Pulse and disable DMA transfer.
elessair	0:7e2bd16f80af	1883
elessair	0:7e2bd16f80af	1884	@endverbatim
elessair	0:7e2bd16f80af	1885	* @{
elessair	0:7e2bd16f80af	1886	*/
elessair	0:7e2bd16f80af	1887	/**
elessair	0:7e2bd16f80af	1888	* @brief Initializes the TIM One Pulse Time Base according to the specified
elessair	0:7e2bd16f80af	1889	* parameters in the TIM_HandleTypeDef and create the associated handle.
elessair	0:7e2bd16f80af	1890	* @param htim: TIM OnePulse handle
elessair	0:7e2bd16f80af	1891	* @param OnePulseMode: Select the One pulse mode.
elessair	0:7e2bd16f80af	1892	* This parameter can be one of the following values:
elessair	0:7e2bd16f80af	1893	* @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
elessair	0:7e2bd16f80af	1894	* @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated.
elessair	0:7e2bd16f80af	1895	* @retval HAL status
elessair	0:7e2bd16f80af	1896	*/
elessair	0:7e2bd16f80af	1897	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
elessair	0:7e2bd16f80af	1898	{
elessair	0:7e2bd16f80af	1899	/* Check the TIM handle allocation */
elessair	0:7e2bd16f80af	1900	if(htim == HAL_NULL)
elessair	0:7e2bd16f80af	1901	{
elessair	0:7e2bd16f80af	1902	return HAL_ERROR;
elessair	0:7e2bd16f80af	1903	}
elessair	0:7e2bd16f80af	1904
elessair	0:7e2bd16f80af	1905	/* Check the parameters */
elessair	0:7e2bd16f80af	1906	assert_param(IS_TIM_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	1907	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
elessair	0:7e2bd16f80af	1908	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
elessair	0:7e2bd16f80af	1909	assert_param(IS_TIM_OPM_MODE(OnePulseMode));
elessair	0:7e2bd16f80af	1910
elessair	0:7e2bd16f80af	1911	if(htim->State == HAL_TIM_STATE_RESET)
elessair	0:7e2bd16f80af	1912	{
elessair	0:7e2bd16f80af	1913	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
elessair	0:7e2bd16f80af	1914	HAL_TIM_OnePulse_MspInit(htim);
elessair	0:7e2bd16f80af	1915	}
elessair	0:7e2bd16f80af	1916
elessair	0:7e2bd16f80af	1917	/* Set the TIM state */
elessair	0:7e2bd16f80af	1918	htim->State= HAL_TIM_STATE_BUSY;
elessair	0:7e2bd16f80af	1919
elessair	0:7e2bd16f80af	1920	/* Configure the Time base in the One Pulse Mode */
elessair	0:7e2bd16f80af	1921	TIM_Base_SetConfig(htim->Instance, &htim->Init);
elessair	0:7e2bd16f80af	1922
elessair	0:7e2bd16f80af	1923	/* Reset the OPM Bit */
elessair	0:7e2bd16f80af	1924	htim->Instance->CR1 &= ~TIM_CR1_OPM;
elessair	0:7e2bd16f80af	1925
elessair	0:7e2bd16f80af	1926	/* Configure the OPM Mode */
elessair	0:7e2bd16f80af	1927	htim->Instance->CR1 \|= OnePulseMode;
elessair	0:7e2bd16f80af	1928
elessair	0:7e2bd16f80af	1929	/* Initialize the TIM state*/
elessair	0:7e2bd16f80af	1930	htim->State= HAL_TIM_STATE_READY;
elessair	0:7e2bd16f80af	1931
elessair	0:7e2bd16f80af	1932	return HAL_OK;
elessair	0:7e2bd16f80af	1933	}
elessair	0:7e2bd16f80af	1934
elessair	0:7e2bd16f80af	1935	/**
elessair	0:7e2bd16f80af	1936	* @brief DeInitializes the TIM One Pulse
elessair	0:7e2bd16f80af	1937	* @param htim: TIM One Pulse handle
elessair	0:7e2bd16f80af	1938	* @retval HAL status
elessair	0:7e2bd16f80af	1939	*/
elessair	0:7e2bd16f80af	1940	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
elessair	0:7e2bd16f80af	1941	{
elessair	0:7e2bd16f80af	1942	/* Check the parameters */
elessair	0:7e2bd16f80af	1943	assert_param(IS_TIM_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	1944
elessair	0:7e2bd16f80af	1945	htim->State = HAL_TIM_STATE_BUSY;
elessair	0:7e2bd16f80af	1946
elessair	0:7e2bd16f80af	1947	/* Disable the TIM Peripheral Clock */
elessair	0:7e2bd16f80af	1948	__HAL_TIM_DISABLE(htim);
elessair	0:7e2bd16f80af	1949
elessair	0:7e2bd16f80af	1950	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
elessair	0:7e2bd16f80af	1951	HAL_TIM_OnePulse_MspDeInit(htim);
elessair	0:7e2bd16f80af	1952
elessair	0:7e2bd16f80af	1953	/* Change TIM state */
elessair	0:7e2bd16f80af	1954	htim->State = HAL_TIM_STATE_RESET;
elessair	0:7e2bd16f80af	1955
elessair	0:7e2bd16f80af	1956	/* Release Lock */
elessair	0:7e2bd16f80af	1957	__HAL_UNLOCK(htim);
elessair	0:7e2bd16f80af	1958
elessair	0:7e2bd16f80af	1959	return HAL_OK;
elessair	0:7e2bd16f80af	1960	}
elessair	0:7e2bd16f80af	1961
elessair	0:7e2bd16f80af	1962	/**
elessair	0:7e2bd16f80af	1963	* @brief Initializes the TIM One Pulse MSP.
elessair	0:7e2bd16f80af	1964	* @param htim: TIM handle
elessair	0:7e2bd16f80af	1965	* @retval None
elessair	0:7e2bd16f80af	1966	*/
elessair	0:7e2bd16f80af	1967	__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
elessair	0:7e2bd16f80af	1968	{
elessair	0:7e2bd16f80af	1969	/* NOTE : This function Should not be modified, when the callback is needed,
elessair	0:7e2bd16f80af	1970	the HAL_TIM_OnePulse_MspInit could be implemented in the user file
elessair	0:7e2bd16f80af	1971	*/
elessair	0:7e2bd16f80af	1972	}
elessair	0:7e2bd16f80af	1973
elessair	0:7e2bd16f80af	1974	/**
elessair	0:7e2bd16f80af	1975	* @brief DeInitializes TIM One Pulse MSP.
elessair	0:7e2bd16f80af	1976	* @param htim: TIM handle
elessair	0:7e2bd16f80af	1977	* @retval None
elessair	0:7e2bd16f80af	1978	*/
elessair	0:7e2bd16f80af	1979	__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
elessair	0:7e2bd16f80af	1980	{
elessair	0:7e2bd16f80af	1981	/* NOTE : This function Should not be modified, when the callback is needed,
elessair	0:7e2bd16f80af	1982	the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
elessair	0:7e2bd16f80af	1983	*/
elessair	0:7e2bd16f80af	1984	}
elessair	0:7e2bd16f80af	1985
elessair	0:7e2bd16f80af	1986	/**
elessair	0:7e2bd16f80af	1987	* @brief Starts the TIM One Pulse signal generation.
elessair	0:7e2bd16f80af	1988	* @param htim : TIM One Pulse handle
elessair	0:7e2bd16f80af	1989	* @param OutputChannel : TIM Channels to be enabled
elessair	0:7e2bd16f80af	1990	* This parameter can be one of the following values:
elessair	0:7e2bd16f80af	1991	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
elessair	0:7e2bd16f80af	1992	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
elessair	0:7e2bd16f80af	1993	* @retval HAL status
elessair	0:7e2bd16f80af	1994	*/
elessair	0:7e2bd16f80af	1995	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
elessair	0:7e2bd16f80af	1996	{
elessair	0:7e2bd16f80af	1997	/* Enable the Capture compare and the Input Capture channels
elessair	0:7e2bd16f80af	1998	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
elessair	0:7e2bd16f80af	1999	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
elessair	0:7e2bd16f80af	2000	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
elessair	0:7e2bd16f80af	2001	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
elessair	0:7e2bd16f80af	2002
elessair	0:7e2bd16f80af	2003	No need to enable the counter, it's enabled automatically by hardware
elessair	0:7e2bd16f80af	2004	(the counter starts in response to a stimulus and generate a pulse */
elessair	0:7e2bd16f80af	2005
elessair	0:7e2bd16f80af	2006	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
elessair	0:7e2bd16f80af	2007	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
elessair	0:7e2bd16f80af	2008
elessair	0:7e2bd16f80af	2009	/* Return function status */
elessair	0:7e2bd16f80af	2010	return HAL_OK;
elessair	0:7e2bd16f80af	2011	}
elessair	0:7e2bd16f80af	2012
elessair	0:7e2bd16f80af	2013	/**
elessair	0:7e2bd16f80af	2014	* @brief Stops the TIM One Pulse signal generation.
elessair	0:7e2bd16f80af	2015	* @param htim : TIM One Pulse handle
elessair	0:7e2bd16f80af	2016	* @param OutputChannel : TIM Channels to be disable
elessair	0:7e2bd16f80af	2017	* This parameter can be one of the following values:
elessair	0:7e2bd16f80af	2018	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
elessair	0:7e2bd16f80af	2019	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
elessair	0:7e2bd16f80af	2020	* @retval HAL status
elessair	0:7e2bd16f80af	2021	*/
elessair	0:7e2bd16f80af	2022	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
elessair	0:7e2bd16f80af	2023	{
elessair	0:7e2bd16f80af	2024	/* Disable the Capture compare and the Input Capture channels
elessair	0:7e2bd16f80af	2025	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
elessair	0:7e2bd16f80af	2026	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
elessair	0:7e2bd16f80af	2027	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
elessair	0:7e2bd16f80af	2028	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
elessair	0:7e2bd16f80af	2029
elessair	0:7e2bd16f80af	2030	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
elessair	0:7e2bd16f80af	2031	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
elessair	0:7e2bd16f80af	2032
elessair	0:7e2bd16f80af	2033	/* Disable the Peripheral */
elessair	0:7e2bd16f80af	2034	__HAL_TIM_DISABLE(htim);
elessair	0:7e2bd16f80af	2035
elessair	0:7e2bd16f80af	2036	/* Return function status */
elessair	0:7e2bd16f80af	2037	return HAL_OK;
elessair	0:7e2bd16f80af	2038	}
elessair	0:7e2bd16f80af	2039
elessair	0:7e2bd16f80af	2040	/**
elessair	0:7e2bd16f80af	2041	* @brief Starts the TIM One Pulse signal generation in interrupt mode.
elessair	0:7e2bd16f80af	2042	* @param htim : TIM One Pulse handle
elessair	0:7e2bd16f80af	2043	* @param OutputChannel : TIM Channels to be enabled
elessair	0:7e2bd16f80af	2044	* This parameter can be one of the following values:
elessair	0:7e2bd16f80af	2045	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
elessair	0:7e2bd16f80af	2046	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
elessair	0:7e2bd16f80af	2047	* @retval HAL status
elessair	0:7e2bd16f80af	2048	*/
elessair	0:7e2bd16f80af	2049	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
elessair	0:7e2bd16f80af	2050	{
elessair	0:7e2bd16f80af	2051	/* Enable the Capture compare and the Input Capture channels
elessair	0:7e2bd16f80af	2052	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
elessair	0:7e2bd16f80af	2053	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
elessair	0:7e2bd16f80af	2054	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
elessair	0:7e2bd16f80af	2055	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
elessair	0:7e2bd16f80af	2056
elessair	0:7e2bd16f80af	2057	No need to enable the counter, it's enabled automatically by hardware
elessair	0:7e2bd16f80af	2058	(the counter starts in response to a stimulus and generate a pulse */
elessair	0:7e2bd16f80af	2059
elessair	0:7e2bd16f80af	2060	/* Enable the TIM Capture/Compare 1 interrupt */
elessair	0:7e2bd16f80af	2061	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
elessair	0:7e2bd16f80af	2062
elessair	0:7e2bd16f80af	2063	/* Enable the TIM Capture/Compare 2 interrupt */
elessair	0:7e2bd16f80af	2064	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
elessair	0:7e2bd16f80af	2065
elessair	0:7e2bd16f80af	2066	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
elessair	0:7e2bd16f80af	2067	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
elessair	0:7e2bd16f80af	2068
elessair	0:7e2bd16f80af	2069	/* Return function status */
elessair	0:7e2bd16f80af	2070	return HAL_OK;
elessair	0:7e2bd16f80af	2071	}
elessair	0:7e2bd16f80af	2072
elessair	0:7e2bd16f80af	2073	/**
elessair	0:7e2bd16f80af	2074	* @brief Stops the TIM One Pulse signal generation in interrupt mode.
elessair	0:7e2bd16f80af	2075	* @param htim : TIM One Pulse handle
elessair	0:7e2bd16f80af	2076	* @param OutputChannel : TIM Channels to be enabled
elessair	0:7e2bd16f80af	2077	* This parameter can be one of the following values:
elessair	0:7e2bd16f80af	2078	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
elessair	0:7e2bd16f80af	2079	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
elessair	0:7e2bd16f80af	2080	* @retval HAL status
elessair	0:7e2bd16f80af	2081	*/
elessair	0:7e2bd16f80af	2082	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
elessair	0:7e2bd16f80af	2083	{
elessair	0:7e2bd16f80af	2084	/* Disable the TIM Capture/Compare 1 interrupt */
elessair	0:7e2bd16f80af	2085	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
elessair	0:7e2bd16f80af	2086
elessair	0:7e2bd16f80af	2087	/* Disable the TIM Capture/Compare 2 interrupt */
elessair	0:7e2bd16f80af	2088	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
elessair	0:7e2bd16f80af	2089
elessair	0:7e2bd16f80af	2090	/* Disable the Capture compare and the Input Capture channels
elessair	0:7e2bd16f80af	2091	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
elessair	0:7e2bd16f80af	2092	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
elessair	0:7e2bd16f80af	2093	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
elessair	0:7e2bd16f80af	2094	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
elessair	0:7e2bd16f80af	2095	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
elessair	0:7e2bd16f80af	2096	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
elessair	0:7e2bd16f80af	2097
elessair	0:7e2bd16f80af	2098	/* Disable the Peripheral */
elessair	0:7e2bd16f80af	2099	__HAL_TIM_DISABLE(htim);
elessair	0:7e2bd16f80af	2100
elessair	0:7e2bd16f80af	2101	/* Return function status */
elessair	0:7e2bd16f80af	2102	return HAL_OK;
elessair	0:7e2bd16f80af	2103	}
elessair	0:7e2bd16f80af	2104
elessair	0:7e2bd16f80af	2105	/**
elessair	0:7e2bd16f80af	2106	* @}
elessair	0:7e2bd16f80af	2107	*/
elessair	0:7e2bd16f80af	2108
elessair	0:7e2bd16f80af	2109	/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
elessair	0:7e2bd16f80af	2110	* @brief Time Encoder functions
elessair	0:7e2bd16f80af	2111	*
elessair	0:7e2bd16f80af	2112	@verbatim
elessair	0:7e2bd16f80af	2113	==============================================================================
elessair	0:7e2bd16f80af	2114	##### Time Encoder functions #####
elessair	0:7e2bd16f80af	2115	==============================================================================
elessair	0:7e2bd16f80af	2116	[..]
elessair	0:7e2bd16f80af	2117	This section provides functions allowing to:
elessair	0:7e2bd16f80af	2118	(+) Initialize and configure the TIM Encoder.
elessair	0:7e2bd16f80af	2119	(+) De-initialize the TIM Encoder.
elessair	0:7e2bd16f80af	2120	(+) Start the Time Encoder.
elessair	0:7e2bd16f80af	2121	(+) Stop the Time Encoder.
elessair	0:7e2bd16f80af	2122	(+) Start the Time Encoder and enable interrupt.
elessair	0:7e2bd16f80af	2123	(+) Stop the Time Encoder and disable interrupt.
elessair	0:7e2bd16f80af	2124	(+) Start the Time Encoder and enable DMA transfer.
elessair	0:7e2bd16f80af	2125	(+) Stop the Time Encoder and disable DMA transfer.
elessair	0:7e2bd16f80af	2126
elessair	0:7e2bd16f80af	2127	@endverbatim
elessair	0:7e2bd16f80af	2128	* @{
elessair	0:7e2bd16f80af	2129	*/
elessair	0:7e2bd16f80af	2130	/**
elessair	0:7e2bd16f80af	2131	* @brief Initializes the TIM Encoder Interface and create the associated handle.
elessair	0:7e2bd16f80af	2132	* @param htim: TIM Encoder Interface handle
elessair	0:7e2bd16f80af	2133	* @param sConfig: TIM Encoder Interface configuration structure
elessair	0:7e2bd16f80af	2134	* @retval HAL status
elessair	0:7e2bd16f80af	2135	*/
elessair	0:7e2bd16f80af	2136	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig)
elessair	0:7e2bd16f80af	2137	{
elessair	0:7e2bd16f80af	2138	uint32_t tmpsmcr = 0;
elessair	0:7e2bd16f80af	2139	uint32_t tmpccmr1 = 0;
elessair	0:7e2bd16f80af	2140	uint32_t tmpccer = 0;
elessair	0:7e2bd16f80af	2141
elessair	0:7e2bd16f80af	2142	/* Check the TIM handle allocation */
elessair	0:7e2bd16f80af	2143	if(htim == HAL_NULL)
elessair	0:7e2bd16f80af	2144	{
elessair	0:7e2bd16f80af	2145	return HAL_ERROR;
elessair	0:7e2bd16f80af	2146	}
elessair	0:7e2bd16f80af	2147
elessair	0:7e2bd16f80af	2148	/* Check the parameters */
elessair	0:7e2bd16f80af	2149	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	2150	assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
elessair	0:7e2bd16f80af	2151	assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
elessair	0:7e2bd16f80af	2152	assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
elessair	0:7e2bd16f80af	2153	assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
elessair	0:7e2bd16f80af	2154	assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
elessair	0:7e2bd16f80af	2155	assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
elessair	0:7e2bd16f80af	2156	assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
elessair	0:7e2bd16f80af	2157	assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
elessair	0:7e2bd16f80af	2158	assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
elessair	0:7e2bd16f80af	2159
elessair	0:7e2bd16f80af	2160	if(htim->State == HAL_TIM_STATE_RESET)
elessair	0:7e2bd16f80af	2161	{
elessair	0:7e2bd16f80af	2162	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
elessair	0:7e2bd16f80af	2163	HAL_TIM_Encoder_MspInit(htim);
elessair	0:7e2bd16f80af	2164	}
elessair	0:7e2bd16f80af	2165
elessair	0:7e2bd16f80af	2166	/* Set the TIM state */
elessair	0:7e2bd16f80af	2167	htim->State= HAL_TIM_STATE_BUSY;
elessair	0:7e2bd16f80af	2168
elessair	0:7e2bd16f80af	2169	/* Reset the SMS bits */
elessair	0:7e2bd16f80af	2170	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
elessair	0:7e2bd16f80af	2171
elessair	0:7e2bd16f80af	2172	/* Configure the Time base in the Encoder Mode */
elessair	0:7e2bd16f80af	2173	TIM_Base_SetConfig(htim->Instance, &htim->Init);
elessair	0:7e2bd16f80af	2174
elessair	0:7e2bd16f80af	2175	/* Get the TIMx SMCR register value */
elessair	0:7e2bd16f80af	2176	tmpsmcr = htim->Instance->SMCR;
elessair	0:7e2bd16f80af	2177
elessair	0:7e2bd16f80af	2178	/* Get the TIMx CCMR1 register value */
elessair	0:7e2bd16f80af	2179	tmpccmr1 = htim->Instance->CCMR1;
elessair	0:7e2bd16f80af	2180
elessair	0:7e2bd16f80af	2181	/* Get the TIMx CCER register value */
elessair	0:7e2bd16f80af	2182	tmpccer = htim->Instance->CCER;
elessair	0:7e2bd16f80af	2183
elessair	0:7e2bd16f80af	2184	/* Set the encoder Mode */
elessair	0:7e2bd16f80af	2185	tmpsmcr \|= sConfig->EncoderMode;
elessair	0:7e2bd16f80af	2186
elessair	0:7e2bd16f80af	2187	/* Select the Capture Compare 1 and the Capture Compare 2 as input */
elessair	0:7e2bd16f80af	2188	tmpccmr1 &= ~(TIM_CCMR1_CC1S \| TIM_CCMR1_CC2S);
elessair	0:7e2bd16f80af	2189	tmpccmr1 \|= (sConfig->IC1Selection \| (sConfig->IC2Selection << 8));
elessair	0:7e2bd16f80af	2190
elessair	0:7e2bd16f80af	2191	/* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
elessair	0:7e2bd16f80af	2192	tmpccmr1 &= ~(TIM_CCMR1_IC1PSC \| TIM_CCMR1_IC2PSC);
elessair	0:7e2bd16f80af	2193	tmpccmr1 &= (~(TIM_CCMR1_IC1F \| TIM_CCMR1_IC2F));
elessair	0:7e2bd16f80af	2194	tmpccmr1 \|= sConfig->IC1Prescaler \| (sConfig->IC2Prescaler << 8);
elessair	0:7e2bd16f80af	2195	tmpccmr1 \|= (sConfig->IC1Filter << 4) \| (sConfig->IC2Filter << 12);
elessair	0:7e2bd16f80af	2196
elessair	0:7e2bd16f80af	2197	/* Set the TI1 and the TI2 Polarities */
elessair	0:7e2bd16f80af	2198	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC2P);
elessair	0:7e2bd16f80af	2199	tmpccer &= ~(TIM_CCER_CC1NP \| TIM_CCER_CC2NP);
elessair	0:7e2bd16f80af	2200	tmpccer \|= sConfig->IC1Polarity \| (sConfig->IC2Polarity << 4);
elessair	0:7e2bd16f80af	2201
elessair	0:7e2bd16f80af	2202	/* Write to TIMx SMCR */
elessair	0:7e2bd16f80af	2203	htim->Instance->SMCR = tmpsmcr;
elessair	0:7e2bd16f80af	2204
elessair	0:7e2bd16f80af	2205	/* Write to TIMx CCMR1 */
elessair	0:7e2bd16f80af	2206	htim->Instance->CCMR1 = tmpccmr1;
elessair	0:7e2bd16f80af	2207
elessair	0:7e2bd16f80af	2208	/* Write to TIMx CCER */
elessair	0:7e2bd16f80af	2209	htim->Instance->CCER = tmpccer;
elessair	0:7e2bd16f80af	2210
elessair	0:7e2bd16f80af	2211	/* Initialize the TIM state*/
elessair	0:7e2bd16f80af	2212	htim->State= HAL_TIM_STATE_READY;
elessair	0:7e2bd16f80af	2213
elessair	0:7e2bd16f80af	2214	return HAL_OK;
elessair	0:7e2bd16f80af	2215	}
elessair	0:7e2bd16f80af	2216
elessair	0:7e2bd16f80af	2217
elessair	0:7e2bd16f80af	2218	/**
elessair	0:7e2bd16f80af	2219	* @brief DeInitializes the TIM Encoder interface
elessair	0:7e2bd16f80af	2220	* @param htim: TIM Encoder handle
elessair	0:7e2bd16f80af	2221	* @retval HAL status
elessair	0:7e2bd16f80af	2222	*/
elessair	0:7e2bd16f80af	2223	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
elessair	0:7e2bd16f80af	2224	{
elessair	0:7e2bd16f80af	2225	/* Check the parameters */
elessair	0:7e2bd16f80af	2226	assert_param(IS_TIM_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	2227
elessair	0:7e2bd16f80af	2228	htim->State = HAL_TIM_STATE_BUSY;
elessair	0:7e2bd16f80af	2229
elessair	0:7e2bd16f80af	2230	/* Disable the TIM Peripheral Clock */
elessair	0:7e2bd16f80af	2231	__HAL_TIM_DISABLE(htim);
elessair	0:7e2bd16f80af	2232
elessair	0:7e2bd16f80af	2233	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
elessair	0:7e2bd16f80af	2234	HAL_TIM_Encoder_MspDeInit(htim);
elessair	0:7e2bd16f80af	2235
elessair	0:7e2bd16f80af	2236	/* Change TIM state */
elessair	0:7e2bd16f80af	2237	htim->State = HAL_TIM_STATE_RESET;
elessair	0:7e2bd16f80af	2238
elessair	0:7e2bd16f80af	2239	/* Release Lock */
elessair	0:7e2bd16f80af	2240	__HAL_UNLOCK(htim);
elessair	0:7e2bd16f80af	2241
elessair	0:7e2bd16f80af	2242	return HAL_OK;
elessair	0:7e2bd16f80af	2243	}
elessair	0:7e2bd16f80af	2244
elessair	0:7e2bd16f80af	2245	/**
elessair	0:7e2bd16f80af	2246	* @brief Initializes the TIM Encoder Interface MSP.
elessair	0:7e2bd16f80af	2247	* @param htim: TIM handle
elessair	0:7e2bd16f80af	2248	* @retval None
elessair	0:7e2bd16f80af	2249	*/
elessair	0:7e2bd16f80af	2250	__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
elessair	0:7e2bd16f80af	2251	{
elessair	0:7e2bd16f80af	2252	/* NOTE : This function Should not be modified, when the callback is needed,
elessair	0:7e2bd16f80af	2253	the HAL_TIM_Encoder_MspInit could be implemented in the user file
elessair	0:7e2bd16f80af	2254	*/
elessair	0:7e2bd16f80af	2255	}
elessair	0:7e2bd16f80af	2256
elessair	0:7e2bd16f80af	2257	/**
elessair	0:7e2bd16f80af	2258	* @brief DeInitializes TIM Encoder Interface MSP.
elessair	0:7e2bd16f80af	2259	* @param htim: TIM handle
elessair	0:7e2bd16f80af	2260	* @retval None
elessair	0:7e2bd16f80af	2261	*/
elessair	0:7e2bd16f80af	2262	__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
elessair	0:7e2bd16f80af	2263	{
elessair	0:7e2bd16f80af	2264	/* NOTE : This function Should not be modified, when the callback is needed,
elessair	0:7e2bd16f80af	2265	the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
elessair	0:7e2bd16f80af	2266	*/
elessair	0:7e2bd16f80af	2267	}
elessair	0:7e2bd16f80af	2268
elessair	0:7e2bd16f80af	2269	/**
elessair	0:7e2bd16f80af	2270	* @brief Starts the TIM Encoder Interface.
elessair	0:7e2bd16f80af	2271	* @param htim : TIM Encoder Interface handle
elessair	0:7e2bd16f80af	2272	* @param Channel : TIM Channels to be enabled
elessair	0:7e2bd16f80af	2273	* This parameter can be one of the following values:
elessair	0:7e2bd16f80af	2274	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
elessair	0:7e2bd16f80af	2275	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
elessair	0:7e2bd16f80af	2276	* @retval HAL status
elessair	0:7e2bd16f80af	2277	*/
elessair	0:7e2bd16f80af	2278	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
elessair	0:7e2bd16f80af	2279	{
elessair	0:7e2bd16f80af	2280	/* Check the parameters */
elessair	0:7e2bd16f80af	2281	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	2282
elessair	0:7e2bd16f80af	2283	/* Enable the encoder interface channels */
elessair	0:7e2bd16f80af	2284	switch (Channel)
elessair	0:7e2bd16f80af	2285	{
elessair	0:7e2bd16f80af	2286	case TIM_CHANNEL_1:
elessair	0:7e2bd16f80af	2287	{
elessair	0:7e2bd16f80af	2288	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
elessair	0:7e2bd16f80af	2289	break;
elessair	0:7e2bd16f80af	2290	}
elessair	0:7e2bd16f80af	2291	case TIM_CHANNEL_2:
elessair	0:7e2bd16f80af	2292	{
elessair	0:7e2bd16f80af	2293	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
elessair	0:7e2bd16f80af	2294	break;
elessair	0:7e2bd16f80af	2295	}
elessair	0:7e2bd16f80af	2296	default :
elessair	0:7e2bd16f80af	2297	{
elessair	0:7e2bd16f80af	2298	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
elessair	0:7e2bd16f80af	2299	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
elessair	0:7e2bd16f80af	2300	break;
elessair	0:7e2bd16f80af	2301	}
elessair	0:7e2bd16f80af	2302	}
elessair	0:7e2bd16f80af	2303	/* Enable the Peripheral */
elessair	0:7e2bd16f80af	2304	__HAL_TIM_ENABLE(htim);
elessair	0:7e2bd16f80af	2305
elessair	0:7e2bd16f80af	2306	/* Return function status */
elessair	0:7e2bd16f80af	2307	return HAL_OK;
elessair	0:7e2bd16f80af	2308	}
elessair	0:7e2bd16f80af	2309
elessair	0:7e2bd16f80af	2310	/**
elessair	0:7e2bd16f80af	2311	* @brief Stops the TIM Encoder Interface.
elessair	0:7e2bd16f80af	2312	* @param htim : TIM Encoder Interface handle
elessair	0:7e2bd16f80af	2313	* @param Channel : TIM Channels to be disabled
elessair	0:7e2bd16f80af	2314	* This parameter can be one of the following values:
elessair	0:7e2bd16f80af	2315	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
elessair	0:7e2bd16f80af	2316	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
elessair	0:7e2bd16f80af	2317	* @retval HAL status
elessair	0:7e2bd16f80af	2318	*/
elessair	0:7e2bd16f80af	2319	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
elessair	0:7e2bd16f80af	2320	{
elessair	0:7e2bd16f80af	2321	/* Check the parameters */
elessair	0:7e2bd16f80af	2322	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	2323
elessair	0:7e2bd16f80af	2324	/* Disable the Input Capture channels 1 and 2
elessair	0:7e2bd16f80af	2325	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
elessair	0:7e2bd16f80af	2326	switch (Channel)
elessair	0:7e2bd16f80af	2327	{
elessair	0:7e2bd16f80af	2328	case TIM_CHANNEL_1:
elessair	0:7e2bd16f80af	2329	{
elessair	0:7e2bd16f80af	2330	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
elessair	0:7e2bd16f80af	2331	break;
elessair	0:7e2bd16f80af	2332	}
elessair	0:7e2bd16f80af	2333	case TIM_CHANNEL_2:
elessair	0:7e2bd16f80af	2334	{
elessair	0:7e2bd16f80af	2335	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
elessair	0:7e2bd16f80af	2336	break;
elessair	0:7e2bd16f80af	2337	}
elessair	0:7e2bd16f80af	2338	default :
elessair	0:7e2bd16f80af	2339	{
elessair	0:7e2bd16f80af	2340	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
elessair	0:7e2bd16f80af	2341	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
elessair	0:7e2bd16f80af	2342	break;
elessair	0:7e2bd16f80af	2343	}
elessair	0:7e2bd16f80af	2344	}
elessair	0:7e2bd16f80af	2345
elessair	0:7e2bd16f80af	2346	/* Disable the Peripheral */
elessair	0:7e2bd16f80af	2347	__HAL_TIM_DISABLE(htim);
elessair	0:7e2bd16f80af	2348
elessair	0:7e2bd16f80af	2349	/* Return function status */
elessair	0:7e2bd16f80af	2350	return HAL_OK;
elessair	0:7e2bd16f80af	2351	}
elessair	0:7e2bd16f80af	2352
elessair	0:7e2bd16f80af	2353	/**
elessair	0:7e2bd16f80af	2354	* @brief Starts the TIM Encoder Interface in interrupt mode.
elessair	0:7e2bd16f80af	2355	* @param htim : TIM Encoder Interface handle
elessair	0:7e2bd16f80af	2356	* @param Channel : TIM Channels to be enabled
elessair	0:7e2bd16f80af	2357	* This parameter can be one of the following values:
elessair	0:7e2bd16f80af	2358	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
elessair	0:7e2bd16f80af	2359	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
elessair	0:7e2bd16f80af	2360	* @retval HAL status
elessair	0:7e2bd16f80af	2361	*/
elessair	0:7e2bd16f80af	2362	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
elessair	0:7e2bd16f80af	2363	{
elessair	0:7e2bd16f80af	2364	/* Check the parameters */
elessair	0:7e2bd16f80af	2365	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	2366
elessair	0:7e2bd16f80af	2367	/* Enable the encoder interface channels */
elessair	0:7e2bd16f80af	2368	/* Enable the capture compare Interrupts 1 and/or 2 */
elessair	0:7e2bd16f80af	2369	switch (Channel)
elessair	0:7e2bd16f80af	2370	{
elessair	0:7e2bd16f80af	2371	case TIM_CHANNEL_1:
elessair	0:7e2bd16f80af	2372	{
elessair	0:7e2bd16f80af	2373	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
elessair	0:7e2bd16f80af	2374	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
elessair	0:7e2bd16f80af	2375	break;
elessair	0:7e2bd16f80af	2376	}
elessair	0:7e2bd16f80af	2377	case TIM_CHANNEL_2:
elessair	0:7e2bd16f80af	2378	{
elessair	0:7e2bd16f80af	2379	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
elessair	0:7e2bd16f80af	2380	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
elessair	0:7e2bd16f80af	2381	break;
elessair	0:7e2bd16f80af	2382	}
elessair	0:7e2bd16f80af	2383	default :
elessair	0:7e2bd16f80af	2384	{
elessair	0:7e2bd16f80af	2385	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
elessair	0:7e2bd16f80af	2386	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
elessair	0:7e2bd16f80af	2387	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
elessair	0:7e2bd16f80af	2388	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
elessair	0:7e2bd16f80af	2389	break;
elessair	0:7e2bd16f80af	2390	}
elessair	0:7e2bd16f80af	2391	}
elessair	0:7e2bd16f80af	2392
elessair	0:7e2bd16f80af	2393	/* Enable the Peripheral */
elessair	0:7e2bd16f80af	2394	__HAL_TIM_ENABLE(htim);
elessair	0:7e2bd16f80af	2395
elessair	0:7e2bd16f80af	2396	/* Return function status */
elessair	0:7e2bd16f80af	2397	return HAL_OK;
elessair	0:7e2bd16f80af	2398	}
elessair	0:7e2bd16f80af	2399
elessair	0:7e2bd16f80af	2400	/**
elessair	0:7e2bd16f80af	2401	* @brief Stops the TIM Encoder Interface in interrupt mode.
elessair	0:7e2bd16f80af	2402	* @param htim : TIM Encoder Interface handle
elessair	0:7e2bd16f80af	2403	* @param Channel : TIM Channels to be disabled
elessair	0:7e2bd16f80af	2404	* This parameter can be one of the following values:
elessair	0:7e2bd16f80af	2405	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
elessair	0:7e2bd16f80af	2406	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
elessair	0:7e2bd16f80af	2407	* @retval HAL status
elessair	0:7e2bd16f80af	2408	*/
elessair	0:7e2bd16f80af	2409	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
elessair	0:7e2bd16f80af	2410	{
elessair	0:7e2bd16f80af	2411	/* Check the parameters */
elessair	0:7e2bd16f80af	2412	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	2413
elessair	0:7e2bd16f80af	2414	/* Disable the Input Capture channels 1 and 2
elessair	0:7e2bd16f80af	2415	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
elessair	0:7e2bd16f80af	2416	if(Channel == TIM_CHANNEL_1)
elessair	0:7e2bd16f80af	2417	{
elessair	0:7e2bd16f80af	2418	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
elessair	0:7e2bd16f80af	2419
elessair	0:7e2bd16f80af	2420	/* Disable the capture compare Interrupts 1 */
elessair	0:7e2bd16f80af	2421	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
elessair	0:7e2bd16f80af	2422	}
elessair	0:7e2bd16f80af	2423	else if(Channel == TIM_CHANNEL_2)
elessair	0:7e2bd16f80af	2424	{
elessair	0:7e2bd16f80af	2425	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
elessair	0:7e2bd16f80af	2426
elessair	0:7e2bd16f80af	2427	/* Disable the capture compare Interrupts 2 */
elessair	0:7e2bd16f80af	2428	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
elessair	0:7e2bd16f80af	2429	}
elessair	0:7e2bd16f80af	2430	else
elessair	0:7e2bd16f80af	2431	{
elessair	0:7e2bd16f80af	2432	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
elessair	0:7e2bd16f80af	2433	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
elessair	0:7e2bd16f80af	2434
elessair	0:7e2bd16f80af	2435	/* Disable the capture compare Interrupts 1 and 2 */
elessair	0:7e2bd16f80af	2436	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
elessair	0:7e2bd16f80af	2437	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
elessair	0:7e2bd16f80af	2438	}
elessair	0:7e2bd16f80af	2439
elessair	0:7e2bd16f80af	2440	/* Disable the Peripheral */
elessair	0:7e2bd16f80af	2441	__HAL_TIM_DISABLE(htim);
elessair	0:7e2bd16f80af	2442
elessair	0:7e2bd16f80af	2443	/* Change the htim state */
elessair	0:7e2bd16f80af	2444	htim->State = HAL_TIM_STATE_READY;
elessair	0:7e2bd16f80af	2445
elessair	0:7e2bd16f80af	2446	/* Return function status */
elessair	0:7e2bd16f80af	2447	return HAL_OK;
elessair	0:7e2bd16f80af	2448	}
elessair	0:7e2bd16f80af	2449
elessair	0:7e2bd16f80af	2450	/**
elessair	0:7e2bd16f80af	2451	* @brief Starts the TIM Encoder Interface in DMA mode.
elessair	0:7e2bd16f80af	2452	* @param htim : TIM Encoder Interface handle
elessair	0:7e2bd16f80af	2453	* @param Channel : TIM Channels to be enabled
elessair	0:7e2bd16f80af	2454	* This parameter can be one of the following values:
elessair	0:7e2bd16f80af	2455	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
elessair	0:7e2bd16f80af	2456	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
elessair	0:7e2bd16f80af	2457	* @param pData1: The destination Buffer address for IC1.
elessair	0:7e2bd16f80af	2458	* @param pData2: The destination Buffer address for IC2.
elessair	0:7e2bd16f80af	2459	* @param Length: The length of data to be transferred from TIM peripheral to memory.
elessair	0:7e2bd16f80af	2460	* @retval HAL status
elessair	0:7e2bd16f80af	2461	*/
elessair	0:7e2bd16f80af	2462	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length)
elessair	0:7e2bd16f80af	2463	{
elessair	0:7e2bd16f80af	2464	/* Check the parameters */
elessair	0:7e2bd16f80af	2465	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	2466
elessair	0:7e2bd16f80af	2467	if((htim->State == HAL_TIM_STATE_BUSY))
elessair	0:7e2bd16f80af	2468	{
elessair	0:7e2bd16f80af	2469	return HAL_BUSY;
elessair	0:7e2bd16f80af	2470	}
elessair	0:7e2bd16f80af	2471	else if((htim->State == HAL_TIM_STATE_READY))
elessair	0:7e2bd16f80af	2472	{
elessair	0:7e2bd16f80af	2473	if((((pData1 == 0) \|\| (pData2 == 0) )) && (Length > 0))
elessair	0:7e2bd16f80af	2474	{
elessair	0:7e2bd16f80af	2475	return HAL_ERROR;
elessair	0:7e2bd16f80af	2476	}
elessair	0:7e2bd16f80af	2477	else
elessair	0:7e2bd16f80af	2478	{
elessair	0:7e2bd16f80af	2479	htim->State = HAL_TIM_STATE_BUSY;
elessair	0:7e2bd16f80af	2480	}
elessair	0:7e2bd16f80af	2481	}
elessair	0:7e2bd16f80af	2482	else
elessair	0:7e2bd16f80af	2483	{
elessair	0:7e2bd16f80af	2484	return HAL_ERROR;
elessair	0:7e2bd16f80af	2485	}
elessair	0:7e2bd16f80af	2486
elessair	0:7e2bd16f80af	2487	switch (Channel)
elessair	0:7e2bd16f80af	2488	{
elessair	0:7e2bd16f80af	2489	case TIM_CHANNEL_1:
elessair	0:7e2bd16f80af	2490	{
elessair	0:7e2bd16f80af	2491	/* Set the DMA Period elapsed callback */
elessair	0:7e2bd16f80af	2492	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
elessair	0:7e2bd16f80af	2493
elessair	0:7e2bd16f80af	2494	/* Set the DMA error callback */
elessair	0:7e2bd16f80af	2495	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
elessair	0:7e2bd16f80af	2496
elessair	0:7e2bd16f80af	2497	/* Enable the DMA channel */
elessair	0:7e2bd16f80af	2498	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
elessair	0:7e2bd16f80af	2499
elessair	0:7e2bd16f80af	2500	/* Enable the TIM Input Capture DMA request */
elessair	0:7e2bd16f80af	2501	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
elessair	0:7e2bd16f80af	2502
elessair	0:7e2bd16f80af	2503	/* Enable the Peripheral */
elessair	0:7e2bd16f80af	2504	__HAL_TIM_ENABLE(htim);
elessair	0:7e2bd16f80af	2505
elessair	0:7e2bd16f80af	2506	/* Enable the Capture compare channel */
elessair	0:7e2bd16f80af	2507	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
elessair	0:7e2bd16f80af	2508	}
elessair	0:7e2bd16f80af	2509	break;
elessair	0:7e2bd16f80af	2510
elessair	0:7e2bd16f80af	2511	case TIM_CHANNEL_2:
elessair	0:7e2bd16f80af	2512	{
elessair	0:7e2bd16f80af	2513	/* Set the DMA Period elapsed callback */
elessair	0:7e2bd16f80af	2514	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
elessair	0:7e2bd16f80af	2515
elessair	0:7e2bd16f80af	2516	/* Set the DMA error callback */
elessair	0:7e2bd16f80af	2517	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
elessair	0:7e2bd16f80af	2518	/* Enable the DMA channel */
elessair	0:7e2bd16f80af	2519	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
elessair	0:7e2bd16f80af	2520
elessair	0:7e2bd16f80af	2521	/* Enable the TIM Input Capture DMA request */
elessair	0:7e2bd16f80af	2522	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
elessair	0:7e2bd16f80af	2523
elessair	0:7e2bd16f80af	2524	/* Enable the Peripheral */
elessair	0:7e2bd16f80af	2525	__HAL_TIM_ENABLE(htim);
elessair	0:7e2bd16f80af	2526
elessair	0:7e2bd16f80af	2527	/* Enable the Capture compare channel */
elessair	0:7e2bd16f80af	2528	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
elessair	0:7e2bd16f80af	2529	}
elessair	0:7e2bd16f80af	2530	break;
elessair	0:7e2bd16f80af	2531
elessair	0:7e2bd16f80af	2532	case TIM_CHANNEL_ALL:
elessair	0:7e2bd16f80af	2533	{
elessair	0:7e2bd16f80af	2534	/* Set the DMA Period elapsed callback */
elessair	0:7e2bd16f80af	2535	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
elessair	0:7e2bd16f80af	2536
elessair	0:7e2bd16f80af	2537	/* Set the DMA error callback */
elessair	0:7e2bd16f80af	2538	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
elessair	0:7e2bd16f80af	2539
elessair	0:7e2bd16f80af	2540	/* Enable the DMA channel */
elessair	0:7e2bd16f80af	2541	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
elessair	0:7e2bd16f80af	2542
elessair	0:7e2bd16f80af	2543	/* Set the DMA Period elapsed callback */
elessair	0:7e2bd16f80af	2544	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
elessair	0:7e2bd16f80af	2545
elessair	0:7e2bd16f80af	2546	/* Set the DMA error callback */
elessair	0:7e2bd16f80af	2547	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
elessair	0:7e2bd16f80af	2548
elessair	0:7e2bd16f80af	2549	/* Enable the DMA channel */
elessair	0:7e2bd16f80af	2550	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
elessair	0:7e2bd16f80af	2551
elessair	0:7e2bd16f80af	2552	/* Enable the Peripheral */
elessair	0:7e2bd16f80af	2553	__HAL_TIM_ENABLE(htim);
elessair	0:7e2bd16f80af	2554
elessair	0:7e2bd16f80af	2555	/* Enable the Capture compare channel */
elessair	0:7e2bd16f80af	2556	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
elessair	0:7e2bd16f80af	2557	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
elessair	0:7e2bd16f80af	2558
elessair	0:7e2bd16f80af	2559	/* Enable the TIM Input Capture DMA request */
elessair	0:7e2bd16f80af	2560	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
elessair	0:7e2bd16f80af	2561	/* Enable the TIM Input Capture DMA request */
elessair	0:7e2bd16f80af	2562	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
elessair	0:7e2bd16f80af	2563	}
elessair	0:7e2bd16f80af	2564	break;
elessair	0:7e2bd16f80af	2565
elessair	0:7e2bd16f80af	2566	default:
elessair	0:7e2bd16f80af	2567	break;
elessair	0:7e2bd16f80af	2568	}
elessair	0:7e2bd16f80af	2569	/* Return function status */
elessair	0:7e2bd16f80af	2570	return HAL_OK;
elessair	0:7e2bd16f80af	2571	}
elessair	0:7e2bd16f80af	2572
elessair	0:7e2bd16f80af	2573	/**
elessair	0:7e2bd16f80af	2574	* @brief Stops the TIM Encoder Interface in DMA mode.
elessair	0:7e2bd16f80af	2575	* @param htim : TIM Encoder Interface handle
elessair	0:7e2bd16f80af	2576	* @param Channel : TIM Channels to be enabled
elessair	0:7e2bd16f80af	2577	* This parameter can be one of the following values:
elessair	0:7e2bd16f80af	2578	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
elessair	0:7e2bd16f80af	2579	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
elessair	0:7e2bd16f80af	2580	* @retval HAL status
elessair	0:7e2bd16f80af	2581	*/
elessair	0:7e2bd16f80af	2582	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
elessair	0:7e2bd16f80af	2583	{
elessair	0:7e2bd16f80af	2584	/* Check the parameters */
elessair	0:7e2bd16f80af	2585	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	2586
elessair	0:7e2bd16f80af	2587	/* Disable the Input Capture channels 1 and 2
elessair	0:7e2bd16f80af	2588	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
elessair	0:7e2bd16f80af	2589	if(Channel == TIM_CHANNEL_1)
elessair	0:7e2bd16f80af	2590	{
elessair	0:7e2bd16f80af	2591	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
elessair	0:7e2bd16f80af	2592
elessair	0:7e2bd16f80af	2593	/* Disable the capture compare DMA Request 1 */
elessair	0:7e2bd16f80af	2594	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
elessair	0:7e2bd16f80af	2595	}
elessair	0:7e2bd16f80af	2596	else if(Channel == TIM_CHANNEL_2)
elessair	0:7e2bd16f80af	2597	{
elessair	0:7e2bd16f80af	2598	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
elessair	0:7e2bd16f80af	2599
elessair	0:7e2bd16f80af	2600	/* Disable the capture compare DMA Request 2 */
elessair	0:7e2bd16f80af	2601	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
elessair	0:7e2bd16f80af	2602	}
elessair	0:7e2bd16f80af	2603	else
elessair	0:7e2bd16f80af	2604	{
elessair	0:7e2bd16f80af	2605	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
elessair	0:7e2bd16f80af	2606	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
elessair	0:7e2bd16f80af	2607
elessair	0:7e2bd16f80af	2608	/* Disable the capture compare DMA Request 1 and 2 */
elessair	0:7e2bd16f80af	2609	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
elessair	0:7e2bd16f80af	2610	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
elessair	0:7e2bd16f80af	2611	}
elessair	0:7e2bd16f80af	2612
elessair	0:7e2bd16f80af	2613	/* Disable the Peripheral */
elessair	0:7e2bd16f80af	2614	__HAL_TIM_DISABLE(htim);
elessair	0:7e2bd16f80af	2615
elessair	0:7e2bd16f80af	2616	/* Change the htim state */
elessair	0:7e2bd16f80af	2617	htim->State = HAL_TIM_STATE_READY;
elessair	0:7e2bd16f80af	2618
elessair	0:7e2bd16f80af	2619	/* Return function status */
elessair	0:7e2bd16f80af	2620	return HAL_OK;
elessair	0:7e2bd16f80af	2621	}
elessair	0:7e2bd16f80af	2622
elessair	0:7e2bd16f80af	2623	/**
elessair	0:7e2bd16f80af	2624	* @}
elessair	0:7e2bd16f80af	2625	*/
elessair	0:7e2bd16f80af	2626	/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
elessair	0:7e2bd16f80af	2627	* @brief IRQ handler management
elessair	0:7e2bd16f80af	2628	*
elessair	0:7e2bd16f80af	2629	@verbatim
elessair	0:7e2bd16f80af	2630	==============================================================================
elessair	0:7e2bd16f80af	2631	##### IRQ handler management #####
elessair	0:7e2bd16f80af	2632	==============================================================================
elessair	0:7e2bd16f80af	2633	[..]
elessair	0:7e2bd16f80af	2634	This section provides Timer IRQ handler function.
elessair	0:7e2bd16f80af	2635
elessair	0:7e2bd16f80af	2636	@endverbatim
elessair	0:7e2bd16f80af	2637	* @{
elessair	0:7e2bd16f80af	2638	*/
elessair	0:7e2bd16f80af	2639	/**
elessair	0:7e2bd16f80af	2640	* @brief This function handles TIM interrupts requests.
elessair	0:7e2bd16f80af	2641	* @param htim: TIM handle
elessair	0:7e2bd16f80af	2642	* @retval None
elessair	0:7e2bd16f80af	2643	*/
elessair	0:7e2bd16f80af	2644	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
elessair	0:7e2bd16f80af	2645	{
elessair	0:7e2bd16f80af	2646	/* Capture compare 1 event */
elessair	0:7e2bd16f80af	2647	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
elessair	0:7e2bd16f80af	2648	{
elessair	0:7e2bd16f80af	2649	if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC1) !=RESET)
elessair	0:7e2bd16f80af	2650	{
elessair	0:7e2bd16f80af	2651	{
elessair	0:7e2bd16f80af	2652	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
elessair	0:7e2bd16f80af	2653	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
elessair	0:7e2bd16f80af	2654
elessair	0:7e2bd16f80af	2655	/* Input capture event */
elessair	0:7e2bd16f80af	2656	if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
elessair	0:7e2bd16f80af	2657	{
elessair	0:7e2bd16f80af	2658	HAL_TIM_IC_CaptureCallback(htim);
elessair	0:7e2bd16f80af	2659	}
elessair	0:7e2bd16f80af	2660	/* Output compare event */
elessair	0:7e2bd16f80af	2661	else
elessair	0:7e2bd16f80af	2662	{
elessair	0:7e2bd16f80af	2663	HAL_TIM_OC_DelayElapsedCallback(htim);
elessair	0:7e2bd16f80af	2664	HAL_TIM_PWM_PulseFinishedCallback(htim);
elessair	0:7e2bd16f80af	2665	}
elessair	0:7e2bd16f80af	2666	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
elessair	0:7e2bd16f80af	2667	}
elessair	0:7e2bd16f80af	2668	}
elessair	0:7e2bd16f80af	2669	}
elessair	0:7e2bd16f80af	2670	/* Capture compare 2 event */
elessair	0:7e2bd16f80af	2671	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
elessair	0:7e2bd16f80af	2672	{
elessair	0:7e2bd16f80af	2673	if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC2) !=RESET)
elessair	0:7e2bd16f80af	2674	{
elessair	0:7e2bd16f80af	2675	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
elessair	0:7e2bd16f80af	2676	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
elessair	0:7e2bd16f80af	2677	/* Input capture event */
elessair	0:7e2bd16f80af	2678	if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
elessair	0:7e2bd16f80af	2679	{
elessair	0:7e2bd16f80af	2680	HAL_TIM_IC_CaptureCallback(htim);
elessair	0:7e2bd16f80af	2681	}
elessair	0:7e2bd16f80af	2682	/* Output compare event */
elessair	0:7e2bd16f80af	2683	else
elessair	0:7e2bd16f80af	2684	{
elessair	0:7e2bd16f80af	2685	HAL_TIM_OC_DelayElapsedCallback(htim);
elessair	0:7e2bd16f80af	2686	HAL_TIM_PWM_PulseFinishedCallback(htim);
elessair	0:7e2bd16f80af	2687	}
elessair	0:7e2bd16f80af	2688	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
elessair	0:7e2bd16f80af	2689	}
elessair	0:7e2bd16f80af	2690	}
elessair	0:7e2bd16f80af	2691	/* Capture compare 3 event */
elessair	0:7e2bd16f80af	2692	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
elessair	0:7e2bd16f80af	2693	{
elessair	0:7e2bd16f80af	2694	if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC3) !=RESET)
elessair	0:7e2bd16f80af	2695	{
elessair	0:7e2bd16f80af	2696	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
elessair	0:7e2bd16f80af	2697	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
elessair	0:7e2bd16f80af	2698	/* Input capture event */
elessair	0:7e2bd16f80af	2699	if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
elessair	0:7e2bd16f80af	2700	{
elessair	0:7e2bd16f80af	2701	HAL_TIM_IC_CaptureCallback(htim);
elessair	0:7e2bd16f80af	2702	}
elessair	0:7e2bd16f80af	2703	/* Output compare event */
elessair	0:7e2bd16f80af	2704	else
elessair	0:7e2bd16f80af	2705	{
elessair	0:7e2bd16f80af	2706	HAL_TIM_OC_DelayElapsedCallback(htim);
elessair	0:7e2bd16f80af	2707	HAL_TIM_PWM_PulseFinishedCallback(htim);
elessair	0:7e2bd16f80af	2708	}
elessair	0:7e2bd16f80af	2709	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
elessair	0:7e2bd16f80af	2710	}
elessair	0:7e2bd16f80af	2711	}
elessair	0:7e2bd16f80af	2712	/* Capture compare 4 event */
elessair	0:7e2bd16f80af	2713	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
elessair	0:7e2bd16f80af	2714	{
elessair	0:7e2bd16f80af	2715	if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC4) !=RESET)
elessair	0:7e2bd16f80af	2716	{
elessair	0:7e2bd16f80af	2717	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
elessair	0:7e2bd16f80af	2718	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
elessair	0:7e2bd16f80af	2719	/* Input capture event */
elessair	0:7e2bd16f80af	2720	if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)
elessair	0:7e2bd16f80af	2721	{
elessair	0:7e2bd16f80af	2722	HAL_TIM_IC_CaptureCallback(htim);
elessair	0:7e2bd16f80af	2723	}
elessair	0:7e2bd16f80af	2724	/* Output compare event */
elessair	0:7e2bd16f80af	2725	else
elessair	0:7e2bd16f80af	2726	{
elessair	0:7e2bd16f80af	2727	HAL_TIM_OC_DelayElapsedCallback(htim);
elessair	0:7e2bd16f80af	2728	HAL_TIM_PWM_PulseFinishedCallback(htim);
elessair	0:7e2bd16f80af	2729	}
elessair	0:7e2bd16f80af	2730	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
elessair	0:7e2bd16f80af	2731	}
elessair	0:7e2bd16f80af	2732	}
elessair	0:7e2bd16f80af	2733	/* TIM Update event */
elessair	0:7e2bd16f80af	2734	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
elessair	0:7e2bd16f80af	2735	{
elessair	0:7e2bd16f80af	2736	if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_UPDATE) !=RESET)
elessair	0:7e2bd16f80af	2737	{
elessair	0:7e2bd16f80af	2738	__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
elessair	0:7e2bd16f80af	2739	HAL_TIM_PeriodElapsedCallback(htim);
elessair	0:7e2bd16f80af	2740	}
elessair	0:7e2bd16f80af	2741	}
elessair	0:7e2bd16f80af	2742	/* TIM Trigger detection event */
elessair	0:7e2bd16f80af	2743	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
elessair	0:7e2bd16f80af	2744	{
elessair	0:7e2bd16f80af	2745	if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_TRIGGER) !=RESET)
elessair	0:7e2bd16f80af	2746	{
elessair	0:7e2bd16f80af	2747	__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
elessair	0:7e2bd16f80af	2748	HAL_TIM_TriggerCallback(htim);
elessair	0:7e2bd16f80af	2749	}
elessair	0:7e2bd16f80af	2750	}
elessair	0:7e2bd16f80af	2751	}
elessair	0:7e2bd16f80af	2752
elessair	0:7e2bd16f80af	2753	/**
elessair	0:7e2bd16f80af	2754	* @}
elessair	0:7e2bd16f80af	2755	*/
elessair	0:7e2bd16f80af	2756
elessair	0:7e2bd16f80af	2757	/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
elessair	0:7e2bd16f80af	2758	* @brief Peripheral Control functions
elessair	0:7e2bd16f80af	2759	*
elessair	0:7e2bd16f80af	2760	@verbatim
elessair	0:7e2bd16f80af	2761	==============================================================================
elessair	0:7e2bd16f80af	2762	##### Peripheral Control functions #####
elessair	0:7e2bd16f80af	2763	==============================================================================
elessair	0:7e2bd16f80af	2764	[..]
elessair	0:7e2bd16f80af	2765	This section provides functions allowing to:
elessair	0:7e2bd16f80af	2766	(+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
elessair	0:7e2bd16f80af	2767	(+) Configure External Clock source.
elessair	0:7e2bd16f80af	2768	(+) Configure Complementary channels, break features and dead time.
elessair	0:7e2bd16f80af	2769	(+) Configure Master and the Slave synchronization.
elessair	0:7e2bd16f80af	2770	(+) Configure the DMA Burst Mode.
elessair	0:7e2bd16f80af	2771
elessair	0:7e2bd16f80af	2772	@endverbatim
elessair	0:7e2bd16f80af	2773	* @{
elessair	0:7e2bd16f80af	2774	*/
elessair	0:7e2bd16f80af	2775
elessair	0:7e2bd16f80af	2776	/**
elessair	0:7e2bd16f80af	2777	* @brief Initializes the TIM Output Compare Channels according to the specified
elessair	0:7e2bd16f80af	2778	* parameters in the TIM_OC_InitTypeDef.
elessair	0:7e2bd16f80af	2779	* @param htim: TIM Output Compare handle
elessair	0:7e2bd16f80af	2780	* @param sConfig: TIM Output Compare configuration structure
elessair	0:7e2bd16f80af	2781	* @param Channel : TIM Channels to be enabled
elessair	0:7e2bd16f80af	2782	* This parameter can be one of the following values:
elessair	0:7e2bd16f80af	2783	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
elessair	0:7e2bd16f80af	2784	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
elessair	0:7e2bd16f80af	2785	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
elessair	0:7e2bd16f80af	2786	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
elessair	0:7e2bd16f80af	2787	* @retval HAL status
elessair	0:7e2bd16f80af	2788	*/
elessair	0:7e2bd16f80af	2789	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel)
elessair	0:7e2bd16f80af	2790	{
elessair	0:7e2bd16f80af	2791	/* Check the parameters */
elessair	0:7e2bd16f80af	2792	assert_param(IS_TIM_CHANNELS(Channel));
elessair	0:7e2bd16f80af	2793	assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
elessair	0:7e2bd16f80af	2794	assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
elessair	0:7e2bd16f80af	2795	assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
elessair	0:7e2bd16f80af	2796
elessair	0:7e2bd16f80af	2797	/* Check input state */
elessair	0:7e2bd16f80af	2798	__HAL_LOCK(htim);
elessair	0:7e2bd16f80af	2799
elessair	0:7e2bd16f80af	2800	htim->State = HAL_TIM_STATE_BUSY;
elessair	0:7e2bd16f80af	2801
elessair	0:7e2bd16f80af	2802	switch (Channel)
elessair	0:7e2bd16f80af	2803	{
elessair	0:7e2bd16f80af	2804	case TIM_CHANNEL_1:
elessair	0:7e2bd16f80af	2805	{
elessair	0:7e2bd16f80af	2806	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	2807	/* Configure the TIM Channel 1 in Output Compare */
elessair	0:7e2bd16f80af	2808	TIM_OC1_SetConfig(htim->Instance, sConfig);
elessair	0:7e2bd16f80af	2809	}
elessair	0:7e2bd16f80af	2810	break;
elessair	0:7e2bd16f80af	2811
elessair	0:7e2bd16f80af	2812	case TIM_CHANNEL_2:
elessair	0:7e2bd16f80af	2813	{
elessair	0:7e2bd16f80af	2814	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	2815	/* Configure the TIM Channel 2 in Output Compare */
elessair	0:7e2bd16f80af	2816	TIM_OC2_SetConfig(htim->Instance, sConfig);
elessair	0:7e2bd16f80af	2817	}
elessair	0:7e2bd16f80af	2818	break;
elessair	0:7e2bd16f80af	2819
elessair	0:7e2bd16f80af	2820	case TIM_CHANNEL_3:
elessair	0:7e2bd16f80af	2821	{
elessair	0:7e2bd16f80af	2822	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	2823	/* Configure the TIM Channel 3 in Output Compare */
elessair	0:7e2bd16f80af	2824	TIM_OC3_SetConfig(htim->Instance, sConfig);
elessair	0:7e2bd16f80af	2825	}
elessair	0:7e2bd16f80af	2826	break;
elessair	0:7e2bd16f80af	2827
elessair	0:7e2bd16f80af	2828	case TIM_CHANNEL_4:
elessair	0:7e2bd16f80af	2829	{
elessair	0:7e2bd16f80af	2830	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	2831	/* Configure the TIM Channel 4 in Output Compare */
elessair	0:7e2bd16f80af	2832	TIM_OC4_SetConfig(htim->Instance, sConfig);
elessair	0:7e2bd16f80af	2833	}
elessair	0:7e2bd16f80af	2834	break;
elessair	0:7e2bd16f80af	2835
elessair	0:7e2bd16f80af	2836	default:
elessair	0:7e2bd16f80af	2837	break;
elessair	0:7e2bd16f80af	2838	}
elessair	0:7e2bd16f80af	2839	htim->State = HAL_TIM_STATE_READY;
elessair	0:7e2bd16f80af	2840
elessair	0:7e2bd16f80af	2841	__HAL_UNLOCK(htim);
elessair	0:7e2bd16f80af	2842
elessair	0:7e2bd16f80af	2843	return HAL_OK;
elessair	0:7e2bd16f80af	2844	}
elessair	0:7e2bd16f80af	2845
elessair	0:7e2bd16f80af	2846	/**
elessair	0:7e2bd16f80af	2847	* @brief Initializes the TIM Input Capture Channels according to the specified
elessair	0:7e2bd16f80af	2848	* parameters in the TIM_IC_InitTypeDef.
elessair	0:7e2bd16f80af	2849	* @param htim: TIM IC handle
elessair	0:7e2bd16f80af	2850	* @param sConfig: TIM Input Capture configuration structure
elessair	0:7e2bd16f80af	2851	* @param Channel : TIM Channels to be enabled
elessair	0:7e2bd16f80af	2852	* This parameter can be one of the following values:
elessair	0:7e2bd16f80af	2853	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
elessair	0:7e2bd16f80af	2854	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
elessair	0:7e2bd16f80af	2855	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
elessair	0:7e2bd16f80af	2856	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
elessair	0:7e2bd16f80af	2857	* @retval HAL status
elessair	0:7e2bd16f80af	2858	*/
elessair	0:7e2bd16f80af	2859	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel)
elessair	0:7e2bd16f80af	2860	{
elessair	0:7e2bd16f80af	2861	/* Check the parameters */
elessair	0:7e2bd16f80af	2862	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	2863	assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
elessair	0:7e2bd16f80af	2864	assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
elessair	0:7e2bd16f80af	2865	assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
elessair	0:7e2bd16f80af	2866	assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
elessair	0:7e2bd16f80af	2867
elessair	0:7e2bd16f80af	2868	__HAL_LOCK(htim);
elessair	0:7e2bd16f80af	2869
elessair	0:7e2bd16f80af	2870	htim->State = HAL_TIM_STATE_BUSY;
elessair	0:7e2bd16f80af	2871
elessair	0:7e2bd16f80af	2872	if (Channel == TIM_CHANNEL_1)
elessair	0:7e2bd16f80af	2873	{
elessair	0:7e2bd16f80af	2874	/* TI1 Configuration */
elessair	0:7e2bd16f80af	2875	TIM_TI1_SetConfig(htim->Instance,
elessair	0:7e2bd16f80af	2876	sConfig->ICPolarity,
elessair	0:7e2bd16f80af	2877	sConfig->ICSelection,
elessair	0:7e2bd16f80af	2878	sConfig->ICFilter);
elessair	0:7e2bd16f80af	2879
elessair	0:7e2bd16f80af	2880	/* Reset the IC1PSC Bits */
elessair	0:7e2bd16f80af	2881	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
elessair	0:7e2bd16f80af	2882
elessair	0:7e2bd16f80af	2883	/* Set the IC1PSC value */
elessair	0:7e2bd16f80af	2884	htim->Instance->CCMR1 \|= sConfig->ICPrescaler;
elessair	0:7e2bd16f80af	2885	}
elessair	0:7e2bd16f80af	2886	else if (Channel == TIM_CHANNEL_2)
elessair	0:7e2bd16f80af	2887	{
elessair	0:7e2bd16f80af	2888	/* TI2 Configuration */
elessair	0:7e2bd16f80af	2889	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	2890
elessair	0:7e2bd16f80af	2891	TIM_TI2_SetConfig(htim->Instance,
elessair	0:7e2bd16f80af	2892	sConfig->ICPolarity,
elessair	0:7e2bd16f80af	2893	sConfig->ICSelection,
elessair	0:7e2bd16f80af	2894	sConfig->ICFilter);
elessair	0:7e2bd16f80af	2895
elessair	0:7e2bd16f80af	2896	/* Reset the IC2PSC Bits */
elessair	0:7e2bd16f80af	2897	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
elessair	0:7e2bd16f80af	2898
elessair	0:7e2bd16f80af	2899	/* Set the IC2PSC value */
elessair	0:7e2bd16f80af	2900	htim->Instance->CCMR1 \|= (sConfig->ICPrescaler << 8);
elessair	0:7e2bd16f80af	2901	}
elessair	0:7e2bd16f80af	2902	else if (Channel == TIM_CHANNEL_3)
elessair	0:7e2bd16f80af	2903	{
elessair	0:7e2bd16f80af	2904	/* TI3 Configuration */
elessair	0:7e2bd16f80af	2905	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	2906
elessair	0:7e2bd16f80af	2907	TIM_TI3_SetConfig(htim->Instance,
elessair	0:7e2bd16f80af	2908	sConfig->ICPolarity,
elessair	0:7e2bd16f80af	2909	sConfig->ICSelection,
elessair	0:7e2bd16f80af	2910	sConfig->ICFilter);
elessair	0:7e2bd16f80af	2911
elessair	0:7e2bd16f80af	2912	/* Reset the IC3PSC Bits */
elessair	0:7e2bd16f80af	2913	htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
elessair	0:7e2bd16f80af	2914
elessair	0:7e2bd16f80af	2915	/* Set the IC3PSC value */
elessair	0:7e2bd16f80af	2916	htim->Instance->CCMR2 \|= sConfig->ICPrescaler;
elessair	0:7e2bd16f80af	2917	}
elessair	0:7e2bd16f80af	2918	else
elessair	0:7e2bd16f80af	2919	{
elessair	0:7e2bd16f80af	2920	/* TI4 Configuration */
elessair	0:7e2bd16f80af	2921	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	2922
elessair	0:7e2bd16f80af	2923	TIM_TI4_SetConfig(htim->Instance,
elessair	0:7e2bd16f80af	2924	sConfig->ICPolarity,
elessair	0:7e2bd16f80af	2925	sConfig->ICSelection,
elessair	0:7e2bd16f80af	2926	sConfig->ICFilter);
elessair	0:7e2bd16f80af	2927
elessair	0:7e2bd16f80af	2928	/* Reset the IC4PSC Bits */
elessair	0:7e2bd16f80af	2929	htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
elessair	0:7e2bd16f80af	2930
elessair	0:7e2bd16f80af	2931	/* Set the IC4PSC value */
elessair	0:7e2bd16f80af	2932	htim->Instance->CCMR2 \|= (sConfig->ICPrescaler << 8);
elessair	0:7e2bd16f80af	2933	}
elessair	0:7e2bd16f80af	2934
elessair	0:7e2bd16f80af	2935	htim->State = HAL_TIM_STATE_READY;
elessair	0:7e2bd16f80af	2936
elessair	0:7e2bd16f80af	2937	__HAL_UNLOCK(htim);
elessair	0:7e2bd16f80af	2938
elessair	0:7e2bd16f80af	2939	return HAL_OK;
elessair	0:7e2bd16f80af	2940	}
elessair	0:7e2bd16f80af	2941
elessair	0:7e2bd16f80af	2942	/**
elessair	0:7e2bd16f80af	2943	* @brief Initializes the TIM PWM channels according to the specified
elessair	0:7e2bd16f80af	2944	* parameters in the TIM_OC_InitTypeDef.
elessair	0:7e2bd16f80af	2945	* @param htim: TIM handle
elessair	0:7e2bd16f80af	2946	* @param sConfig: TIM PWM configuration structure
elessair	0:7e2bd16f80af	2947	* @param Channel : TIM Channels to be enabled
elessair	0:7e2bd16f80af	2948	* This parameter can be one of the following values:
elessair	0:7e2bd16f80af	2949	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
elessair	0:7e2bd16f80af	2950	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
elessair	0:7e2bd16f80af	2951	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
elessair	0:7e2bd16f80af	2952	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
elessair	0:7e2bd16f80af	2953	* @retval HAL status
elessair	0:7e2bd16f80af	2954	*/
elessair	0:7e2bd16f80af	2955	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel)
elessair	0:7e2bd16f80af	2956	{
elessair	0:7e2bd16f80af	2957	/* Check the parameters */
elessair	0:7e2bd16f80af	2958	assert_param(IS_TIM_CHANNELS(Channel));
elessair	0:7e2bd16f80af	2959	assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
elessair	0:7e2bd16f80af	2960	assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
elessair	0:7e2bd16f80af	2961
elessair	0:7e2bd16f80af	2962	__HAL_LOCK(htim);
elessair	0:7e2bd16f80af	2963
elessair	0:7e2bd16f80af	2964	htim->State = HAL_TIM_STATE_BUSY;
elessair	0:7e2bd16f80af	2965
elessair	0:7e2bd16f80af	2966	switch (Channel)
elessair	0:7e2bd16f80af	2967	{
elessair	0:7e2bd16f80af	2968	case TIM_CHANNEL_1:
elessair	0:7e2bd16f80af	2969	{
elessair	0:7e2bd16f80af	2970	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	2971	/* Configure the Channel 1 in PWM mode */
elessair	0:7e2bd16f80af	2972	TIM_OC1_SetConfig(htim->Instance, sConfig);
elessair	0:7e2bd16f80af	2973
elessair	0:7e2bd16f80af	2974	/* Set the Preload enable bit for channel1 */
elessair	0:7e2bd16f80af	2975	htim->Instance->CCMR1 \|= TIM_CCMR1_OC1PE;
elessair	0:7e2bd16f80af	2976
elessair	0:7e2bd16f80af	2977	/* Configure the Output Fast mode */
elessair	0:7e2bd16f80af	2978	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
elessair	0:7e2bd16f80af	2979	htim->Instance->CCMR1 \|= sConfig->OCFastMode;
elessair	0:7e2bd16f80af	2980	}
elessair	0:7e2bd16f80af	2981	break;
elessair	0:7e2bd16f80af	2982
elessair	0:7e2bd16f80af	2983	case TIM_CHANNEL_2:
elessair	0:7e2bd16f80af	2984	{
elessair	0:7e2bd16f80af	2985	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	2986	/* Configure the Channel 2 in PWM mode */
elessair	0:7e2bd16f80af	2987	TIM_OC2_SetConfig(htim->Instance, sConfig);
elessair	0:7e2bd16f80af	2988
elessair	0:7e2bd16f80af	2989	/* Set the Preload enable bit for channel2 */
elessair	0:7e2bd16f80af	2990	htim->Instance->CCMR1 \|= TIM_CCMR1_OC2PE;
elessair	0:7e2bd16f80af	2991
elessair	0:7e2bd16f80af	2992	/* Configure the Output Fast mode */
elessair	0:7e2bd16f80af	2993	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
elessair	0:7e2bd16f80af	2994	htim->Instance->CCMR1 \|= sConfig->OCFastMode << 8;
elessair	0:7e2bd16f80af	2995	}
elessair	0:7e2bd16f80af	2996	break;
elessair	0:7e2bd16f80af	2997
elessair	0:7e2bd16f80af	2998	case TIM_CHANNEL_3:
elessair	0:7e2bd16f80af	2999	{
elessair	0:7e2bd16f80af	3000	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	3001	/* Configure the Channel 3 in PWM mode */
elessair	0:7e2bd16f80af	3002	TIM_OC3_SetConfig(htim->Instance, sConfig);
elessair	0:7e2bd16f80af	3003
elessair	0:7e2bd16f80af	3004	/* Set the Preload enable bit for channel3 */
elessair	0:7e2bd16f80af	3005	htim->Instance->CCMR2 \|= TIM_CCMR2_OC3PE;
elessair	0:7e2bd16f80af	3006
elessair	0:7e2bd16f80af	3007	/* Configure the Output Fast mode */
elessair	0:7e2bd16f80af	3008	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
elessair	0:7e2bd16f80af	3009	htim->Instance->CCMR2 \|= sConfig->OCFastMode;
elessair	0:7e2bd16f80af	3010	}
elessair	0:7e2bd16f80af	3011	break;
elessair	0:7e2bd16f80af	3012
elessair	0:7e2bd16f80af	3013	case TIM_CHANNEL_4:
elessair	0:7e2bd16f80af	3014	{
elessair	0:7e2bd16f80af	3015	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	3016	/* Configure the Channel 4 in PWM mode */
elessair	0:7e2bd16f80af	3017	TIM_OC4_SetConfig(htim->Instance, sConfig);
elessair	0:7e2bd16f80af	3018
elessair	0:7e2bd16f80af	3019	/* Set the Preload enable bit for channel4 */
elessair	0:7e2bd16f80af	3020	htim->Instance->CCMR2 \|= TIM_CCMR2_OC4PE;
elessair	0:7e2bd16f80af	3021
elessair	0:7e2bd16f80af	3022	/* Configure the Output Fast mode */
elessair	0:7e2bd16f80af	3023	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
elessair	0:7e2bd16f80af	3024	htim->Instance->CCMR2 \|= sConfig->OCFastMode << 8;
elessair	0:7e2bd16f80af	3025	}
elessair	0:7e2bd16f80af	3026	break;
elessair	0:7e2bd16f80af	3027
elessair	0:7e2bd16f80af	3028	default:
elessair	0:7e2bd16f80af	3029	break;
elessair	0:7e2bd16f80af	3030	}
elessair	0:7e2bd16f80af	3031
elessair	0:7e2bd16f80af	3032	htim->State = HAL_TIM_STATE_READY;
elessair	0:7e2bd16f80af	3033
elessair	0:7e2bd16f80af	3034	__HAL_UNLOCK(htim);
elessair	0:7e2bd16f80af	3035
elessair	0:7e2bd16f80af	3036	return HAL_OK;
elessair	0:7e2bd16f80af	3037	}
elessair	0:7e2bd16f80af	3038
elessair	0:7e2bd16f80af	3039	/**
elessair	0:7e2bd16f80af	3040	* @brief Initializes the TIM One Pulse Channels according to the specified
elessair	0:7e2bd16f80af	3041	* parameters in the TIM_OnePulse_InitTypeDef.
elessair	0:7e2bd16f80af	3042	* @param htim: TIM One Pulse handle
elessair	0:7e2bd16f80af	3043	* @param sConfig: TIM One Pulse configuration structure
elessair	0:7e2bd16f80af	3044	* @param OutputChannel : TIM Channels to be enabled
elessair	0:7e2bd16f80af	3045	* This parameter can be one of the following values:
elessair	0:7e2bd16f80af	3046	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
elessair	0:7e2bd16f80af	3047	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
elessair	0:7e2bd16f80af	3048	* @param InputChannel : TIM Channels to be enabled
elessair	0:7e2bd16f80af	3049	* This parameter can be one of the following values:
elessair	0:7e2bd16f80af	3050	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
elessair	0:7e2bd16f80af	3051	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
elessair	0:7e2bd16f80af	3052	* @retval HAL status
elessair	0:7e2bd16f80af	3053	*/
elessair	0:7e2bd16f80af	3054	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel)
elessair	0:7e2bd16f80af	3055	{
elessair	0:7e2bd16f80af	3056	TIM_OC_InitTypeDef temp1;
elessair	0:7e2bd16f80af	3057
elessair	0:7e2bd16f80af	3058	/* Check the parameters */
elessair	0:7e2bd16f80af	3059	assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
elessair	0:7e2bd16f80af	3060	assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
elessair	0:7e2bd16f80af	3061
elessair	0:7e2bd16f80af	3062	if(OutputChannel != InputChannel)
elessair	0:7e2bd16f80af	3063	{
elessair	0:7e2bd16f80af	3064	__HAL_LOCK(htim);
elessair	0:7e2bd16f80af	3065
elessair	0:7e2bd16f80af	3066	htim->State = HAL_TIM_STATE_BUSY;
elessair	0:7e2bd16f80af	3067
elessair	0:7e2bd16f80af	3068	/* Extract the Ouput compare configuration from sConfig structure */
elessair	0:7e2bd16f80af	3069	temp1.OCMode = sConfig->OCMode;
elessair	0:7e2bd16f80af	3070	temp1.Pulse = sConfig->Pulse;
elessair	0:7e2bd16f80af	3071	temp1.OCPolarity = sConfig->OCPolarity;
elessair	0:7e2bd16f80af	3072	temp1.OCIdleState = sConfig->OCIdleState;
elessair	0:7e2bd16f80af	3073
elessair	0:7e2bd16f80af	3074	switch (OutputChannel)
elessair	0:7e2bd16f80af	3075	{
elessair	0:7e2bd16f80af	3076	case TIM_CHANNEL_1:
elessair	0:7e2bd16f80af	3077	{
elessair	0:7e2bd16f80af	3078	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	3079
elessair	0:7e2bd16f80af	3080	TIM_OC1_SetConfig(htim->Instance, &temp1);
elessair	0:7e2bd16f80af	3081	}
elessair	0:7e2bd16f80af	3082	break;
elessair	0:7e2bd16f80af	3083	case TIM_CHANNEL_2:
elessair	0:7e2bd16f80af	3084	{
elessair	0:7e2bd16f80af	3085	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	3086
elessair	0:7e2bd16f80af	3087	TIM_OC2_SetConfig(htim->Instance, &temp1);
elessair	0:7e2bd16f80af	3088	}
elessair	0:7e2bd16f80af	3089	break;
elessair	0:7e2bd16f80af	3090	default:
elessair	0:7e2bd16f80af	3091	break;
elessair	0:7e2bd16f80af	3092	}
elessair	0:7e2bd16f80af	3093	switch (InputChannel)
elessair	0:7e2bd16f80af	3094	{
elessair	0:7e2bd16f80af	3095	case TIM_CHANNEL_1:
elessair	0:7e2bd16f80af	3096	{
elessair	0:7e2bd16f80af	3097	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	3098
elessair	0:7e2bd16f80af	3099	TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
elessair	0:7e2bd16f80af	3100	sConfig->ICSelection, sConfig->ICFilter);
elessair	0:7e2bd16f80af	3101
elessair	0:7e2bd16f80af	3102	/* Reset the IC1PSC Bits */
elessair	0:7e2bd16f80af	3103	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
elessair	0:7e2bd16f80af	3104
elessair	0:7e2bd16f80af	3105	/* Select the Trigger source */
elessair	0:7e2bd16f80af	3106	htim->Instance->SMCR &= ~TIM_SMCR_TS;
elessair	0:7e2bd16f80af	3107	htim->Instance->SMCR \|= TIM_TS_TI1FP1;
elessair	0:7e2bd16f80af	3108
elessair	0:7e2bd16f80af	3109	/* Select the Slave Mode */
elessair	0:7e2bd16f80af	3110	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
elessair	0:7e2bd16f80af	3111	htim->Instance->SMCR \|= TIM_SLAVEMODE_TRIGGER;
elessair	0:7e2bd16f80af	3112	}
elessair	0:7e2bd16f80af	3113	break;
elessair	0:7e2bd16f80af	3114	case TIM_CHANNEL_2:
elessair	0:7e2bd16f80af	3115	{
elessair	0:7e2bd16f80af	3116	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	3117
elessair	0:7e2bd16f80af	3118	TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
elessair	0:7e2bd16f80af	3119	sConfig->ICSelection, sConfig->ICFilter);
elessair	0:7e2bd16f80af	3120
elessair	0:7e2bd16f80af	3121	/* Reset the IC2PSC Bits */
elessair	0:7e2bd16f80af	3122	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
elessair	0:7e2bd16f80af	3123
elessair	0:7e2bd16f80af	3124	/* Select the Trigger source */
elessair	0:7e2bd16f80af	3125	htim->Instance->SMCR &= ~TIM_SMCR_TS;
elessair	0:7e2bd16f80af	3126	htim->Instance->SMCR \|= TIM_TS_TI2FP2;
elessair	0:7e2bd16f80af	3127
elessair	0:7e2bd16f80af	3128	/* Select the Slave Mode */
elessair	0:7e2bd16f80af	3129	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
elessair	0:7e2bd16f80af	3130	htim->Instance->SMCR \|= TIM_SLAVEMODE_TRIGGER;
elessair	0:7e2bd16f80af	3131	}
elessair	0:7e2bd16f80af	3132	break;
elessair	0:7e2bd16f80af	3133
elessair	0:7e2bd16f80af	3134	default:
elessair	0:7e2bd16f80af	3135	break;
elessair	0:7e2bd16f80af	3136	}
elessair	0:7e2bd16f80af	3137
elessair	0:7e2bd16f80af	3138	htim->State = HAL_TIM_STATE_READY;
elessair	0:7e2bd16f80af	3139
elessair	0:7e2bd16f80af	3140	__HAL_UNLOCK(htim);
elessair	0:7e2bd16f80af	3141
elessair	0:7e2bd16f80af	3142	return HAL_OK;
elessair	0:7e2bd16f80af	3143	}
elessair	0:7e2bd16f80af	3144	else
elessair	0:7e2bd16f80af	3145	{
elessair	0:7e2bd16f80af	3146	return HAL_ERROR;
elessair	0:7e2bd16f80af	3147	}
elessair	0:7e2bd16f80af	3148	}
elessair	0:7e2bd16f80af	3149
elessair	0:7e2bd16f80af	3150	/**
elessair	0:7e2bd16f80af	3151	* @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
elessair	0:7e2bd16f80af	3152	* @param htim: TIM handle
elessair	0:7e2bd16f80af	3153	* @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write
elessair	0:7e2bd16f80af	3154	* This parameters can be on of the following values:
elessair	0:7e2bd16f80af	3155	* @arg TIM_DMABase_CR1
elessair	0:7e2bd16f80af	3156	* @arg TIM_DMABase_CR2
elessair	0:7e2bd16f80af	3157	* @arg TIM_DMABase_SMCR
elessair	0:7e2bd16f80af	3158	* @arg TIM_DMABase_DIER
elessair	0:7e2bd16f80af	3159	* @arg TIM_DMABase_SR
elessair	0:7e2bd16f80af	3160	* @arg TIM_DMABase_EGR
elessair	0:7e2bd16f80af	3161	* @arg TIM_DMABase_CCMR1
elessair	0:7e2bd16f80af	3162	* @arg TIM_DMABase_CCMR2
elessair	0:7e2bd16f80af	3163	* @arg TIM_DMABase_CCER
elessair	0:7e2bd16f80af	3164	* @arg TIM_DMABase_CNT
elessair	0:7e2bd16f80af	3165	* @arg TIM_DMABase_PSC
elessair	0:7e2bd16f80af	3166	* @arg TIM_DMABase_ARR
elessair	0:7e2bd16f80af	3167	* @arg TIM_DMABase_CCR1
elessair	0:7e2bd16f80af	3168	* @arg TIM_DMABase_CCR2
elessair	0:7e2bd16f80af	3169	* @arg TIM_DMABase_CCR3
elessair	0:7e2bd16f80af	3170	* @arg TIM_DMABase_CCR4
elessair	0:7e2bd16f80af	3171	* @arg TIM_DMABase_DCR
elessair	0:7e2bd16f80af	3172	* @param BurstRequestSrc: TIM DMA Request sources
elessair	0:7e2bd16f80af	3173	* This parameters can be on of the following values:
elessair	0:7e2bd16f80af	3174	* @arg TIM_DMA_UPDATE: TIM update Interrupt source
elessair	0:7e2bd16f80af	3175	* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
elessair	0:7e2bd16f80af	3176	* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
elessair	0:7e2bd16f80af	3177	* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
elessair	0:7e2bd16f80af	3178	* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
elessair	0:7e2bd16f80af	3179	* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
elessair	0:7e2bd16f80af	3180	* @param BurstBuffer: The Buffer address.
elessair	0:7e2bd16f80af	3181	* @param BurstLength: DMA Burst length. This parameter can be one value
elessair	0:7e2bd16f80af	3182	* between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
elessair	0:7e2bd16f80af	3183	* @retval HAL status
elessair	0:7e2bd16f80af	3184	*/
elessair	0:7e2bd16f80af	3185	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
elessair	0:7e2bd16f80af	3186	uint32_t* BurstBuffer, uint32_t BurstLength)
elessair	0:7e2bd16f80af	3187	{
elessair	0:7e2bd16f80af	3188	/* Check the parameters */
elessair	0:7e2bd16f80af	3189	assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	3190	assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
elessair	0:7e2bd16f80af	3191	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
elessair	0:7e2bd16f80af	3192	assert_param(IS_TIM_DMA_LENGTH(BurstLength));
elessair	0:7e2bd16f80af	3193
elessair	0:7e2bd16f80af	3194	if((htim->State == HAL_TIM_STATE_BUSY))
elessair	0:7e2bd16f80af	3195	{
elessair	0:7e2bd16f80af	3196	return HAL_BUSY;
elessair	0:7e2bd16f80af	3197	}
elessair	0:7e2bd16f80af	3198	else if((htim->State == HAL_TIM_STATE_READY))
elessair	0:7e2bd16f80af	3199	{
elessair	0:7e2bd16f80af	3200	if((BurstBuffer == 0 ) && (BurstLength > 0))
elessair	0:7e2bd16f80af	3201	{
elessair	0:7e2bd16f80af	3202	return HAL_ERROR;
elessair	0:7e2bd16f80af	3203	}
elessair	0:7e2bd16f80af	3204	else
elessair	0:7e2bd16f80af	3205	{
elessair	0:7e2bd16f80af	3206	htim->State = HAL_TIM_STATE_BUSY;
elessair	0:7e2bd16f80af	3207	}
elessair	0:7e2bd16f80af	3208	}
elessair	0:7e2bd16f80af	3209	else
elessair	0:7e2bd16f80af	3210	{
elessair	0:7e2bd16f80af	3211	return HAL_ERROR;
elessair	0:7e2bd16f80af	3212	}
elessair	0:7e2bd16f80af	3213
elessair	0:7e2bd16f80af	3214	switch(BurstRequestSrc)
elessair	0:7e2bd16f80af	3215	{
elessair	0:7e2bd16f80af	3216	case TIM_DMA_UPDATE:
elessair	0:7e2bd16f80af	3217	{
elessair	0:7e2bd16f80af	3218	/* Set the DMA Period elapsed callback */
elessair	0:7e2bd16f80af	3219	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
elessair	0:7e2bd16f80af	3220
elessair	0:7e2bd16f80af	3221	/* Set the DMA error callback */
elessair	0:7e2bd16f80af	3222	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
elessair	0:7e2bd16f80af	3223
elessair	0:7e2bd16f80af	3224	/* Enable the DMA channel */
elessair	0:7e2bd16f80af	3225	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
elessair	0:7e2bd16f80af	3226	}
elessair	0:7e2bd16f80af	3227	break;
elessair	0:7e2bd16f80af	3228	case TIM_DMA_CC1:
elessair	0:7e2bd16f80af	3229	{
elessair	0:7e2bd16f80af	3230	/* Set the DMA Period elapsed callback */
elessair	0:7e2bd16f80af	3231	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
elessair	0:7e2bd16f80af	3232
elessair	0:7e2bd16f80af	3233	/* Set the DMA error callback */
elessair	0:7e2bd16f80af	3234	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
elessair	0:7e2bd16f80af	3235
elessair	0:7e2bd16f80af	3236	/* Enable the DMA channel */
elessair	0:7e2bd16f80af	3237	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
elessair	0:7e2bd16f80af	3238	}
elessair	0:7e2bd16f80af	3239	break;
elessair	0:7e2bd16f80af	3240	case TIM_DMA_CC2:
elessair	0:7e2bd16f80af	3241	{
elessair	0:7e2bd16f80af	3242	/* Set the DMA Period elapsed callback */
elessair	0:7e2bd16f80af	3243	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
elessair	0:7e2bd16f80af	3244
elessair	0:7e2bd16f80af	3245	/* Set the DMA error callback */
elessair	0:7e2bd16f80af	3246	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
elessair	0:7e2bd16f80af	3247
elessair	0:7e2bd16f80af	3248	/* Enable the DMA channel */
elessair	0:7e2bd16f80af	3249	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
elessair	0:7e2bd16f80af	3250	}
elessair	0:7e2bd16f80af	3251	break;
elessair	0:7e2bd16f80af	3252	case TIM_DMA_CC3:
elessair	0:7e2bd16f80af	3253	{
elessair	0:7e2bd16f80af	3254	/* Set the DMA Period elapsed callback */
elessair	0:7e2bd16f80af	3255	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
elessair	0:7e2bd16f80af	3256
elessair	0:7e2bd16f80af	3257	/* Set the DMA error callback */
elessair	0:7e2bd16f80af	3258	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
elessair	0:7e2bd16f80af	3259
elessair	0:7e2bd16f80af	3260	/* Enable the DMA channel */
elessair	0:7e2bd16f80af	3261	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
elessair	0:7e2bd16f80af	3262	}
elessair	0:7e2bd16f80af	3263	break;
elessair	0:7e2bd16f80af	3264	case TIM_DMA_CC4:
elessair	0:7e2bd16f80af	3265	{
elessair	0:7e2bd16f80af	3266	/* Set the DMA Period elapsed callback */
elessair	0:7e2bd16f80af	3267	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
elessair	0:7e2bd16f80af	3268
elessair	0:7e2bd16f80af	3269	/* Set the DMA error callback */
elessair	0:7e2bd16f80af	3270	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
elessair	0:7e2bd16f80af	3271
elessair	0:7e2bd16f80af	3272	/* Enable the DMA channel */
elessair	0:7e2bd16f80af	3273	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
elessair	0:7e2bd16f80af	3274	}
elessair	0:7e2bd16f80af	3275	break;
elessair	0:7e2bd16f80af	3276	case TIM_DMA_TRIGGER:
elessair	0:7e2bd16f80af	3277	{
elessair	0:7e2bd16f80af	3278	/* Set the DMA Period elapsed callback */
elessair	0:7e2bd16f80af	3279	htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
elessair	0:7e2bd16f80af	3280
elessair	0:7e2bd16f80af	3281	/* Set the DMA error callback */
elessair	0:7e2bd16f80af	3282	htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
elessair	0:7e2bd16f80af	3283
elessair	0:7e2bd16f80af	3284	/* Enable the DMA channel */
elessair	0:7e2bd16f80af	3285	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
elessair	0:7e2bd16f80af	3286	}
elessair	0:7e2bd16f80af	3287	break;
elessair	0:7e2bd16f80af	3288	default:
elessair	0:7e2bd16f80af	3289	break;
elessair	0:7e2bd16f80af	3290	}
elessair	0:7e2bd16f80af	3291	/* configure the DMA Burst Mode */
elessair	0:7e2bd16f80af	3292	htim->Instance->DCR = BurstBaseAddress \| BurstLength;
elessair	0:7e2bd16f80af	3293
elessair	0:7e2bd16f80af	3294	/* Enable the TIM DMA Request */
elessair	0:7e2bd16f80af	3295	__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
elessair	0:7e2bd16f80af	3296
elessair	0:7e2bd16f80af	3297	htim->State = HAL_TIM_STATE_READY;
elessair	0:7e2bd16f80af	3298
elessair	0:7e2bd16f80af	3299	/* Return function status */
elessair	0:7e2bd16f80af	3300	return HAL_OK;
elessair	0:7e2bd16f80af	3301	}
elessair	0:7e2bd16f80af	3302
elessair	0:7e2bd16f80af	3303	/**
elessair	0:7e2bd16f80af	3304	* @brief Stops the TIM DMA Burst mode
elessair	0:7e2bd16f80af	3305	* @param htim: TIM handle
elessair	0:7e2bd16f80af	3306	* @param BurstRequestSrc: TIM DMA Request sources to disable
elessair	0:7e2bd16f80af	3307	* @retval HAL status
elessair	0:7e2bd16f80af	3308	*/
elessair	0:7e2bd16f80af	3309	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
elessair	0:7e2bd16f80af	3310	{
elessair	0:7e2bd16f80af	3311	/* Check the parameters */
elessair	0:7e2bd16f80af	3312	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
elessair	0:7e2bd16f80af	3313
elessair	0:7e2bd16f80af	3314	/* Abort the DMA transfer (at least disable the DMA channel) */
elessair	0:7e2bd16f80af	3315	switch(BurstRequestSrc)
elessair	0:7e2bd16f80af	3316	{
elessair	0:7e2bd16f80af	3317	case TIM_DMA_UPDATE:
elessair	0:7e2bd16f80af	3318	{
elessair	0:7e2bd16f80af	3319	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
elessair	0:7e2bd16f80af	3320	}
elessair	0:7e2bd16f80af	3321	break;
elessair	0:7e2bd16f80af	3322	case TIM_DMA_CC1:
elessair	0:7e2bd16f80af	3323	{
elessair	0:7e2bd16f80af	3324	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
elessair	0:7e2bd16f80af	3325	}
elessair	0:7e2bd16f80af	3326	break;
elessair	0:7e2bd16f80af	3327	case TIM_DMA_CC2:
elessair	0:7e2bd16f80af	3328	{
elessair	0:7e2bd16f80af	3329	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
elessair	0:7e2bd16f80af	3330	}
elessair	0:7e2bd16f80af	3331	break;
elessair	0:7e2bd16f80af	3332	case TIM_DMA_CC3:
elessair	0:7e2bd16f80af	3333	{
elessair	0:7e2bd16f80af	3334	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
elessair	0:7e2bd16f80af	3335	}
elessair	0:7e2bd16f80af	3336	break;
elessair	0:7e2bd16f80af	3337	case TIM_DMA_CC4:
elessair	0:7e2bd16f80af	3338	{
elessair	0:7e2bd16f80af	3339	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
elessair	0:7e2bd16f80af	3340	}
elessair	0:7e2bd16f80af	3341	break;
elessair	0:7e2bd16f80af	3342	case TIM_DMA_TRIGGER:
elessair	0:7e2bd16f80af	3343	{
elessair	0:7e2bd16f80af	3344	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
elessair	0:7e2bd16f80af	3345	}
elessair	0:7e2bd16f80af	3346	break;
elessair	0:7e2bd16f80af	3347	default:
elessair	0:7e2bd16f80af	3348	break;
elessair	0:7e2bd16f80af	3349	}
elessair	0:7e2bd16f80af	3350
elessair	0:7e2bd16f80af	3351	/* Disable the TIM Update DMA request */
elessair	0:7e2bd16f80af	3352	__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
elessair	0:7e2bd16f80af	3353
elessair	0:7e2bd16f80af	3354	/* Return function status */
elessair	0:7e2bd16f80af	3355	return HAL_OK;
elessair	0:7e2bd16f80af	3356	}
elessair	0:7e2bd16f80af	3357
elessair	0:7e2bd16f80af	3358	/**
elessair	0:7e2bd16f80af	3359	* @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
elessair	0:7e2bd16f80af	3360	* @param htim: TIM handle
elessair	0:7e2bd16f80af	3361	* @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read
elessair	0:7e2bd16f80af	3362	* This parameters can be on of the following values:
elessair	0:7e2bd16f80af	3363	* @arg TIM_DMABase_CR1
elessair	0:7e2bd16f80af	3364	* @arg TIM_DMABase_CR2
elessair	0:7e2bd16f80af	3365	* @arg TIM_DMABase_SMCR
elessair	0:7e2bd16f80af	3366	* @arg TIM_DMABase_DIER
elessair	0:7e2bd16f80af	3367	* @arg TIM_DMABase_SR
elessair	0:7e2bd16f80af	3368	* @arg TIM_DMABase_EGR
elessair	0:7e2bd16f80af	3369	* @arg TIM_DMABase_CCMR1
elessair	0:7e2bd16f80af	3370	* @arg TIM_DMABase_CCMR2
elessair	0:7e2bd16f80af	3371	* @arg TIM_DMABase_CCER
elessair	0:7e2bd16f80af	3372	* @arg TIM_DMABase_CNT
elessair	0:7e2bd16f80af	3373	* @arg TIM_DMABase_PSC
elessair	0:7e2bd16f80af	3374	* @arg TIM_DMABase_ARR
elessair	0:7e2bd16f80af	3375	* @arg TIM_DMABase_RCR
elessair	0:7e2bd16f80af	3376	* @arg TIM_DMABase_CCR1
elessair	0:7e2bd16f80af	3377	* @arg TIM_DMABase_CCR2
elessair	0:7e2bd16f80af	3378	* @arg TIM_DMABase_CCR3
elessair	0:7e2bd16f80af	3379	* @arg TIM_DMABase_CCR4
elessair	0:7e2bd16f80af	3380	* @arg TIM_DMABase_BDTR
elessair	0:7e2bd16f80af	3381	* @arg TIM_DMABase_DCR
elessair	0:7e2bd16f80af	3382	* @param BurstRequestSrc: TIM DMA Request sources
elessair	0:7e2bd16f80af	3383	* This parameters can be on of the following values:
elessair	0:7e2bd16f80af	3384	* @arg TIM_DMA_UPDATE: TIM update Interrupt source
elessair	0:7e2bd16f80af	3385	* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
elessair	0:7e2bd16f80af	3386	* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
elessair	0:7e2bd16f80af	3387	* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
elessair	0:7e2bd16f80af	3388	* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
elessair	0:7e2bd16f80af	3389	* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
elessair	0:7e2bd16f80af	3390	* @param BurstBuffer: The Buffer address.
elessair	0:7e2bd16f80af	3391	* @param BurstLength: DMA Burst length. This parameter can be one value
elessair	0:7e2bd16f80af	3392	* between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
elessair	0:7e2bd16f80af	3393	* @retval HAL status
elessair	0:7e2bd16f80af	3394	*/
elessair	0:7e2bd16f80af	3395	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
elessair	0:7e2bd16f80af	3396	uint32_t *BurstBuffer, uint32_t BurstLength)
elessair	0:7e2bd16f80af	3397	{
elessair	0:7e2bd16f80af	3398	/* Check the parameters */
elessair	0:7e2bd16f80af	3399	assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	3400	assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
elessair	0:7e2bd16f80af	3401	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
elessair	0:7e2bd16f80af	3402	assert_param(IS_TIM_DMA_LENGTH(BurstLength));
elessair	0:7e2bd16f80af	3403
elessair	0:7e2bd16f80af	3404	if((htim->State == HAL_TIM_STATE_BUSY))
elessair	0:7e2bd16f80af	3405	{
elessair	0:7e2bd16f80af	3406	return HAL_BUSY;
elessair	0:7e2bd16f80af	3407	}
elessair	0:7e2bd16f80af	3408	else if((htim->State == HAL_TIM_STATE_READY))
elessair	0:7e2bd16f80af	3409	{
elessair	0:7e2bd16f80af	3410	if((BurstBuffer == 0 ) && (BurstLength > 0))
elessair	0:7e2bd16f80af	3411	{
elessair	0:7e2bd16f80af	3412	return HAL_ERROR;
elessair	0:7e2bd16f80af	3413	}
elessair	0:7e2bd16f80af	3414	else
elessair	0:7e2bd16f80af	3415	{
elessair	0:7e2bd16f80af	3416	htim->State = HAL_TIM_STATE_BUSY;
elessair	0:7e2bd16f80af	3417	}
elessair	0:7e2bd16f80af	3418	}
elessair	0:7e2bd16f80af	3419	else
elessair	0:7e2bd16f80af	3420	{
elessair	0:7e2bd16f80af	3421	return HAL_ERROR;
elessair	0:7e2bd16f80af	3422	}
elessair	0:7e2bd16f80af	3423
elessair	0:7e2bd16f80af	3424	switch(BurstRequestSrc)
elessair	0:7e2bd16f80af	3425	{
elessair	0:7e2bd16f80af	3426	case TIM_DMA_UPDATE:
elessair	0:7e2bd16f80af	3427	{
elessair	0:7e2bd16f80af	3428	/* Set the DMA Period elapsed callback */
elessair	0:7e2bd16f80af	3429	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
elessair	0:7e2bd16f80af	3430
elessair	0:7e2bd16f80af	3431	/* Set the DMA error callback */
elessair	0:7e2bd16f80af	3432	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
elessair	0:7e2bd16f80af	3433
elessair	0:7e2bd16f80af	3434	/* Enable the DMA channel */
elessair	0:7e2bd16f80af	3435	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
elessair	0:7e2bd16f80af	3436	}
elessair	0:7e2bd16f80af	3437	break;
elessair	0:7e2bd16f80af	3438	case TIM_DMA_CC1:
elessair	0:7e2bd16f80af	3439	{
elessair	0:7e2bd16f80af	3440	/* Set the DMA Period elapsed callback */
elessair	0:7e2bd16f80af	3441	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
elessair	0:7e2bd16f80af	3442
elessair	0:7e2bd16f80af	3443	/* Set the DMA error callback */
elessair	0:7e2bd16f80af	3444	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
elessair	0:7e2bd16f80af	3445
elessair	0:7e2bd16f80af	3446	/* Enable the DMA channel */
elessair	0:7e2bd16f80af	3447	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
elessair	0:7e2bd16f80af	3448	}
elessair	0:7e2bd16f80af	3449	break;
elessair	0:7e2bd16f80af	3450	case TIM_DMA_CC2:
elessair	0:7e2bd16f80af	3451	{
elessair	0:7e2bd16f80af	3452	/* Set the DMA Period elapsed callback */
elessair	0:7e2bd16f80af	3453	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
elessair	0:7e2bd16f80af	3454
elessair	0:7e2bd16f80af	3455	/* Set the DMA error callback */
elessair	0:7e2bd16f80af	3456	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
elessair	0:7e2bd16f80af	3457
elessair	0:7e2bd16f80af	3458	/* Enable the DMA channel */
elessair	0:7e2bd16f80af	3459	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
elessair	0:7e2bd16f80af	3460	}
elessair	0:7e2bd16f80af	3461	break;
elessair	0:7e2bd16f80af	3462	case TIM_DMA_CC3:
elessair	0:7e2bd16f80af	3463	{
elessair	0:7e2bd16f80af	3464	/* Set the DMA Period elapsed callback */
elessair	0:7e2bd16f80af	3465	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
elessair	0:7e2bd16f80af	3466
elessair	0:7e2bd16f80af	3467	/* Set the DMA error callback */
elessair	0:7e2bd16f80af	3468	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
elessair	0:7e2bd16f80af	3469
elessair	0:7e2bd16f80af	3470	/* Enable the DMA channel */
elessair	0:7e2bd16f80af	3471	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
elessair	0:7e2bd16f80af	3472	}
elessair	0:7e2bd16f80af	3473	break;
elessair	0:7e2bd16f80af	3474	case TIM_DMA_CC4:
elessair	0:7e2bd16f80af	3475	{
elessair	0:7e2bd16f80af	3476	/* Set the DMA Period elapsed callback */
elessair	0:7e2bd16f80af	3477	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
elessair	0:7e2bd16f80af	3478
elessair	0:7e2bd16f80af	3479	/* Set the DMA error callback */
elessair	0:7e2bd16f80af	3480	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
elessair	0:7e2bd16f80af	3481
elessair	0:7e2bd16f80af	3482	/* Enable the DMA channel */
elessair	0:7e2bd16f80af	3483	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
elessair	0:7e2bd16f80af	3484	}
elessair	0:7e2bd16f80af	3485	break;
elessair	0:7e2bd16f80af	3486	case TIM_DMA_TRIGGER:
elessair	0:7e2bd16f80af	3487	{
elessair	0:7e2bd16f80af	3488	/* Set the DMA Period elapsed callback */
elessair	0:7e2bd16f80af	3489	htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
elessair	0:7e2bd16f80af	3490
elessair	0:7e2bd16f80af	3491	/* Set the DMA error callback */
elessair	0:7e2bd16f80af	3492	htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
elessair	0:7e2bd16f80af	3493
elessair	0:7e2bd16f80af	3494	/* Enable the DMA channel */
elessair	0:7e2bd16f80af	3495	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
elessair	0:7e2bd16f80af	3496	}
elessair	0:7e2bd16f80af	3497	break;
elessair	0:7e2bd16f80af	3498	default:
elessair	0:7e2bd16f80af	3499	break;
elessair	0:7e2bd16f80af	3500	}
elessair	0:7e2bd16f80af	3501
elessair	0:7e2bd16f80af	3502	/* configure the DMA Burst Mode */
elessair	0:7e2bd16f80af	3503	htim->Instance->DCR = BurstBaseAddress \| BurstLength;
elessair	0:7e2bd16f80af	3504
elessair	0:7e2bd16f80af	3505	/* Enable the TIM DMA Request */
elessair	0:7e2bd16f80af	3506	__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
elessair	0:7e2bd16f80af	3507
elessair	0:7e2bd16f80af	3508	htim->State = HAL_TIM_STATE_READY;
elessair	0:7e2bd16f80af	3509
elessair	0:7e2bd16f80af	3510	/* Return function status */
elessair	0:7e2bd16f80af	3511	return HAL_OK;
elessair	0:7e2bd16f80af	3512	}
elessair	0:7e2bd16f80af	3513
elessair	0:7e2bd16f80af	3514	/**
elessair	0:7e2bd16f80af	3515	* @brief Stop the DMA burst reading
elessair	0:7e2bd16f80af	3516	* @param htim: TIM handle
elessair	0:7e2bd16f80af	3517	* @param BurstRequestSrc: TIM DMA Request sources to disable.
elessair	0:7e2bd16f80af	3518	* @retval HAL status
elessair	0:7e2bd16f80af	3519	*/
elessair	0:7e2bd16f80af	3520	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
elessair	0:7e2bd16f80af	3521	{
elessair	0:7e2bd16f80af	3522	/* Check the parameters */
elessair	0:7e2bd16f80af	3523	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
elessair	0:7e2bd16f80af	3524
elessair	0:7e2bd16f80af	3525	/* Abort the DMA transfer (at least disable the DMA channel) */
elessair	0:7e2bd16f80af	3526	switch(BurstRequestSrc)
elessair	0:7e2bd16f80af	3527	{
elessair	0:7e2bd16f80af	3528	case TIM_DMA_UPDATE:
elessair	0:7e2bd16f80af	3529	{
elessair	0:7e2bd16f80af	3530	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
elessair	0:7e2bd16f80af	3531	}
elessair	0:7e2bd16f80af	3532	break;
elessair	0:7e2bd16f80af	3533	case TIM_DMA_CC1:
elessair	0:7e2bd16f80af	3534	{
elessair	0:7e2bd16f80af	3535	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
elessair	0:7e2bd16f80af	3536	}
elessair	0:7e2bd16f80af	3537	break;
elessair	0:7e2bd16f80af	3538	case TIM_DMA_CC2:
elessair	0:7e2bd16f80af	3539	{
elessair	0:7e2bd16f80af	3540	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
elessair	0:7e2bd16f80af	3541	}
elessair	0:7e2bd16f80af	3542	break;
elessair	0:7e2bd16f80af	3543	case TIM_DMA_CC3:
elessair	0:7e2bd16f80af	3544	{
elessair	0:7e2bd16f80af	3545	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
elessair	0:7e2bd16f80af	3546	}
elessair	0:7e2bd16f80af	3547	break;
elessair	0:7e2bd16f80af	3548	case TIM_DMA_CC4:
elessair	0:7e2bd16f80af	3549	{
elessair	0:7e2bd16f80af	3550	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
elessair	0:7e2bd16f80af	3551	}
elessair	0:7e2bd16f80af	3552	break;
elessair	0:7e2bd16f80af	3553	case TIM_DMA_TRIGGER:
elessair	0:7e2bd16f80af	3554	{
elessair	0:7e2bd16f80af	3555	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
elessair	0:7e2bd16f80af	3556	}
elessair	0:7e2bd16f80af	3557	break;
elessair	0:7e2bd16f80af	3558	default:
elessair	0:7e2bd16f80af	3559	break;
elessair	0:7e2bd16f80af	3560	}
elessair	0:7e2bd16f80af	3561
elessair	0:7e2bd16f80af	3562	/* Disable the TIM Update DMA request */
elessair	0:7e2bd16f80af	3563	__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
elessair	0:7e2bd16f80af	3564
elessair	0:7e2bd16f80af	3565	/* Return function status */
elessair	0:7e2bd16f80af	3566	return HAL_OK;
elessair	0:7e2bd16f80af	3567	}
elessair	0:7e2bd16f80af	3568
elessair	0:7e2bd16f80af	3569	/**
elessair	0:7e2bd16f80af	3570	* @brief Generate a software event
elessair	0:7e2bd16f80af	3571	* @param htim: TIM handle
elessair	0:7e2bd16f80af	3572	* @param EventSource: specifies the event source.
elessair	0:7e2bd16f80af	3573	* This parameter can be one of the following values:
elessair	0:7e2bd16f80af	3574	* @arg TIM_EventSource_Update: Timer update Event source
elessair	0:7e2bd16f80af	3575	* @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
elessair	0:7e2bd16f80af	3576	* @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
elessair	0:7e2bd16f80af	3577	* @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
elessair	0:7e2bd16f80af	3578	* @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
elessair	0:7e2bd16f80af	3579	* @arg TIM_EventSource_COM: Timer COM event source
elessair	0:7e2bd16f80af	3580	* @arg TIM_EventSource_Trigger: Timer Trigger Event source
elessair	0:7e2bd16f80af	3581	* @arg TIM_EventSource_Break: Timer Break event source
elessair	0:7e2bd16f80af	3582	* @note TBC can only generate an update event.
elessair	0:7e2bd16f80af	3583	* @note TIM_EventSource_COM and TIM_EventSource_Break are used only with TBC.
elessair	0:7e2bd16f80af	3584	* @retval HAL status
elessair	0:7e2bd16f80af	3585	*/
elessair	0:7e2bd16f80af	3586
elessair	0:7e2bd16f80af	3587	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
elessair	0:7e2bd16f80af	3588	{
elessair	0:7e2bd16f80af	3589	/* Check the parameters */
elessair	0:7e2bd16f80af	3590	assert_param(IS_TIM_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	3591	assert_param(IS_TIM_EVENT_SOURCE(EventSource));
elessair	0:7e2bd16f80af	3592
elessair	0:7e2bd16f80af	3593	/* Process Locked */
elessair	0:7e2bd16f80af	3594	__HAL_LOCK(htim);
elessair	0:7e2bd16f80af	3595
elessair	0:7e2bd16f80af	3596	/* Change the TIM state */
elessair	0:7e2bd16f80af	3597	htim->State = HAL_TIM_STATE_BUSY;
elessair	0:7e2bd16f80af	3598
elessair	0:7e2bd16f80af	3599	/* Set the event sources */
elessair	0:7e2bd16f80af	3600	htim->Instance->EGR = EventSource;
elessair	0:7e2bd16f80af	3601
elessair	0:7e2bd16f80af	3602	/* Change the TIM state */
elessair	0:7e2bd16f80af	3603	htim->State = HAL_TIM_STATE_READY;
elessair	0:7e2bd16f80af	3604
elessair	0:7e2bd16f80af	3605	__HAL_UNLOCK(htim);
elessair	0:7e2bd16f80af	3606
elessair	0:7e2bd16f80af	3607	/* Return function status */
elessair	0:7e2bd16f80af	3608	return HAL_OK;
elessair	0:7e2bd16f80af	3609	}
elessair	0:7e2bd16f80af	3610
elessair	0:7e2bd16f80af	3611	/**
elessair	0:7e2bd16f80af	3612	* @brief Configures the OCRef clear feature
elessair	0:7e2bd16f80af	3613	* @param htim: TIM handle
elessair	0:7e2bd16f80af	3614	* @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
elessair	0:7e2bd16f80af	3615	* contains the OCREF clear feature and parameters for the TIM peripheral.
elessair	0:7e2bd16f80af	3616	* @param Channel: specifies the TIM Channel
elessair	0:7e2bd16f80af	3617	* This parameter can be one of the following values:
elessair	0:7e2bd16f80af	3618	* @arg TIM_CHANNEL_1: TIM Channel 1
elessair	0:7e2bd16f80af	3619	* @arg TIM_CHANNEL_2: TIM Channel 2
elessair	0:7e2bd16f80af	3620	* @arg TIM_CHANNEL_3: TIM Channel 3
elessair	0:7e2bd16f80af	3621	* @arg TIM_CHANNEL_4: TIM Channel 4
elessair	0:7e2bd16f80af	3622	* @retval HAL status
elessair	0:7e2bd16f80af	3623	*/
elessair	0:7e2bd16f80af	3624	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel)
elessair	0:7e2bd16f80af	3625	{
elessair	0:7e2bd16f80af	3626
elessair	0:7e2bd16f80af	3627	/* Check the parameters */
elessair	0:7e2bd16f80af	3628	assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	3629	assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
elessair	0:7e2bd16f80af	3630	assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
elessair	0:7e2bd16f80af	3631	assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
elessair	0:7e2bd16f80af	3632	assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
elessair	0:7e2bd16f80af	3633
elessair	0:7e2bd16f80af	3634	/* Process Locked */
elessair	0:7e2bd16f80af	3635	__HAL_LOCK(htim);
elessair	0:7e2bd16f80af	3636
elessair	0:7e2bd16f80af	3637	htim->State = HAL_TIM_STATE_BUSY;
elessair	0:7e2bd16f80af	3638
elessair	0:7e2bd16f80af	3639	switch (sClearInputConfig->ClearInputSource)
elessair	0:7e2bd16f80af	3640	{
elessair	0:7e2bd16f80af	3641	case TIM_CLEARINPUTSOURCE_NONE:
elessair	0:7e2bd16f80af	3642	{
elessair	0:7e2bd16f80af	3643	/* Clear the OCREF clear selection bit */
elessair	0:7e2bd16f80af	3644	CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
elessair	0:7e2bd16f80af	3645
elessair	0:7e2bd16f80af	3646	/* Clear the ETR Bits */
elessair	0:7e2bd16f80af	3647	CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP));
elessair	0:7e2bd16f80af	3648
elessair	0:7e2bd16f80af	3649	}
elessair	0:7e2bd16f80af	3650	break;
elessair	0:7e2bd16f80af	3651
elessair	0:7e2bd16f80af	3652	case TIM_CLEARINPUTSOURCE_OCREFCLR:
elessair	0:7e2bd16f80af	3653	{
elessair	0:7e2bd16f80af	3654	/* Clear the OCREF clear selection bit */
elessair	0:7e2bd16f80af	3655	CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
elessair	0:7e2bd16f80af	3656	}
elessair	0:7e2bd16f80af	3657	break;
elessair	0:7e2bd16f80af	3658
elessair	0:7e2bd16f80af	3659	case TIM_CLEARINPUTSOURCE_ETR:
elessair	0:7e2bd16f80af	3660	{
elessair	0:7e2bd16f80af	3661	TIM_ETR_SetConfig(htim->Instance,
elessair	0:7e2bd16f80af	3662	sClearInputConfig->ClearInputPrescaler,
elessair	0:7e2bd16f80af	3663	sClearInputConfig->ClearInputPolarity,
elessair	0:7e2bd16f80af	3664	sClearInputConfig->ClearInputFilter);
elessair	0:7e2bd16f80af	3665
elessair	0:7e2bd16f80af	3666	/* Set the OCREF clear selection bit */
elessair	0:7e2bd16f80af	3667	SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
elessair	0:7e2bd16f80af	3668	}
elessair	0:7e2bd16f80af	3669	break;
elessair	0:7e2bd16f80af	3670
elessair	0:7e2bd16f80af	3671	default:
elessair	0:7e2bd16f80af	3672	break;
elessair	0:7e2bd16f80af	3673
elessair	0:7e2bd16f80af	3674	}
elessair	0:7e2bd16f80af	3675
elessair	0:7e2bd16f80af	3676	switch (Channel)
elessair	0:7e2bd16f80af	3677	{
elessair	0:7e2bd16f80af	3678	case TIM_CHANNEL_1:
elessair	0:7e2bd16f80af	3679	{
elessair	0:7e2bd16f80af	3680	if(sClearInputConfig->ClearInputState != RESET)
elessair	0:7e2bd16f80af	3681	{
elessair	0:7e2bd16f80af	3682	/* Enable the Ocref clear feature for Channel 1 */
elessair	0:7e2bd16f80af	3683	htim->Instance->CCMR1 \|= TIM_CCMR1_OC1CE;
elessair	0:7e2bd16f80af	3684	}
elessair	0:7e2bd16f80af	3685	else
elessair	0:7e2bd16f80af	3686	{
elessair	0:7e2bd16f80af	3687	/* Disable the Ocref clear feature for Channel 1 */
elessair	0:7e2bd16f80af	3688	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
elessair	0:7e2bd16f80af	3689	}
elessair	0:7e2bd16f80af	3690	}
elessair	0:7e2bd16f80af	3691	break;
elessair	0:7e2bd16f80af	3692	case TIM_CHANNEL_2:
elessair	0:7e2bd16f80af	3693	{
elessair	0:7e2bd16f80af	3694	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	3695	if(sClearInputConfig->ClearInputState != RESET)
elessair	0:7e2bd16f80af	3696	{
elessair	0:7e2bd16f80af	3697	/* Enable the Ocref clear feature for Channel 2 */
elessair	0:7e2bd16f80af	3698	htim->Instance->CCMR1 \|= TIM_CCMR1_OC2CE;
elessair	0:7e2bd16f80af	3699	}
elessair	0:7e2bd16f80af	3700	else
elessair	0:7e2bd16f80af	3701	{
elessair	0:7e2bd16f80af	3702	/* Disable the Ocref clear feature for Channel 2 */
elessair	0:7e2bd16f80af	3703	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
elessair	0:7e2bd16f80af	3704	}
elessair	0:7e2bd16f80af	3705	}
elessair	0:7e2bd16f80af	3706	break;
elessair	0:7e2bd16f80af	3707	case TIM_CHANNEL_3:
elessair	0:7e2bd16f80af	3708	{
elessair	0:7e2bd16f80af	3709	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	3710	if(sClearInputConfig->ClearInputState != RESET)
elessair	0:7e2bd16f80af	3711	{
elessair	0:7e2bd16f80af	3712	/* Enable the Ocref clear feature for Channel 3 */
elessair	0:7e2bd16f80af	3713	htim->Instance->CCMR2 \|= TIM_CCMR2_OC3CE;
elessair	0:7e2bd16f80af	3714	}
elessair	0:7e2bd16f80af	3715	else
elessair	0:7e2bd16f80af	3716	{
elessair	0:7e2bd16f80af	3717	/* Disable the Ocref clear feature for Channel 3 */
elessair	0:7e2bd16f80af	3718	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
elessair	0:7e2bd16f80af	3719	}
elessair	0:7e2bd16f80af	3720	}
elessair	0:7e2bd16f80af	3721	break;
elessair	0:7e2bd16f80af	3722	case TIM_CHANNEL_4:
elessair	0:7e2bd16f80af	3723	{
elessair	0:7e2bd16f80af	3724	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	3725	if(sClearInputConfig->ClearInputState != RESET)
elessair	0:7e2bd16f80af	3726	{
elessair	0:7e2bd16f80af	3727	/* Enable the Ocref clear feature for Channel 4 */
elessair	0:7e2bd16f80af	3728	htim->Instance->CCMR2 \|= TIM_CCMR2_OC4CE;
elessair	0:7e2bd16f80af	3729	}
elessair	0:7e2bd16f80af	3730	else
elessair	0:7e2bd16f80af	3731	{
elessair	0:7e2bd16f80af	3732	/* Disable the Ocref clear feature for Channel 4 */
elessair	0:7e2bd16f80af	3733	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
elessair	0:7e2bd16f80af	3734	}
elessair	0:7e2bd16f80af	3735	}
elessair	0:7e2bd16f80af	3736	break;
elessair	0:7e2bd16f80af	3737	default:
elessair	0:7e2bd16f80af	3738	break;
elessair	0:7e2bd16f80af	3739	}
elessair	0:7e2bd16f80af	3740
elessair	0:7e2bd16f80af	3741	htim->State = HAL_TIM_STATE_READY;
elessair	0:7e2bd16f80af	3742
elessair	0:7e2bd16f80af	3743	__HAL_UNLOCK(htim);
elessair	0:7e2bd16f80af	3744
elessair	0:7e2bd16f80af	3745	return HAL_OK;
elessair	0:7e2bd16f80af	3746	}
elessair	0:7e2bd16f80af	3747
elessair	0:7e2bd16f80af	3748	/**
elessair	0:7e2bd16f80af	3749	* @brief Configures the clock source to be used
elessair	0:7e2bd16f80af	3750	* @param htim: TIM handle
elessair	0:7e2bd16f80af	3751	* @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that
elessair	0:7e2bd16f80af	3752	* contains the clock source information for the TIM peripheral.
elessair	0:7e2bd16f80af	3753	* @retval HAL status
elessair	0:7e2bd16f80af	3754	*/
elessair	0:7e2bd16f80af	3755	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig)
elessair	0:7e2bd16f80af	3756	{
elessair	0:7e2bd16f80af	3757	uint32_t tmpsmcr = 0;
elessair	0:7e2bd16f80af	3758
elessair	0:7e2bd16f80af	3759	/* Check the parameters */
elessair	0:7e2bd16f80af	3760	assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
elessair	0:7e2bd16f80af	3761	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
elessair	0:7e2bd16f80af	3762	assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
elessair	0:7e2bd16f80af	3763	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
elessair	0:7e2bd16f80af	3764
elessair	0:7e2bd16f80af	3765	/* Process Locked */
elessair	0:7e2bd16f80af	3766	__HAL_LOCK(htim);
elessair	0:7e2bd16f80af	3767
elessair	0:7e2bd16f80af	3768	htim->State = HAL_TIM_STATE_BUSY;
elessair	0:7e2bd16f80af	3769
elessair	0:7e2bd16f80af	3770	/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
elessair	0:7e2bd16f80af	3771	tmpsmcr = htim->Instance->SMCR;
elessair	0:7e2bd16f80af	3772	tmpsmcr &= ~(TIM_SMCR_SMS \| TIM_SMCR_TS);
elessair	0:7e2bd16f80af	3773	tmpsmcr &= ~(TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP);
elessair	0:7e2bd16f80af	3774	htim->Instance->SMCR = tmpsmcr;
elessair	0:7e2bd16f80af	3775
elessair	0:7e2bd16f80af	3776	switch (sClockSourceConfig->ClockSource)
elessair	0:7e2bd16f80af	3777	{
elessair	0:7e2bd16f80af	3778	case TIM_CLOCKSOURCE_INTERNAL:
elessair	0:7e2bd16f80af	3779	{
elessair	0:7e2bd16f80af	3780	assert_param(IS_TIM_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	3781	/* Disable slave mode to clock the prescaler directly with the internal clock */
elessair	0:7e2bd16f80af	3782	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
elessair	0:7e2bd16f80af	3783	}
elessair	0:7e2bd16f80af	3784	break;
elessair	0:7e2bd16f80af	3785
elessair	0:7e2bd16f80af	3786	case TIM_CLOCKSOURCE_ETRMODE1:
elessair	0:7e2bd16f80af	3787	{
elessair	0:7e2bd16f80af	3788	/* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
elessair	0:7e2bd16f80af	3789	assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	3790
elessair	0:7e2bd16f80af	3791	/* Configure the ETR Clock source */
elessair	0:7e2bd16f80af	3792	TIM_ETR_SetConfig(htim->Instance,
elessair	0:7e2bd16f80af	3793	sClockSourceConfig->ClockPrescaler,
elessair	0:7e2bd16f80af	3794	sClockSourceConfig->ClockPolarity,
elessair	0:7e2bd16f80af	3795	sClockSourceConfig->ClockFilter);
elessair	0:7e2bd16f80af	3796	/* Get the TIMx SMCR register value */
elessair	0:7e2bd16f80af	3797	tmpsmcr = htim->Instance->SMCR;
elessair	0:7e2bd16f80af	3798	/* Reset the SMS and TS Bits */
elessair	0:7e2bd16f80af	3799	tmpsmcr &= ~(TIM_SMCR_SMS \| TIM_SMCR_TS);
elessair	0:7e2bd16f80af	3800	/* Select the External clock mode1 and the ETRF trigger */
elessair	0:7e2bd16f80af	3801	tmpsmcr \|= (TIM_SLAVEMODE_EXTERNAL1 \| TIM_CLOCKSOURCE_ETRMODE1);
elessair	0:7e2bd16f80af	3802	/* Write to TIMx SMCR */
elessair	0:7e2bd16f80af	3803	htim->Instance->SMCR = tmpsmcr;
elessair	0:7e2bd16f80af	3804	}
elessair	0:7e2bd16f80af	3805	break;
elessair	0:7e2bd16f80af	3806
elessair	0:7e2bd16f80af	3807	case TIM_CLOCKSOURCE_ETRMODE2:
elessair	0:7e2bd16f80af	3808	{
elessair	0:7e2bd16f80af	3809	/* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
elessair	0:7e2bd16f80af	3810	assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	3811
elessair	0:7e2bd16f80af	3812	/* Configure the ETR Clock source */
elessair	0:7e2bd16f80af	3813	TIM_ETR_SetConfig(htim->Instance,
elessair	0:7e2bd16f80af	3814	sClockSourceConfig->ClockPrescaler,
elessair	0:7e2bd16f80af	3815	sClockSourceConfig->ClockPolarity,
elessair	0:7e2bd16f80af	3816	sClockSourceConfig->ClockFilter);
elessair	0:7e2bd16f80af	3817	/* Enable the External clock mode2 */
elessair	0:7e2bd16f80af	3818	htim->Instance->SMCR \|= TIM_SMCR_ECE;
elessair	0:7e2bd16f80af	3819	}
elessair	0:7e2bd16f80af	3820	break;
elessair	0:7e2bd16f80af	3821
elessair	0:7e2bd16f80af	3822	case TIM_CLOCKSOURCE_TI1:
elessair	0:7e2bd16f80af	3823	{
elessair	0:7e2bd16f80af	3824	/* Check whether or not the timer instance supports external clock mode 1 */
elessair	0:7e2bd16f80af	3825	assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	3826
elessair	0:7e2bd16f80af	3827	TIM_TI1_ConfigInputStage(htim->Instance,
elessair	0:7e2bd16f80af	3828	sClockSourceConfig->ClockPolarity,
elessair	0:7e2bd16f80af	3829	sClockSourceConfig->ClockFilter);
elessair	0:7e2bd16f80af	3830	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
elessair	0:7e2bd16f80af	3831	}
elessair	0:7e2bd16f80af	3832	break;
elessair	0:7e2bd16f80af	3833	case TIM_CLOCKSOURCE_TI2:
elessair	0:7e2bd16f80af	3834	{
elessair	0:7e2bd16f80af	3835	/* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
elessair	0:7e2bd16f80af	3836	assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	3837
elessair	0:7e2bd16f80af	3838	TIM_TI2_ConfigInputStage(htim->Instance,
elessair	0:7e2bd16f80af	3839	sClockSourceConfig->ClockPolarity,
elessair	0:7e2bd16f80af	3840	sClockSourceConfig->ClockFilter);
elessair	0:7e2bd16f80af	3841	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
elessair	0:7e2bd16f80af	3842	}
elessair	0:7e2bd16f80af	3843	break;
elessair	0:7e2bd16f80af	3844	case TIM_CLOCKSOURCE_TI1ED:
elessair	0:7e2bd16f80af	3845	{
elessair	0:7e2bd16f80af	3846	/* Check whether or not the timer instance supports external clock mode 1 */
elessair	0:7e2bd16f80af	3847	assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	3848
elessair	0:7e2bd16f80af	3849	TIM_TI1_ConfigInputStage(htim->Instance,
elessair	0:7e2bd16f80af	3850	sClockSourceConfig->ClockPolarity,
elessair	0:7e2bd16f80af	3851	sClockSourceConfig->ClockFilter);
elessair	0:7e2bd16f80af	3852	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
elessair	0:7e2bd16f80af	3853	}
elessair	0:7e2bd16f80af	3854	break;
elessair	0:7e2bd16f80af	3855	case TIM_CLOCKSOURCE_ITR0:
elessair	0:7e2bd16f80af	3856	{
elessair	0:7e2bd16f80af	3857	/* Check whether or not the timer instance supports external clock mode 1 */
elessair	0:7e2bd16f80af	3858	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	3859
elessair	0:7e2bd16f80af	3860	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
elessair	0:7e2bd16f80af	3861	}
elessair	0:7e2bd16f80af	3862	break;
elessair	0:7e2bd16f80af	3863	case TIM_CLOCKSOURCE_ITR1:
elessair	0:7e2bd16f80af	3864	{
elessair	0:7e2bd16f80af	3865	/* Check whether or not the timer instance supports external clock mode 1 */
elessair	0:7e2bd16f80af	3866	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	3867
elessair	0:7e2bd16f80af	3868	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
elessair	0:7e2bd16f80af	3869	}
elessair	0:7e2bd16f80af	3870	break;
elessair	0:7e2bd16f80af	3871	case TIM_CLOCKSOURCE_ITR2:
elessair	0:7e2bd16f80af	3872	{
elessair	0:7e2bd16f80af	3873	/* Check whether or not the timer instance supports external clock mode 1 */
elessair	0:7e2bd16f80af	3874	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	3875
elessair	0:7e2bd16f80af	3876	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
elessair	0:7e2bd16f80af	3877	}
elessair	0:7e2bd16f80af	3878	break;
elessair	0:7e2bd16f80af	3879	case TIM_CLOCKSOURCE_ITR3:
elessair	0:7e2bd16f80af	3880	{
elessair	0:7e2bd16f80af	3881	/* Check whether or not the timer instance supports external clock mode 1 */
elessair	0:7e2bd16f80af	3882	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	3883
elessair	0:7e2bd16f80af	3884	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
elessair	0:7e2bd16f80af	3885	}
elessair	0:7e2bd16f80af	3886	break;
elessair	0:7e2bd16f80af	3887
elessair	0:7e2bd16f80af	3888	default:
elessair	0:7e2bd16f80af	3889	break;
elessair	0:7e2bd16f80af	3890	}
elessair	0:7e2bd16f80af	3891	htim->State = HAL_TIM_STATE_READY;
elessair	0:7e2bd16f80af	3892
elessair	0:7e2bd16f80af	3893	__HAL_UNLOCK(htim);
elessair	0:7e2bd16f80af	3894
elessair	0:7e2bd16f80af	3895	return HAL_OK;
elessair	0:7e2bd16f80af	3896	}
elessair	0:7e2bd16f80af	3897
elessair	0:7e2bd16f80af	3898	/**
elessair	0:7e2bd16f80af	3899	* @brief Selects the signal connected to the TI1 input: direct from CH1_input
elessair	0:7e2bd16f80af	3900	* or a XOR combination between CH1_input, CH2_input & CH3_input
elessair	0:7e2bd16f80af	3901	* @param htim: TIM handle.
elessair	0:7e2bd16f80af	3902	* @param TI1_Selection: Indicate whether or not channel 1 is connected to the
elessair	0:7e2bd16f80af	3903	* output of a XOR gate.
elessair	0:7e2bd16f80af	3904	* This parameter can be one of the following values:
elessair	0:7e2bd16f80af	3905	* @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
elessair	0:7e2bd16f80af	3906	* @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
elessair	0:7e2bd16f80af	3907	* pins are connected to the TI1 input (XOR combination)
elessair	0:7e2bd16f80af	3908	* @retval HAL status
elessair	0:7e2bd16f80af	3909	*/
elessair	0:7e2bd16f80af	3910	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
elessair	0:7e2bd16f80af	3911	{
elessair	0:7e2bd16f80af	3912	uint32_t tmpcr2 = 0;
elessair	0:7e2bd16f80af	3913
elessair	0:7e2bd16f80af	3914	/* Check the parameters */
elessair	0:7e2bd16f80af	3915	assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	3916	assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
elessair	0:7e2bd16f80af	3917
elessair	0:7e2bd16f80af	3918	/* Get the TIMx CR2 register value */
elessair	0:7e2bd16f80af	3919	tmpcr2 = htim->Instance->CR2;
elessair	0:7e2bd16f80af	3920
elessair	0:7e2bd16f80af	3921	/* Reset the TI1 selection */
elessair	0:7e2bd16f80af	3922	tmpcr2 &= ~TIM_CR2_TI1S;
elessair	0:7e2bd16f80af	3923
elessair	0:7e2bd16f80af	3924	/* Set the the TI1 selection */
elessair	0:7e2bd16f80af	3925	tmpcr2 \|= TI1_Selection;
elessair	0:7e2bd16f80af	3926
elessair	0:7e2bd16f80af	3927	/* Write to TIMxCR2 */
elessair	0:7e2bd16f80af	3928	htim->Instance->CR2 = tmpcr2;
elessair	0:7e2bd16f80af	3929
elessair	0:7e2bd16f80af	3930	return HAL_OK;
elessair	0:7e2bd16f80af	3931	}
elessair	0:7e2bd16f80af	3932
elessair	0:7e2bd16f80af	3933	/**
elessair	0:7e2bd16f80af	3934	* @brief Configures the TIM in Slave mode
elessair	0:7e2bd16f80af	3935	* @param htim: TIM handle.
elessair	0:7e2bd16f80af	3936	* @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
elessair	0:7e2bd16f80af	3937	* contains the selected trigger (internal trigger input, filtered
elessair	0:7e2bd16f80af	3938	* timer input or external trigger input) and the ) and the Slave
elessair	0:7e2bd16f80af	3939	* mode (Disable, Reset, Gated, Trigger, External clock mode 1).
elessair	0:7e2bd16f80af	3940	* @retval HAL status
elessair	0:7e2bd16f80af	3941	*/
elessair	0:7e2bd16f80af	3942	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig)
elessair	0:7e2bd16f80af	3943	{
elessair	0:7e2bd16f80af	3944	uint32_t tmpsmcr = 0;
elessair	0:7e2bd16f80af	3945	uint32_t tmpccmr1 = 0;
elessair	0:7e2bd16f80af	3946	uint32_t tmpccer = 0;
elessair	0:7e2bd16f80af	3947
elessair	0:7e2bd16f80af	3948	/* Check the parameters */
elessair	0:7e2bd16f80af	3949	assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	3950	assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
elessair	0:7e2bd16f80af	3951	assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
elessair	0:7e2bd16f80af	3952
elessair	0:7e2bd16f80af	3953	__HAL_LOCK(htim);
elessair	0:7e2bd16f80af	3954
elessair	0:7e2bd16f80af	3955	htim->State = HAL_TIM_STATE_BUSY;
elessair	0:7e2bd16f80af	3956
elessair	0:7e2bd16f80af	3957	/* Get the TIMx SMCR register value */
elessair	0:7e2bd16f80af	3958	tmpsmcr = htim->Instance->SMCR;
elessair	0:7e2bd16f80af	3959
elessair	0:7e2bd16f80af	3960	/* Reset the Trigger Selection Bits */
elessair	0:7e2bd16f80af	3961	tmpsmcr &= ~TIM_SMCR_TS;
elessair	0:7e2bd16f80af	3962	/* Set the Input Trigger source */
elessair	0:7e2bd16f80af	3963	tmpsmcr \|= sSlaveConfig->InputTrigger;
elessair	0:7e2bd16f80af	3964
elessair	0:7e2bd16f80af	3965	/* Reset the slave mode Bits */
elessair	0:7e2bd16f80af	3966	tmpsmcr &= ~TIM_SMCR_SMS;
elessair	0:7e2bd16f80af	3967	/* Set the slave mode */
elessair	0:7e2bd16f80af	3968	tmpsmcr \|= sSlaveConfig->SlaveMode;
elessair	0:7e2bd16f80af	3969
elessair	0:7e2bd16f80af	3970	/* Write to TIMx SMCR */
elessair	0:7e2bd16f80af	3971	htim->Instance->SMCR = tmpsmcr;
elessair	0:7e2bd16f80af	3972
elessair	0:7e2bd16f80af	3973	/* Configure the trigger prescaler, filter, and polarity */
elessair	0:7e2bd16f80af	3974	switch (sSlaveConfig->InputTrigger)
elessair	0:7e2bd16f80af	3975	{
elessair	0:7e2bd16f80af	3976	case TIM_TS_ETRF:
elessair	0:7e2bd16f80af	3977	{
elessair	0:7e2bd16f80af	3978	/* Check the parameters */
elessair	0:7e2bd16f80af	3979	assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	3980	assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
elessair	0:7e2bd16f80af	3981	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
elessair	0:7e2bd16f80af	3982	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
elessair	0:7e2bd16f80af	3983	/* Configure the ETR Trigger source */
elessair	0:7e2bd16f80af	3984	TIM_ETR_SetConfig(htim->Instance,
elessair	0:7e2bd16f80af	3985	sSlaveConfig->TriggerPrescaler,
elessair	0:7e2bd16f80af	3986	sSlaveConfig->TriggerPolarity,
elessair	0:7e2bd16f80af	3987	sSlaveConfig->TriggerFilter);
elessair	0:7e2bd16f80af	3988	}
elessair	0:7e2bd16f80af	3989	break;
elessair	0:7e2bd16f80af	3990
elessair	0:7e2bd16f80af	3991	case TIM_TS_TI1F_ED:
elessair	0:7e2bd16f80af	3992	{
elessair	0:7e2bd16f80af	3993	/* Check the parameters */
elessair	0:7e2bd16f80af	3994	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	3995	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
elessair	0:7e2bd16f80af	3996	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
elessair	0:7e2bd16f80af	3997
elessair	0:7e2bd16f80af	3998	/* Disable the Channel 1: Reset the CC1E Bit */
elessair	0:7e2bd16f80af	3999	tmpccer = htim->Instance->CCER;
elessair	0:7e2bd16f80af	4000	htim->Instance->CCER &= ~TIM_CCER_CC1E;
elessair	0:7e2bd16f80af	4001	tmpccmr1 = htim->Instance->CCMR1;
elessair	0:7e2bd16f80af	4002
elessair	0:7e2bd16f80af	4003	/* Set the filter */
elessair	0:7e2bd16f80af	4004	tmpccmr1 &= ~TIM_CCMR1_IC1F;
elessair	0:7e2bd16f80af	4005	tmpccmr1 \|= ((sSlaveConfig->TriggerFilter) << 4);
elessair	0:7e2bd16f80af	4006
elessair	0:7e2bd16f80af	4007	/* Write to TIMx CCMR1 and CCER registers */
elessair	0:7e2bd16f80af	4008	htim->Instance->CCMR1 = tmpccmr1;
elessair	0:7e2bd16f80af	4009	htim->Instance->CCER = tmpccer;
elessair	0:7e2bd16f80af	4010
elessair	0:7e2bd16f80af	4011	}
elessair	0:7e2bd16f80af	4012	break;
elessair	0:7e2bd16f80af	4013
elessair	0:7e2bd16f80af	4014	case TIM_TS_TI1FP1:
elessair	0:7e2bd16f80af	4015	{
elessair	0:7e2bd16f80af	4016	/* Check the parameters */
elessair	0:7e2bd16f80af	4017	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	4018	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
elessair	0:7e2bd16f80af	4019	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
elessair	0:7e2bd16f80af	4020
elessair	0:7e2bd16f80af	4021	/* Configure TI1 Filter and Polarity */
elessair	0:7e2bd16f80af	4022	TIM_TI1_ConfigInputStage(htim->Instance,
elessair	0:7e2bd16f80af	4023	sSlaveConfig->TriggerPolarity,
elessair	0:7e2bd16f80af	4024	sSlaveConfig->TriggerFilter);
elessair	0:7e2bd16f80af	4025	}
elessair	0:7e2bd16f80af	4026	break;
elessair	0:7e2bd16f80af	4027
elessair	0:7e2bd16f80af	4028	case TIM_TS_TI2FP2:
elessair	0:7e2bd16f80af	4029	{
elessair	0:7e2bd16f80af	4030	/* Check the parameters */
elessair	0:7e2bd16f80af	4031	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	4032	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
elessair	0:7e2bd16f80af	4033	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
elessair	0:7e2bd16f80af	4034
elessair	0:7e2bd16f80af	4035	/* Configure TI2 Filter and Polarity */
elessair	0:7e2bd16f80af	4036	TIM_TI2_ConfigInputStage(htim->Instance,
elessair	0:7e2bd16f80af	4037	sSlaveConfig->TriggerPolarity,
elessair	0:7e2bd16f80af	4038	sSlaveConfig->TriggerFilter);
elessair	0:7e2bd16f80af	4039	}
elessair	0:7e2bd16f80af	4040	break;
elessair	0:7e2bd16f80af	4041
elessair	0:7e2bd16f80af	4042	case TIM_TS_ITR0:
elessair	0:7e2bd16f80af	4043	{
elessair	0:7e2bd16f80af	4044	/* Check the parameter */
elessair	0:7e2bd16f80af	4045	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	4046	}
elessair	0:7e2bd16f80af	4047	break;
elessair	0:7e2bd16f80af	4048
elessair	0:7e2bd16f80af	4049	case TIM_TS_ITR1:
elessair	0:7e2bd16f80af	4050	{
elessair	0:7e2bd16f80af	4051	/* Check the parameter */
elessair	0:7e2bd16f80af	4052	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	4053	}
elessair	0:7e2bd16f80af	4054	break;
elessair	0:7e2bd16f80af	4055
elessair	0:7e2bd16f80af	4056	case TIM_TS_ITR2:
elessair	0:7e2bd16f80af	4057	{
elessair	0:7e2bd16f80af	4058	/* Check the parameter */
elessair	0:7e2bd16f80af	4059	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	4060	}
elessair	0:7e2bd16f80af	4061	break;
elessair	0:7e2bd16f80af	4062
elessair	0:7e2bd16f80af	4063	case TIM_TS_ITR3:
elessair	0:7e2bd16f80af	4064	{
elessair	0:7e2bd16f80af	4065	/* Check the parameter */
elessair	0:7e2bd16f80af	4066	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	4067	}
elessair	0:7e2bd16f80af	4068	break;
elessair	0:7e2bd16f80af	4069
elessair	0:7e2bd16f80af	4070	default:
elessair	0:7e2bd16f80af	4071	break;
elessair	0:7e2bd16f80af	4072	}
elessair	0:7e2bd16f80af	4073
elessair	0:7e2bd16f80af	4074	htim->State = HAL_TIM_STATE_READY;
elessair	0:7e2bd16f80af	4075
elessair	0:7e2bd16f80af	4076	__HAL_UNLOCK(htim);
elessair	0:7e2bd16f80af	4077
elessair	0:7e2bd16f80af	4078	return HAL_OK;
elessair	0:7e2bd16f80af	4079	}
elessair	0:7e2bd16f80af	4080
elessair	0:7e2bd16f80af	4081	/**
elessair	0:7e2bd16f80af	4082	* @brief Read the captured value from Capture Compare unit
elessair	0:7e2bd16f80af	4083	* @param htim: TIM handle.
elessair	0:7e2bd16f80af	4084	* @param Channel : TIM Channels to be enabled
elessair	0:7e2bd16f80af	4085	* This parameter can be one of the following values:
elessair	0:7e2bd16f80af	4086	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
elessair	0:7e2bd16f80af	4087	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
elessair	0:7e2bd16f80af	4088	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
elessair	0:7e2bd16f80af	4089	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
elessair	0:7e2bd16f80af	4090	* @retval Captured value
elessair	0:7e2bd16f80af	4091	*/
elessair	0:7e2bd16f80af	4092	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
elessair	0:7e2bd16f80af	4093	{
elessair	0:7e2bd16f80af	4094	uint32_t tmpreg = 0;
elessair	0:7e2bd16f80af	4095
elessair	0:7e2bd16f80af	4096	__HAL_LOCK(htim);
elessair	0:7e2bd16f80af	4097
elessair	0:7e2bd16f80af	4098	switch (Channel)
elessair	0:7e2bd16f80af	4099	{
elessair	0:7e2bd16f80af	4100	case TIM_CHANNEL_1:
elessair	0:7e2bd16f80af	4101	{
elessair	0:7e2bd16f80af	4102	/* Check the parameters */
elessair	0:7e2bd16f80af	4103	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	4104
elessair	0:7e2bd16f80af	4105	/* Return the capture 1 value */
elessair	0:7e2bd16f80af	4106	tmpreg = htim->Instance->CCR1;
elessair	0:7e2bd16f80af	4107
elessair	0:7e2bd16f80af	4108	break;
elessair	0:7e2bd16f80af	4109	}
elessair	0:7e2bd16f80af	4110	case TIM_CHANNEL_2:
elessair	0:7e2bd16f80af	4111	{
elessair	0:7e2bd16f80af	4112	/* Check the parameters */
elessair	0:7e2bd16f80af	4113	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	4114
elessair	0:7e2bd16f80af	4115	/* Return the capture 2 value */
elessair	0:7e2bd16f80af	4116	tmpreg = htim->Instance->CCR2;
elessair	0:7e2bd16f80af	4117
elessair	0:7e2bd16f80af	4118	break;
elessair	0:7e2bd16f80af	4119	}
elessair	0:7e2bd16f80af	4120
elessair	0:7e2bd16f80af	4121	case TIM_CHANNEL_3:
elessair	0:7e2bd16f80af	4122	{
elessair	0:7e2bd16f80af	4123	/* Check the parameters */
elessair	0:7e2bd16f80af	4124	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	4125
elessair	0:7e2bd16f80af	4126	/* Return the capture 3 value */
elessair	0:7e2bd16f80af	4127	tmpreg = htim->Instance->CCR3;
elessair	0:7e2bd16f80af	4128
elessair	0:7e2bd16f80af	4129	break;
elessair	0:7e2bd16f80af	4130	}
elessair	0:7e2bd16f80af	4131
elessair	0:7e2bd16f80af	4132	case TIM_CHANNEL_4:
elessair	0:7e2bd16f80af	4133	{
elessair	0:7e2bd16f80af	4134	/* Check the parameters */
elessair	0:7e2bd16f80af	4135	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
elessair	0:7e2bd16f80af	4136
elessair	0:7e2bd16f80af	4137	/* Return the capture 4 value */
elessair	0:7e2bd16f80af	4138	tmpreg = htim->Instance->CCR4;
elessair	0:7e2bd16f80af	4139
elessair	0:7e2bd16f80af	4140	break;
elessair	0:7e2bd16f80af	4141	}
elessair	0:7e2bd16f80af	4142
elessair	0:7e2bd16f80af	4143	default:
elessair	0:7e2bd16f80af	4144	break;
elessair	0:7e2bd16f80af	4145	}
elessair	0:7e2bd16f80af	4146
elessair	0:7e2bd16f80af	4147	__HAL_UNLOCK(htim);
elessair	0:7e2bd16f80af	4148	return tmpreg;
elessair	0:7e2bd16f80af	4149	}
elessair	0:7e2bd16f80af	4150
elessair	0:7e2bd16f80af	4151	/**
elessair	0:7e2bd16f80af	4152	* @}
elessair	0:7e2bd16f80af	4153	*/
elessair	0:7e2bd16f80af	4154
elessair	0:7e2bd16f80af	4155	/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
elessair	0:7e2bd16f80af	4156	* @brief TIM Callbacks functions
elessair	0:7e2bd16f80af	4157	*
elessair	0:7e2bd16f80af	4158	@verbatim
elessair	0:7e2bd16f80af	4159	==============================================================================
elessair	0:7e2bd16f80af	4160	##### TIM Callbacks functions #####
elessair	0:7e2bd16f80af	4161	==============================================================================
elessair	0:7e2bd16f80af	4162	[..]
elessair	0:7e2bd16f80af	4163	This section provides TIM callback functions:
elessair	0:7e2bd16f80af	4164	(+) Timer Period elapsed callback
elessair	0:7e2bd16f80af	4165	(+) Timer Output Compare callback
elessair	0:7e2bd16f80af	4166	(+) Timer Input capture callback
elessair	0:7e2bd16f80af	4167	(+) Timer Trigger callback
elessair	0:7e2bd16f80af	4168	(+) Timer Error callback
elessair	0:7e2bd16f80af	4169
elessair	0:7e2bd16f80af	4170	@endverbatim
elessair	0:7e2bd16f80af	4171	* @{
elessair	0:7e2bd16f80af	4172	*/
elessair	0:7e2bd16f80af	4173
elessair	0:7e2bd16f80af	4174	/**
elessair	0:7e2bd16f80af	4175	* @brief Period elapsed callback in non blocking mode
elessair	0:7e2bd16f80af	4176	* @param htim : TIM handle
elessair	0:7e2bd16f80af	4177	* @retval None
elessair	0:7e2bd16f80af	4178	*/
elessair	0:7e2bd16f80af	4179	__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
elessair	0:7e2bd16f80af	4180	{
elessair	0:7e2bd16f80af	4181	/* NOTE : This function Should not be modified, when the callback is needed,
elessair	0:7e2bd16f80af	4182	the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
elessair	0:7e2bd16f80af	4183	*/
elessair	0:7e2bd16f80af	4184
elessair	0:7e2bd16f80af	4185	}
elessair	0:7e2bd16f80af	4186	/**
elessair	0:7e2bd16f80af	4187	* @brief Output Compare callback in non blocking mode
elessair	0:7e2bd16f80af	4188	* @param htim : TIM OC handle
elessair	0:7e2bd16f80af	4189	* @retval None
elessair	0:7e2bd16f80af	4190	*/
elessair	0:7e2bd16f80af	4191	__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
elessair	0:7e2bd16f80af	4192	{
elessair	0:7e2bd16f80af	4193	/* NOTE : This function Should not be modified, when the callback is needed,
elessair	0:7e2bd16f80af	4194	the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
elessair	0:7e2bd16f80af	4195	*/
elessair	0:7e2bd16f80af	4196	}
elessair	0:7e2bd16f80af	4197	/**
elessair	0:7e2bd16f80af	4198	* @brief Input Capture callback in non blocking mode
elessair	0:7e2bd16f80af	4199	* @param htim : TIM IC handle
elessair	0:7e2bd16f80af	4200	* @retval None
elessair	0:7e2bd16f80af	4201	*/
elessair	0:7e2bd16f80af	4202	__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
elessair	0:7e2bd16f80af	4203	{
elessair	0:7e2bd16f80af	4204	/* NOTE : This function Should not be modified, when the callback is needed,
elessair	0:7e2bd16f80af	4205	the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
elessair	0:7e2bd16f80af	4206	*/
elessair	0:7e2bd16f80af	4207	}
elessair	0:7e2bd16f80af	4208
elessair	0:7e2bd16f80af	4209	/**
elessair	0:7e2bd16f80af	4210	* @brief PWM Pulse finished callback in non blocking mode
elessair	0:7e2bd16f80af	4211	* @param htim : TIM handle
elessair	0:7e2bd16f80af	4212	* @retval None
elessair	0:7e2bd16f80af	4213	*/
elessair	0:7e2bd16f80af	4214	__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
elessair	0:7e2bd16f80af	4215	{
elessair	0:7e2bd16f80af	4216	/* NOTE : This function Should not be modified, when the callback is needed,
elessair	0:7e2bd16f80af	4217	the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
elessair	0:7e2bd16f80af	4218	*/
elessair	0:7e2bd16f80af	4219	}
elessair	0:7e2bd16f80af	4220
elessair	0:7e2bd16f80af	4221	/**
elessair	0:7e2bd16f80af	4222	* @brief Hall Trigger detection callback in non blocking mode
elessair	0:7e2bd16f80af	4223	* @param htim : TIM handle
elessair	0:7e2bd16f80af	4224	* @retval None
elessair	0:7e2bd16f80af	4225	*/
elessair	0:7e2bd16f80af	4226	__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
elessair	0:7e2bd16f80af	4227	{
elessair	0:7e2bd16f80af	4228	/* NOTE : This function Should not be modified, when the callback is needed,
elessair	0:7e2bd16f80af	4229	the HAL_TIM_TriggerCallback could be implemented in the user file
elessair	0:7e2bd16f80af	4230	*/
elessair	0:7e2bd16f80af	4231	}
elessair	0:7e2bd16f80af	4232
elessair	0:7e2bd16f80af	4233	/**
elessair	0:7e2bd16f80af	4234	* @brief Timer error callback in non blocking mode
elessair	0:7e2bd16f80af	4235	* @param htim : TIM handle
elessair	0:7e2bd16f80af	4236	* @retval None
elessair	0:7e2bd16f80af	4237	*/
elessair	0:7e2bd16f80af	4238	__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
elessair	0:7e2bd16f80af	4239	{
elessair	0:7e2bd16f80af	4240	/* NOTE : This function Should not be modified, when the callback is needed,
elessair	0:7e2bd16f80af	4241	the HAL_TIM_ErrorCallback could be implemented in the user file
elessair	0:7e2bd16f80af	4242	*/
elessair	0:7e2bd16f80af	4243	}
elessair	0:7e2bd16f80af	4244
elessair	0:7e2bd16f80af	4245	/**
elessair	0:7e2bd16f80af	4246	* @}
elessair	0:7e2bd16f80af	4247	*/
elessair	0:7e2bd16f80af	4248
elessair	0:7e2bd16f80af	4249	/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
elessair	0:7e2bd16f80af	4250	* @brief Peripheral State functions
elessair	0:7e2bd16f80af	4251	*
elessair	0:7e2bd16f80af	4252	@verbatim
elessair	0:7e2bd16f80af	4253	==============================================================================
elessair	0:7e2bd16f80af	4254	##### Peripheral State functions #####
elessair	0:7e2bd16f80af	4255	==============================================================================
elessair	0:7e2bd16f80af	4256	[..]
elessair	0:7e2bd16f80af	4257	This subsection permit to get in run-time the status of the peripheral
elessair	0:7e2bd16f80af	4258	and the data flow.
elessair	0:7e2bd16f80af	4259
elessair	0:7e2bd16f80af	4260	@endverbatim
elessair	0:7e2bd16f80af	4261	* @{
elessair	0:7e2bd16f80af	4262	*/
elessair	0:7e2bd16f80af	4263
elessair	0:7e2bd16f80af	4264	/**
elessair	0:7e2bd16f80af	4265	* @brief Return the TIM Base state
elessair	0:7e2bd16f80af	4266	* @param htim: TIM Base handle
elessair	0:7e2bd16f80af	4267	* @retval HAL state
elessair	0:7e2bd16f80af	4268	*/
elessair	0:7e2bd16f80af	4269	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
elessair	0:7e2bd16f80af	4270	{
elessair	0:7e2bd16f80af	4271	return htim->State;
elessair	0:7e2bd16f80af	4272	}
elessair	0:7e2bd16f80af	4273
elessair	0:7e2bd16f80af	4274	/**
elessair	0:7e2bd16f80af	4275	* @brief Return the TIM OC state
elessair	0:7e2bd16f80af	4276	* @param htim: TIM Ouput Compare handle
elessair	0:7e2bd16f80af	4277	* @retval HAL state
elessair	0:7e2bd16f80af	4278	*/
elessair	0:7e2bd16f80af	4279	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
elessair	0:7e2bd16f80af	4280	{
elessair	0:7e2bd16f80af	4281	return htim->State;
elessair	0:7e2bd16f80af	4282	}
elessair	0:7e2bd16f80af	4283
elessair	0:7e2bd16f80af	4284	/**
elessair	0:7e2bd16f80af	4285	* @brief Return the TIM PWM state
elessair	0:7e2bd16f80af	4286	* @param htim: TIM handle
elessair	0:7e2bd16f80af	4287	* @retval HAL state
elessair	0:7e2bd16f80af	4288	*/
elessair	0:7e2bd16f80af	4289	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
elessair	0:7e2bd16f80af	4290	{
elessair	0:7e2bd16f80af	4291	return htim->State;
elessair	0:7e2bd16f80af	4292	}
elessair	0:7e2bd16f80af	4293
elessair	0:7e2bd16f80af	4294	/**
elessair	0:7e2bd16f80af	4295	* @brief Return the TIM Input Capture state
elessair	0:7e2bd16f80af	4296	* @param htim: TIM IC handle
elessair	0:7e2bd16f80af	4297	* @retval HAL state
elessair	0:7e2bd16f80af	4298	*/
elessair	0:7e2bd16f80af	4299	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
elessair	0:7e2bd16f80af	4300	{
elessair	0:7e2bd16f80af	4301	return htim->State;
elessair	0:7e2bd16f80af	4302	}
elessair	0:7e2bd16f80af	4303
elessair	0:7e2bd16f80af	4304	/**
elessair	0:7e2bd16f80af	4305	* @brief Return the TIM One Pulse Mode state
elessair	0:7e2bd16f80af	4306	* @param htim: TIM OPM handle
elessair	0:7e2bd16f80af	4307	* @retval HAL state
elessair	0:7e2bd16f80af	4308	*/
elessair	0:7e2bd16f80af	4309	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
elessair	0:7e2bd16f80af	4310	{
elessair	0:7e2bd16f80af	4311	return htim->State;
elessair	0:7e2bd16f80af	4312	}
elessair	0:7e2bd16f80af	4313
elessair	0:7e2bd16f80af	4314	/**
elessair	0:7e2bd16f80af	4315	* @brief Return the TIM Encoder Mode state
elessair	0:7e2bd16f80af	4316	* @param htim: TIM Encoder handle
elessair	0:7e2bd16f80af	4317	* @retval HAL state
elessair	0:7e2bd16f80af	4318	*/
elessair	0:7e2bd16f80af	4319	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
elessair	0:7e2bd16f80af	4320	{
elessair	0:7e2bd16f80af	4321	return htim->State;
elessair	0:7e2bd16f80af	4322	}
elessair	0:7e2bd16f80af	4323
elessair	0:7e2bd16f80af	4324	/**
elessair	0:7e2bd16f80af	4325	* @}
elessair	0:7e2bd16f80af	4326	*/
elessair	0:7e2bd16f80af	4327
elessair	0:7e2bd16f80af	4328	/**
elessair	0:7e2bd16f80af	4329	* @}
elessair	0:7e2bd16f80af	4330	*/
elessair	0:7e2bd16f80af	4331
elessair	0:7e2bd16f80af	4332
elessair	0:7e2bd16f80af	4333	/** @addtogroup TIM_Private_Functions
elessair	0:7e2bd16f80af	4334	* @{
elessair	0:7e2bd16f80af	4335	*/
elessair	0:7e2bd16f80af	4336
elessair	0:7e2bd16f80af	4337
elessair	0:7e2bd16f80af	4338	/**
elessair	0:7e2bd16f80af	4339	* @brief TIM DMA error callback
elessair	0:7e2bd16f80af	4340	* @param hdma : pointer to DMA handle.
elessair	0:7e2bd16f80af	4341	* @retval None
elessair	0:7e2bd16f80af	4342	*/
elessair	0:7e2bd16f80af	4343	static void TIM_DMAError(DMA_HandleTypeDef *hdma)
elessair	0:7e2bd16f80af	4344	{
elessair	0:7e2bd16f80af	4345	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
elessair	0:7e2bd16f80af	4346
elessair	0:7e2bd16f80af	4347	htim->State= HAL_TIM_STATE_READY;
elessair	0:7e2bd16f80af	4348
elessair	0:7e2bd16f80af	4349	HAL_TIM_ErrorCallback(htim);
elessair	0:7e2bd16f80af	4350	}
elessair	0:7e2bd16f80af	4351
elessair	0:7e2bd16f80af	4352	/**
elessair	0:7e2bd16f80af	4353	* @brief TIM DMA Delay Pulse complete callback.
elessair	0:7e2bd16f80af	4354	* @param hdma : pointer to DMA handle.
elessair	0:7e2bd16f80af	4355	* @retval None
elessair	0:7e2bd16f80af	4356	*/
elessair	0:7e2bd16f80af	4357	static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
elessair	0:7e2bd16f80af	4358	{
elessair	0:7e2bd16f80af	4359	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
elessair	0:7e2bd16f80af	4360
elessair	0:7e2bd16f80af	4361	htim->State= HAL_TIM_STATE_READY;
elessair	0:7e2bd16f80af	4362
elessair	0:7e2bd16f80af	4363	if (hdma == htim->hdma[TIM_DMA_ID_CC1])
elessair	0:7e2bd16f80af	4364	{
elessair	0:7e2bd16f80af	4365	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
elessair	0:7e2bd16f80af	4366	}
elessair	0:7e2bd16f80af	4367	else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
elessair	0:7e2bd16f80af	4368	{
elessair	0:7e2bd16f80af	4369	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
elessair	0:7e2bd16f80af	4370	}
elessair	0:7e2bd16f80af	4371	else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
elessair	0:7e2bd16f80af	4372	{
elessair	0:7e2bd16f80af	4373	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
elessair	0:7e2bd16f80af	4374	}
elessair	0:7e2bd16f80af	4375	else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
elessair	0:7e2bd16f80af	4376	{
elessair	0:7e2bd16f80af	4377	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
elessair	0:7e2bd16f80af	4378	}
elessair	0:7e2bd16f80af	4379
elessair	0:7e2bd16f80af	4380	HAL_TIM_PWM_PulseFinishedCallback(htim);
elessair	0:7e2bd16f80af	4381
elessair	0:7e2bd16f80af	4382	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
elessair	0:7e2bd16f80af	4383	}
elessair	0:7e2bd16f80af	4384
elessair	0:7e2bd16f80af	4385	/**
elessair	0:7e2bd16f80af	4386	* @brief TIM DMA Capture complete callback.
elessair	0:7e2bd16f80af	4387	* @param hdma : pointer to DMA handle.
elessair	0:7e2bd16f80af	4388	* @retval None
elessair	0:7e2bd16f80af	4389	*/
elessair	0:7e2bd16f80af	4390	static void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
elessair	0:7e2bd16f80af	4391	{
elessair	0:7e2bd16f80af	4392	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
elessair	0:7e2bd16f80af	4393
elessair	0:7e2bd16f80af	4394	htim->State= HAL_TIM_STATE_READY;
elessair	0:7e2bd16f80af	4395
elessair	0:7e2bd16f80af	4396	if (hdma == htim->hdma[TIM_DMA_ID_CC1])
elessair	0:7e2bd16f80af	4397	{
elessair	0:7e2bd16f80af	4398	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
elessair	0:7e2bd16f80af	4399	}
elessair	0:7e2bd16f80af	4400	else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
elessair	0:7e2bd16f80af	4401	{
elessair	0:7e2bd16f80af	4402	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
elessair	0:7e2bd16f80af	4403	}
elessair	0:7e2bd16f80af	4404	else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
elessair	0:7e2bd16f80af	4405	{
elessair	0:7e2bd16f80af	4406	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
elessair	0:7e2bd16f80af	4407	}
elessair	0:7e2bd16f80af	4408	else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
elessair	0:7e2bd16f80af	4409	{
elessair	0:7e2bd16f80af	4410	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
elessair	0:7e2bd16f80af	4411	}
elessair	0:7e2bd16f80af	4412
elessair	0:7e2bd16f80af	4413	HAL_TIM_IC_CaptureCallback(htim);
elessair	0:7e2bd16f80af	4414
elessair	0:7e2bd16f80af	4415	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
elessair	0:7e2bd16f80af	4416	}
elessair	0:7e2bd16f80af	4417
elessair	0:7e2bd16f80af	4418	/**
elessair	0:7e2bd16f80af	4419	* @brief TIM DMA Period Elapse complete callback.
elessair	0:7e2bd16f80af	4420	* @param hdma : pointer to DMA handle.
elessair	0:7e2bd16f80af	4421	* @retval None
elessair	0:7e2bd16f80af	4422	*/
elessair	0:7e2bd16f80af	4423	static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
elessair	0:7e2bd16f80af	4424	{
elessair	0:7e2bd16f80af	4425	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
elessair	0:7e2bd16f80af	4426
elessair	0:7e2bd16f80af	4427	htim->State= HAL_TIM_STATE_READY;
elessair	0:7e2bd16f80af	4428
elessair	0:7e2bd16f80af	4429	HAL_TIM_PeriodElapsedCallback(htim);
elessair	0:7e2bd16f80af	4430	}
elessair	0:7e2bd16f80af	4431
elessair	0:7e2bd16f80af	4432	/**
elessair	0:7e2bd16f80af	4433	* @brief TIM DMA Trigger callback.
elessair	0:7e2bd16f80af	4434	* @param hdma : pointer to DMA handle.
elessair	0:7e2bd16f80af	4435	* @retval None
elessair	0:7e2bd16f80af	4436	*/
elessair	0:7e2bd16f80af	4437	static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
elessair	0:7e2bd16f80af	4438	{
elessair	0:7e2bd16f80af	4439	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
elessair	0:7e2bd16f80af	4440
elessair	0:7e2bd16f80af	4441	htim->State= HAL_TIM_STATE_READY;
elessair	0:7e2bd16f80af	4442
elessair	0:7e2bd16f80af	4443	HAL_TIM_TriggerCallback(htim);
elessair	0:7e2bd16f80af	4444	}
elessair	0:7e2bd16f80af	4445
elessair	0:7e2bd16f80af	4446	/**
elessair	0:7e2bd16f80af	4447	* @brief Time Base configuration
elessair	0:7e2bd16f80af	4448	* @param TIMx: TIM periheral
elessair	0:7e2bd16f80af	4449	* @param Structure: TIM Base configuration structure
elessair	0:7e2bd16f80af	4450	* @retval None
elessair	0:7e2bd16f80af	4451	*/
elessair	0:7e2bd16f80af	4452	static void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure)
elessair	0:7e2bd16f80af	4453	{
elessair	0:7e2bd16f80af	4454	uint32_t tmpcr1 = 0;
elessair	0:7e2bd16f80af	4455	tmpcr1 = TIMx->CR1;
elessair	0:7e2bd16f80af	4456
elessair	0:7e2bd16f80af	4457	/* Set TIM Time Base Unit parameters ---------------------------------------*/
elessair	0:7e2bd16f80af	4458	if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
elessair	0:7e2bd16f80af	4459	{
elessair	0:7e2bd16f80af	4460	/* Select the Counter Mode */
elessair	0:7e2bd16f80af	4461	tmpcr1 &= ~(TIM_CR1_DIR \| TIM_CR1_CMS);
elessair	0:7e2bd16f80af	4462	tmpcr1 \|= Structure->CounterMode;
elessair	0:7e2bd16f80af	4463	}
elessair	0:7e2bd16f80af	4464
elessair	0:7e2bd16f80af	4465	if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
elessair	0:7e2bd16f80af	4466	{
elessair	0:7e2bd16f80af	4467	/* Set the clock division */
elessair	0:7e2bd16f80af	4468	tmpcr1 &= ~TIM_CR1_CKD;
elessair	0:7e2bd16f80af	4469	tmpcr1 \|= (uint32_t)Structure->ClockDivision;
elessair	0:7e2bd16f80af	4470	}
elessair	0:7e2bd16f80af	4471
elessair	0:7e2bd16f80af	4472	TIMx->CR1 = tmpcr1;
elessair	0:7e2bd16f80af	4473
elessair	0:7e2bd16f80af	4474	/* Set the Autoreload value */
elessair	0:7e2bd16f80af	4475	TIMx->ARR = (uint32_t)Structure->Period ;
elessair	0:7e2bd16f80af	4476
elessair	0:7e2bd16f80af	4477	/* Set the Prescaler value */
elessair	0:7e2bd16f80af	4478	TIMx->PSC = (uint32_t)Structure->Prescaler;
elessair	0:7e2bd16f80af	4479
elessair	0:7e2bd16f80af	4480	/* Generate an update event to reload the Prescaler
elessair	0:7e2bd16f80af	4481	and the repetition counter(only for TIM1 and TIM8) value immediatly */
elessair	0:7e2bd16f80af	4482	TIMx->EGR = TIM_EGR_UG;
elessair	0:7e2bd16f80af	4483	}
elessair	0:7e2bd16f80af	4484
elessair	0:7e2bd16f80af	4485	/**
elessair	0:7e2bd16f80af	4486	* @brief Time Ouput Compare 1 configuration
elessair	0:7e2bd16f80af	4487	* @param TIMx to select the TIM peripheral
elessair	0:7e2bd16f80af	4488	* @param OC_Config: The ouput configuration structure
elessair	0:7e2bd16f80af	4489	* @retval None
elessair	0:7e2bd16f80af	4490	*/
elessair	0:7e2bd16f80af	4491	static void TIM_OC1_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
elessair	0:7e2bd16f80af	4492	{
elessair	0:7e2bd16f80af	4493	uint32_t tmpccmrx = 0;
elessair	0:7e2bd16f80af	4494	uint32_t tmpccer = 0;
elessair	0:7e2bd16f80af	4495	uint32_t tmpcr2 = 0;
elessair	0:7e2bd16f80af	4496
elessair	0:7e2bd16f80af	4497	/* Disable the Channel 1: Reset the CC1E Bit */
elessair	0:7e2bd16f80af	4498	TIMx->CCER &= ~TIM_CCER_CC1E;
elessair	0:7e2bd16f80af	4499
elessair	0:7e2bd16f80af	4500	/* Get the TIMx CCER register value */
elessair	0:7e2bd16f80af	4501	tmpccer = TIMx->CCER;
elessair	0:7e2bd16f80af	4502	/* Get the TIMx CR2 register value */
elessair	0:7e2bd16f80af	4503	tmpcr2 = TIMx->CR2;
elessair	0:7e2bd16f80af	4504
elessair	0:7e2bd16f80af	4505	/* Get the TIMx CCMR1 register value */
elessair	0:7e2bd16f80af	4506	tmpccmrx = TIMx->CCMR1;
elessair	0:7e2bd16f80af	4507
elessair	0:7e2bd16f80af	4508	/* Reset the Output Compare Mode Bits */
elessair	0:7e2bd16f80af	4509	tmpccmrx &= ~TIM_CCMR1_OC1M;
elessair	0:7e2bd16f80af	4510	tmpccmrx &= ~TIM_CCMR1_CC1S;
elessair	0:7e2bd16f80af	4511	/* Select the Output Compare Mode */
elessair	0:7e2bd16f80af	4512	tmpccmrx \|= OC_Config->OCMode;
elessair	0:7e2bd16f80af	4513
elessair	0:7e2bd16f80af	4514	/* Reset the Output Polarity level */
elessair	0:7e2bd16f80af	4515	tmpccer &= ~TIM_CCER_CC1P;
elessair	0:7e2bd16f80af	4516	/* Set the Output Compare Polarity */
elessair	0:7e2bd16f80af	4517	tmpccer \|= OC_Config->OCPolarity;
elessair	0:7e2bd16f80af	4518
elessair	0:7e2bd16f80af	4519	/* Write to TIMx CR2 */
elessair	0:7e2bd16f80af	4520	TIMx->CR2 = tmpcr2;
elessair	0:7e2bd16f80af	4521
elessair	0:7e2bd16f80af	4522	/* Write to TIMx CCMR1 */
elessair	0:7e2bd16f80af	4523	TIMx->CCMR1 = tmpccmrx;
elessair	0:7e2bd16f80af	4524
elessair	0:7e2bd16f80af	4525	/* Set the Capture Compare Register value */
elessair	0:7e2bd16f80af	4526	TIMx->CCR1 = OC_Config->Pulse;
elessair	0:7e2bd16f80af	4527
elessair	0:7e2bd16f80af	4528	/* Write to TIMx CCER */
elessair	0:7e2bd16f80af	4529	TIMx->CCER = tmpccer;
elessair	0:7e2bd16f80af	4530	}
elessair	0:7e2bd16f80af	4531
elessair	0:7e2bd16f80af	4532	/**
elessair	0:7e2bd16f80af	4533	* @brief Time Ouput Compare 2 configuration
elessair	0:7e2bd16f80af	4534	* @param TIMx to select the TIM peripheral
elessair	0:7e2bd16f80af	4535	* @param OC_Config: The ouput configuration structure
elessair	0:7e2bd16f80af	4536	* @retval None
elessair	0:7e2bd16f80af	4537	*/
elessair	0:7e2bd16f80af	4538	static void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
elessair	0:7e2bd16f80af	4539	{
elessair	0:7e2bd16f80af	4540	uint32_t tmpccmrx = 0;
elessair	0:7e2bd16f80af	4541	uint32_t tmpccer = 0;
elessair	0:7e2bd16f80af	4542	uint32_t tmpcr2 = 0;
elessair	0:7e2bd16f80af	4543
elessair	0:7e2bd16f80af	4544	/* Disable the Channel 2: Reset the CC2E Bit */
elessair	0:7e2bd16f80af	4545	TIMx->CCER &= ~TIM_CCER_CC2E;
elessair	0:7e2bd16f80af	4546
elessair	0:7e2bd16f80af	4547	/* Get the TIMx CCER register value */
elessair	0:7e2bd16f80af	4548	tmpccer = TIMx->CCER;
elessair	0:7e2bd16f80af	4549	/* Get the TIMx CR2 register value */
elessair	0:7e2bd16f80af	4550	tmpcr2 = TIMx->CR2;
elessair	0:7e2bd16f80af	4551
elessair	0:7e2bd16f80af	4552	/* Get the TIMx CCMR1 register value */
elessair	0:7e2bd16f80af	4553	tmpccmrx = TIMx->CCMR1;
elessair	0:7e2bd16f80af	4554
elessair	0:7e2bd16f80af	4555	/* Reset the Output Compare mode and Capture/Compare selection Bits */
elessair	0:7e2bd16f80af	4556	tmpccmrx &= ~TIM_CCMR1_OC2M;
elessair	0:7e2bd16f80af	4557	tmpccmrx &= ~TIM_CCMR1_CC2S;
elessair	0:7e2bd16f80af	4558
elessair	0:7e2bd16f80af	4559	/* Select the Output Compare Mode */
elessair	0:7e2bd16f80af	4560	tmpccmrx \|= (OC_Config->OCMode << 8);
elessair	0:7e2bd16f80af	4561
elessair	0:7e2bd16f80af	4562	/* Reset the Output Polarity level */
elessair	0:7e2bd16f80af	4563	tmpccer &= ~TIM_CCER_CC2P;
elessair	0:7e2bd16f80af	4564	/* Set the Output Compare Polarity */
elessair	0:7e2bd16f80af	4565	tmpccer \|= (OC_Config->OCPolarity << 4);
elessair	0:7e2bd16f80af	4566
elessair	0:7e2bd16f80af	4567	/* Write to TIMx CR2 */
elessair	0:7e2bd16f80af	4568	TIMx->CR2 = tmpcr2;
elessair	0:7e2bd16f80af	4569
elessair	0:7e2bd16f80af	4570	/* Write to TIMx CCMR1 */
elessair	0:7e2bd16f80af	4571	TIMx->CCMR1 = tmpccmrx;
elessair	0:7e2bd16f80af	4572
elessair	0:7e2bd16f80af	4573	/* Set the Capture Compare Register value */
elessair	0:7e2bd16f80af	4574	TIMx->CCR2 = OC_Config->Pulse;
elessair	0:7e2bd16f80af	4575
elessair	0:7e2bd16f80af	4576	/* Write to TIMx CCER */
elessair	0:7e2bd16f80af	4577	TIMx->CCER = tmpccer;
elessair	0:7e2bd16f80af	4578	}
elessair	0:7e2bd16f80af	4579
elessair	0:7e2bd16f80af	4580	/**
elessair	0:7e2bd16f80af	4581	* @brief Time Ouput Compare 3 configuration
elessair	0:7e2bd16f80af	4582	* @param TIMx to select the TIM peripheral
elessair	0:7e2bd16f80af	4583	* @param OC_Config: The ouput configuration structure
elessair	0:7e2bd16f80af	4584	* @retval None
elessair	0:7e2bd16f80af	4585	*/
elessair	0:7e2bd16f80af	4586	static void TIM_OC3_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
elessair	0:7e2bd16f80af	4587	{
elessair	0:7e2bd16f80af	4588	uint32_t tmpccmrx = 0;
elessair	0:7e2bd16f80af	4589	uint32_t tmpccer = 0;
elessair	0:7e2bd16f80af	4590	uint32_t tmpcr2 = 0;
elessair	0:7e2bd16f80af	4591
elessair	0:7e2bd16f80af	4592	/* Disable the Channel 3: Reset the CC2E Bit */
elessair	0:7e2bd16f80af	4593	TIMx->CCER &= ~TIM_CCER_CC3E;
elessair	0:7e2bd16f80af	4594
elessair	0:7e2bd16f80af	4595	/* Get the TIMx CCER register value */
elessair	0:7e2bd16f80af	4596	tmpccer = TIMx->CCER;
elessair	0:7e2bd16f80af	4597	/* Get the TIMx CR2 register value */
elessair	0:7e2bd16f80af	4598	tmpcr2 = TIMx->CR2;
elessair	0:7e2bd16f80af	4599
elessair	0:7e2bd16f80af	4600	/* Get the TIMx CCMR2 register value */
elessair	0:7e2bd16f80af	4601	tmpccmrx = TIMx->CCMR2;
elessair	0:7e2bd16f80af	4602
elessair	0:7e2bd16f80af	4603	/* Reset the Output Compare mode and Capture/Compare selection Bits */
elessair	0:7e2bd16f80af	4604	tmpccmrx &= ~TIM_CCMR2_OC3M;
elessair	0:7e2bd16f80af	4605	tmpccmrx &= ~TIM_CCMR2_CC3S;
elessair	0:7e2bd16f80af	4606	/* Select the Output Compare Mode */
elessair	0:7e2bd16f80af	4607	tmpccmrx \|= OC_Config->OCMode;
elessair	0:7e2bd16f80af	4608
elessair	0:7e2bd16f80af	4609	/* Reset the Output Polarity level */
elessair	0:7e2bd16f80af	4610	tmpccer &= ~TIM_CCER_CC3P;
elessair	0:7e2bd16f80af	4611	/* Set the Output Compare Polarity */
elessair	0:7e2bd16f80af	4612	tmpccer \|= (OC_Config->OCPolarity << 8);
elessair	0:7e2bd16f80af	4613
elessair	0:7e2bd16f80af	4614	/* Write to TIMx CR2 */
elessair	0:7e2bd16f80af	4615	TIMx->CR2 = tmpcr2;
elessair	0:7e2bd16f80af	4616
elessair	0:7e2bd16f80af	4617	/* Write to TIMx CCMR2 */
elessair	0:7e2bd16f80af	4618	TIMx->CCMR2 = tmpccmrx;
elessair	0:7e2bd16f80af	4619
elessair	0:7e2bd16f80af	4620	/* Set the Capture Compare Register value */
elessair	0:7e2bd16f80af	4621	TIMx->CCR3 = OC_Config->Pulse;
elessair	0:7e2bd16f80af	4622
elessair	0:7e2bd16f80af	4623	/* Write to TIMx CCER */
elessair	0:7e2bd16f80af	4624	TIMx->CCER = tmpccer;
elessair	0:7e2bd16f80af	4625	}
elessair	0:7e2bd16f80af	4626
elessair	0:7e2bd16f80af	4627	/**
elessair	0:7e2bd16f80af	4628	* @brief Time Ouput Compare 4 configuration
elessair	0:7e2bd16f80af	4629	* @param TIMx to select the TIM peripheral
elessair	0:7e2bd16f80af	4630	* @param OC_Config: The ouput configuration structure
elessair	0:7e2bd16f80af	4631	* @retval None
elessair	0:7e2bd16f80af	4632	*/
elessair	0:7e2bd16f80af	4633	static void TIM_OC4_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
elessair	0:7e2bd16f80af	4634	{
elessair	0:7e2bd16f80af	4635	uint32_t tmpccmrx = 0;
elessair	0:7e2bd16f80af	4636	uint32_t tmpccer = 0;
elessair	0:7e2bd16f80af	4637	uint32_t tmpcr2 = 0;
elessair	0:7e2bd16f80af	4638
elessair	0:7e2bd16f80af	4639	/* Disable the Channel 4: Reset the CC4E Bit */
elessair	0:7e2bd16f80af	4640	TIMx->CCER &= ~TIM_CCER_CC4E;
elessair	0:7e2bd16f80af	4641
elessair	0:7e2bd16f80af	4642	/* Get the TIMx CCER register value */
elessair	0:7e2bd16f80af	4643	tmpccer = TIMx->CCER;
elessair	0:7e2bd16f80af	4644	/* Get the TIMx CR2 register value */
elessair	0:7e2bd16f80af	4645	tmpcr2 = TIMx->CR2;
elessair	0:7e2bd16f80af	4646
elessair	0:7e2bd16f80af	4647	/* Get the TIMx CCMR2 register value */
elessair	0:7e2bd16f80af	4648	tmpccmrx = TIMx->CCMR2;
elessair	0:7e2bd16f80af	4649
elessair	0:7e2bd16f80af	4650	/* Reset the Output Compare mode and Capture/Compare selection Bits */
elessair	0:7e2bd16f80af	4651	tmpccmrx &= ~TIM_CCMR2_OC4M;
elessair	0:7e2bd16f80af	4652	tmpccmrx &= ~TIM_CCMR2_CC4S;
elessair	0:7e2bd16f80af	4653
elessair	0:7e2bd16f80af	4654	/* Select the Output Compare Mode */
elessair	0:7e2bd16f80af	4655	tmpccmrx \|= (OC_Config->OCMode << 8);
elessair	0:7e2bd16f80af	4656
elessair	0:7e2bd16f80af	4657	/* Reset the Output Polarity level */
elessair	0:7e2bd16f80af	4658	tmpccer &= ~TIM_CCER_CC4P;
elessair	0:7e2bd16f80af	4659	/* Set the Output Compare Polarity */
elessair	0:7e2bd16f80af	4660	tmpccer \|= (OC_Config->OCPolarity << 12);
elessair	0:7e2bd16f80af	4661
elessair	0:7e2bd16f80af	4662	/* Write to TIMx CR2 */
elessair	0:7e2bd16f80af	4663	TIMx->CR2 = tmpcr2;
elessair	0:7e2bd16f80af	4664
elessair	0:7e2bd16f80af	4665	/* Write to TIMx CCMR2 */
elessair	0:7e2bd16f80af	4666	TIMx->CCMR2 = tmpccmrx;
elessair	0:7e2bd16f80af	4667
elessair	0:7e2bd16f80af	4668	/* Set the Capture Compare Register value */
elessair	0:7e2bd16f80af	4669	TIMx->CCR4 = OC_Config->Pulse;
elessair	0:7e2bd16f80af	4670
elessair	0:7e2bd16f80af	4671	/* Write to TIMx CCER */
elessair	0:7e2bd16f80af	4672	TIMx->CCER = tmpccer;
elessair	0:7e2bd16f80af	4673	}
elessair	0:7e2bd16f80af	4674
elessair	0:7e2bd16f80af	4675	/**
elessair	0:7e2bd16f80af	4676	* @brief Configure the TI1 as Input.
elessair	0:7e2bd16f80af	4677	* @param TIMx to select the TIM peripheral.
elessair	0:7e2bd16f80af	4678	* @param TIM_ICPolarity : The Input Polarity.
elessair	0:7e2bd16f80af	4679	* This parameter can be one of the following values:
elessair	0:7e2bd16f80af	4680	* @arg TIM_ICPOLARITY_RISING
elessair	0:7e2bd16f80af	4681	* @arg TIM_ICPOLARITY_FALLING
elessair	0:7e2bd16f80af	4682	* @arg TIM_ICPOLARITY_BOTHEDGE
elessair	0:7e2bd16f80af	4683	* @param TIM_ICSelection: specifies the input to be used.
elessair	0:7e2bd16f80af	4684	* This parameter can be one of the following values:
elessair	0:7e2bd16f80af	4685	* @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
elessair	0:7e2bd16f80af	4686	* @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
elessair	0:7e2bd16f80af	4687	* @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
elessair	0:7e2bd16f80af	4688	* @param TIM_ICFilter: Specifies the Input Capture Filter.
elessair	0:7e2bd16f80af	4689	* This parameter must be a value between 0x00 and 0x0F.
elessair	0:7e2bd16f80af	4690	* @retval None
elessair	0:7e2bd16f80af	4691	*/
elessair	0:7e2bd16f80af	4692	static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
elessair	0:7e2bd16f80af	4693	uint32_t TIM_ICFilter)
elessair	0:7e2bd16f80af	4694	{
elessair	0:7e2bd16f80af	4695	uint32_t tmpccmr1 = 0;
elessair	0:7e2bd16f80af	4696	uint32_t tmpccer = 0;
elessair	0:7e2bd16f80af	4697
elessair	0:7e2bd16f80af	4698	/* Disable the Channel 1: Reset the CC1E Bit */
elessair	0:7e2bd16f80af	4699	TIMx->CCER &= ~TIM_CCER_CC1E;
elessair	0:7e2bd16f80af	4700	tmpccmr1 = TIMx->CCMR1;
elessair	0:7e2bd16f80af	4701	tmpccer = TIMx->CCER;
elessair	0:7e2bd16f80af	4702
elessair	0:7e2bd16f80af	4703	/* Select the Input */
elessair	0:7e2bd16f80af	4704	if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
elessair	0:7e2bd16f80af	4705	{
elessair	0:7e2bd16f80af	4706	tmpccmr1 &= ~TIM_CCMR1_CC1S;
elessair	0:7e2bd16f80af	4707	tmpccmr1 \|= TIM_ICSelection;
elessair	0:7e2bd16f80af	4708	}
elessair	0:7e2bd16f80af	4709	else
elessair	0:7e2bd16f80af	4710	{
elessair	0:7e2bd16f80af	4711	tmpccmr1 \|= TIM_CCMR1_CC1S_0;
elessair	0:7e2bd16f80af	4712	}
elessair	0:7e2bd16f80af	4713
elessair	0:7e2bd16f80af	4714	/* Set the filter */
elessair	0:7e2bd16f80af	4715	tmpccmr1 &= ~TIM_CCMR1_IC1F;
elessair	0:7e2bd16f80af	4716	tmpccmr1 \|= (TIM_ICFilter << 4);
elessair	0:7e2bd16f80af	4717
elessair	0:7e2bd16f80af	4718	/* Select the Polarity and set the CC1E Bit */
elessair	0:7e2bd16f80af	4719	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC1NP);
elessair	0:7e2bd16f80af	4720	tmpccer \|= TIM_ICPolarity;
elessair	0:7e2bd16f80af	4721
elessair	0:7e2bd16f80af	4722	/* Write to TIMx CCMR1 and CCER registers */
elessair	0:7e2bd16f80af	4723	TIMx->CCMR1 = tmpccmr1;
elessair	0:7e2bd16f80af	4724	TIMx->CCER = tmpccer;
elessair	0:7e2bd16f80af	4725	}
elessair	0:7e2bd16f80af	4726
elessair	0:7e2bd16f80af	4727	/**
elessair	0:7e2bd16f80af	4728	* @brief Configure the Polarity and Filter for TI1.
elessair	0:7e2bd16f80af	4729	* @param TIMx to select the TIM peripheral.
elessair	0:7e2bd16f80af	4730	* @param TIM_ICPolarity : The Input Polarity.
elessair	0:7e2bd16f80af	4731	* This parameter can be one of the following values:
elessair	0:7e2bd16f80af	4732	* @arg TIM_ICPOLARITY_RISING
elessair	0:7e2bd16f80af	4733	* @arg TIM_ICPOLARITY_FALLING
elessair	0:7e2bd16f80af	4734	* @arg TIM_ICPOLARITY_BOTHEDGE
elessair	0:7e2bd16f80af	4735	* @param TIM_ICFilter: Specifies the Input Capture Filter.
elessair	0:7e2bd16f80af	4736	* This parameter must be a value between 0x00 and 0x0F.
elessair	0:7e2bd16f80af	4737	* @retval None
elessair	0:7e2bd16f80af	4738	*/
elessair	0:7e2bd16f80af	4739	static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
elessair	0:7e2bd16f80af	4740	{
elessair	0:7e2bd16f80af	4741	uint32_t tmpccmr1 = 0;
elessair	0:7e2bd16f80af	4742	uint32_t tmpccer = 0;
elessair	0:7e2bd16f80af	4743
elessair	0:7e2bd16f80af	4744	/* Disable the Channel 1: Reset the CC1E Bit */
elessair	0:7e2bd16f80af	4745	tmpccer = TIMx->CCER;
elessair	0:7e2bd16f80af	4746	TIMx->CCER &= ~TIM_CCER_CC1E;
elessair	0:7e2bd16f80af	4747	tmpccmr1 = TIMx->CCMR1;
elessair	0:7e2bd16f80af	4748
elessair	0:7e2bd16f80af	4749	/* Set the filter */
elessair	0:7e2bd16f80af	4750	tmpccmr1 &= ~TIM_CCMR1_IC1F;
elessair	0:7e2bd16f80af	4751	tmpccmr1 \|= (TIM_ICFilter << 4);
elessair	0:7e2bd16f80af	4752
elessair	0:7e2bd16f80af	4753	/* Select the Polarity and set the CC1E Bit */
elessair	0:7e2bd16f80af	4754	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC1NP);
elessair	0:7e2bd16f80af	4755	tmpccer \|= TIM_ICPolarity;
elessair	0:7e2bd16f80af	4756
elessair	0:7e2bd16f80af	4757	/* Write to TIMx CCMR1 and CCER registers */
elessair	0:7e2bd16f80af	4758	TIMx->CCMR1 = tmpccmr1;
elessair	0:7e2bd16f80af	4759	TIMx->CCER = tmpccer;
elessair	0:7e2bd16f80af	4760	}
elessair	0:7e2bd16f80af	4761
elessair	0:7e2bd16f80af	4762	/**
elessair	0:7e2bd16f80af	4763	* @brief Configure the TI2 as Input.
elessair	0:7e2bd16f80af	4764	* @param TIMx to select the TIM peripheral
elessair	0:7e2bd16f80af	4765	* @param TIM_ICPolarity : The Input Polarity.
elessair	0:7e2bd16f80af	4766	* This parameter can be one of the following values:
elessair	0:7e2bd16f80af	4767	* @arg TIM_ICPOLARITY_RISING
elessair	0:7e2bd16f80af	4768	* @arg TIM_ICPOLARITY_FALLING
elessair	0:7e2bd16f80af	4769	* @arg TIM_ICPOLARITY_BOTHEDGE
elessair	0:7e2bd16f80af	4770	* @param TIM_ICSelection: specifies the input to be used.
elessair	0:7e2bd16f80af	4771	* This parameter can be one of the following values:
elessair	0:7e2bd16f80af	4772	* @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
elessair	0:7e2bd16f80af	4773	* @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
elessair	0:7e2bd16f80af	4774	* @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
elessair	0:7e2bd16f80af	4775	* @param TIM_ICFilter: Specifies the Input Capture Filter.
elessair	0:7e2bd16f80af	4776	* This parameter must be a value between 0x00 and 0x0F.
elessair	0:7e2bd16f80af	4777	* @retval None
elessair	0:7e2bd16f80af	4778	*/
elessair	0:7e2bd16f80af	4779	static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
elessair	0:7e2bd16f80af	4780	uint32_t TIM_ICFilter)
elessair	0:7e2bd16f80af	4781	{
elessair	0:7e2bd16f80af	4782	uint32_t tmpccmr1 = 0;
elessair	0:7e2bd16f80af	4783	uint32_t tmpccer = 0;
elessair	0:7e2bd16f80af	4784
elessair	0:7e2bd16f80af	4785	/* Disable the Channel 2: Reset the CC2E Bit */
elessair	0:7e2bd16f80af	4786	TIMx->CCER &= ~TIM_CCER_CC2E;
elessair	0:7e2bd16f80af	4787	tmpccmr1 = TIMx->CCMR1;
elessair	0:7e2bd16f80af	4788	tmpccer = TIMx->CCER;
elessair	0:7e2bd16f80af	4789
elessair	0:7e2bd16f80af	4790	/* Select the Input */
elessair	0:7e2bd16f80af	4791	tmpccmr1 &= ~TIM_CCMR1_CC2S;
elessair	0:7e2bd16f80af	4792	tmpccmr1 \|= (TIM_ICSelection << 8);
elessair	0:7e2bd16f80af	4793
elessair	0:7e2bd16f80af	4794	/* Set the filter */
elessair	0:7e2bd16f80af	4795	tmpccmr1 &= ~TIM_CCMR1_IC2F;
elessair	0:7e2bd16f80af	4796	tmpccmr1 \|= (TIM_ICFilter << 12);
elessair	0:7e2bd16f80af	4797
elessair	0:7e2bd16f80af	4798	/* Select the Polarity and set the CC2E Bit */
elessair	0:7e2bd16f80af	4799	tmpccer &= ~(TIM_CCER_CC2P \| TIM_CCER_CC2NP);
elessair	0:7e2bd16f80af	4800	tmpccer \|= (TIM_ICPolarity << 4);
elessair	0:7e2bd16f80af	4801
elessair	0:7e2bd16f80af	4802	/* Write to TIMx CCMR1 and CCER registers */
elessair	0:7e2bd16f80af	4803	TIMx->CCMR1 = tmpccmr1 ;
elessair	0:7e2bd16f80af	4804	TIMx->CCER = tmpccer;
elessair	0:7e2bd16f80af	4805	}
elessair	0:7e2bd16f80af	4806
elessair	0:7e2bd16f80af	4807	/**
elessair	0:7e2bd16f80af	4808	* @brief Configure the Polarity and Filter for TI2.
elessair	0:7e2bd16f80af	4809	* @param TIMx to select the TIM peripheral.
elessair	0:7e2bd16f80af	4810	* @param TIM_ICPolarity : The Input Polarity.
elessair	0:7e2bd16f80af	4811	* This parameter can be one of the following values:
elessair	0:7e2bd16f80af	4812	* @arg TIM_ICPOLARITY_RISING
elessair	0:7e2bd16f80af	4813	* @arg TIM_ICPOLARITY_FALLING
elessair	0:7e2bd16f80af	4814	* @arg TIM_ICPOLARITY_BOTHEDGE
elessair	0:7e2bd16f80af	4815	* @param TIM_ICFilter: Specifies the Input Capture Filter.
elessair	0:7e2bd16f80af	4816	* This parameter must be a value between 0x00 and 0x0F.
elessair	0:7e2bd16f80af	4817	* @retval None
elessair	0:7e2bd16f80af	4818	*/
elessair	0:7e2bd16f80af	4819	static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
elessair	0:7e2bd16f80af	4820	{
elessair	0:7e2bd16f80af	4821	uint32_t tmpccmr1 = 0;
elessair	0:7e2bd16f80af	4822	uint32_t tmpccer = 0;
elessair	0:7e2bd16f80af	4823
elessair	0:7e2bd16f80af	4824	/* Disable the Channel 2: Reset the CC2E Bit */
elessair	0:7e2bd16f80af	4825	TIMx->CCER &= ~TIM_CCER_CC2E;
elessair	0:7e2bd16f80af	4826	tmpccmr1 = TIMx->CCMR1;
elessair	0:7e2bd16f80af	4827	tmpccer = TIMx->CCER;
elessair	0:7e2bd16f80af	4828
elessair	0:7e2bd16f80af	4829	/* Set the filter */
elessair	0:7e2bd16f80af	4830	tmpccmr1 &= ~TIM_CCMR1_IC2F;
elessair	0:7e2bd16f80af	4831	tmpccmr1 \|= (TIM_ICFilter << 12);
elessair	0:7e2bd16f80af	4832
elessair	0:7e2bd16f80af	4833	/* Select the Polarity and set the CC2E Bit */
elessair	0:7e2bd16f80af	4834	tmpccer &= ~(TIM_CCER_CC2P \| TIM_CCER_CC2NP);
elessair	0:7e2bd16f80af	4835	tmpccer \|= (TIM_ICPolarity << 4);
elessair	0:7e2bd16f80af	4836
elessair	0:7e2bd16f80af	4837	/* Write to TIMx CCMR1 and CCER registers */
elessair	0:7e2bd16f80af	4838	TIMx->CCMR1 = tmpccmr1 ;
elessair	0:7e2bd16f80af	4839	TIMx->CCER = tmpccer;
elessair	0:7e2bd16f80af	4840	}
elessair	0:7e2bd16f80af	4841
elessair	0:7e2bd16f80af	4842	/**
elessair	0:7e2bd16f80af	4843	* @brief Configure the TI3 as Input.
elessair	0:7e2bd16f80af	4844	* @param TIMx to select the TIM peripheral
elessair	0:7e2bd16f80af	4845	* @param TIM_ICPolarity : The Input Polarity.
elessair	0:7e2bd16f80af	4846	* This parameter can be one of the following values:
elessair	0:7e2bd16f80af	4847	* @arg TIM_ICPOLARITY_RISING
elessair	0:7e2bd16f80af	4848	* @arg TIM_ICPOLARITY_FALLING
elessair	0:7e2bd16f80af	4849	* @arg TIM_ICPOLARITY_BOTHEDGE
elessair	0:7e2bd16f80af	4850	* @param TIM_ICSelection: specifies the input to be used.
elessair	0:7e2bd16f80af	4851	* This parameter can be one of the following values:
elessair	0:7e2bd16f80af	4852	* @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
elessair	0:7e2bd16f80af	4853	* @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
elessair	0:7e2bd16f80af	4854	* @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
elessair	0:7e2bd16f80af	4855	* @param TIM_ICFilter: Specifies the Input Capture Filter.
elessair	0:7e2bd16f80af	4856	* This parameter must be a value between 0x00 and 0x0F.
elessair	0:7e2bd16f80af	4857	* @retval None
elessair	0:7e2bd16f80af	4858	*/
elessair	0:7e2bd16f80af	4859	static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
elessair	0:7e2bd16f80af	4860	uint32_t TIM_ICFilter)
elessair	0:7e2bd16f80af	4861	{
elessair	0:7e2bd16f80af	4862	uint32_t tmpccmr2 = 0;
elessair	0:7e2bd16f80af	4863	uint32_t tmpccer = 0;
elessair	0:7e2bd16f80af	4864
elessair	0:7e2bd16f80af	4865	/* Disable the Channel 3: Reset the CC3E Bit */
elessair	0:7e2bd16f80af	4866	TIMx->CCER &= ~TIM_CCER_CC3E;
elessair	0:7e2bd16f80af	4867	tmpccmr2 = TIMx->CCMR2;
elessair	0:7e2bd16f80af	4868	tmpccer = TIMx->CCER;
elessair	0:7e2bd16f80af	4869
elessair	0:7e2bd16f80af	4870	/* Select the Input */
elessair	0:7e2bd16f80af	4871	tmpccmr2 &= ~TIM_CCMR2_CC3S;
elessair	0:7e2bd16f80af	4872	tmpccmr2 \|= TIM_ICSelection;
elessair	0:7e2bd16f80af	4873
elessair	0:7e2bd16f80af	4874	/* Set the filter */
elessair	0:7e2bd16f80af	4875	tmpccmr2 &= ~TIM_CCMR2_IC3F;
elessair	0:7e2bd16f80af	4876	tmpccmr2 \|= (TIM_ICFilter << 4);
elessair	0:7e2bd16f80af	4877
elessair	0:7e2bd16f80af	4878	/* Select the Polarity and set the CC3E Bit */
elessair	0:7e2bd16f80af	4879	tmpccer &= ~(TIM_CCER_CC3P \| TIM_CCER_CC3NP);
elessair	0:7e2bd16f80af	4880	tmpccer \|= (TIM_ICPolarity << 8);
elessair	0:7e2bd16f80af	4881
elessair	0:7e2bd16f80af	4882	/* Write to TIMx CCMR2 and CCER registers */
elessair	0:7e2bd16f80af	4883	TIMx->CCMR2 = tmpccmr2;
elessair	0:7e2bd16f80af	4884	TIMx->CCER = tmpccer;
elessair	0:7e2bd16f80af	4885	}
elessair	0:7e2bd16f80af	4886
elessair	0:7e2bd16f80af	4887	/**
elessair	0:7e2bd16f80af	4888	* @brief Configure the TI4 as Input.
elessair	0:7e2bd16f80af	4889	* @param TIMx to select the TIM peripheral
elessair	0:7e2bd16f80af	4890	* @param TIM_ICPolarity : The Input Polarity.
elessair	0:7e2bd16f80af	4891	* This parameter can be one of the following values:
elessair	0:7e2bd16f80af	4892	* @arg TIM_ICPOLARITY_RISING
elessair	0:7e2bd16f80af	4893	* @arg TIM_ICPOLARITY_FALLING
elessair	0:7e2bd16f80af	4894	* @arg TIM_ICPOLARITY_BOTHEDGE
elessair	0:7e2bd16f80af	4895	* @param TIM_ICSelection: specifies the input to be used.
elessair	0:7e2bd16f80af	4896	* This parameter can be one of the following values:
elessair	0:7e2bd16f80af	4897	* @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
elessair	0:7e2bd16f80af	4898	* @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
elessair	0:7e2bd16f80af	4899	* @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
elessair	0:7e2bd16f80af	4900	* @param TIM_ICFilter: Specifies the Input Capture Filter.
elessair	0:7e2bd16f80af	4901	* This parameter must be a value between 0x00 and 0x0F.
elessair	0:7e2bd16f80af	4902	* @retval None
elessair	0:7e2bd16f80af	4903	*/
elessair	0:7e2bd16f80af	4904	static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
elessair	0:7e2bd16f80af	4905	uint32_t TIM_ICFilter)
elessair	0:7e2bd16f80af	4906	{
elessair	0:7e2bd16f80af	4907	uint32_t tmpccmr2 = 0;
elessair	0:7e2bd16f80af	4908	uint32_t tmpccer = 0;
elessair	0:7e2bd16f80af	4909
elessair	0:7e2bd16f80af	4910	/* Disable the Channel 4: Reset the CC4E Bit */
elessair	0:7e2bd16f80af	4911	TIMx->CCER &= ~TIM_CCER_CC4E;
elessair	0:7e2bd16f80af	4912	tmpccmr2 = TIMx->CCMR2;
elessair	0:7e2bd16f80af	4913	tmpccer = TIMx->CCER;
elessair	0:7e2bd16f80af	4914
elessair	0:7e2bd16f80af	4915	/* Select the Input */
elessair	0:7e2bd16f80af	4916	tmpccmr2 &= ~TIM_CCMR2_CC4S;
elessair	0:7e2bd16f80af	4917	tmpccmr2 \|= (TIM_ICSelection << 8);
elessair	0:7e2bd16f80af	4918
elessair	0:7e2bd16f80af	4919	/* Set the filter */
elessair	0:7e2bd16f80af	4920	tmpccmr2 &= ~TIM_CCMR2_IC4F;
elessair	0:7e2bd16f80af	4921	tmpccmr2 \|= (TIM_ICFilter << 12);
elessair	0:7e2bd16f80af	4922
elessair	0:7e2bd16f80af	4923	/* Select the Polarity and set the CC4E Bit */
elessair	0:7e2bd16f80af	4924	tmpccer &= ~(TIM_CCER_CC4P \| TIM_CCER_CC4NP);
elessair	0:7e2bd16f80af	4925	tmpccer \|= (TIM_ICPolarity << 12);
elessair	0:7e2bd16f80af	4926
elessair	0:7e2bd16f80af	4927	/* Write to TIMx CCMR2 and CCER registers */
elessair	0:7e2bd16f80af	4928	TIMx->CCMR2 = tmpccmr2;
elessair	0:7e2bd16f80af	4929	TIMx->CCER = tmpccer ;
elessair	0:7e2bd16f80af	4930	}
elessair	0:7e2bd16f80af	4931
elessair	0:7e2bd16f80af	4932	/**
elessair	0:7e2bd16f80af	4933	* @brief Selects the Input Trigger source
elessair	0:7e2bd16f80af	4934	* @param TIMx to select the TIM peripheral
elessair	0:7e2bd16f80af	4935	* @param InputTriggerSource: The Input Trigger source.
elessair	0:7e2bd16f80af	4936	* This parameter can be one of the following values:
elessair	0:7e2bd16f80af	4937	* @arg TIM_TS_ITR0: Internal Trigger 0
elessair	0:7e2bd16f80af	4938	* @arg TIM_TS_ITR1: Internal Trigger 1
elessair	0:7e2bd16f80af	4939	* @arg TIM_TS_ITR2: Internal Trigger 2
elessair	0:7e2bd16f80af	4940	* @arg TIM_TS_ITR3: Internal Trigger 3
elessair	0:7e2bd16f80af	4941	* @arg TIM_TS_TI1F_ED: TI1 Edge Detector
elessair	0:7e2bd16f80af	4942	* @arg TIM_TS_TI1FP1: Filtered Timer Input 1
elessair	0:7e2bd16f80af	4943	* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
elessair	0:7e2bd16f80af	4944	* @arg TIM_TS_ETRF: External Trigger input
elessair	0:7e2bd16f80af	4945	* @retval None
elessair	0:7e2bd16f80af	4946	*/
elessair	0:7e2bd16f80af	4947	static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
elessair	0:7e2bd16f80af	4948	{
elessair	0:7e2bd16f80af	4949	uint32_t tmpsmcr = 0;
elessair	0:7e2bd16f80af	4950
elessair	0:7e2bd16f80af	4951	/* Get the TIMx SMCR register value */
elessair	0:7e2bd16f80af	4952	tmpsmcr = TIMx->SMCR;
elessair	0:7e2bd16f80af	4953	/* Reset the TS Bits */
elessair	0:7e2bd16f80af	4954	tmpsmcr &= ~TIM_SMCR_TS;
elessair	0:7e2bd16f80af	4955	/* Set the Input Trigger source and the slave mode*/
elessair	0:7e2bd16f80af	4956	tmpsmcr \|= InputTriggerSource \| TIM_SLAVEMODE_EXTERNAL1;
elessair	0:7e2bd16f80af	4957	/* Write to TIMx SMCR */
elessair	0:7e2bd16f80af	4958	TIMx->SMCR = tmpsmcr;
elessair	0:7e2bd16f80af	4959	}
elessair	0:7e2bd16f80af	4960	/**
elessair	0:7e2bd16f80af	4961	* @brief Configures the TIMx External Trigger (ETR).
elessair	0:7e2bd16f80af	4962	* @param TIMx to select the TIM peripheral
elessair	0:7e2bd16f80af	4963	* @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
elessair	0:7e2bd16f80af	4964	* This parameter can be one of the following values:
elessair	0:7e2bd16f80af	4965	* @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
elessair	0:7e2bd16f80af	4966	* @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
elessair	0:7e2bd16f80af	4967	* @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
elessair	0:7e2bd16f80af	4968	* @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
elessair	0:7e2bd16f80af	4969	* @param TIM_ExtTRGPolarity: The external Trigger Polarity.
elessair	0:7e2bd16f80af	4970	* This parameter can be one of the following values:
elessair	0:7e2bd16f80af	4971	* @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
elessair	0:7e2bd16f80af	4972	* @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
elessair	0:7e2bd16f80af	4973	* @param ExtTRGFilter: External Trigger Filter.
elessair	0:7e2bd16f80af	4974	* This parameter must be a value between 0x00 and 0x0F
elessair	0:7e2bd16f80af	4975	* @retval None
elessair	0:7e2bd16f80af	4976	*/
elessair	0:7e2bd16f80af	4977	static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
elessair	0:7e2bd16f80af	4978	uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
elessair	0:7e2bd16f80af	4979	{
elessair	0:7e2bd16f80af	4980	uint32_t tmpsmcr = 0;
elessair	0:7e2bd16f80af	4981
elessair	0:7e2bd16f80af	4982	tmpsmcr = TIMx->SMCR;
elessair	0:7e2bd16f80af	4983
elessair	0:7e2bd16f80af	4984	/* Reset the ETR Bits */
elessair	0:7e2bd16f80af	4985	tmpsmcr &= (uint32_t)(~(TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP));
elessair	0:7e2bd16f80af	4986
elessair	0:7e2bd16f80af	4987	/* Set the Prescaler, the Filter value and the Polarity */
elessair	0:7e2bd16f80af	4988	tmpsmcr \|= (uint32_t)(TIM_ExtTRGPrescaler \| (TIM_ExtTRGPolarity \| (ExtTRGFilter << 8)));
elessair	0:7e2bd16f80af	4989
elessair	0:7e2bd16f80af	4990	/* Write to TIMx SMCR */
elessair	0:7e2bd16f80af	4991	TIMx->SMCR = tmpsmcr;
elessair	0:7e2bd16f80af	4992	}
elessair	0:7e2bd16f80af	4993
elessair	0:7e2bd16f80af	4994	/**
elessair	0:7e2bd16f80af	4995	* @brief Enables or disables the TIM Capture Compare Channel x.
elessair	0:7e2bd16f80af	4996	* @param TIMx to select the TIM peripheral
elessair	0:7e2bd16f80af	4997	* @param Channel: specifies the TIM Channel
elessair	0:7e2bd16f80af	4998	* This parameter can be one of the following values:
elessair	0:7e2bd16f80af	4999	* @arg TIM_CHANNEL_1: TIM Channel 1
elessair	0:7e2bd16f80af	5000	* @arg TIM_CHANNEL_2: TIM Channel 2
elessair	0:7e2bd16f80af	5001	* @arg TIM_CHANNEL_3: TIM Channel 3
elessair	0:7e2bd16f80af	5002	* @arg TIM_CHANNEL_4: TIM Channel 4
elessair	0:7e2bd16f80af	5003	* @param ChannelState: specifies the TIM Channel CCxE bit new state.
elessair	0:7e2bd16f80af	5004	* This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
elessair	0:7e2bd16f80af	5005	* @retval None
elessair	0:7e2bd16f80af	5006	*/
elessair	0:7e2bd16f80af	5007	static void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
elessair	0:7e2bd16f80af	5008	{
elessair	0:7e2bd16f80af	5009	uint32_t tmp = 0;
elessair	0:7e2bd16f80af	5010
elessair	0:7e2bd16f80af	5011	/* Check the parameters */
elessair	0:7e2bd16f80af	5012	assert_param(IS_TIM_CC1_INSTANCE(TIMx));
elessair	0:7e2bd16f80af	5013	assert_param(IS_TIM_CHANNELS(Channel));
elessair	0:7e2bd16f80af	5014
elessair	0:7e2bd16f80af	5015	tmp = (uint16_t)(TIM_CCER_CC1E << Channel);
elessair	0:7e2bd16f80af	5016
elessair	0:7e2bd16f80af	5017	/* Reset the CCxE Bit */
elessair	0:7e2bd16f80af	5018	TIMx->CCER &= ~tmp;
elessair	0:7e2bd16f80af	5019
elessair	0:7e2bd16f80af	5020	/* Set or reset the CCxE Bit */
elessair	0:7e2bd16f80af	5021	TIMx->CCER \|= (uint32_t)(ChannelState << Channel);
elessair	0:7e2bd16f80af	5022	}
elessair	0:7e2bd16f80af	5023
elessair	0:7e2bd16f80af	5024	/**
elessair	0:7e2bd16f80af	5025	* @}
elessair	0:7e2bd16f80af	5026	*/
elessair	0:7e2bd16f80af	5027
elessair	0:7e2bd16f80af	5028	#endif /* HAL_TIM_MODULE_ENABLED */
elessair	0:7e2bd16f80af	5029
elessair	0:7e2bd16f80af	5030
elessair	0:7e2bd16f80af	5031
elessair	0:7e2bd16f80af	5032	/**
elessair	0:7e2bd16f80af	5033	* @}
elessair	0:7e2bd16f80af	5034	*/
elessair	0:7e2bd16f80af	5035
elessair	0:7e2bd16f80af	5036	/**
elessair	0:7e2bd16f80af	5037	* @}
elessair	0:7e2bd16f80af	5038	*/
elessair	0:7e2bd16f80af	5039	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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