CRAC Team / CRAC-Strat_2017_homologation_petit_rob

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Fork of CRAC-Strat_2017_HOMOLOGATION_PETIT_ROBOT by CRAC Team

mbed/SPI.h@21:590cdacb6a35, 2017-05-25 (annotated)

Committer:
ClementBreteau
Date:
Thu May 25 06:34:53 2017 +0000
Revision:
21:590cdacb6a35
Parent:
0:ad97421fb1fb 
homologation petit robot

Who changed what in which revision?

UserRevisionLine numberNew contents of line
antbig 0:ad97421fb1fb 1 /* mbed Microcontroller Library - SPI
antbig 0:ad97421fb1fb 2 * Copyright (c) 2010-2011 ARM Limited. All rights reserved.
antbig 0:ad97421fb1fb 3 */
antbig 0:ad97421fb1fb 4
antbig 0:ad97421fb1fb 5 #ifndef MBED_SPI_H
antbig 0:ad97421fb1fb 6 #define MBED_SPI_H
antbig 0:ad97421fb1fb 7
antbig 0:ad97421fb1fb 8 #include "device.h"
antbig 0:ad97421fb1fb 9
antbig 0:ad97421fb1fb 10 #if DEVICE_SPI
antbig 0:ad97421fb1fb 11
antbig 0:ad97421fb1fb 12 #include "platform.h"
antbig 0:ad97421fb1fb 13 #include "PinNames.h"
antbig 0:ad97421fb1fb 14 #include "PeripheralNames.h"
antbig 0:ad97421fb1fb 15 #include "Base.h"
antbig 0:ad97421fb1fb 16
antbig 0:ad97421fb1fb 17 namespace mbed {
antbig 0:ad97421fb1fb 18
antbig 0:ad97421fb1fb 19 /* Class: SPI
antbig 0:ad97421fb1fb 20 * A SPI Master, used for communicating with SPI slave devices
antbig 0:ad97421fb1fb 21 *
antbig 0:ad97421fb1fb 22 * The default format is set to 8-bits, mode 0, and a clock frequency of 1MHz
antbig 0:ad97421fb1fb 23 *
antbig 0:ad97421fb1fb 24 * Most SPI devices will also require Chip Select and Reset signals. These
antbig 0:ad97421fb1fb 25 * can be controlled using <DigitalOut> pins
antbig 0:ad97421fb1fb 26 *
antbig 0:ad97421fb1fb 27 * Example:
antbig 0:ad97421fb1fb 28 * > // Send a byte to a SPI slave, and record the response
antbig 0:ad97421fb1fb 29 * >
antbig 0:ad97421fb1fb 30 * > #include "mbed.h"
antbig 0:ad97421fb1fb 31 * >
antbig 0:ad97421fb1fb 32 * > SPI device(p5, p6, p7); // mosi, miso, sclk
antbig 0:ad97421fb1fb 33 * >
antbig 0:ad97421fb1fb 34 * > int main() {
antbig 0:ad97421fb1fb 35 * > int response = device.write(0xFF);
antbig 0:ad97421fb1fb 36 * > }
antbig 0:ad97421fb1fb 37 */
antbig 0:ad97421fb1fb 38 class SPI : public Base {
antbig 0:ad97421fb1fb 39
antbig 0:ad97421fb1fb 40 public:
antbig 0:ad97421fb1fb 41
antbig 0:ad97421fb1fb 42 /* Constructor: SPI
antbig 0:ad97421fb1fb 43 * Create a SPI master connected to the specified pins
antbig 0:ad97421fb1fb 44 *
antbig 0:ad97421fb1fb 45 * Variables:
antbig 0:ad97421fb1fb 46 * mosi - SPI Master Out, Slave In pin
antbig 0:ad97421fb1fb 47 * miso - SPI Master In, Slave Out pin
antbig 0:ad97421fb1fb 48 * sclk - SPI Clock pin
antbig 0:ad97421fb1fb 49 * name - (optional) A string to identify the object
antbig 0:ad97421fb1fb 50 *
antbig 0:ad97421fb1fb 51 * Pin Options:
antbig 0:ad97421fb1fb 52 * (5, 6, 7) or (11, 12, 13)
antbig 0:ad97421fb1fb 53 *
antbig 0:ad97421fb1fb 54 * mosi or miso can be specfied as NC if not used
antbig 0:ad97421fb1fb 55 */
antbig 0:ad97421fb1fb 56 SPI(PinName mosi, PinName miso, PinName sclk, const char *name = NULL);
antbig 0:ad97421fb1fb 57
antbig 0:ad97421fb1fb 58 /* Function: format
antbig 0:ad97421fb1fb 59 * Configure the data transmission format
antbig 0:ad97421fb1fb 60 *
antbig 0:ad97421fb1fb 61 * Variables:
antbig 0:ad97421fb1fb 62 * bits - Number of bits per SPI frame (4 - 16)
antbig 0:ad97421fb1fb 63 * mode - Clock polarity and phase mode (0 - 3)
antbig 0:ad97421fb1fb 64 *
antbig 0:ad97421fb1fb 65 * > mode | POL PHA
antbig 0:ad97421fb1fb 66 * > -----+--------
antbig 0:ad97421fb1fb 67 * > 0 | 0 0
antbig 0:ad97421fb1fb 68 * > 1 | 0 1
antbig 0:ad97421fb1fb 69 * > 2 | 1 0
antbig 0:ad97421fb1fb 70 * > 3 | 1 1
antbig 0:ad97421fb1fb 71 */
antbig 0:ad97421fb1fb 72 void format(int bits, int mode = 0);
antbig 0:ad97421fb1fb 73
antbig 0:ad97421fb1fb 74 /* Function: frequency
antbig 0:ad97421fb1fb 75 * Set the spi bus clock frequency
antbig 0:ad97421fb1fb 76 *
antbig 0:ad97421fb1fb 77 * Variables:
antbig 0:ad97421fb1fb 78 * hz - SCLK frequency in hz (default = 1MHz)
antbig 0:ad97421fb1fb 79 */
antbig 0:ad97421fb1fb 80 void frequency(int hz = 1000000);
antbig 0:ad97421fb1fb 81
antbig 0:ad97421fb1fb 82 /* Function: write
antbig 0:ad97421fb1fb 83 * Write to the SPI Slave and return the response
antbig 0:ad97421fb1fb 84 *
antbig 0:ad97421fb1fb 85 * Variables:
antbig 0:ad97421fb1fb 86 * value - Data to be sent to the SPI slave
antbig 0:ad97421fb1fb 87 * returns - Response from the SPI slave
antbig 0:ad97421fb1fb 88 */
antbig 0:ad97421fb1fb 89 virtual int write(int value);
antbig 0:ad97421fb1fb 90
antbig 0:ad97421fb1fb 91
antbig 0:ad97421fb1fb 92 #ifdef MBED_RPC
antbig 0:ad97421fb1fb 93 virtual const struct rpc_method *get_rpc_methods();
antbig 0:ad97421fb1fb 94 static struct rpc_class *get_rpc_class();
antbig 0:ad97421fb1fb 95 #endif
antbig 0:ad97421fb1fb 96
antbig 0:ad97421fb1fb 97 protected:
antbig 0:ad97421fb1fb 98
antbig 0:ad97421fb1fb 99 SPIName _spi;
antbig 0:ad97421fb1fb 100
antbig 0:ad97421fb1fb 101 void aquire(void);
antbig 0:ad97421fb1fb 102 static SPI *_owner;
antbig 0:ad97421fb1fb 103 int _bits;
antbig 0:ad97421fb1fb 104 int _mode;
antbig 0:ad97421fb1fb 105 int _hz;
antbig 0:ad97421fb1fb 106
antbig 0:ad97421fb1fb 107 };
antbig 0:ad97421fb1fb 108
antbig 0:ad97421fb1fb 109 } // namespace mbed
antbig 0:ad97421fb1fb 110
antbig 0:ad97421fb1fb 111 #endif
antbig 0:ad97421fb1fb 112
antbig 0:ad97421fb1fb 113 #endif