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Dependents:   mbed_USBserial

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include/lpc17xx_clkpwr.h@32:1e1e7730b6c8, 2014-06-16 (annotated)

Committer:
jvanhook
Date:
Mon Jun 16 15:36:29 2014 +0000
Revision:
32:1e1e7730b6c8
dfsdfgsdf

Who changed what in which revision?

UserRevisionLine numberNew contents of line
jvanhook 32:1e1e7730b6c8 1 /***********************************************************************//**
jvanhook 32:1e1e7730b6c8 2 * @file : lpc17xx_clkpwr.h
jvanhook 32:1e1e7730b6c8 3 * @brief : Contains all macro definitions and function prototypes
jvanhook 32:1e1e7730b6c8 4 * support for Clock and Power Control firmware library on LPC17xx
jvanhook 32:1e1e7730b6c8 5 * @version : 1.0
jvanhook 32:1e1e7730b6c8 6 * @date : 18. Mar. 2009
jvanhook 32:1e1e7730b6c8 7 * @author : HieuNguyen
jvanhook 32:1e1e7730b6c8 8 **************************************************************************
jvanhook 32:1e1e7730b6c8 9 * Software that is described herein is for illustrative purposes only
jvanhook 32:1e1e7730b6c8 10 * which provides customers with programming information regarding the
jvanhook 32:1e1e7730b6c8 11 * products. This software is supplied "AS IS" without any warranties.
jvanhook 32:1e1e7730b6c8 12 * NXP Semiconductors assumes no responsibility or liability for the
jvanhook 32:1e1e7730b6c8 13 * use of the software, conveys no license or title under any patent,
jvanhook 32:1e1e7730b6c8 14 * copyright, or mask work right to the product. NXP Semiconductors
jvanhook 32:1e1e7730b6c8 15 * reserves the right to make changes in the software without
jvanhook 32:1e1e7730b6c8 16 * notification. NXP Semiconductors also make no representation or
jvanhook 32:1e1e7730b6c8 17 * warranty that such application will be suitable for the specified
jvanhook 32:1e1e7730b6c8 18 * use without further testing or modification.
jvanhook 32:1e1e7730b6c8 19 **************************************************************************/
jvanhook 32:1e1e7730b6c8 20
jvanhook 32:1e1e7730b6c8 21 /* Peripheral group ----------------------------------------------------------- */
jvanhook 32:1e1e7730b6c8 22 /** @defgroup CLKPWR
jvanhook 32:1e1e7730b6c8 23 * @ingroup LPC1700CMSIS_FwLib_Drivers
jvanhook 32:1e1e7730b6c8 24 * @{
jvanhook 32:1e1e7730b6c8 25 */
jvanhook 32:1e1e7730b6c8 26
jvanhook 32:1e1e7730b6c8 27 #ifndef LPC17XX_CLKPWR_H_
jvanhook 32:1e1e7730b6c8 28 #define LPC17XX_CLKPWR_H_
jvanhook 32:1e1e7730b6c8 29
jvanhook 32:1e1e7730b6c8 30 /* Includes ------------------------------------------------------------------- */
jvanhook 32:1e1e7730b6c8 31 #include "lpc17xx.h"
jvanhook 32:1e1e7730b6c8 32 #include "lpc_types.h"
jvanhook 32:1e1e7730b6c8 33
jvanhook 32:1e1e7730b6c8 34 #ifdef __cplusplus
jvanhook 32:1e1e7730b6c8 35 extern "C"
jvanhook 32:1e1e7730b6c8 36 {
jvanhook 32:1e1e7730b6c8 37 #endif
jvanhook 32:1e1e7730b6c8 38
jvanhook 32:1e1e7730b6c8 39
jvanhook 32:1e1e7730b6c8 40 /* Private Macros ------------------------------------------------------------- */
jvanhook 32:1e1e7730b6c8 41 /** @defgroup CLKPWR_Private_Macros
jvanhook 32:1e1e7730b6c8 42 * @{
jvanhook 32:1e1e7730b6c8 43 */
jvanhook 32:1e1e7730b6c8 44
jvanhook 32:1e1e7730b6c8 45 /** @defgroup CLKPPWR_REGISTER_BIT_DEFINITIONS
jvanhook 32:1e1e7730b6c8 46 * @{
jvanhook 32:1e1e7730b6c8 47 */
jvanhook 32:1e1e7730b6c8 48
jvanhook 32:1e1e7730b6c8 49 /* Clock source selection multiplexer definition */
jvanhook 32:1e1e7730b6c8 50 /** Internal RC oscillator */
jvanhook 32:1e1e7730b6c8 51 #define CLKPWR_CLKSRCSEL_CLKSRC_IRC ((uint32_t)(0x00))
jvanhook 32:1e1e7730b6c8 52 /** Main oscillator */
jvanhook 32:1e1e7730b6c8 53 #define CLKPWR_CLKSRCSEL_CLKSRC_MAINOSC ((uint32_t)(0x01))
jvanhook 32:1e1e7730b6c8 54 /** RTC oscillator */
jvanhook 32:1e1e7730b6c8 55 #define CLKPWR_CLKSRCSEL_CLKSRC_RTC ((uint32_t)(0x02))
jvanhook 32:1e1e7730b6c8 56 /** Clock source selection bit mask */
jvanhook 32:1e1e7730b6c8 57 #define CLKPWR_CLKSRCSEL_BITMASK ((uint32_t)(0x03))
jvanhook 32:1e1e7730b6c8 58
jvanhook 32:1e1e7730b6c8 59
jvanhook 32:1e1e7730b6c8 60 /* Clock Output Configuration register definition */
jvanhook 32:1e1e7730b6c8 61 /** Selects the CPU clock as the CLKOUT source */
jvanhook 32:1e1e7730b6c8 62 #define CLKPWR_CLKOUTCFG_CLKOUTSEL_CPU ((uint32_t)(0x00))
jvanhook 32:1e1e7730b6c8 63 /** Selects the main oscillator as the CLKOUT source */
jvanhook 32:1e1e7730b6c8 64 #define CLKPWR_CLKOUTCFG_CLKOUTSEL_MAINOSC ((uint32_t)(0x01))
jvanhook 32:1e1e7730b6c8 65 /** Selects the Internal RC oscillator as the CLKOUT source */
jvanhook 32:1e1e7730b6c8 66 #define CLKPWR_CLKOUTCFG_CLKOUTSEL_RC ((uint32_t)(0x02))
jvanhook 32:1e1e7730b6c8 67 /** Selects the USB clock as the CLKOUT source */
jvanhook 32:1e1e7730b6c8 68 #define CLKPWR_CLKOUTCFG_CLKOUTSEL_USB ((uint32_t)(0x03))
jvanhook 32:1e1e7730b6c8 69 /** Selects the RTC oscillator as the CLKOUT source */
jvanhook 32:1e1e7730b6c8 70 #define CLKPWR_CLKOUTCFG_CLKOUTSEL_RTC ((uint32_t)(0x04))
jvanhook 32:1e1e7730b6c8 71 /** Integer value to divide the output clock by, minus one */
jvanhook 32:1e1e7730b6c8 72 #define CLKPWR_CLKOUTCFG_CLKOUTDIV(n) ((uint32_t)((n&0x0F)<<4))
jvanhook 32:1e1e7730b6c8 73 /** CLKOUT enable control */
jvanhook 32:1e1e7730b6c8 74 #define CLKPWR_CLKOUTCFG_CLKOUT_EN ((uint32_t)(1<<8))
jvanhook 32:1e1e7730b6c8 75 /** CLKOUT activity indication */
jvanhook 32:1e1e7730b6c8 76 #define CLKPWR_CLKOUTCFG_CLKOUT_ACT ((uint32_t)(1<<9))
jvanhook 32:1e1e7730b6c8 77 /** Clock source selection bit mask */
jvanhook 32:1e1e7730b6c8 78 #define CLKPWR_CLKOUTCFG_BITMASK ((uint32_t)(0x3FF))
jvanhook 32:1e1e7730b6c8 79
jvanhook 32:1e1e7730b6c8 80
jvanhook 32:1e1e7730b6c8 81 /* PLL 0 control definition */
jvanhook 32:1e1e7730b6c8 82 /** PLL 0 control enable */
jvanhook 32:1e1e7730b6c8 83 #define CLKPWR_PLL0CON_ENABLE ((uint32_t)(0x01))
jvanhook 32:1e1e7730b6c8 84 /** PLL 0 control connect */
jvanhook 32:1e1e7730b6c8 85 #define CLKPWR_PLL0CON_CONNECT ((uint32_t)(0x02))
jvanhook 32:1e1e7730b6c8 86 /** PLL 0 control bit mask */
jvanhook 32:1e1e7730b6c8 87 #define CLKPWR_PLL0CON_BITMASK ((uint32_t)(0x03))
jvanhook 32:1e1e7730b6c8 88
jvanhook 32:1e1e7730b6c8 89
jvanhook 32:1e1e7730b6c8 90 /* PLL 0 Configuration register definition */
jvanhook 32:1e1e7730b6c8 91 /** PLL 0 Configuration MSEL field */
jvanhook 32:1e1e7730b6c8 92 #define CLKPWR_PLL0CFG_MSEL(n) ((uint32_t)(n&0x7FFF))
jvanhook 32:1e1e7730b6c8 93 /** PLL 0 Configuration NSEL field */
jvanhook 32:1e1e7730b6c8 94 #define CLKPWR_PLL0CFG_NSEL(n) ((uint32_t)((n<<16)&0xFF0000))
jvanhook 32:1e1e7730b6c8 95 /** PLL 0 Configuration bit mask */
jvanhook 32:1e1e7730b6c8 96 #define CLKPWR_PLL0CFG_BITMASK ((uint32_t)(0xFF7FFF))
jvanhook 32:1e1e7730b6c8 97
jvanhook 32:1e1e7730b6c8 98
jvanhook 32:1e1e7730b6c8 99 /* PLL 0 status definition */
jvanhook 32:1e1e7730b6c8 100 /** PLL 0 MSEL value */
jvanhook 32:1e1e7730b6c8 101 #define CLKPWR_PLL0STAT_MSEL(n) ((uint32_t)(n&0x7FFF))
jvanhook 32:1e1e7730b6c8 102 /** PLL NSEL get value */
jvanhook 32:1e1e7730b6c8 103 #define CLKPWR_PLL0STAT_NSEL(n) ((uint32_t)((n>>16)&0xFF))
jvanhook 32:1e1e7730b6c8 104 /** PLL status enable bit */
jvanhook 32:1e1e7730b6c8 105 #define CLKPWR_PLL0STAT_PLLE ((uint32_t)(1<<24))
jvanhook 32:1e1e7730b6c8 106 /** PLL status Connect bit */
jvanhook 32:1e1e7730b6c8 107 #define CLKPWR_PLL0STAT_PLLC ((uint32_t)(1<<25))
jvanhook 32:1e1e7730b6c8 108 /** PLL status lock */
jvanhook 32:1e1e7730b6c8 109 #define CLKPWR_PLL0STAT_PLOCK ((uint32_t)(1<<26))
jvanhook 32:1e1e7730b6c8 110
jvanhook 32:1e1e7730b6c8 111
jvanhook 32:1e1e7730b6c8 112 /* PLL0 Feed register definition */
jvanhook 32:1e1e7730b6c8 113 /** PLL0 Feed bit mask */
jvanhook 32:1e1e7730b6c8 114 #define CLKPWR_PLL0FEED_BITMASK ((uint32_t)0xFF)
jvanhook 32:1e1e7730b6c8 115
jvanhook 32:1e1e7730b6c8 116
jvanhook 32:1e1e7730b6c8 117 /* USB PLL control definition */
jvanhook 32:1e1e7730b6c8 118 /** USB PLL control enable */
jvanhook 32:1e1e7730b6c8 119 #define CLKPWR_PLL1CON_ENABLE ((uint32_t)(0x01))
jvanhook 32:1e1e7730b6c8 120 /** USB PLL control connect */
jvanhook 32:1e1e7730b6c8 121 #define CLKPWR_PLL1CON_CONNECT ((uint32_t)(0x02))
jvanhook 32:1e1e7730b6c8 122 /** USB PLL control bit mask */
jvanhook 32:1e1e7730b6c8 123 #define CLKPWR_PLL1CON_BITMASK ((uint32_t)(0x03))
jvanhook 32:1e1e7730b6c8 124
jvanhook 32:1e1e7730b6c8 125
jvanhook 32:1e1e7730b6c8 126 /* USB PLL configuration definition */
jvanhook 32:1e1e7730b6c8 127 /** USB PLL MSEL set value */
jvanhook 32:1e1e7730b6c8 128 #define CLKPWR_PLL1CFG_MSEL(n) ((uint32_t)(n&0x1F))
jvanhook 32:1e1e7730b6c8 129 /** USB PLL PSEL set value */
jvanhook 32:1e1e7730b6c8 130 #define CLKPWR_PLL1CFG_PSEL(n) ((uint32_t)((n&0x03)<<5))
jvanhook 32:1e1e7730b6c8 131 /** USB PLL configuration bit mask */
jvanhook 32:1e1e7730b6c8 132 #define CLKPWR_PLL1CFG_BITMASK ((uint32_t)(0x7F))
jvanhook 32:1e1e7730b6c8 133
jvanhook 32:1e1e7730b6c8 134
jvanhook 32:1e1e7730b6c8 135 /* USB PLL status definition */
jvanhook 32:1e1e7730b6c8 136 /** USB PLL MSEL get value */
jvanhook 32:1e1e7730b6c8 137 #define CLKPWR_PLL1STAT_MSEL(n) ((uint32_t)(n&0x1F))
jvanhook 32:1e1e7730b6c8 138 /** USB PLL PSEL get value */
jvanhook 32:1e1e7730b6c8 139 #define CLKPWR_PLL1STAT_PSEL(n) ((uint32_t)((n>>5)&0x03))
jvanhook 32:1e1e7730b6c8 140 /** USB PLL status enable bit */
jvanhook 32:1e1e7730b6c8 141 #define CLKPWR_PLL1STAT_PLLE ((uint32_t)(1<<8))
jvanhook 32:1e1e7730b6c8 142 /** USB PLL status Connect bit */
jvanhook 32:1e1e7730b6c8 143 #define CLKPWR_PLL1STAT_PLLC ((uint32_t)(1<<9))
jvanhook 32:1e1e7730b6c8 144 /** USB PLL status lock */
jvanhook 32:1e1e7730b6c8 145 #define CLKPWR_PLL1STAT_PLOCK ((uint32_t)(1<<10))
jvanhook 32:1e1e7730b6c8 146
jvanhook 32:1e1e7730b6c8 147
jvanhook 32:1e1e7730b6c8 148 /* PLL1 Feed register definition */
jvanhook 32:1e1e7730b6c8 149 /** PLL1 Feed bit mask */
jvanhook 32:1e1e7730b6c8 150 #define CLKPWR_PLL1FEED_BITMASK ((uint32_t)0xFF)
jvanhook 32:1e1e7730b6c8 151
jvanhook 32:1e1e7730b6c8 152
jvanhook 32:1e1e7730b6c8 153 /* CPU Clock Configuration register definition */
jvanhook 32:1e1e7730b6c8 154 /** CPU Clock configuration bit mask */
jvanhook 32:1e1e7730b6c8 155 #define CLKPWR_CCLKCFG_BITMASK ((uint32_t)(0xFF))
jvanhook 32:1e1e7730b6c8 156
jvanhook 32:1e1e7730b6c8 157 /* USB Clock Configuration register definition */
jvanhook 32:1e1e7730b6c8 158 /** USB Clock Configuration bit mask */
jvanhook 32:1e1e7730b6c8 159 #define CLKPWR_USBCLKCFG_BITMASK ((uint32_t)(0x0F))
jvanhook 32:1e1e7730b6c8 160
jvanhook 32:1e1e7730b6c8 161 /* IRC Trim register definition */
jvanhook 32:1e1e7730b6c8 162 /** IRC Trim bit mask */
jvanhook 32:1e1e7730b6c8 163 #define CLKPWR_IRCTRIM_BITMASK ((uint32_t)(0x0F))
jvanhook 32:1e1e7730b6c8 164
jvanhook 32:1e1e7730b6c8 165
jvanhook 32:1e1e7730b6c8 166 /* Peripheral clock divider bit position definition */
jvanhook 32:1e1e7730b6c8 167 /** Peripheral Clock Selection 0 mask bit */
jvanhook 32:1e1e7730b6c8 168 #define CLKPWR_PCLKSEL0_BITMASK ((uint32_t)(0xFFF3F3FF))
jvanhook 32:1e1e7730b6c8 169 /** Peripheral Clock Selection 1 mask bit */
jvanhook 32:1e1e7730b6c8 170 #define CLKPWR_PCLKSEL1_BITMASK ((uint32_t)(0xFCF3F0F3))
jvanhook 32:1e1e7730b6c8 171
jvanhook 32:1e1e7730b6c8 172
jvanhook 32:1e1e7730b6c8 173 /** Macro to set peripheral clock of each type
jvanhook 32:1e1e7730b6c8 174 * p: position of two bits that hold divider of peripheral clock
jvanhook 32:1e1e7730b6c8 175 * n: value of divider of peripheral clock to be set */
jvanhook 32:1e1e7730b6c8 176 #define CLKPWR_PCLKSEL_SET(p,n) _SBF(p,n)
jvanhook 32:1e1e7730b6c8 177 /** Macro to mask peripheral clock of each type */
jvanhook 32:1e1e7730b6c8 178 #define CLKPWR_PCLKSEL_BITMASK(p) _SBF(p,0x03)
jvanhook 32:1e1e7730b6c8 179 /** Macro to get peripheral clock of each type */
jvanhook 32:1e1e7730b6c8 180 #define CLKPWR_PCLKSEL_GET(p, n) ((uint32_t)((n>>p)&0x03))
jvanhook 32:1e1e7730b6c8 181
jvanhook 32:1e1e7730b6c8 182
jvanhook 32:1e1e7730b6c8 183 /* Power Mode Control register definition */
jvanhook 32:1e1e7730b6c8 184 /** Power mode control bit 0 */
jvanhook 32:1e1e7730b6c8 185 #define CLKPWR_PCON_PM0 ((uint32_t)(1<<0))
jvanhook 32:1e1e7730b6c8 186 /** Power mode control bit 1 */
jvanhook 32:1e1e7730b6c8 187 #define CLKPWR_PCON_PM1 ((uint32_t)(1<<1))
jvanhook 32:1e1e7730b6c8 188 /** Brown-Out Reduced Power Mode */
jvanhook 32:1e1e7730b6c8 189 #define CLKPWR_PCON_BODPDM ((uint32_t)(1<<2))
jvanhook 32:1e1e7730b6c8 190 /** Brown-Out Global Disable */
jvanhook 32:1e1e7730b6c8 191 #define CLKPWR_PCON_BOGD ((uint32_t)(1<<3))
jvanhook 32:1e1e7730b6c8 192 /** Brown Out Reset Disable */
jvanhook 32:1e1e7730b6c8 193 #define CLKPWR_PCON_BORD ((uint32_t)(1<<4))
jvanhook 32:1e1e7730b6c8 194 /** Sleep Mode entry flag */
jvanhook 32:1e1e7730b6c8 195 #define CLKPWR_PCON_SMFLAG ((uint32_t)(1<<8))
jvanhook 32:1e1e7730b6c8 196 /** Deep Sleep entry flag */
jvanhook 32:1e1e7730b6c8 197 #define CLKPWR_PCON_DSFLAG ((uint32_t)(1<<9))
jvanhook 32:1e1e7730b6c8 198 /** Power-down entry flag */
jvanhook 32:1e1e7730b6c8 199 #define CLKPWR_PCON_PDFLAG ((uint32_t)(1<<10))
jvanhook 32:1e1e7730b6c8 200 /** Deep Power-down entry flag */
jvanhook 32:1e1e7730b6c8 201 #define CLKPWR_PCON_DPDFLAG ((uint32_t)(1<<11))
jvanhook 32:1e1e7730b6c8 202
jvanhook 32:1e1e7730b6c8 203
jvanhook 32:1e1e7730b6c8 204 /** Power Control for Peripherals bit mask */
jvanhook 32:1e1e7730b6c8 205 #define CLKPWR_PCONP_BITMASK 0xEFEFF7DE
jvanhook 32:1e1e7730b6c8 206
jvanhook 32:1e1e7730b6c8 207 /**
jvanhook 32:1e1e7730b6c8 208 * @}
jvanhook 32:1e1e7730b6c8 209 */
jvanhook 32:1e1e7730b6c8 210
jvanhook 32:1e1e7730b6c8 211 /**
jvanhook 32:1e1e7730b6c8 212 * @}
jvanhook 32:1e1e7730b6c8 213 */
jvanhook 32:1e1e7730b6c8 214
jvanhook 32:1e1e7730b6c8 215
jvanhook 32:1e1e7730b6c8 216 /* Public Macros -------------------------------------------------------------- */
jvanhook 32:1e1e7730b6c8 217 /** @defgroup CLKPWR_Public_Macros
jvanhook 32:1e1e7730b6c8 218 * @{
jvanhook 32:1e1e7730b6c8 219 */
jvanhook 32:1e1e7730b6c8 220
jvanhook 32:1e1e7730b6c8 221 /**********************************************************************
jvanhook 32:1e1e7730b6c8 222 * Peripheral Clock Selection Definitions
jvanhook 32:1e1e7730b6c8 223 **********************************************************************/
jvanhook 32:1e1e7730b6c8 224 /** Peripheral clock divider bit position for WDT */
jvanhook 32:1e1e7730b6c8 225 #define CLKPWR_PCLKSEL_WDT ((uint32_t)(0))
jvanhook 32:1e1e7730b6c8 226 /** Peripheral clock divider bit position for TIMER0 */
jvanhook 32:1e1e7730b6c8 227 #define CLKPWR_PCLKSEL_TIMER0 ((uint32_t)(2))
jvanhook 32:1e1e7730b6c8 228 /** Peripheral clock divider bit position for TIMER1 */
jvanhook 32:1e1e7730b6c8 229 #define CLKPWR_PCLKSEL_TIMER1 ((uint32_t)(4))
jvanhook 32:1e1e7730b6c8 230 /** Peripheral clock divider bit position for UART0 */
jvanhook 32:1e1e7730b6c8 231 #define CLKPWR_PCLKSEL_UART0 ((uint32_t)(6))
jvanhook 32:1e1e7730b6c8 232 /** Peripheral clock divider bit position for UART1 */
jvanhook 32:1e1e7730b6c8 233 #define CLKPWR_PCLKSEL_UART1 ((uint32_t)(8))
jvanhook 32:1e1e7730b6c8 234 /** Peripheral clock divider bit position for PWM1 */
jvanhook 32:1e1e7730b6c8 235 #define CLKPWR_PCLKSEL_PWM1 ((uint32_t)(12))
jvanhook 32:1e1e7730b6c8 236 /** Peripheral clock divider bit position for I2C0 */
jvanhook 32:1e1e7730b6c8 237 #define CLKPWR_PCLKSEL_I2C0 ((uint32_t)(14))
jvanhook 32:1e1e7730b6c8 238 /** Peripheral clock divider bit position for SPI */
jvanhook 32:1e1e7730b6c8 239 #define CLKPWR_PCLKSEL_SPI ((uint32_t)(16))
jvanhook 32:1e1e7730b6c8 240 /** Peripheral clock divider bit position for SSP1 */
jvanhook 32:1e1e7730b6c8 241 #define CLKPWR_PCLKSEL_SSP1 ((uint32_t)(20))
jvanhook 32:1e1e7730b6c8 242 /** Peripheral clock divider bit position for DAC */
jvanhook 32:1e1e7730b6c8 243 #define CLKPWR_PCLKSEL_DAC ((uint32_t)(22))
jvanhook 32:1e1e7730b6c8 244 /** Peripheral clock divider bit position for ADC */
jvanhook 32:1e1e7730b6c8 245 #define CLKPWR_PCLKSEL_ADC ((uint32_t)(24))
jvanhook 32:1e1e7730b6c8 246 /** Peripheral clock divider bit position for CAN1 */
jvanhook 32:1e1e7730b6c8 247 #define CLKPWR_PCLKSEL_CAN1 ((uint32_t)(26))
jvanhook 32:1e1e7730b6c8 248 /** Peripheral clock divider bit position for CAN2 */
jvanhook 32:1e1e7730b6c8 249 #define CLKPWR_PCLKSEL_CAN2 ((uint32_t)(28))
jvanhook 32:1e1e7730b6c8 250 /** Peripheral clock divider bit position for ACF */
jvanhook 32:1e1e7730b6c8 251 #define CLKPWR_PCLKSEL_ACF ((uint32_t)(30))
jvanhook 32:1e1e7730b6c8 252 /** Peripheral clock divider bit position for QEI */
jvanhook 32:1e1e7730b6c8 253 #define CLKPWR_PCLKSEL_QEI ((uint32_t)(32))
jvanhook 32:1e1e7730b6c8 254 /** Peripheral clock divider bit position for PCB */
jvanhook 32:1e1e7730b6c8 255 #define CLKPWR_PCLKSEL_PCB ((uint32_t)(36))
jvanhook 32:1e1e7730b6c8 256 /** Peripheral clock divider bit position for I2C1 */
jvanhook 32:1e1e7730b6c8 257 #define CLKPWR_PCLKSEL_I2C1 ((uint32_t)(38))
jvanhook 32:1e1e7730b6c8 258 /** Peripheral clock divider bit position for SSP0 */
jvanhook 32:1e1e7730b6c8 259 #define CLKPWR_PCLKSEL_SSP0 ((uint32_t)(42))
jvanhook 32:1e1e7730b6c8 260 /** Peripheral clock divider bit position for TIMER2 */
jvanhook 32:1e1e7730b6c8 261 #define CLKPWR_PCLKSEL_TIMER2 ((uint32_t)(44))
jvanhook 32:1e1e7730b6c8 262 /** Peripheral clock divider bit position for TIMER3 */
jvanhook 32:1e1e7730b6c8 263 #define CLKPWR_PCLKSEL_TIMER3 ((uint32_t)(46))
jvanhook 32:1e1e7730b6c8 264 /** Peripheral clock divider bit position for UART2 */
jvanhook 32:1e1e7730b6c8 265 #define CLKPWR_PCLKSEL_UART2 ((uint32_t)(48))
jvanhook 32:1e1e7730b6c8 266 /** Peripheral clock divider bit position for UART3 */
jvanhook 32:1e1e7730b6c8 267 #define CLKPWR_PCLKSEL_UART3 ((uint32_t)(50))
jvanhook 32:1e1e7730b6c8 268 /** Peripheral clock divider bit position for I2C2 */
jvanhook 32:1e1e7730b6c8 269 #define CLKPWR_PCLKSEL_I2C2 ((uint32_t)(52))
jvanhook 32:1e1e7730b6c8 270 /** Peripheral clock divider bit position for I2S */
jvanhook 32:1e1e7730b6c8 271 #define CLKPWR_PCLKSEL_I2S ((uint32_t)(54))
jvanhook 32:1e1e7730b6c8 272 /** Peripheral clock divider bit position for RIT */
jvanhook 32:1e1e7730b6c8 273 #define CLKPWR_PCLKSEL_RIT ((uint32_t)(58))
jvanhook 32:1e1e7730b6c8 274 /** Peripheral clock divider bit position for SYSCON */
jvanhook 32:1e1e7730b6c8 275 #define CLKPWR_PCLKSEL_SYSCON ((uint32_t)(60))
jvanhook 32:1e1e7730b6c8 276 /** Peripheral clock divider bit position for MC */
jvanhook 32:1e1e7730b6c8 277 #define CLKPWR_PCLKSEL_MC ((uint32_t)(62))
jvanhook 32:1e1e7730b6c8 278
jvanhook 32:1e1e7730b6c8 279 /** Macro for Peripheral Clock Selection register bit values
jvanhook 32:1e1e7730b6c8 280 * Note: When CCLK_DIV_8, Peripheral’s clock is selected to
jvanhook 32:1e1e7730b6c8 281 * PCLK_xyz = CCLK/8 except for CAN1, CAN2, and CAN filtering
jvanhook 32:1e1e7730b6c8 282 * when ’11’selects PCLK_xyz = CCLK/6 */
jvanhook 32:1e1e7730b6c8 283 /* Peripheral clock divider is set to 4 from CCLK */
jvanhook 32:1e1e7730b6c8 284 #define CLKPWR_PCLKSEL_CCLK_DIV_4 ((uint32_t)(0))
jvanhook 32:1e1e7730b6c8 285 /** Peripheral clock divider is the same with CCLK */
jvanhook 32:1e1e7730b6c8 286 #define CLKPWR_PCLKSEL_CCLK_DIV_1 ((uint32_t)(1))
jvanhook 32:1e1e7730b6c8 287 /** Peripheral clock divider is set to 2 from CCLK */
jvanhook 32:1e1e7730b6c8 288 #define CLKPWR_PCLKSEL_CCLK_DIV_2 ((uint32_t)(2))
jvanhook 32:1e1e7730b6c8 289
jvanhook 32:1e1e7730b6c8 290
jvanhook 32:1e1e7730b6c8 291 /********************************************************************
jvanhook 32:1e1e7730b6c8 292 * Power Control for Peripherals Definitions
jvanhook 32:1e1e7730b6c8 293 **********************************************************************/
jvanhook 32:1e1e7730b6c8 294 /** Timer/Counter 0 power/clock control bit */
jvanhook 32:1e1e7730b6c8 295 #define CLKPWR_PCONP_PCTIM0 ((uint32_t)(1<<1))
jvanhook 32:1e1e7730b6c8 296 /* Timer/Counter 1 power/clock control bit */
jvanhook 32:1e1e7730b6c8 297 #define CLKPWR_PCONP_PCTIM1 ((uint32_t)(1<<2))
jvanhook 32:1e1e7730b6c8 298 /** UART0 power/clock control bit */
jvanhook 32:1e1e7730b6c8 299 #define CLKPWR_PCONP_PCUART0 ((uint32_t)(1<<3))
jvanhook 32:1e1e7730b6c8 300 /** UART1 power/clock control bit */
jvanhook 32:1e1e7730b6c8 301 #define CLKPWR_PCONP_PCUART1 ((uint32_t)(1<<4))
jvanhook 32:1e1e7730b6c8 302 /** PWM1 power/clock control bit */
jvanhook 32:1e1e7730b6c8 303 #define CLKPWR_PCONP_PCPWM1 ((uint32_t)(1<<6))
jvanhook 32:1e1e7730b6c8 304 /** The I2C0 interface power/clock control bit */
jvanhook 32:1e1e7730b6c8 305 #define CLKPWR_PCONP_PCI2C0 ((uint32_t)(1<<7))
jvanhook 32:1e1e7730b6c8 306 /** The SPI interface power/clock control bit */
jvanhook 32:1e1e7730b6c8 307 #define CLKPWR_PCONP_PCSPI ((uint32_t)(1<<8))
jvanhook 32:1e1e7730b6c8 308 /** The RTC power/clock control bit */
jvanhook 32:1e1e7730b6c8 309 #define CLKPWR_PCONP_PCRTC ((uint32_t)(1<<9))
jvanhook 32:1e1e7730b6c8 310 /** The SSP1 interface power/clock control bit */
jvanhook 32:1e1e7730b6c8 311 #define CLKPWR_PCONP_PCSSP1 ((uint32_t)(1<<10))
jvanhook 32:1e1e7730b6c8 312 /** A/D converter 0 (ADC0) power/clock control bit */
jvanhook 32:1e1e7730b6c8 313 #define CLKPWR_PCONP_PCAD ((uint32_t)(1<<12))
jvanhook 32:1e1e7730b6c8 314 /** CAN Controller 1 power/clock control bit */
jvanhook 32:1e1e7730b6c8 315 #define CLKPWR_PCONP_PCAN1 ((uint32_t)(1<<13))
jvanhook 32:1e1e7730b6c8 316 /** CAN Controller 2 power/clock control bit */
jvanhook 32:1e1e7730b6c8 317 #define CLKPWR_PCONP_PCAN2 ((uint32_t)(1<<14))
jvanhook 32:1e1e7730b6c8 318 /** GPIO power/clock control bit */
jvanhook 32:1e1e7730b6c8 319 #define CLKPWR_PCONP_PCGPIO ((uint32_t)(1<<15))
jvanhook 32:1e1e7730b6c8 320 /** Repetitive Interrupt Timer power/clock control bit */
jvanhook 32:1e1e7730b6c8 321 #define CLKPWR_PCONP_PCRIT ((uint32_t)(1<<16))
jvanhook 32:1e1e7730b6c8 322 /** Motor Control PWM */
jvanhook 32:1e1e7730b6c8 323 #define CLKPWR_PCONP_PCMC ((uint32_t)(1<<17))
jvanhook 32:1e1e7730b6c8 324 /** Quadrature Encoder Interface power/clock control bit */
jvanhook 32:1e1e7730b6c8 325 #define CLKPWR_PCONP_PCQEI ((uint32_t)(1<<18))
jvanhook 32:1e1e7730b6c8 326 /** The I2C1 interface power/clock control bit */
jvanhook 32:1e1e7730b6c8 327 #define CLKPWR_PCONP_PCI2C1 ((uint32_t)(1<<19))
jvanhook 32:1e1e7730b6c8 328 /** The SSP0 interface power/clock control bit */
jvanhook 32:1e1e7730b6c8 329 #define CLKPWR_PCONP_PCSSP0 ((uint32_t)(1<<21))
jvanhook 32:1e1e7730b6c8 330 /** Timer 2 power/clock control bit */
jvanhook 32:1e1e7730b6c8 331 #define CLKPWR_PCONP_PCTIM2 ((uint32_t)(1<<22))
jvanhook 32:1e1e7730b6c8 332 /** Timer 3 power/clock control bit */
jvanhook 32:1e1e7730b6c8 333 #define CLKPWR_PCONP_PCTIM3 ((uint32_t)(1<<23))
jvanhook 32:1e1e7730b6c8 334 /** UART 2 power/clock control bit */
jvanhook 32:1e1e7730b6c8 335 #define CLKPWR_PCONP_PCUART2 ((uint32_t)(1<<24))
jvanhook 32:1e1e7730b6c8 336 /** UART 3 power/clock control bit */
jvanhook 32:1e1e7730b6c8 337 #define CLKPWR_PCONP_PCUART3 ((uint32_t)(1<<25))
jvanhook 32:1e1e7730b6c8 338 /** I2C interface 2 power/clock control bit */
jvanhook 32:1e1e7730b6c8 339 #define CLKPWR_PCONP_PCI2C2 ((uint32_t)(1<<26))
jvanhook 32:1e1e7730b6c8 340 /** I2S interface power/clock control bit*/
jvanhook 32:1e1e7730b6c8 341 #define CLKPWR_PCONP_PCI2S ((uint32_t)(1<<27))
jvanhook 32:1e1e7730b6c8 342 /** GP DMA function power/clock control bit*/
jvanhook 32:1e1e7730b6c8 343 #define CLKPWR_PCONP_PCGPDMA ((uint32_t)(1<<29))
jvanhook 32:1e1e7730b6c8 344 /** Ethernet block power/clock control bit*/
jvanhook 32:1e1e7730b6c8 345 #define CLKPWR_PCONP_PCENET ((uint32_t)(1<<30))
jvanhook 32:1e1e7730b6c8 346 /** USB interface power/clock control bit*/
jvanhook 32:1e1e7730b6c8 347 #define CLKPWR_PCONP_PCUSB ((uint32_t)(1<<31))
jvanhook 32:1e1e7730b6c8 348
jvanhook 32:1e1e7730b6c8 349
jvanhook 32:1e1e7730b6c8 350 /**
jvanhook 32:1e1e7730b6c8 351 * @}
jvanhook 32:1e1e7730b6c8 352 */
jvanhook 32:1e1e7730b6c8 353
jvanhook 32:1e1e7730b6c8 354
jvanhook 32:1e1e7730b6c8 355 /* Public Functions ----------------------------------------------------------- */
jvanhook 32:1e1e7730b6c8 356 /** @defgroup CLKPWR_Public_Functions
jvanhook 32:1e1e7730b6c8 357 * @{
jvanhook 32:1e1e7730b6c8 358 */
jvanhook 32:1e1e7730b6c8 359 #define CHECK_PARAM ;
jvanhook 32:1e1e7730b6c8 360
jvanhook 32:1e1e7730b6c8 361 void CLKPWR_SetPCLKDiv (uint32_t ClkType, uint32_t DivVal);
jvanhook 32:1e1e7730b6c8 362 uint32_t CLKPWR_GetPCLKSEL (uint32_t ClkType);
jvanhook 32:1e1e7730b6c8 363 uint32_t CLKPWR_GetPCLK (uint32_t ClkType);
jvanhook 32:1e1e7730b6c8 364 void CLKPWR_ConfigPPWR (uint32_t PPType, FunctionalState NewState);
jvanhook 32:1e1e7730b6c8 365 void CLKPWR_Sleep(void);
jvanhook 32:1e1e7730b6c8 366 void CLKPWR_DeepSleep(void);
jvanhook 32:1e1e7730b6c8 367 void CLKPWR_PowerDown(void);
jvanhook 32:1e1e7730b6c8 368 void CLKPWR_DeepPowerDown(void);
jvanhook 32:1e1e7730b6c8 369
jvanhook 32:1e1e7730b6c8 370 /**
jvanhook 32:1e1e7730b6c8 371 * @}
jvanhook 32:1e1e7730b6c8 372 */
jvanhook 32:1e1e7730b6c8 373
jvanhook 32:1e1e7730b6c8 374
jvanhook 32:1e1e7730b6c8 375 #ifdef __cplusplus
jvanhook 32:1e1e7730b6c8 376 }
jvanhook 32:1e1e7730b6c8 377 #endif
jvanhook 32:1e1e7730b6c8 378
jvanhook 32:1e1e7730b6c8 379 #endif /* LPC17XX_CLKPWR_H_ */
jvanhook 32:1e1e7730b6c8 380
jvanhook 32:1e1e7730b6c8 381 /**
jvanhook 32:1e1e7730b6c8 382 * @}
jvanhook 32:1e1e7730b6c8 383 */
jvanhook 32:1e1e7730b6c8 384
jvanhook 32:1e1e7730b6c8 385 /* --------------------------------- End Of File ------------------------------ */
jvanhook 32:1e1e7730b6c8 386