Bose Automation / mbed-rtos

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Dependents:   mbed_USBserial

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include/lpc17xx.h@32:1e1e7730b6c8, 2014-06-16 (annotated)

Committer:
jvanhook
Date:
Mon Jun 16 15:36:29 2014 +0000
Revision:
32:1e1e7730b6c8
dfsdfgsdf

Who changed what in which revision?

UserRevisionLine numberNew contents of line
jvanhook 32:1e1e7730b6c8 1 /**************************************************************************//**
jvanhook 32:1e1e7730b6c8 2 * @file LPC17xx.h
jvanhook 32:1e1e7730b6c8 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
jvanhook 32:1e1e7730b6c8 4 * NXP LPC17xx Device Series
jvanhook 32:1e1e7730b6c8 5 * @version: V1.09
jvanhook 32:1e1e7730b6c8 6 * @date: 17. March 2010
jvanhook 32:1e1e7730b6c8 7
jvanhook 32:1e1e7730b6c8 8 *
jvanhook 32:1e1e7730b6c8 9 * @note
jvanhook 32:1e1e7730b6c8 10 * Copyright (C) 2009 ARM Limited. All rights reserved.
jvanhook 32:1e1e7730b6c8 11 *
jvanhook 32:1e1e7730b6c8 12 * @par
jvanhook 32:1e1e7730b6c8 13 * ARM Limited (ARM) is supplying this software for use with Cortex-M
jvanhook 32:1e1e7730b6c8 14 * processor based microcontrollers. This file can be freely distributed
jvanhook 32:1e1e7730b6c8 15 * within development tools that are supporting such ARM based processors.
jvanhook 32:1e1e7730b6c8 16 *
jvanhook 32:1e1e7730b6c8 17 * @par
jvanhook 32:1e1e7730b6c8 18 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
jvanhook 32:1e1e7730b6c8 19 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
jvanhook 32:1e1e7730b6c8 20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
jvanhook 32:1e1e7730b6c8 21 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
jvanhook 32:1e1e7730b6c8 22 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
jvanhook 32:1e1e7730b6c8 23 *
jvanhook 32:1e1e7730b6c8 24 ******************************************************************************/
jvanhook 32:1e1e7730b6c8 25
jvanhook 32:1e1e7730b6c8 26
jvanhook 32:1e1e7730b6c8 27 #ifndef __LPC17xx_H__
jvanhook 32:1e1e7730b6c8 28 #define __LPC17xx_H__
jvanhook 32:1e1e7730b6c8 29
jvanhook 32:1e1e7730b6c8 30 /*
jvanhook 32:1e1e7730b6c8 31 * ==========================================================================
jvanhook 32:1e1e7730b6c8 32 * ---------- Interrupt Number Definition -----------------------------------
jvanhook 32:1e1e7730b6c8 33 * ==========================================================================
jvanhook 32:1e1e7730b6c8 34 */
jvanhook 32:1e1e7730b6c8 35
jvanhook 32:1e1e7730b6c8 36 typedef enum IRQn
jvanhook 32:1e1e7730b6c8 37 {
jvanhook 32:1e1e7730b6c8 38 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
jvanhook 32:1e1e7730b6c8 39 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
jvanhook 32:1e1e7730b6c8 40 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
jvanhook 32:1e1e7730b6c8 41 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
jvanhook 32:1e1e7730b6c8 42 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
jvanhook 32:1e1e7730b6c8 43 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
jvanhook 32:1e1e7730b6c8 44 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
jvanhook 32:1e1e7730b6c8 45 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
jvanhook 32:1e1e7730b6c8 46 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
jvanhook 32:1e1e7730b6c8 47
jvanhook 32:1e1e7730b6c8 48 /****** LPC17xx Specific Interrupt Numbers *******************************************************/
jvanhook 32:1e1e7730b6c8 49 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
jvanhook 32:1e1e7730b6c8 50 TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
jvanhook 32:1e1e7730b6c8 51 TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
jvanhook 32:1e1e7730b6c8 52 TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
jvanhook 32:1e1e7730b6c8 53 TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
jvanhook 32:1e1e7730b6c8 54 UART0_IRQn = 5, /*!< UART0 Interrupt */
jvanhook 32:1e1e7730b6c8 55 UART1_IRQn = 6, /*!< UART1 Interrupt */
jvanhook 32:1e1e7730b6c8 56 UART2_IRQn = 7, /*!< UART2 Interrupt */
jvanhook 32:1e1e7730b6c8 57 UART3_IRQn = 8, /*!< UART3 Interrupt */
jvanhook 32:1e1e7730b6c8 58 PWM1_IRQn = 9, /*!< PWM1 Interrupt */
jvanhook 32:1e1e7730b6c8 59 I2C0_IRQn = 10, /*!< I2C0 Interrupt */
jvanhook 32:1e1e7730b6c8 60 I2C1_IRQn = 11, /*!< I2C1 Interrupt */
jvanhook 32:1e1e7730b6c8 61 I2C2_IRQn = 12, /*!< I2C2 Interrupt */
jvanhook 32:1e1e7730b6c8 62 SPI_IRQn = 13, /*!< SPI Interrupt */
jvanhook 32:1e1e7730b6c8 63 SSP0_IRQn = 14, /*!< SSP0 Interrupt */
jvanhook 32:1e1e7730b6c8 64 SSP1_IRQn = 15, /*!< SSP1 Interrupt */
jvanhook 32:1e1e7730b6c8 65 PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
jvanhook 32:1e1e7730b6c8 66 RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
jvanhook 32:1e1e7730b6c8 67 EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
jvanhook 32:1e1e7730b6c8 68 EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
jvanhook 32:1e1e7730b6c8 69 EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
jvanhook 32:1e1e7730b6c8 70 EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
jvanhook 32:1e1e7730b6c8 71 ADC_IRQn = 22, /*!< A/D Converter Interrupt */
jvanhook 32:1e1e7730b6c8 72 BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
jvanhook 32:1e1e7730b6c8 73 USB_IRQn = 24, /*!< USB Interrupt */
jvanhook 32:1e1e7730b6c8 74 CAN_IRQn = 25, /*!< CAN Interrupt */
jvanhook 32:1e1e7730b6c8 75 DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
jvanhook 32:1e1e7730b6c8 76 I2S_IRQn = 27, /*!< I2S Interrupt */
jvanhook 32:1e1e7730b6c8 77 ENET_IRQn = 28, /*!< Ethernet Interrupt */
jvanhook 32:1e1e7730b6c8 78 RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */
jvanhook 32:1e1e7730b6c8 79 MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
jvanhook 32:1e1e7730b6c8 80 QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
jvanhook 32:1e1e7730b6c8 81 PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
jvanhook 32:1e1e7730b6c8 82 USBActivity_IRQn = 33, /* USB Activity interrupt */
jvanhook 32:1e1e7730b6c8 83 CANActivity_IRQn = 34, /* CAN Activity interrupt */
jvanhook 32:1e1e7730b6c8 84 } IRQn_Type;
jvanhook 32:1e1e7730b6c8 85
jvanhook 32:1e1e7730b6c8 86
jvanhook 32:1e1e7730b6c8 87 /*
jvanhook 32:1e1e7730b6c8 88 * ==========================================================================
jvanhook 32:1e1e7730b6c8 89 * ----------- Processor and Core Peripheral Section ------------------------
jvanhook 32:1e1e7730b6c8 90 * ==========================================================================
jvanhook 32:1e1e7730b6c8 91 */
jvanhook 32:1e1e7730b6c8 92
jvanhook 32:1e1e7730b6c8 93 /* Configuration of the Cortex-M3 Processor and Core Peripherals */
jvanhook 32:1e1e7730b6c8 94 #define __MPU_PRESENT 1 /*!< MPU present or not */
jvanhook 32:1e1e7730b6c8 95 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
jvanhook 32:1e1e7730b6c8 96 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
jvanhook 32:1e1e7730b6c8 97
jvanhook 32:1e1e7730b6c8 98
jvanhook 32:1e1e7730b6c8 99 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
jvanhook 32:1e1e7730b6c8 100 #include "system_LPC17xx.h" /* System Header */
jvanhook 32:1e1e7730b6c8 101
jvanhook 32:1e1e7730b6c8 102
jvanhook 32:1e1e7730b6c8 103 /******************************************************************************/
jvanhook 32:1e1e7730b6c8 104 /* Device Specific Peripheral registers structures */
jvanhook 32:1e1e7730b6c8 105 /******************************************************************************/
jvanhook 32:1e1e7730b6c8 106
jvanhook 32:1e1e7730b6c8 107 #if defined ( __CC_ARM )
jvanhook 32:1e1e7730b6c8 108 #pragma anon_unions
jvanhook 32:1e1e7730b6c8 109 #endif
jvanhook 32:1e1e7730b6c8 110
jvanhook 32:1e1e7730b6c8 111 /*------------- System Control (SC) ------------------------------------------*/
jvanhook 32:1e1e7730b6c8 112 typedef struct
jvanhook 32:1e1e7730b6c8 113 {
jvanhook 32:1e1e7730b6c8 114 __IO uint32_t FLASHCFG; /* Flash Accelerator Module */
jvanhook 32:1e1e7730b6c8 115 uint32_t RESERVED0[31];
jvanhook 32:1e1e7730b6c8 116 __IO uint32_t PLL0CON; /* Clocking and Power Control */
jvanhook 32:1e1e7730b6c8 117 __IO uint32_t PLL0CFG;
jvanhook 32:1e1e7730b6c8 118 __I uint32_t PLL0STAT;
jvanhook 32:1e1e7730b6c8 119 __O uint32_t PLL0FEED;
jvanhook 32:1e1e7730b6c8 120 uint32_t RESERVED1[4];
jvanhook 32:1e1e7730b6c8 121 __IO uint32_t PLL1CON;
jvanhook 32:1e1e7730b6c8 122 __IO uint32_t PLL1CFG;
jvanhook 32:1e1e7730b6c8 123 __I uint32_t PLL1STAT;
jvanhook 32:1e1e7730b6c8 124 __O uint32_t PLL1FEED;
jvanhook 32:1e1e7730b6c8 125 uint32_t RESERVED2[4];
jvanhook 32:1e1e7730b6c8 126 __IO uint32_t PCON;
jvanhook 32:1e1e7730b6c8 127 __IO uint32_t PCONP;
jvanhook 32:1e1e7730b6c8 128 uint32_t RESERVED3[15];
jvanhook 32:1e1e7730b6c8 129 __IO uint32_t CCLKCFG;
jvanhook 32:1e1e7730b6c8 130 __IO uint32_t USBCLKCFG;
jvanhook 32:1e1e7730b6c8 131 __IO uint32_t CLKSRCSEL;
jvanhook 32:1e1e7730b6c8 132 __IO uint32_t CANSLEEPCLR;
jvanhook 32:1e1e7730b6c8 133 __IO uint32_t CANWAKEFLAGS;
jvanhook 32:1e1e7730b6c8 134 uint32_t RESERVED4[10];
jvanhook 32:1e1e7730b6c8 135 __IO uint32_t EXTINT; /* External Interrupts */
jvanhook 32:1e1e7730b6c8 136 uint32_t RESERVED5;
jvanhook 32:1e1e7730b6c8 137 __IO uint32_t EXTMODE;
jvanhook 32:1e1e7730b6c8 138 __IO uint32_t EXTPOLAR;
jvanhook 32:1e1e7730b6c8 139 uint32_t RESERVED6[12];
jvanhook 32:1e1e7730b6c8 140 __IO uint32_t RSID; /* Reset */
jvanhook 32:1e1e7730b6c8 141 uint32_t RESERVED7[7];
jvanhook 32:1e1e7730b6c8 142 __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
jvanhook 32:1e1e7730b6c8 143 __IO uint32_t IRCTRIM; /* Clock Dividers */
jvanhook 32:1e1e7730b6c8 144 __IO uint32_t PCLKSEL0;
jvanhook 32:1e1e7730b6c8 145 __IO uint32_t PCLKSEL1;
jvanhook 32:1e1e7730b6c8 146 uint32_t RESERVED8[4];
jvanhook 32:1e1e7730b6c8 147 __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
jvanhook 32:1e1e7730b6c8 148 __IO uint32_t DMAREQSEL;
jvanhook 32:1e1e7730b6c8 149 __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
jvanhook 32:1e1e7730b6c8 150 } LPC_SC_TypeDef;
jvanhook 32:1e1e7730b6c8 151
jvanhook 32:1e1e7730b6c8 152 /*------------- Pin Connect Block (PINCON) -----------------------------------*/
jvanhook 32:1e1e7730b6c8 153 typedef struct
jvanhook 32:1e1e7730b6c8 154 {
jvanhook 32:1e1e7730b6c8 155 __IO uint32_t PINSEL0;
jvanhook 32:1e1e7730b6c8 156 __IO uint32_t PINSEL1;
jvanhook 32:1e1e7730b6c8 157 __IO uint32_t PINSEL2;
jvanhook 32:1e1e7730b6c8 158 __IO uint32_t PINSEL3;
jvanhook 32:1e1e7730b6c8 159 __IO uint32_t PINSEL4;
jvanhook 32:1e1e7730b6c8 160 __IO uint32_t PINSEL5;
jvanhook 32:1e1e7730b6c8 161 __IO uint32_t PINSEL6;
jvanhook 32:1e1e7730b6c8 162 __IO uint32_t PINSEL7;
jvanhook 32:1e1e7730b6c8 163 __IO uint32_t PINSEL8;
jvanhook 32:1e1e7730b6c8 164 __IO uint32_t PINSEL9;
jvanhook 32:1e1e7730b6c8 165 __IO uint32_t PINSEL10;
jvanhook 32:1e1e7730b6c8 166 uint32_t RESERVED0[5];
jvanhook 32:1e1e7730b6c8 167 __IO uint32_t PINMODE0;
jvanhook 32:1e1e7730b6c8 168 __IO uint32_t PINMODE1;
jvanhook 32:1e1e7730b6c8 169 __IO uint32_t PINMODE2;
jvanhook 32:1e1e7730b6c8 170 __IO uint32_t PINMODE3;
jvanhook 32:1e1e7730b6c8 171 __IO uint32_t PINMODE4;
jvanhook 32:1e1e7730b6c8 172 __IO uint32_t PINMODE5;
jvanhook 32:1e1e7730b6c8 173 __IO uint32_t PINMODE6;
jvanhook 32:1e1e7730b6c8 174 __IO uint32_t PINMODE7;
jvanhook 32:1e1e7730b6c8 175 __IO uint32_t PINMODE8;
jvanhook 32:1e1e7730b6c8 176 __IO uint32_t PINMODE9;
jvanhook 32:1e1e7730b6c8 177 __IO uint32_t PINMODE_OD0;
jvanhook 32:1e1e7730b6c8 178 __IO uint32_t PINMODE_OD1;
jvanhook 32:1e1e7730b6c8 179 __IO uint32_t PINMODE_OD2;
jvanhook 32:1e1e7730b6c8 180 __IO uint32_t PINMODE_OD3;
jvanhook 32:1e1e7730b6c8 181 __IO uint32_t PINMODE_OD4;
jvanhook 32:1e1e7730b6c8 182 __IO uint32_t I2CPADCFG;
jvanhook 32:1e1e7730b6c8 183 } LPC_PINCON_TypeDef;
jvanhook 32:1e1e7730b6c8 184
jvanhook 32:1e1e7730b6c8 185 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
jvanhook 32:1e1e7730b6c8 186 typedef struct
jvanhook 32:1e1e7730b6c8 187 {
jvanhook 32:1e1e7730b6c8 188 union {
jvanhook 32:1e1e7730b6c8 189 __IO uint32_t FIODIR;
jvanhook 32:1e1e7730b6c8 190 struct {
jvanhook 32:1e1e7730b6c8 191 __IO uint16_t FIODIRL;
jvanhook 32:1e1e7730b6c8 192 __IO uint16_t FIODIRH;
jvanhook 32:1e1e7730b6c8 193 };
jvanhook 32:1e1e7730b6c8 194 struct {
jvanhook 32:1e1e7730b6c8 195 __IO uint8_t FIODIR0;
jvanhook 32:1e1e7730b6c8 196 __IO uint8_t FIODIR1;
jvanhook 32:1e1e7730b6c8 197 __IO uint8_t FIODIR2;
jvanhook 32:1e1e7730b6c8 198 __IO uint8_t FIODIR3;
jvanhook 32:1e1e7730b6c8 199 };
jvanhook 32:1e1e7730b6c8 200 };
jvanhook 32:1e1e7730b6c8 201 uint32_t RESERVED0[3];
jvanhook 32:1e1e7730b6c8 202 union {
jvanhook 32:1e1e7730b6c8 203 __IO uint32_t FIOMASK;
jvanhook 32:1e1e7730b6c8 204 struct {
jvanhook 32:1e1e7730b6c8 205 __IO uint16_t FIOMASKL;
jvanhook 32:1e1e7730b6c8 206 __IO uint16_t FIOMASKH;
jvanhook 32:1e1e7730b6c8 207 };
jvanhook 32:1e1e7730b6c8 208 struct {
jvanhook 32:1e1e7730b6c8 209 __IO uint8_t FIOMASK0;
jvanhook 32:1e1e7730b6c8 210 __IO uint8_t FIOMASK1;
jvanhook 32:1e1e7730b6c8 211 __IO uint8_t FIOMASK2;
jvanhook 32:1e1e7730b6c8 212 __IO uint8_t FIOMASK3;
jvanhook 32:1e1e7730b6c8 213 };
jvanhook 32:1e1e7730b6c8 214 };
jvanhook 32:1e1e7730b6c8 215 union {
jvanhook 32:1e1e7730b6c8 216 __IO uint32_t FIOPIN;
jvanhook 32:1e1e7730b6c8 217 struct {
jvanhook 32:1e1e7730b6c8 218 __IO uint16_t FIOPINL;
jvanhook 32:1e1e7730b6c8 219 __IO uint16_t FIOPINH;
jvanhook 32:1e1e7730b6c8 220 };
jvanhook 32:1e1e7730b6c8 221 struct {
jvanhook 32:1e1e7730b6c8 222 __IO uint8_t FIOPIN0;
jvanhook 32:1e1e7730b6c8 223 __IO uint8_t FIOPIN1;
jvanhook 32:1e1e7730b6c8 224 __IO uint8_t FIOPIN2;
jvanhook 32:1e1e7730b6c8 225 __IO uint8_t FIOPIN3;
jvanhook 32:1e1e7730b6c8 226 };
jvanhook 32:1e1e7730b6c8 227 };
jvanhook 32:1e1e7730b6c8 228 union {
jvanhook 32:1e1e7730b6c8 229 __IO uint32_t FIOSET;
jvanhook 32:1e1e7730b6c8 230 struct {
jvanhook 32:1e1e7730b6c8 231 __IO uint16_t FIOSETL;
jvanhook 32:1e1e7730b6c8 232 __IO uint16_t FIOSETH;
jvanhook 32:1e1e7730b6c8 233 };
jvanhook 32:1e1e7730b6c8 234 struct {
jvanhook 32:1e1e7730b6c8 235 __IO uint8_t FIOSET0;
jvanhook 32:1e1e7730b6c8 236 __IO uint8_t FIOSET1;
jvanhook 32:1e1e7730b6c8 237 __IO uint8_t FIOSET2;
jvanhook 32:1e1e7730b6c8 238 __IO uint8_t FIOSET3;
jvanhook 32:1e1e7730b6c8 239 };
jvanhook 32:1e1e7730b6c8 240 };
jvanhook 32:1e1e7730b6c8 241 union {
jvanhook 32:1e1e7730b6c8 242 __O uint32_t FIOCLR;
jvanhook 32:1e1e7730b6c8 243 struct {
jvanhook 32:1e1e7730b6c8 244 __O uint16_t FIOCLRL;
jvanhook 32:1e1e7730b6c8 245 __O uint16_t FIOCLRH;
jvanhook 32:1e1e7730b6c8 246 };
jvanhook 32:1e1e7730b6c8 247 struct {
jvanhook 32:1e1e7730b6c8 248 __O uint8_t FIOCLR0;
jvanhook 32:1e1e7730b6c8 249 __O uint8_t FIOCLR1;
jvanhook 32:1e1e7730b6c8 250 __O uint8_t FIOCLR2;
jvanhook 32:1e1e7730b6c8 251 __O uint8_t FIOCLR3;
jvanhook 32:1e1e7730b6c8 252 };
jvanhook 32:1e1e7730b6c8 253 };
jvanhook 32:1e1e7730b6c8 254 } LPC_GPIO_TypeDef;
jvanhook 32:1e1e7730b6c8 255
jvanhook 32:1e1e7730b6c8 256 typedef struct
jvanhook 32:1e1e7730b6c8 257 {
jvanhook 32:1e1e7730b6c8 258 __I uint32_t IntStatus;
jvanhook 32:1e1e7730b6c8 259 __I uint32_t IO0IntStatR;
jvanhook 32:1e1e7730b6c8 260 __I uint32_t IO0IntStatF;
jvanhook 32:1e1e7730b6c8 261 __O uint32_t IO0IntClr;
jvanhook 32:1e1e7730b6c8 262 __IO uint32_t IO0IntEnR;
jvanhook 32:1e1e7730b6c8 263 __IO uint32_t IO0IntEnF;
jvanhook 32:1e1e7730b6c8 264 uint32_t RESERVED0[3];
jvanhook 32:1e1e7730b6c8 265 __I uint32_t IO2IntStatR;
jvanhook 32:1e1e7730b6c8 266 __I uint32_t IO2IntStatF;
jvanhook 32:1e1e7730b6c8 267 __O uint32_t IO2IntClr;
jvanhook 32:1e1e7730b6c8 268 __IO uint32_t IO2IntEnR;
jvanhook 32:1e1e7730b6c8 269 __IO uint32_t IO2IntEnF;
jvanhook 32:1e1e7730b6c8 270 } LPC_GPIOINT_TypeDef;
jvanhook 32:1e1e7730b6c8 271
jvanhook 32:1e1e7730b6c8 272 /*------------- Timer (TIM) --------------------------------------------------*/
jvanhook 32:1e1e7730b6c8 273 typedef struct
jvanhook 32:1e1e7730b6c8 274 {
jvanhook 32:1e1e7730b6c8 275 __IO uint32_t IR;
jvanhook 32:1e1e7730b6c8 276 __IO uint32_t TCR;
jvanhook 32:1e1e7730b6c8 277 __IO uint32_t TC;
jvanhook 32:1e1e7730b6c8 278 __IO uint32_t PR;
jvanhook 32:1e1e7730b6c8 279 __IO uint32_t PC;
jvanhook 32:1e1e7730b6c8 280 __IO uint32_t MCR;
jvanhook 32:1e1e7730b6c8 281 __IO uint32_t MR0;
jvanhook 32:1e1e7730b6c8 282 __IO uint32_t MR1;
jvanhook 32:1e1e7730b6c8 283 __IO uint32_t MR2;
jvanhook 32:1e1e7730b6c8 284 __IO uint32_t MR3;
jvanhook 32:1e1e7730b6c8 285 __IO uint32_t CCR;
jvanhook 32:1e1e7730b6c8 286 __I uint32_t CR0;
jvanhook 32:1e1e7730b6c8 287 __I uint32_t CR1;
jvanhook 32:1e1e7730b6c8 288 uint32_t RESERVED0[2];
jvanhook 32:1e1e7730b6c8 289 __IO uint32_t EMR;
jvanhook 32:1e1e7730b6c8 290 uint32_t RESERVED1[12];
jvanhook 32:1e1e7730b6c8 291 __IO uint32_t CTCR;
jvanhook 32:1e1e7730b6c8 292 } LPC_TIM_TypeDef;
jvanhook 32:1e1e7730b6c8 293
jvanhook 32:1e1e7730b6c8 294 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
jvanhook 32:1e1e7730b6c8 295 typedef struct
jvanhook 32:1e1e7730b6c8 296 {
jvanhook 32:1e1e7730b6c8 297 __IO uint32_t IR;
jvanhook 32:1e1e7730b6c8 298 __IO uint32_t TCR;
jvanhook 32:1e1e7730b6c8 299 __IO uint32_t TC;
jvanhook 32:1e1e7730b6c8 300 __IO uint32_t PR;
jvanhook 32:1e1e7730b6c8 301 __IO uint32_t PC;
jvanhook 32:1e1e7730b6c8 302 __IO uint32_t MCR;
jvanhook 32:1e1e7730b6c8 303 __IO uint32_t MR0;
jvanhook 32:1e1e7730b6c8 304 __IO uint32_t MR1;
jvanhook 32:1e1e7730b6c8 305 __IO uint32_t MR2;
jvanhook 32:1e1e7730b6c8 306 __IO uint32_t MR3;
jvanhook 32:1e1e7730b6c8 307 __IO uint32_t CCR;
jvanhook 32:1e1e7730b6c8 308 __I uint32_t CR0;
jvanhook 32:1e1e7730b6c8 309 __I uint32_t CR1;
jvanhook 32:1e1e7730b6c8 310 __I uint32_t CR2;
jvanhook 32:1e1e7730b6c8 311 __I uint32_t CR3;
jvanhook 32:1e1e7730b6c8 312 uint32_t RESERVED0;
jvanhook 32:1e1e7730b6c8 313 __IO uint32_t MR4;
jvanhook 32:1e1e7730b6c8 314 __IO uint32_t MR5;
jvanhook 32:1e1e7730b6c8 315 __IO uint32_t MR6;
jvanhook 32:1e1e7730b6c8 316 __IO uint32_t PCR;
jvanhook 32:1e1e7730b6c8 317 __IO uint32_t LER;
jvanhook 32:1e1e7730b6c8 318 uint32_t RESERVED1[7];
jvanhook 32:1e1e7730b6c8 319 __IO uint32_t CTCR;
jvanhook 32:1e1e7730b6c8 320 } LPC_PWM_TypeDef;
jvanhook 32:1e1e7730b6c8 321
jvanhook 32:1e1e7730b6c8 322 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
jvanhook 32:1e1e7730b6c8 323 typedef struct
jvanhook 32:1e1e7730b6c8 324 {
jvanhook 32:1e1e7730b6c8 325 union {
jvanhook 32:1e1e7730b6c8 326 __I uint8_t RBR;
jvanhook 32:1e1e7730b6c8 327 __O uint8_t THR;
jvanhook 32:1e1e7730b6c8 328 __IO uint8_t DLL;
jvanhook 32:1e1e7730b6c8 329 uint32_t RESERVED0;
jvanhook 32:1e1e7730b6c8 330 };
jvanhook 32:1e1e7730b6c8 331 union {
jvanhook 32:1e1e7730b6c8 332 __IO uint8_t DLM;
jvanhook 32:1e1e7730b6c8 333 __IO uint32_t IER;
jvanhook 32:1e1e7730b6c8 334 };
jvanhook 32:1e1e7730b6c8 335 union {
jvanhook 32:1e1e7730b6c8 336 __I uint32_t IIR;
jvanhook 32:1e1e7730b6c8 337 __O uint8_t FCR;
jvanhook 32:1e1e7730b6c8 338 };
jvanhook 32:1e1e7730b6c8 339 __IO uint8_t LCR;
jvanhook 32:1e1e7730b6c8 340 uint8_t RESERVED1[7];
jvanhook 32:1e1e7730b6c8 341 __I uint8_t LSR;
jvanhook 32:1e1e7730b6c8 342 uint8_t RESERVED2[7];
jvanhook 32:1e1e7730b6c8 343 __IO uint8_t SCR;
jvanhook 32:1e1e7730b6c8 344 uint8_t RESERVED3[3];
jvanhook 32:1e1e7730b6c8 345 __IO uint32_t ACR;
jvanhook 32:1e1e7730b6c8 346 __IO uint8_t ICR;
jvanhook 32:1e1e7730b6c8 347 uint8_t RESERVED4[3];
jvanhook 32:1e1e7730b6c8 348 __IO uint8_t FDR;
jvanhook 32:1e1e7730b6c8 349 uint8_t RESERVED5[7];
jvanhook 32:1e1e7730b6c8 350 __IO uint8_t TER;
jvanhook 32:1e1e7730b6c8 351 uint8_t RESERVED6[39];
jvanhook 32:1e1e7730b6c8 352 __IO uint32_t FIFOLVL;
jvanhook 32:1e1e7730b6c8 353 } LPC_UART_TypeDef;
jvanhook 32:1e1e7730b6c8 354
jvanhook 32:1e1e7730b6c8 355 typedef struct
jvanhook 32:1e1e7730b6c8 356 {
jvanhook 32:1e1e7730b6c8 357 union {
jvanhook 32:1e1e7730b6c8 358 __I uint8_t RBR;
jvanhook 32:1e1e7730b6c8 359 __O uint8_t THR;
jvanhook 32:1e1e7730b6c8 360 __IO uint8_t DLL;
jvanhook 32:1e1e7730b6c8 361 uint32_t RESERVED0;
jvanhook 32:1e1e7730b6c8 362 };
jvanhook 32:1e1e7730b6c8 363 union {
jvanhook 32:1e1e7730b6c8 364 __IO uint8_t DLM;
jvanhook 32:1e1e7730b6c8 365 __IO uint32_t IER;
jvanhook 32:1e1e7730b6c8 366 };
jvanhook 32:1e1e7730b6c8 367 union {
jvanhook 32:1e1e7730b6c8 368 __I uint32_t IIR;
jvanhook 32:1e1e7730b6c8 369 __O uint8_t FCR;
jvanhook 32:1e1e7730b6c8 370 };
jvanhook 32:1e1e7730b6c8 371 __IO uint8_t LCR;
jvanhook 32:1e1e7730b6c8 372 uint8_t RESERVED1[7];
jvanhook 32:1e1e7730b6c8 373 __I uint8_t LSR;
jvanhook 32:1e1e7730b6c8 374 uint8_t RESERVED2[7];
jvanhook 32:1e1e7730b6c8 375 __IO uint8_t SCR;
jvanhook 32:1e1e7730b6c8 376 uint8_t RESERVED3[3];
jvanhook 32:1e1e7730b6c8 377 __IO uint32_t ACR;
jvanhook 32:1e1e7730b6c8 378 __IO uint8_t ICR;
jvanhook 32:1e1e7730b6c8 379 uint8_t RESERVED4[3];
jvanhook 32:1e1e7730b6c8 380 __IO uint8_t FDR;
jvanhook 32:1e1e7730b6c8 381 uint8_t RESERVED5[7];
jvanhook 32:1e1e7730b6c8 382 __IO uint8_t TER;
jvanhook 32:1e1e7730b6c8 383 uint8_t RESERVED6[39];
jvanhook 32:1e1e7730b6c8 384 __IO uint32_t FIFOLVL;
jvanhook 32:1e1e7730b6c8 385 } LPC_UART0_TypeDef;
jvanhook 32:1e1e7730b6c8 386
jvanhook 32:1e1e7730b6c8 387 typedef struct
jvanhook 32:1e1e7730b6c8 388 {
jvanhook 32:1e1e7730b6c8 389 union {
jvanhook 32:1e1e7730b6c8 390 __I uint8_t RBR;
jvanhook 32:1e1e7730b6c8 391 __O uint8_t THR;
jvanhook 32:1e1e7730b6c8 392 __IO uint8_t DLL;
jvanhook 32:1e1e7730b6c8 393 uint32_t RESERVED0;
jvanhook 32:1e1e7730b6c8 394 };
jvanhook 32:1e1e7730b6c8 395 union {
jvanhook 32:1e1e7730b6c8 396 __IO uint8_t DLM;
jvanhook 32:1e1e7730b6c8 397 __IO uint32_t IER;
jvanhook 32:1e1e7730b6c8 398 };
jvanhook 32:1e1e7730b6c8 399 union {
jvanhook 32:1e1e7730b6c8 400 __I uint32_t IIR;
jvanhook 32:1e1e7730b6c8 401 __O uint8_t FCR;
jvanhook 32:1e1e7730b6c8 402 };
jvanhook 32:1e1e7730b6c8 403 __IO uint8_t LCR;
jvanhook 32:1e1e7730b6c8 404 uint8_t RESERVED1[3];
jvanhook 32:1e1e7730b6c8 405 __IO uint8_t MCR;
jvanhook 32:1e1e7730b6c8 406 uint8_t RESERVED2[3];
jvanhook 32:1e1e7730b6c8 407 __I uint8_t LSR;
jvanhook 32:1e1e7730b6c8 408 uint8_t RESERVED3[3];
jvanhook 32:1e1e7730b6c8 409 __I uint8_t MSR;
jvanhook 32:1e1e7730b6c8 410 uint8_t RESERVED4[3];
jvanhook 32:1e1e7730b6c8 411 __IO uint8_t SCR;
jvanhook 32:1e1e7730b6c8 412 uint8_t RESERVED5[3];
jvanhook 32:1e1e7730b6c8 413 __IO uint32_t ACR;
jvanhook 32:1e1e7730b6c8 414 uint32_t RESERVED6;
jvanhook 32:1e1e7730b6c8 415 __IO uint32_t FDR;
jvanhook 32:1e1e7730b6c8 416 uint32_t RESERVED7;
jvanhook 32:1e1e7730b6c8 417 __IO uint8_t TER;
jvanhook 32:1e1e7730b6c8 418 uint8_t RESERVED8[27];
jvanhook 32:1e1e7730b6c8 419 __IO uint8_t RS485CTRL;
jvanhook 32:1e1e7730b6c8 420 uint8_t RESERVED9[3];
jvanhook 32:1e1e7730b6c8 421 __IO uint8_t ADRMATCH;
jvanhook 32:1e1e7730b6c8 422 uint8_t RESERVED10[3];
jvanhook 32:1e1e7730b6c8 423 __IO uint8_t RS485DLY;
jvanhook 32:1e1e7730b6c8 424 uint8_t RESERVED11[3];
jvanhook 32:1e1e7730b6c8 425 __IO uint32_t FIFOLVL;
jvanhook 32:1e1e7730b6c8 426 } LPC_UART1_TypeDef;
jvanhook 32:1e1e7730b6c8 427
jvanhook 32:1e1e7730b6c8 428 /*------------- Serial Peripheral Interface (SPI) ----------------------------*/
jvanhook 32:1e1e7730b6c8 429 typedef struct
jvanhook 32:1e1e7730b6c8 430 {
jvanhook 32:1e1e7730b6c8 431 __IO uint32_t SPCR;
jvanhook 32:1e1e7730b6c8 432 __I uint32_t SPSR;
jvanhook 32:1e1e7730b6c8 433 __IO uint32_t SPDR;
jvanhook 32:1e1e7730b6c8 434 __IO uint32_t SPCCR;
jvanhook 32:1e1e7730b6c8 435 uint32_t RESERVED0[3];
jvanhook 32:1e1e7730b6c8 436 __IO uint32_t SPINT;
jvanhook 32:1e1e7730b6c8 437 } LPC_SPI_TypeDef;
jvanhook 32:1e1e7730b6c8 438
jvanhook 32:1e1e7730b6c8 439 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
jvanhook 32:1e1e7730b6c8 440 typedef struct
jvanhook 32:1e1e7730b6c8 441 {
jvanhook 32:1e1e7730b6c8 442 __IO uint32_t CR0;
jvanhook 32:1e1e7730b6c8 443 __IO uint32_t CR1;
jvanhook 32:1e1e7730b6c8 444 __IO uint32_t DR;
jvanhook 32:1e1e7730b6c8 445 __I uint32_t SR;
jvanhook 32:1e1e7730b6c8 446 __IO uint32_t CPSR;
jvanhook 32:1e1e7730b6c8 447 __IO uint32_t IMSC;
jvanhook 32:1e1e7730b6c8 448 __IO uint32_t RIS;
jvanhook 32:1e1e7730b6c8 449 __IO uint32_t MIS;
jvanhook 32:1e1e7730b6c8 450 __IO uint32_t ICR;
jvanhook 32:1e1e7730b6c8 451 __IO uint32_t DMACR;
jvanhook 32:1e1e7730b6c8 452 } LPC_SSP_TypeDef;
jvanhook 32:1e1e7730b6c8 453
jvanhook 32:1e1e7730b6c8 454 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
jvanhook 32:1e1e7730b6c8 455 typedef struct
jvanhook 32:1e1e7730b6c8 456 {
jvanhook 32:1e1e7730b6c8 457 __IO uint32_t I2CONSET;
jvanhook 32:1e1e7730b6c8 458 __I uint32_t I2STAT;
jvanhook 32:1e1e7730b6c8 459 __IO uint32_t I2DAT;
jvanhook 32:1e1e7730b6c8 460 __IO uint32_t I2ADR0;
jvanhook 32:1e1e7730b6c8 461 __IO uint32_t I2SCLH;
jvanhook 32:1e1e7730b6c8 462 __IO uint32_t I2SCLL;
jvanhook 32:1e1e7730b6c8 463 __O uint32_t I2CONCLR;
jvanhook 32:1e1e7730b6c8 464 __IO uint32_t MMCTRL;
jvanhook 32:1e1e7730b6c8 465 __IO uint32_t I2ADR1;
jvanhook 32:1e1e7730b6c8 466 __IO uint32_t I2ADR2;
jvanhook 32:1e1e7730b6c8 467 __IO uint32_t I2ADR3;
jvanhook 32:1e1e7730b6c8 468 __I uint32_t I2DATA_BUFFER;
jvanhook 32:1e1e7730b6c8 469 __IO uint32_t I2MASK0;
jvanhook 32:1e1e7730b6c8 470 __IO uint32_t I2MASK1;
jvanhook 32:1e1e7730b6c8 471 __IO uint32_t I2MASK2;
jvanhook 32:1e1e7730b6c8 472 __IO uint32_t I2MASK3;
jvanhook 32:1e1e7730b6c8 473 } LPC_I2C_TypeDef;
jvanhook 32:1e1e7730b6c8 474
jvanhook 32:1e1e7730b6c8 475 /*------------- Inter IC Sound (I2S) -----------------------------------------*/
jvanhook 32:1e1e7730b6c8 476 typedef struct
jvanhook 32:1e1e7730b6c8 477 {
jvanhook 32:1e1e7730b6c8 478 __IO uint32_t I2SDAO;
jvanhook 32:1e1e7730b6c8 479 __IO uint32_t I2SDAI;
jvanhook 32:1e1e7730b6c8 480 __O uint32_t I2STXFIFO;
jvanhook 32:1e1e7730b6c8 481 __I uint32_t I2SRXFIFO;
jvanhook 32:1e1e7730b6c8 482 __I uint32_t I2SSTATE;
jvanhook 32:1e1e7730b6c8 483 __IO uint32_t I2SDMA1;
jvanhook 32:1e1e7730b6c8 484 __IO uint32_t I2SDMA2;
jvanhook 32:1e1e7730b6c8 485 __IO uint32_t I2SIRQ;
jvanhook 32:1e1e7730b6c8 486 __IO uint32_t I2STXRATE;
jvanhook 32:1e1e7730b6c8 487 __IO uint32_t I2SRXRATE;
jvanhook 32:1e1e7730b6c8 488 __IO uint32_t I2STXBITRATE;
jvanhook 32:1e1e7730b6c8 489 __IO uint32_t I2SRXBITRATE;
jvanhook 32:1e1e7730b6c8 490 __IO uint32_t I2STXMODE;
jvanhook 32:1e1e7730b6c8 491 __IO uint32_t I2SRXMODE;
jvanhook 32:1e1e7730b6c8 492 } LPC_I2S_TypeDef;
jvanhook 32:1e1e7730b6c8 493
jvanhook 32:1e1e7730b6c8 494 /*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
jvanhook 32:1e1e7730b6c8 495 typedef struct
jvanhook 32:1e1e7730b6c8 496 {
jvanhook 32:1e1e7730b6c8 497 __IO uint32_t RICOMPVAL;
jvanhook 32:1e1e7730b6c8 498 __IO uint32_t RIMASK;
jvanhook 32:1e1e7730b6c8 499 __IO uint8_t RICTRL;
jvanhook 32:1e1e7730b6c8 500 uint8_t RESERVED0[3];
jvanhook 32:1e1e7730b6c8 501 __IO uint32_t RICOUNTER;
jvanhook 32:1e1e7730b6c8 502 } LPC_RIT_TypeDef;
jvanhook 32:1e1e7730b6c8 503
jvanhook 32:1e1e7730b6c8 504 /*------------- Real-Time Clock (RTC) ----------------------------------------*/
jvanhook 32:1e1e7730b6c8 505 typedef struct
jvanhook 32:1e1e7730b6c8 506 {
jvanhook 32:1e1e7730b6c8 507 __IO uint8_t ILR;
jvanhook 32:1e1e7730b6c8 508 uint8_t RESERVED0[7];
jvanhook 32:1e1e7730b6c8 509 __IO uint8_t CCR;
jvanhook 32:1e1e7730b6c8 510 uint8_t RESERVED1[3];
jvanhook 32:1e1e7730b6c8 511 __IO uint8_t CIIR;
jvanhook 32:1e1e7730b6c8 512 uint8_t RESERVED2[3];
jvanhook 32:1e1e7730b6c8 513 __IO uint8_t AMR;
jvanhook 32:1e1e7730b6c8 514 uint8_t RESERVED3[3];
jvanhook 32:1e1e7730b6c8 515 __I uint32_t CTIME0;
jvanhook 32:1e1e7730b6c8 516 __I uint32_t CTIME1;
jvanhook 32:1e1e7730b6c8 517 __I uint32_t CTIME2;
jvanhook 32:1e1e7730b6c8 518 __IO uint8_t SEC;
jvanhook 32:1e1e7730b6c8 519 uint8_t RESERVED4[3];
jvanhook 32:1e1e7730b6c8 520 __IO uint8_t MIN;
jvanhook 32:1e1e7730b6c8 521 uint8_t RESERVED5[3];
jvanhook 32:1e1e7730b6c8 522 __IO uint8_t HOUR;
jvanhook 32:1e1e7730b6c8 523 uint8_t RESERVED6[3];
jvanhook 32:1e1e7730b6c8 524 __IO uint8_t DOM;
jvanhook 32:1e1e7730b6c8 525 uint8_t RESERVED7[3];
jvanhook 32:1e1e7730b6c8 526 __IO uint8_t DOW;
jvanhook 32:1e1e7730b6c8 527 uint8_t RESERVED8[3];
jvanhook 32:1e1e7730b6c8 528 __IO uint16_t DOY;
jvanhook 32:1e1e7730b6c8 529 uint16_t RESERVED9;
jvanhook 32:1e1e7730b6c8 530 __IO uint8_t MONTH;
jvanhook 32:1e1e7730b6c8 531 uint8_t RESERVED10[3];
jvanhook 32:1e1e7730b6c8 532 __IO uint16_t YEAR;
jvanhook 32:1e1e7730b6c8 533 uint16_t RESERVED11;
jvanhook 32:1e1e7730b6c8 534 __IO uint32_t CALIBRATION;
jvanhook 32:1e1e7730b6c8 535 __IO uint32_t GPREG0;
jvanhook 32:1e1e7730b6c8 536 __IO uint32_t GPREG1;
jvanhook 32:1e1e7730b6c8 537 __IO uint32_t GPREG2;
jvanhook 32:1e1e7730b6c8 538 __IO uint32_t GPREG3;
jvanhook 32:1e1e7730b6c8 539 __IO uint32_t GPREG4;
jvanhook 32:1e1e7730b6c8 540 __IO uint8_t RTC_AUXEN;
jvanhook 32:1e1e7730b6c8 541 uint8_t RESERVED12[3];
jvanhook 32:1e1e7730b6c8 542 __IO uint8_t RTC_AUX;
jvanhook 32:1e1e7730b6c8 543 uint8_t RESERVED13[3];
jvanhook 32:1e1e7730b6c8 544 __IO uint8_t ALSEC;
jvanhook 32:1e1e7730b6c8 545 uint8_t RESERVED14[3];
jvanhook 32:1e1e7730b6c8 546 __IO uint8_t ALMIN;
jvanhook 32:1e1e7730b6c8 547 uint8_t RESERVED15[3];
jvanhook 32:1e1e7730b6c8 548 __IO uint8_t ALHOUR;
jvanhook 32:1e1e7730b6c8 549 uint8_t RESERVED16[3];
jvanhook 32:1e1e7730b6c8 550 __IO uint8_t ALDOM;
jvanhook 32:1e1e7730b6c8 551 uint8_t RESERVED17[3];
jvanhook 32:1e1e7730b6c8 552 __IO uint8_t ALDOW;
jvanhook 32:1e1e7730b6c8 553 uint8_t RESERVED18[3];
jvanhook 32:1e1e7730b6c8 554 __IO uint16_t ALDOY;
jvanhook 32:1e1e7730b6c8 555 uint16_t RESERVED19;
jvanhook 32:1e1e7730b6c8 556 __IO uint8_t ALMON;
jvanhook 32:1e1e7730b6c8 557 uint8_t RESERVED20[3];
jvanhook 32:1e1e7730b6c8 558 __IO uint16_t ALYEAR;
jvanhook 32:1e1e7730b6c8 559 uint16_t RESERVED21;
jvanhook 32:1e1e7730b6c8 560 } LPC_RTC_TypeDef;
jvanhook 32:1e1e7730b6c8 561
jvanhook 32:1e1e7730b6c8 562 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
jvanhook 32:1e1e7730b6c8 563 typedef struct
jvanhook 32:1e1e7730b6c8 564 {
jvanhook 32:1e1e7730b6c8 565 __IO uint8_t WDMOD;
jvanhook 32:1e1e7730b6c8 566 uint8_t RESERVED0[3];
jvanhook 32:1e1e7730b6c8 567 __IO uint32_t WDTC;
jvanhook 32:1e1e7730b6c8 568 __O uint8_t WDFEED;
jvanhook 32:1e1e7730b6c8 569 uint8_t RESERVED1[3];
jvanhook 32:1e1e7730b6c8 570 __I uint32_t WDTV;
jvanhook 32:1e1e7730b6c8 571 __IO uint32_t WDCLKSEL;
jvanhook 32:1e1e7730b6c8 572 } LPC_WDT_TypeDef;
jvanhook 32:1e1e7730b6c8 573
jvanhook 32:1e1e7730b6c8 574 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
jvanhook 32:1e1e7730b6c8 575 typedef struct
jvanhook 32:1e1e7730b6c8 576 {
jvanhook 32:1e1e7730b6c8 577 __IO uint32_t ADCR;
jvanhook 32:1e1e7730b6c8 578 __IO uint32_t ADGDR;
jvanhook 32:1e1e7730b6c8 579 uint32_t RESERVED0;
jvanhook 32:1e1e7730b6c8 580 __IO uint32_t ADINTEN;
jvanhook 32:1e1e7730b6c8 581 __I uint32_t ADDR0;
jvanhook 32:1e1e7730b6c8 582 __I uint32_t ADDR1;
jvanhook 32:1e1e7730b6c8 583 __I uint32_t ADDR2;
jvanhook 32:1e1e7730b6c8 584 __I uint32_t ADDR3;
jvanhook 32:1e1e7730b6c8 585 __I uint32_t ADDR4;
jvanhook 32:1e1e7730b6c8 586 __I uint32_t ADDR5;
jvanhook 32:1e1e7730b6c8 587 __I uint32_t ADDR6;
jvanhook 32:1e1e7730b6c8 588 __I uint32_t ADDR7;
jvanhook 32:1e1e7730b6c8 589 __I uint32_t ADSTAT;
jvanhook 32:1e1e7730b6c8 590 __IO uint32_t ADTRM;
jvanhook 32:1e1e7730b6c8 591 } LPC_ADC_TypeDef;
jvanhook 32:1e1e7730b6c8 592
jvanhook 32:1e1e7730b6c8 593 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
jvanhook 32:1e1e7730b6c8 594 typedef struct
jvanhook 32:1e1e7730b6c8 595 {
jvanhook 32:1e1e7730b6c8 596 __IO uint32_t DACR;
jvanhook 32:1e1e7730b6c8 597 __IO uint32_t DACCTRL;
jvanhook 32:1e1e7730b6c8 598 __IO uint16_t DACCNTVAL;
jvanhook 32:1e1e7730b6c8 599 } LPC_DAC_TypeDef;
jvanhook 32:1e1e7730b6c8 600
jvanhook 32:1e1e7730b6c8 601 /*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
jvanhook 32:1e1e7730b6c8 602 typedef struct
jvanhook 32:1e1e7730b6c8 603 {
jvanhook 32:1e1e7730b6c8 604 __I uint32_t MCCON;
jvanhook 32:1e1e7730b6c8 605 __O uint32_t MCCON_SET;
jvanhook 32:1e1e7730b6c8 606 __O uint32_t MCCON_CLR;
jvanhook 32:1e1e7730b6c8 607 __I uint32_t MCCAPCON;
jvanhook 32:1e1e7730b6c8 608 __O uint32_t MCCAPCON_SET;
jvanhook 32:1e1e7730b6c8 609 __O uint32_t MCCAPCON_CLR;
jvanhook 32:1e1e7730b6c8 610 __IO uint32_t MCTIM0;
jvanhook 32:1e1e7730b6c8 611 __IO uint32_t MCTIM1;
jvanhook 32:1e1e7730b6c8 612 __IO uint32_t MCTIM2;
jvanhook 32:1e1e7730b6c8 613 __IO uint32_t MCPER0;
jvanhook 32:1e1e7730b6c8 614 __IO uint32_t MCPER1;
jvanhook 32:1e1e7730b6c8 615 __IO uint32_t MCPER2;
jvanhook 32:1e1e7730b6c8 616 __IO uint32_t MCPW0;
jvanhook 32:1e1e7730b6c8 617 __IO uint32_t MCPW1;
jvanhook 32:1e1e7730b6c8 618 __IO uint32_t MCPW2;
jvanhook 32:1e1e7730b6c8 619 __IO uint32_t MCDEADTIME;
jvanhook 32:1e1e7730b6c8 620 __IO uint32_t MCCCP;
jvanhook 32:1e1e7730b6c8 621 __IO uint32_t MCCR0;
jvanhook 32:1e1e7730b6c8 622 __IO uint32_t MCCR1;
jvanhook 32:1e1e7730b6c8 623 __IO uint32_t MCCR2;
jvanhook 32:1e1e7730b6c8 624 __I uint32_t MCINTEN;
jvanhook 32:1e1e7730b6c8 625 __O uint32_t MCINTEN_SET;
jvanhook 32:1e1e7730b6c8 626 __O uint32_t MCINTEN_CLR;
jvanhook 32:1e1e7730b6c8 627 __I uint32_t MCCNTCON;
jvanhook 32:1e1e7730b6c8 628 __O uint32_t MCCNTCON_SET;
jvanhook 32:1e1e7730b6c8 629 __O uint32_t MCCNTCON_CLR;
jvanhook 32:1e1e7730b6c8 630 __I uint32_t MCINTFLAG;
jvanhook 32:1e1e7730b6c8 631 __O uint32_t MCINTFLAG_SET;
jvanhook 32:1e1e7730b6c8 632 __O uint32_t MCINTFLAG_CLR;
jvanhook 32:1e1e7730b6c8 633 __O uint32_t MCCAP_CLR;
jvanhook 32:1e1e7730b6c8 634 } LPC_MCPWM_TypeDef;
jvanhook 32:1e1e7730b6c8 635
jvanhook 32:1e1e7730b6c8 636 /*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
jvanhook 32:1e1e7730b6c8 637 typedef struct
jvanhook 32:1e1e7730b6c8 638 {
jvanhook 32:1e1e7730b6c8 639 __O uint32_t QEICON;
jvanhook 32:1e1e7730b6c8 640 __I uint32_t QEISTAT;
jvanhook 32:1e1e7730b6c8 641 __IO uint32_t QEICONF;
jvanhook 32:1e1e7730b6c8 642 __I uint32_t QEIPOS;
jvanhook 32:1e1e7730b6c8 643 __IO uint32_t QEIMAXPOS;
jvanhook 32:1e1e7730b6c8 644 __IO uint32_t CMPOS0;
jvanhook 32:1e1e7730b6c8 645 __IO uint32_t CMPOS1;
jvanhook 32:1e1e7730b6c8 646 __IO uint32_t CMPOS2;
jvanhook 32:1e1e7730b6c8 647 __I uint32_t INXCNT;
jvanhook 32:1e1e7730b6c8 648 __IO uint32_t INXCMP;
jvanhook 32:1e1e7730b6c8 649 __IO uint32_t QEILOAD;
jvanhook 32:1e1e7730b6c8 650 __I uint32_t QEITIME;
jvanhook 32:1e1e7730b6c8 651 __I uint32_t QEIVEL;
jvanhook 32:1e1e7730b6c8 652 __I uint32_t QEICAP;
jvanhook 32:1e1e7730b6c8 653 __IO uint32_t VELCOMP;
jvanhook 32:1e1e7730b6c8 654 __IO uint32_t FILTER;
jvanhook 32:1e1e7730b6c8 655 uint32_t RESERVED0[998];
jvanhook 32:1e1e7730b6c8 656 __O uint32_t QEIIEC;
jvanhook 32:1e1e7730b6c8 657 __O uint32_t QEIIES;
jvanhook 32:1e1e7730b6c8 658 __I uint32_t QEIINTSTAT;
jvanhook 32:1e1e7730b6c8 659 __I uint32_t QEIIE;
jvanhook 32:1e1e7730b6c8 660 __O uint32_t QEICLR;
jvanhook 32:1e1e7730b6c8 661 __O uint32_t QEISET;
jvanhook 32:1e1e7730b6c8 662 } LPC_QEI_TypeDef;
jvanhook 32:1e1e7730b6c8 663
jvanhook 32:1e1e7730b6c8 664 /*------------- Controller Area Network (CAN) --------------------------------*/
jvanhook 32:1e1e7730b6c8 665 typedef struct
jvanhook 32:1e1e7730b6c8 666 {
jvanhook 32:1e1e7730b6c8 667 __IO uint32_t mask[512]; /* ID Masks */
jvanhook 32:1e1e7730b6c8 668 } LPC_CANAF_RAM_TypeDef;
jvanhook 32:1e1e7730b6c8 669
jvanhook 32:1e1e7730b6c8 670 typedef struct /* Acceptance Filter Registers */
jvanhook 32:1e1e7730b6c8 671 {
jvanhook 32:1e1e7730b6c8 672 __IO uint32_t AFMR;
jvanhook 32:1e1e7730b6c8 673 __IO uint32_t SFF_sa;
jvanhook 32:1e1e7730b6c8 674 __IO uint32_t SFF_GRP_sa;
jvanhook 32:1e1e7730b6c8 675 __IO uint32_t EFF_sa;
jvanhook 32:1e1e7730b6c8 676 __IO uint32_t EFF_GRP_sa;
jvanhook 32:1e1e7730b6c8 677 __IO uint32_t ENDofTable;
jvanhook 32:1e1e7730b6c8 678 __I uint32_t LUTerrAd;
jvanhook 32:1e1e7730b6c8 679 __I uint32_t LUTerr;
jvanhook 32:1e1e7730b6c8 680 __IO uint32_t FCANIE;
jvanhook 32:1e1e7730b6c8 681 __IO uint32_t FCANIC0;
jvanhook 32:1e1e7730b6c8 682 __IO uint32_t FCANIC1;
jvanhook 32:1e1e7730b6c8 683 } LPC_CANAF_TypeDef;
jvanhook 32:1e1e7730b6c8 684
jvanhook 32:1e1e7730b6c8 685 typedef struct /* Central Registers */
jvanhook 32:1e1e7730b6c8 686 {
jvanhook 32:1e1e7730b6c8 687 __I uint32_t CANTxSR;
jvanhook 32:1e1e7730b6c8 688 __I uint32_t CANRxSR;
jvanhook 32:1e1e7730b6c8 689 __I uint32_t CANMSR;
jvanhook 32:1e1e7730b6c8 690 } LPC_CANCR_TypeDef;
jvanhook 32:1e1e7730b6c8 691
jvanhook 32:1e1e7730b6c8 692 typedef struct /* Controller Registers */
jvanhook 32:1e1e7730b6c8 693 {
jvanhook 32:1e1e7730b6c8 694 __IO uint32_t MOD;
jvanhook 32:1e1e7730b6c8 695 __O uint32_t CMR;
jvanhook 32:1e1e7730b6c8 696 __IO uint32_t GSR;
jvanhook 32:1e1e7730b6c8 697 __I uint32_t ICR;
jvanhook 32:1e1e7730b6c8 698 __IO uint32_t IER;
jvanhook 32:1e1e7730b6c8 699 __IO uint32_t BTR;
jvanhook 32:1e1e7730b6c8 700 __IO uint32_t EWL;
jvanhook 32:1e1e7730b6c8 701 __I uint32_t SR;
jvanhook 32:1e1e7730b6c8 702 __IO uint32_t RFS;
jvanhook 32:1e1e7730b6c8 703 __IO uint32_t RID;
jvanhook 32:1e1e7730b6c8 704 __IO uint32_t RDA;
jvanhook 32:1e1e7730b6c8 705 __IO uint32_t RDB;
jvanhook 32:1e1e7730b6c8 706 __IO uint32_t TFI1;
jvanhook 32:1e1e7730b6c8 707 __IO uint32_t TID1;
jvanhook 32:1e1e7730b6c8 708 __IO uint32_t TDA1;
jvanhook 32:1e1e7730b6c8 709 __IO uint32_t TDB1;
jvanhook 32:1e1e7730b6c8 710 __IO uint32_t TFI2;
jvanhook 32:1e1e7730b6c8 711 __IO uint32_t TID2;
jvanhook 32:1e1e7730b6c8 712 __IO uint32_t TDA2;
jvanhook 32:1e1e7730b6c8 713 __IO uint32_t TDB2;
jvanhook 32:1e1e7730b6c8 714 __IO uint32_t TFI3;
jvanhook 32:1e1e7730b6c8 715 __IO uint32_t TID3;
jvanhook 32:1e1e7730b6c8 716 __IO uint32_t TDA3;
jvanhook 32:1e1e7730b6c8 717 __IO uint32_t TDB3;
jvanhook 32:1e1e7730b6c8 718 } LPC_CAN_TypeDef;
jvanhook 32:1e1e7730b6c8 719
jvanhook 32:1e1e7730b6c8 720 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
jvanhook 32:1e1e7730b6c8 721 typedef struct /* Common Registers */
jvanhook 32:1e1e7730b6c8 722 {
jvanhook 32:1e1e7730b6c8 723 __I uint32_t DMACIntStat;
jvanhook 32:1e1e7730b6c8 724 __I uint32_t DMACIntTCStat;
jvanhook 32:1e1e7730b6c8 725 __O uint32_t DMACIntTCClear;
jvanhook 32:1e1e7730b6c8 726 __I uint32_t DMACIntErrStat;
jvanhook 32:1e1e7730b6c8 727 __O uint32_t DMACIntErrClr;
jvanhook 32:1e1e7730b6c8 728 __I uint32_t DMACRawIntTCStat;
jvanhook 32:1e1e7730b6c8 729 __I uint32_t DMACRawIntErrStat;
jvanhook 32:1e1e7730b6c8 730 __I uint32_t DMACEnbldChns;
jvanhook 32:1e1e7730b6c8 731 __IO uint32_t DMACSoftBReq;
jvanhook 32:1e1e7730b6c8 732 __IO uint32_t DMACSoftSReq;
jvanhook 32:1e1e7730b6c8 733 __IO uint32_t DMACSoftLBReq;
jvanhook 32:1e1e7730b6c8 734 __IO uint32_t DMACSoftLSReq;
jvanhook 32:1e1e7730b6c8 735 __IO uint32_t DMACConfig;
jvanhook 32:1e1e7730b6c8 736 __IO uint32_t DMACSync;
jvanhook 32:1e1e7730b6c8 737 } LPC_GPDMA_TypeDef;
jvanhook 32:1e1e7730b6c8 738
jvanhook 32:1e1e7730b6c8 739 typedef struct /* Channel Registers */
jvanhook 32:1e1e7730b6c8 740 {
jvanhook 32:1e1e7730b6c8 741 __IO uint32_t DMACCSrcAddr;
jvanhook 32:1e1e7730b6c8 742 __IO uint32_t DMACCDestAddr;
jvanhook 32:1e1e7730b6c8 743 __IO uint32_t DMACCLLI;
jvanhook 32:1e1e7730b6c8 744 __IO uint32_t DMACCControl;
jvanhook 32:1e1e7730b6c8 745 __IO uint32_t DMACCConfig;
jvanhook 32:1e1e7730b6c8 746 } LPC_GPDMACH_TypeDef;
jvanhook 32:1e1e7730b6c8 747
jvanhook 32:1e1e7730b6c8 748 /*------------- Universal Serial Bus (USB) -----------------------------------*/
jvanhook 32:1e1e7730b6c8 749 typedef struct
jvanhook 32:1e1e7730b6c8 750 {
jvanhook 32:1e1e7730b6c8 751 __I uint32_t HcRevision; /* USB Host Registers */
jvanhook 32:1e1e7730b6c8 752 __IO uint32_t HcControl;
jvanhook 32:1e1e7730b6c8 753 __IO uint32_t HcCommandStatus;
jvanhook 32:1e1e7730b6c8 754 __IO uint32_t HcInterruptStatus;
jvanhook 32:1e1e7730b6c8 755 __IO uint32_t HcInterruptEnable;
jvanhook 32:1e1e7730b6c8 756 __IO uint32_t HcInterruptDisable;
jvanhook 32:1e1e7730b6c8 757 __IO uint32_t HcHCCA;
jvanhook 32:1e1e7730b6c8 758 __I uint32_t HcPeriodCurrentED;
jvanhook 32:1e1e7730b6c8 759 __IO uint32_t HcControlHeadED;
jvanhook 32:1e1e7730b6c8 760 __IO uint32_t HcControlCurrentED;
jvanhook 32:1e1e7730b6c8 761 __IO uint32_t HcBulkHeadED;
jvanhook 32:1e1e7730b6c8 762 __IO uint32_t HcBulkCurrentED;
jvanhook 32:1e1e7730b6c8 763 __I uint32_t HcDoneHead;
jvanhook 32:1e1e7730b6c8 764 __IO uint32_t HcFmInterval;
jvanhook 32:1e1e7730b6c8 765 __I uint32_t HcFmRemaining;
jvanhook 32:1e1e7730b6c8 766 __I uint32_t HcFmNumber;
jvanhook 32:1e1e7730b6c8 767 __IO uint32_t HcPeriodicStart;
jvanhook 32:1e1e7730b6c8 768 __IO uint32_t HcLSTreshold;
jvanhook 32:1e1e7730b6c8 769 __IO uint32_t HcRhDescriptorA;
jvanhook 32:1e1e7730b6c8 770 __IO uint32_t HcRhDescriptorB;
jvanhook 32:1e1e7730b6c8 771 __IO uint32_t HcRhStatus;
jvanhook 32:1e1e7730b6c8 772 __IO uint32_t HcRhPortStatus1;
jvanhook 32:1e1e7730b6c8 773 __IO uint32_t HcRhPortStatus2;
jvanhook 32:1e1e7730b6c8 774 uint32_t RESERVED0[40];
jvanhook 32:1e1e7730b6c8 775 __I uint32_t Module_ID;
jvanhook 32:1e1e7730b6c8 776
jvanhook 32:1e1e7730b6c8 777 __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
jvanhook 32:1e1e7730b6c8 778 __IO uint32_t OTGIntEn;
jvanhook 32:1e1e7730b6c8 779 __O uint32_t OTGIntSet;
jvanhook 32:1e1e7730b6c8 780 __O uint32_t OTGIntClr;
jvanhook 32:1e1e7730b6c8 781 __IO uint32_t OTGStCtrl;
jvanhook 32:1e1e7730b6c8 782 __IO uint32_t OTGTmr;
jvanhook 32:1e1e7730b6c8 783 uint32_t RESERVED1[58];
jvanhook 32:1e1e7730b6c8 784
jvanhook 32:1e1e7730b6c8 785 __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
jvanhook 32:1e1e7730b6c8 786 __IO uint32_t USBDevIntEn;
jvanhook 32:1e1e7730b6c8 787 __O uint32_t USBDevIntClr;
jvanhook 32:1e1e7730b6c8 788 __O uint32_t USBDevIntSet;
jvanhook 32:1e1e7730b6c8 789
jvanhook 32:1e1e7730b6c8 790 __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
jvanhook 32:1e1e7730b6c8 791 __I uint32_t USBCmdData;
jvanhook 32:1e1e7730b6c8 792
jvanhook 32:1e1e7730b6c8 793 __I uint32_t USBRxData; /* USB Device Transfer Registers */
jvanhook 32:1e1e7730b6c8 794 __O uint32_t USBTxData;
jvanhook 32:1e1e7730b6c8 795 __I uint32_t USBRxPLen;
jvanhook 32:1e1e7730b6c8 796 __O uint32_t USBTxPLen;
jvanhook 32:1e1e7730b6c8 797 __IO uint32_t USBCtrl;
jvanhook 32:1e1e7730b6c8 798 __O uint32_t USBDevIntPri;
jvanhook 32:1e1e7730b6c8 799
jvanhook 32:1e1e7730b6c8 800 __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
jvanhook 32:1e1e7730b6c8 801 __IO uint32_t USBEpIntEn;
jvanhook 32:1e1e7730b6c8 802 __O uint32_t USBEpIntClr;
jvanhook 32:1e1e7730b6c8 803 __O uint32_t USBEpIntSet;
jvanhook 32:1e1e7730b6c8 804 __O uint32_t USBEpIntPri;
jvanhook 32:1e1e7730b6c8 805
jvanhook 32:1e1e7730b6c8 806 __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
jvanhook 32:1e1e7730b6c8 807 __O uint32_t USBEpInd;
jvanhook 32:1e1e7730b6c8 808 __IO uint32_t USBMaxPSize;
jvanhook 32:1e1e7730b6c8 809
jvanhook 32:1e1e7730b6c8 810 __I uint32_t USBDMARSt; /* USB Device DMA Registers */
jvanhook 32:1e1e7730b6c8 811 __O uint32_t USBDMARClr;
jvanhook 32:1e1e7730b6c8 812 __O uint32_t USBDMARSet;
jvanhook 32:1e1e7730b6c8 813 uint32_t RESERVED2[9];
jvanhook 32:1e1e7730b6c8 814 __IO uint32_t USBUDCAH;
jvanhook 32:1e1e7730b6c8 815 __I uint32_t USBEpDMASt;
jvanhook 32:1e1e7730b6c8 816 __O uint32_t USBEpDMAEn;
jvanhook 32:1e1e7730b6c8 817 __O uint32_t USBEpDMADis;
jvanhook 32:1e1e7730b6c8 818 __I uint32_t USBDMAIntSt;
jvanhook 32:1e1e7730b6c8 819 __IO uint32_t USBDMAIntEn;
jvanhook 32:1e1e7730b6c8 820 uint32_t RESERVED3[2];
jvanhook 32:1e1e7730b6c8 821 __I uint32_t USBEoTIntSt;
jvanhook 32:1e1e7730b6c8 822 __O uint32_t USBEoTIntClr;
jvanhook 32:1e1e7730b6c8 823 __O uint32_t USBEoTIntSet;
jvanhook 32:1e1e7730b6c8 824 __I uint32_t USBNDDRIntSt;
jvanhook 32:1e1e7730b6c8 825 __O uint32_t USBNDDRIntClr;
jvanhook 32:1e1e7730b6c8 826 __O uint32_t USBNDDRIntSet;
jvanhook 32:1e1e7730b6c8 827 __I uint32_t USBSysErrIntSt;
jvanhook 32:1e1e7730b6c8 828 __O uint32_t USBSysErrIntClr;
jvanhook 32:1e1e7730b6c8 829 __O uint32_t USBSysErrIntSet;
jvanhook 32:1e1e7730b6c8 830 uint32_t RESERVED4[15];
jvanhook 32:1e1e7730b6c8 831
jvanhook 32:1e1e7730b6c8 832 union {
jvanhook 32:1e1e7730b6c8 833 __I uint32_t I2C_RX; /* USB OTG I2C Registers */
jvanhook 32:1e1e7730b6c8 834 __O uint32_t I2C_TX;
jvanhook 32:1e1e7730b6c8 835 };
jvanhook 32:1e1e7730b6c8 836 __I uint32_t I2C_STS;
jvanhook 32:1e1e7730b6c8 837 __IO uint32_t I2C_CTL;
jvanhook 32:1e1e7730b6c8 838 __IO uint32_t I2C_CLKHI;
jvanhook 32:1e1e7730b6c8 839 __O uint32_t I2C_CLKLO;
jvanhook 32:1e1e7730b6c8 840 uint32_t RESERVED5[824];
jvanhook 32:1e1e7730b6c8 841
jvanhook 32:1e1e7730b6c8 842 union {
jvanhook 32:1e1e7730b6c8 843 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
jvanhook 32:1e1e7730b6c8 844 __IO uint32_t OTGClkCtrl;
jvanhook 32:1e1e7730b6c8 845 };
jvanhook 32:1e1e7730b6c8 846 union {
jvanhook 32:1e1e7730b6c8 847 __I uint32_t USBClkSt;
jvanhook 32:1e1e7730b6c8 848 __I uint32_t OTGClkSt;
jvanhook 32:1e1e7730b6c8 849 };
jvanhook 32:1e1e7730b6c8 850 } LPC_USB_TypeDef;
jvanhook 32:1e1e7730b6c8 851
jvanhook 32:1e1e7730b6c8 852 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
jvanhook 32:1e1e7730b6c8 853 typedef struct
jvanhook 32:1e1e7730b6c8 854 {
jvanhook 32:1e1e7730b6c8 855 __IO uint32_t MAC1; /* MAC Registers */
jvanhook 32:1e1e7730b6c8 856 __IO uint32_t MAC2;
jvanhook 32:1e1e7730b6c8 857 __IO uint32_t IPGT;
jvanhook 32:1e1e7730b6c8 858 __IO uint32_t IPGR;
jvanhook 32:1e1e7730b6c8 859 __IO uint32_t CLRT;
jvanhook 32:1e1e7730b6c8 860 __IO uint32_t MAXF;
jvanhook 32:1e1e7730b6c8 861 __IO uint32_t SUPP;
jvanhook 32:1e1e7730b6c8 862 __IO uint32_t TEST;
jvanhook 32:1e1e7730b6c8 863 __IO uint32_t MCFG;
jvanhook 32:1e1e7730b6c8 864 __IO uint32_t MCMD;
jvanhook 32:1e1e7730b6c8 865 __IO uint32_t MADR;
jvanhook 32:1e1e7730b6c8 866 __O uint32_t MWTD;
jvanhook 32:1e1e7730b6c8 867 __I uint32_t MRDD;
jvanhook 32:1e1e7730b6c8 868 __I uint32_t MIND;
jvanhook 32:1e1e7730b6c8 869 uint32_t RESERVED0[2];
jvanhook 32:1e1e7730b6c8 870 __IO uint32_t SA0;
jvanhook 32:1e1e7730b6c8 871 __IO uint32_t SA1;
jvanhook 32:1e1e7730b6c8 872 __IO uint32_t SA2;
jvanhook 32:1e1e7730b6c8 873 uint32_t RESERVED1[45];
jvanhook 32:1e1e7730b6c8 874 __IO uint32_t Command; /* Control Registers */
jvanhook 32:1e1e7730b6c8 875 __I uint32_t Status;
jvanhook 32:1e1e7730b6c8 876 __IO uint32_t RxDescriptor;
jvanhook 32:1e1e7730b6c8 877 __IO uint32_t RxStatus;
jvanhook 32:1e1e7730b6c8 878 __IO uint32_t RxDescriptorNumber;
jvanhook 32:1e1e7730b6c8 879 __I uint32_t RxProduceIndex;
jvanhook 32:1e1e7730b6c8 880 __IO uint32_t RxConsumeIndex;
jvanhook 32:1e1e7730b6c8 881 __IO uint32_t TxDescriptor;
jvanhook 32:1e1e7730b6c8 882 __IO uint32_t TxStatus;
jvanhook 32:1e1e7730b6c8 883 __IO uint32_t TxDescriptorNumber;
jvanhook 32:1e1e7730b6c8 884 __IO uint32_t TxProduceIndex;
jvanhook 32:1e1e7730b6c8 885 __I uint32_t TxConsumeIndex;
jvanhook 32:1e1e7730b6c8 886 uint32_t RESERVED2[10];
jvanhook 32:1e1e7730b6c8 887 __I uint32_t TSV0;
jvanhook 32:1e1e7730b6c8 888 __I uint32_t TSV1;
jvanhook 32:1e1e7730b6c8 889 __I uint32_t RSV;
jvanhook 32:1e1e7730b6c8 890 uint32_t RESERVED3[3];
jvanhook 32:1e1e7730b6c8 891 __IO uint32_t FlowControlCounter;
jvanhook 32:1e1e7730b6c8 892 __I uint32_t FlowControlStatus;
jvanhook 32:1e1e7730b6c8 893 uint32_t RESERVED4[34];
jvanhook 32:1e1e7730b6c8 894 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
jvanhook 32:1e1e7730b6c8 895 __IO uint32_t RxFilterWoLStatus;
jvanhook 32:1e1e7730b6c8 896 __IO uint32_t RxFilterWoLClear;
jvanhook 32:1e1e7730b6c8 897 uint32_t RESERVED5;
jvanhook 32:1e1e7730b6c8 898 __IO uint32_t HashFilterL;
jvanhook 32:1e1e7730b6c8 899 __IO uint32_t HashFilterH;
jvanhook 32:1e1e7730b6c8 900 uint32_t RESERVED6[882];
jvanhook 32:1e1e7730b6c8 901 __I uint32_t IntStatus; /* Module Control Registers */
jvanhook 32:1e1e7730b6c8 902 __IO uint32_t IntEnable;
jvanhook 32:1e1e7730b6c8 903 __O uint32_t IntClear;
jvanhook 32:1e1e7730b6c8 904 __O uint32_t IntSet;
jvanhook 32:1e1e7730b6c8 905 uint32_t RESERVED7;
jvanhook 32:1e1e7730b6c8 906 __IO uint32_t PowerDown;
jvanhook 32:1e1e7730b6c8 907 uint32_t RESERVED8;
jvanhook 32:1e1e7730b6c8 908 __IO uint32_t Module_ID;
jvanhook 32:1e1e7730b6c8 909 } LPC_EMAC_TypeDef;
jvanhook 32:1e1e7730b6c8 910
jvanhook 32:1e1e7730b6c8 911 #if defined ( __CC_ARM )
jvanhook 32:1e1e7730b6c8 912 #pragma no_anon_unions
jvanhook 32:1e1e7730b6c8 913 #endif
jvanhook 32:1e1e7730b6c8 914
jvanhook 32:1e1e7730b6c8 915
jvanhook 32:1e1e7730b6c8 916 /******************************************************************************/
jvanhook 32:1e1e7730b6c8 917 /* Peripheral memory map */
jvanhook 32:1e1e7730b6c8 918 /******************************************************************************/
jvanhook 32:1e1e7730b6c8 919 /* Base addresses */
jvanhook 32:1e1e7730b6c8 920 #define LPC_FLASH_BASE (0x00000000UL)
jvanhook 32:1e1e7730b6c8 921 #define LPC_RAM_BASE (0x10000000UL)
jvanhook 32:1e1e7730b6c8 922 #define LPC_GPIO_BASE (0x2009C000UL)
jvanhook 32:1e1e7730b6c8 923 #define LPC_APB0_BASE (0x40000000UL)
jvanhook 32:1e1e7730b6c8 924 #define LPC_APB1_BASE (0x40080000UL)
jvanhook 32:1e1e7730b6c8 925 #define LPC_AHB_BASE (0x50000000UL)
jvanhook 32:1e1e7730b6c8 926 #define LPC_CM3_BASE (0xE0000000UL)
jvanhook 32:1e1e7730b6c8 927
jvanhook 32:1e1e7730b6c8 928 /* APB0 peripherals */
jvanhook 32:1e1e7730b6c8 929 #define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
jvanhook 32:1e1e7730b6c8 930 #define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
jvanhook 32:1e1e7730b6c8 931 #define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
jvanhook 32:1e1e7730b6c8 932 #define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
jvanhook 32:1e1e7730b6c8 933 #define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
jvanhook 32:1e1e7730b6c8 934 #define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
jvanhook 32:1e1e7730b6c8 935 #define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
jvanhook 32:1e1e7730b6c8 936 #define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000)
jvanhook 32:1e1e7730b6c8 937 #define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
jvanhook 32:1e1e7730b6c8 938 #define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
jvanhook 32:1e1e7730b6c8 939 #define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000)
jvanhook 32:1e1e7730b6c8 940 #define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
jvanhook 32:1e1e7730b6c8 941 #define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
jvanhook 32:1e1e7730b6c8 942 #define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
jvanhook 32:1e1e7730b6c8 943 #define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
jvanhook 32:1e1e7730b6c8 944 #define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
jvanhook 32:1e1e7730b6c8 945 #define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
jvanhook 32:1e1e7730b6c8 946 #define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
jvanhook 32:1e1e7730b6c8 947 #define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
jvanhook 32:1e1e7730b6c8 948
jvanhook 32:1e1e7730b6c8 949 /* APB1 peripherals */
jvanhook 32:1e1e7730b6c8 950 #define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
jvanhook 32:1e1e7730b6c8 951 #define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
jvanhook 32:1e1e7730b6c8 952 #define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
jvanhook 32:1e1e7730b6c8 953 #define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
jvanhook 32:1e1e7730b6c8 954 #define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
jvanhook 32:1e1e7730b6c8 955 #define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
jvanhook 32:1e1e7730b6c8 956 #define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
jvanhook 32:1e1e7730b6c8 957 #define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
jvanhook 32:1e1e7730b6c8 958 #define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000)
jvanhook 32:1e1e7730b6c8 959 #define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
jvanhook 32:1e1e7730b6c8 960 #define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
jvanhook 32:1e1e7730b6c8 961 #define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
jvanhook 32:1e1e7730b6c8 962
jvanhook 32:1e1e7730b6c8 963 /* AHB peripherals */
jvanhook 32:1e1e7730b6c8 964 #define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000)
jvanhook 32:1e1e7730b6c8 965 #define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000)
jvanhook 32:1e1e7730b6c8 966 #define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100)
jvanhook 32:1e1e7730b6c8 967 #define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120)
jvanhook 32:1e1e7730b6c8 968 #define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140)
jvanhook 32:1e1e7730b6c8 969 #define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160)
jvanhook 32:1e1e7730b6c8 970 #define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180)
jvanhook 32:1e1e7730b6c8 971 #define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0)
jvanhook 32:1e1e7730b6c8 972 #define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0)
jvanhook 32:1e1e7730b6c8 973 #define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0)
jvanhook 32:1e1e7730b6c8 974 #define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
jvanhook 32:1e1e7730b6c8 975
jvanhook 32:1e1e7730b6c8 976 /* GPIOs */
jvanhook 32:1e1e7730b6c8 977 #define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000)
jvanhook 32:1e1e7730b6c8 978 #define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020)
jvanhook 32:1e1e7730b6c8 979 #define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040)
jvanhook 32:1e1e7730b6c8 980 #define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060)
jvanhook 32:1e1e7730b6c8 981 #define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080)
jvanhook 32:1e1e7730b6c8 982
jvanhook 32:1e1e7730b6c8 983
jvanhook 32:1e1e7730b6c8 984 /******************************************************************************/
jvanhook 32:1e1e7730b6c8 985 /* Peripheral declaration */
jvanhook 32:1e1e7730b6c8 986 /******************************************************************************/
jvanhook 32:1e1e7730b6c8 987 #define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
jvanhook 32:1e1e7730b6c8 988 #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
jvanhook 32:1e1e7730b6c8 989 #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
jvanhook 32:1e1e7730b6c8 990 #define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
jvanhook 32:1e1e7730b6c8 991 #define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
jvanhook 32:1e1e7730b6c8 992 #define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
jvanhook 32:1e1e7730b6c8 993 #define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
jvanhook 32:1e1e7730b6c8 994 #define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
jvanhook 32:1e1e7730b6c8 995 #define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
jvanhook 32:1e1e7730b6c8 996 #define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
jvanhook 32:1e1e7730b6c8 997 #define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
jvanhook 32:1e1e7730b6c8 998 #define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE )
jvanhook 32:1e1e7730b6c8 999 #define LPC_UART0 ((LPC_UART0_TypeDef *) LPC_UART0_BASE )
jvanhook 32:1e1e7730b6c8 1000 #define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
jvanhook 32:1e1e7730b6c8 1001 #define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
jvanhook 32:1e1e7730b6c8 1002 #define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
jvanhook 32:1e1e7730b6c8 1003 #define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
jvanhook 32:1e1e7730b6c8 1004 #define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
jvanhook 32:1e1e7730b6c8 1005 #define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
jvanhook 32:1e1e7730b6c8 1006 #define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
jvanhook 32:1e1e7730b6c8 1007 #define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
jvanhook 32:1e1e7730b6c8 1008 #define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE )
jvanhook 32:1e1e7730b6c8 1009 #define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
jvanhook 32:1e1e7730b6c8 1010 #define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
jvanhook 32:1e1e7730b6c8 1011 #define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE )
jvanhook 32:1e1e7730b6c8 1012 #define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
jvanhook 32:1e1e7730b6c8 1013 #define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
jvanhook 32:1e1e7730b6c8 1014 #define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
jvanhook 32:1e1e7730b6c8 1015 #define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
jvanhook 32:1e1e7730b6c8 1016 #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
jvanhook 32:1e1e7730b6c8 1017 #define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
jvanhook 32:1e1e7730b6c8 1018 #define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
jvanhook 32:1e1e7730b6c8 1019 #define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
jvanhook 32:1e1e7730b6c8 1020 #define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
jvanhook 32:1e1e7730b6c8 1021 #define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
jvanhook 32:1e1e7730b6c8 1022 #define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
jvanhook 32:1e1e7730b6c8 1023 #define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
jvanhook 32:1e1e7730b6c8 1024 #define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
jvanhook 32:1e1e7730b6c8 1025 #define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
jvanhook 32:1e1e7730b6c8 1026 #define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
jvanhook 32:1e1e7730b6c8 1027 #define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
jvanhook 32:1e1e7730b6c8 1028 #define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
jvanhook 32:1e1e7730b6c8 1029 #define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
jvanhook 32:1e1e7730b6c8 1030 #define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
jvanhook 32:1e1e7730b6c8 1031 #define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
jvanhook 32:1e1e7730b6c8 1032 #define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
jvanhook 32:1e1e7730b6c8 1033 #define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
jvanhook 32:1e1e7730b6c8 1034
jvanhook 32:1e1e7730b6c8 1035 #endif // __LPC17xx_H__