Library SX1272, initially created by C.Pham, University of Pau, France for Arduino. Suitable for MBED / NUCLEO / STM32

Dependents:   LOW_COAST_LORA_NODE

Committer:
cdupaty
Date:
Tue Feb 06 09:58:17 2018 +0000
Revision:
2:a5a72d30cb18
Parent:
1:5d57c6a92509
Version of C.Pham project (university of Pau, France) ; Originally for Arduino. Ported on NUCLEO L073RZ; Please read main.cpp

Who changed what in which revision?

UserRevisionLine numberNew contents of line
cdupaty 0:d974bcee4f69 1 /*
cdupaty 0:d974bcee4f69 2 * Library for LoRa 868 / 915MHz SX1272 LoRa module
cdupaty 0:d974bcee4f69 3 *
cdupaty 0:d974bcee4f69 4 * Copyright (C) Libelium Comunicaciones Distribuidas S.L.
cdupaty 0:d974bcee4f69 5 * http://www.libelium.com
cdupaty 0:d974bcee4f69 6 *
cdupaty 0:d974bcee4f69 7 * This program is free software: you can redistribute it and/or modify
cdupaty 0:d974bcee4f69 8 * it under the terms of the GNU General Public License as published by
cdupaty 0:d974bcee4f69 9 * the Free Software Foundation, either version 3 of the License, or
cdupaty 0:d974bcee4f69 10 * (at your option) any later version.
cdupaty 0:d974bcee4f69 11 *
cdupaty 0:d974bcee4f69 12 * This program is distributed in the hope that it will be useful,
cdupaty 0:d974bcee4f69 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
cdupaty 0:d974bcee4f69 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cdupaty 0:d974bcee4f69 15 * GNU General Public License for more details.
cdupaty 0:d974bcee4f69 16 *
cdupaty 0:d974bcee4f69 17 * You should have received a copy of the GNU General Public License
cdupaty 0:d974bcee4f69 18 * along with this program. If not, see http://www.gnu.org/licenses/.
cdupaty 0:d974bcee4f69 19 *
cdupaty 0:d974bcee4f69 20 * Version: 1.1
cdupaty 0:d974bcee4f69 21 * Design: David Gascón
cdupaty 0:d974bcee4f69 22 * Implementation: Covadonga Albiñana & Victor Boria
cdupaty 0:d974bcee4f69 23 */
cdupaty 0:d974bcee4f69 24
cdupaty 0:d974bcee4f69 25 //**********************************************************************/
cdupaty 0:d974bcee4f69 26 // Includes
cdupaty 0:d974bcee4f69 27 //**********************************************************************/
cdupaty 0:d974bcee4f69 28 #include "mbed.h"
cdupaty 0:d974bcee4f69 29 #include "SX1272.h"
cdupaty 0:d974bcee4f69 30 #include <SPI.h>
cdupaty 0:d974bcee4f69 31
cdupaty 0:d974bcee4f69 32 /* CHANGE LOGS by C. Pham
cdupaty 0:d974bcee4f69 33 * June, 22th, 2017
cdupaty 0:d974bcee4f69 34 * - setPowerDBM(uint8_t dbm) calls setPower('X') when dbm is set to 20
cdupaty 0:d974bcee4f69 35 * Apr, 21th, 2017
cdupaty 0:d974bcee4f69 36 * - change the way timeout are detected: exitTime=millis()+(unsigned long)wait; then millis() < exitTime;
cdupaty 0:d974bcee4f69 37 * Mar, 26th, 2017
cdupaty 0:d974bcee4f69 38 * - insert delay(100) before setting radio module to sleep mode. Remove unstability issue
cdupaty 0:d974bcee4f69 39 * - (proposed by escyes - https://github.com/CongducPham/LowCostLoRaGw/issues/53#issuecomment-289237532)
cdupaty 0:d974bcee4f69 40 * Jan, 11th, 2017
cdupaty 0:d974bcee4f69 41 * - fix bug in getRSSIpacket() when SNR < 0 thanks to John Rohde from Aarhus University
cdupaty 0:d974bcee4f69 42 * Dec, 17th, 2016
cdupaty 0:d974bcee4f69 43 * - fix bug making -DPABOOST in radio.makefile inoperant
cdupaty 0:d974bcee4f69 44 * Dec, 1st, 2016
cdupaty 0:d974bcee4f69 45 * - add RSSI computation while performing CAD with doCAD()
cdupaty 0:d974bcee4f69 46 * - WARNING: the SX1272 lib for gateway (Raspberry) does not have this functionality
cdupaty 0:d974bcee4f69 47 * Nov, 26th, 2016
cdupaty 0:d974bcee4f69 48 * - add preliminary support for ToA limitation
cdupaty 0:d974bcee4f69 49 * - when in "production" mode, uncomment #define LIMIT_TOA
cdupaty 0:d974bcee4f69 50 * Nov, 16th, 2016
cdupaty 0:d974bcee4f69 51 * - provide better power management mechanisms
cdupaty 0:d974bcee4f69 52 * - manage PA_BOOST and dBm setting
cdupaty 0:d974bcee4f69 53 * Jan, 23rd, 2016
cdupaty 0:d974bcee4f69 54 * - the packet format at transmission does not use the original Libelium format anymore
cdupaty 0:d974bcee4f69 55 * * the retry field is removed therefore all operations using retry will probably not work well, not tested though
cdupaty 0:d974bcee4f69 56 * - therefore DO NOT use sendPacketTimeoutACKRetries()
cdupaty 0:d974bcee4f69 57 * - the reason is that we do not want to have a reserved byte after the payload
cdupaty 0:d974bcee4f69 58 * * the length field is removed because it is much better to get the packet length at the reception side
cdupaty 0:d974bcee4f69 59 * * after the dst field, we inserted a packet type field to better identify the packet type: DATA, ACK, encryption, app key,...
cdupaty 0:d974bcee4f69 60 * - the format is now dst(1B) ptype(1B) src(1B) seq(1B) payload(xB)
cdupaty 0:d974bcee4f69 61 * - ptype is decomposed in 2 parts type(4bits) flags(4bits)
cdupaty 0:d974bcee4f69 62 * - type can take current value of DATA=0001 and ACK=0010
cdupaty 0:d974bcee4f69 63 * - the flags are from left to right: ack_requested|encrypted|with_appkey|is_binary
cdupaty 0:d974bcee4f69 64 * - ptype can be set with setPacketType(), see constant defined in SX1272.h
cdupaty 0:d974bcee4f69 65 * - the header length is then 4 instead of 5
cdupaty 0:d974bcee4f69 66 * Jan, 16th, 2016
cdupaty 0:d974bcee4f69 67 * - add support for SX1276, automatic detect
cdupaty 0:d974bcee4f69 68 * - add LF/HF calibaration copied from LoRaMAC-Node. Don't know if it is really necessary though
cdupaty 0:d974bcee4f69 69 * - change various radio settings
cdupaty 0:d974bcee4f69 70 * Dec, 10th, 2015
cdupaty 0:d974bcee4f69 71 * - add SyncWord for test with simple LoRaWAN
cdupaty 0:d974bcee4f69 72 * - add mode 11 that have BW=125, CR=4/5, SF=7 on channel 868.1MHz
cdupaty 0:d974bcee4f69 73 * - use following in your code if (loraMode==11) { e = sx1272.setChannel(CH_18_868); }
cdupaty 0:d974bcee4f69 74 * Nov, 13th, 2015
cdupaty 0:d974bcee4f69 75 * - add CarrierSense() to perform some Listen Before Talk procedure
cdupaty 0:d974bcee4f69 76 * - add dynamic ACK suport
cdupaty 0:d974bcee4f69 77 * - compile with W_REQUESTED_ACK, retry field is used to indicate at the receiver
cdupaty 0:d974bcee4f69 78 * that an ACK should be sent
cdupaty 0:d974bcee4f69 79 * - receiveWithTimeout() has been modified to send an ACK if retry is 1
cdupaty 0:d974bcee4f69 80 * - at sender side, sendPacketTimeoutACK() has been modified to indicate
cdupaty 0:d974bcee4f69 81 * whether retry should be set to 1 or not in setPacket()
cdupaty 0:d974bcee4f69 82 * - receiver should always use receiveWithTimeout() while sender decides to use
cdupaty 0:d974bcee4f69 83 * sendPacketTimeout() or sendPacketTimeoutACK()
cdupaty 0:d974bcee4f69 84 * Jun, 2015
cdupaty 0:d974bcee4f69 85 * - Add time on air computation and CAD features
cdupaty 0:d974bcee4f69 86 */
cdupaty 0:d974bcee4f69 87
cdupaty 0:d974bcee4f69 88 // Added by C. Pham
cdupaty 0:d974bcee4f69 89 // based on SIFS=3CAD
cdupaty 0:d974bcee4f69 90 uint8_t sx1272_SIFS_value[11]={0, 183, 94, 44, 47, 23, 24, 12, 12, 7, 4};
cdupaty 0:d974bcee4f69 91 uint8_t sx1272_CAD_value[11]={0, 62, 31, 16, 16, 8, 9, 5, 3, 1, 1};
cdupaty 0:d974bcee4f69 92
cdupaty 0:d974bcee4f69 93 //#define LIMIT_TOA
cdupaty 0:d974bcee4f69 94 // 0.1% for testing
cdupaty 0:d974bcee4f69 95 //#define MAX_DUTY_CYCLE_PER_HOUR 3600L
cdupaty 0:d974bcee4f69 96 // 1%, regular mode
cdupaty 0:d974bcee4f69 97 #define MAX_DUTY_CYCLE_PER_HOUR 36000L
cdupaty 0:d974bcee4f69 98 // normally 1 hour, set to smaller value for testing
cdupaty 0:d974bcee4f69 99 #define DUTYCYCLE_DURATION 3600000L
cdupaty 0:d974bcee4f69 100 // 4 min for testing
cdupaty 0:d974bcee4f69 101 //#define DUTYCYCLE_DURATION 240000L
cdupaty 0:d974bcee4f69 102
cdupaty 0:d974bcee4f69 103 // end
cdupaty 0:d974bcee4f69 104
cdupaty 0:d974bcee4f69 105 //ajoute par C.DUPATY
cdupaty 0:d974bcee4f69 106 //Serial pc(USBTX, USBRX); // tx, rx
cdupaty 1:5d57c6a92509 107 // config pour SX1272MB2xAS sur NUCLEO-L073RZ
cdupaty 1:5d57c6a92509 108 SPI spi(SPI_MOSI,SPI_MISO,SPI_SCK);; // PA_7, PA_6, PA_5
cdupaty 1:5d57c6a92509 109 DigitalOut ss(SPI_CS); //(PB_6)
cdupaty 1:5d57c6a92509 110 DigitalOut rst(PA_0);
cdupaty 0:d974bcee4f69 111
cdupaty 0:d974bcee4f69 112 //**********************************************************************/
cdupaty 0:d974bcee4f69 113 // Public functions.
cdupaty 0:d974bcee4f69 114 //**********************************************************************/
cdupaty 0:d974bcee4f69 115
cdupaty 0:d974bcee4f69 116 SX1272::SX1272()
cdupaty 0:d974bcee4f69 117 {
cdupaty 0:d974bcee4f69 118 //ajoute par C.DUPATY
cdupaty 0:d974bcee4f69 119 us_ticker_init();
cdupaty 0:d974bcee4f69 120 srand(time(NULL));
cdupaty 0:d974bcee4f69 121 // ajoute parC.Dupaty
cdupaty 0:d974bcee4f69 122 spi.format(8,0); // spi 8 bits mode 0
cdupaty 0:d974bcee4f69 123 spi.frequency(2000000); // spi clock 200KHz a l origine
cdupaty 0:d974bcee4f69 124
cdupaty 0:d974bcee4f69 125 // Initialize class variables
cdupaty 0:d974bcee4f69 126 _bandwidth = BW_125;
cdupaty 0:d974bcee4f69 127 _codingRate = CR_5;
cdupaty 0:d974bcee4f69 128 _spreadingFactor = SF_7;
cdupaty 0:d974bcee4f69 129 _channel = CH_12_900;
cdupaty 0:d974bcee4f69 130 _header = HEADER_ON;
cdupaty 0:d974bcee4f69 131 _CRC = CRC_OFF;
cdupaty 0:d974bcee4f69 132 _modem = FSK;
cdupaty 0:d974bcee4f69 133 _power = 15;
cdupaty 0:d974bcee4f69 134 _packetNumber = 0;
cdupaty 0:d974bcee4f69 135 _reception = CORRECT_PACKET;
cdupaty 0:d974bcee4f69 136 _retries = 0;
cdupaty 0:d974bcee4f69 137 // added by C. Pham
cdupaty 0:d974bcee4f69 138 _defaultSyncWord=0x12;
cdupaty 0:d974bcee4f69 139 _rawFormat=false;
cdupaty 0:d974bcee4f69 140 _extendedIFS=true;
cdupaty 0:d974bcee4f69 141 _RSSIonSend=true;
cdupaty 0:d974bcee4f69 142 // disabled by default
cdupaty 0:d974bcee4f69 143 _enableCarrierSense=false;
cdupaty 0:d974bcee4f69 144 // DIFS by default
cdupaty 0:d974bcee4f69 145 _send_cad_number=9;
cdupaty 0:d974bcee4f69 146 #ifdef PABOOST
cdupaty 0:d974bcee4f69 147 _needPABOOST=true;
cdupaty 0:d974bcee4f69 148 #else
cdupaty 0:d974bcee4f69 149 _needPABOOST=false;
cdupaty 0:d974bcee4f69 150 #endif
cdupaty 0:d974bcee4f69 151 _limitToA=false;
cdupaty 0:d974bcee4f69 152 _startToAcycle=millis();
cdupaty 0:d974bcee4f69 153 _remainingToA=MAX_DUTY_CYCLE_PER_HOUR;
cdupaty 0:d974bcee4f69 154 _endToAcycle=_startToAcycle+DUTYCYCLE_DURATION;
cdupaty 0:d974bcee4f69 155 #ifdef W_REQUESTED_ACK
cdupaty 0:d974bcee4f69 156 _requestACK = 0;
cdupaty 0:d974bcee4f69 157 #endif
cdupaty 0:d974bcee4f69 158 #ifdef W_NET_KEY
cdupaty 0:d974bcee4f69 159 _my_netkey[0] = net_key_0;
cdupaty 0:d974bcee4f69 160 _my_netkey[1] = net_key_1;
cdupaty 0:d974bcee4f69 161 #endif
cdupaty 0:d974bcee4f69 162 // end
cdupaty 0:d974bcee4f69 163 _maxRetries = 3;
cdupaty 0:d974bcee4f69 164 packet_sent.retry = _retries;
cdupaty 0:d974bcee4f69 165 };
cdupaty 0:d974bcee4f69 166
cdupaty 0:d974bcee4f69 167 // added by C. Pham
cdupaty 0:d974bcee4f69 168 // copied from LoRaMAC-Node
cdupaty 0:d974bcee4f69 169 /*!
cdupaty 0:d974bcee4f69 170 * Performs the Rx chain calibration for LF and HF bands
cdupaty 0:d974bcee4f69 171 * \remark Must be called just after the reset so all registers are at their
cdupaty 0:d974bcee4f69 172 * default values
cdupaty 0:d974bcee4f69 173 */
cdupaty 0:d974bcee4f69 174 void SX1272::RxChainCalibration()
cdupaty 0:d974bcee4f69 175 {
cdupaty 0:d974bcee4f69 176 if (_board==SX1276Chip) {
cdupaty 0:d974bcee4f69 177
cdupaty 0:d974bcee4f69 178 printf("SX1276 LF/HF calibration\r");
cdupaty 0:d974bcee4f69 179
cdupaty 0:d974bcee4f69 180 // Cut the PA just in case, RFO output, power = -1 dBm
cdupaty 0:d974bcee4f69 181 writeRegister( REG_PA_CONFIG, 0x00 );
cdupaty 0:d974bcee4f69 182
cdupaty 0:d974bcee4f69 183 // Launch Rx chain calibration for LF band
cdupaty 0:d974bcee4f69 184 writeRegister( REG_IMAGE_CAL, ( readRegister( REG_IMAGE_CAL ) & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START );
cdupaty 0:d974bcee4f69 185 while( ( readRegister( REG_IMAGE_CAL ) & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING )
cdupaty 0:d974bcee4f69 186 {
cdupaty 0:d974bcee4f69 187 }
cdupaty 0:d974bcee4f69 188
cdupaty 0:d974bcee4f69 189 // Sets a Frequency in HF band
cdupaty 0:d974bcee4f69 190 setChannel(CH_17_868);
cdupaty 0:d974bcee4f69 191
cdupaty 0:d974bcee4f69 192 // Launch Rx chain calibration for HF band
cdupaty 0:d974bcee4f69 193 writeRegister( REG_IMAGE_CAL, ( readRegister( REG_IMAGE_CAL ) & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START );
cdupaty 0:d974bcee4f69 194 while( ( readRegister( REG_IMAGE_CAL ) & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING )
cdupaty 0:d974bcee4f69 195 {
cdupaty 0:d974bcee4f69 196 }
cdupaty 0:d974bcee4f69 197 }
cdupaty 0:d974bcee4f69 198 }
cdupaty 0:d974bcee4f69 199
cdupaty 0:d974bcee4f69 200
cdupaty 0:d974bcee4f69 201 /*
cdupaty 0:d974bcee4f69 202 Function: Sets the module ON.
cdupaty 0:d974bcee4f69 203 Returns: uint8_t setLORA state
cdupaty 0:d974bcee4f69 204 */
cdupaty 0:d974bcee4f69 205 uint8_t SX1272::ON()
cdupaty 0:d974bcee4f69 206 {
cdupaty 0:d974bcee4f69 207 uint8_t state = 2;
cdupaty 0:d974bcee4f69 208
cdupaty 0:d974bcee4f69 209 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 210 printf("\n");
cdupaty 0:d974bcee4f69 211 printf("Starting 'ON'\n");
cdupaty 0:d974bcee4f69 212 #endif
cdupaty 0:d974bcee4f69 213
cdupaty 0:d974bcee4f69 214 // Powering the module
cdupaty 0:d974bcee4f69 215 // pinMode(SX1272_SS,OUTPUT);
cdupaty 0:d974bcee4f69 216 // digitalWrite(SX1272_SS,HIGH);
cdupaty 0:d974bcee4f69 217 ss=1;
cdupaty 0:d974bcee4f69 218 wait_ms(100);
cdupaty 0:d974bcee4f69 219
cdupaty 0:d974bcee4f69 220 //#define USE_SPI_SETTINGS
cdupaty 0:d974bcee4f69 221 /*
cdupaty 0:d974bcee4f69 222 #ifdef USE_SPI_SETTINGS
cdupaty 0:d974bcee4f69 223 SPI.beginTransaction(SPISettings(2000000, MSBFIRST, SPI_MODE0));
cdupaty 0:d974bcee4f69 224 #else
cdupaty 0:d974bcee4f69 225 //Configure the MISO, MOSI, CS, SPCR.
cdupaty 0:d974bcee4f69 226 SPI.begin();
cdupaty 0:d974bcee4f69 227 //Set Most significant bit first
cdupaty 0:d974bcee4f69 228 SPI.setBitOrder(MSBFIRST);
cdupaty 0:d974bcee4f69 229 #ifdef _VARIANT_ARDUINO_DUE_X_
cdupaty 0:d974bcee4f69 230 // for the DUE, set to 4MHz
cdupaty 0:d974bcee4f69 231 SPI.setClockDivider(42);
cdupaty 0:d974bcee4f69 232 #else
cdupaty 0:d974bcee4f69 233 // for the MEGA, set to 2MHz
cdupaty 0:d974bcee4f69 234 SPI.setClockDivider(SPI_CLOCK_DIV8);
cdupaty 0:d974bcee4f69 235 #endif
cdupaty 0:d974bcee4f69 236 //Set data mode
cdupaty 0:d974bcee4f69 237 SPI.setDataMode(SPI_MODE0);
cdupaty 0:d974bcee4f69 238 #endif
cdupaty 0:d974bcee4f69 239 */
cdupaty 0:d974bcee4f69 240 wait_ms(100);
cdupaty 0:d974bcee4f69 241
cdupaty 0:d974bcee4f69 242 /* // added by C. Pham
cdupaty 0:d974bcee4f69 243 pinMode(SX1272_RST,OUTPUT);
cdupaty 0:d974bcee4f69 244 digitalWrite(SX1272_RST,HIGH);
cdupaty 0:d974bcee4f69 245 wait_ms(100);
cdupaty 0:d974bcee4f69 246 digitalWrite(SX1272_RST,LOW);
cdupaty 0:d974bcee4f69 247 wait_ms(100);
cdupaty 0:d974bcee4f69 248 */
cdupaty 0:d974bcee4f69 249
cdupaty 0:d974bcee4f69 250 rst=1;
cdupaty 0:d974bcee4f69 251 wait_ms(100);
cdupaty 0:d974bcee4f69 252 rst=0;
cdupaty 0:d974bcee4f69 253
cdupaty 0:d974bcee4f69 254 // from single_chan_pkt_fwd by Thomas Telkamp
cdupaty 0:d974bcee4f69 255 uint8_t version = readRegister(REG_VERSION);
cdupaty 0:d974bcee4f69 256
cdupaty 0:d974bcee4f69 257 if (version == 0x22) {
cdupaty 0:d974bcee4f69 258 // sx1272
cdupaty 0:d974bcee4f69 259 printf("SX1272 detected, starting\n");
cdupaty 0:d974bcee4f69 260 _board = SX1272Chip;
cdupaty 0:d974bcee4f69 261 } else {
cdupaty 0:d974bcee4f69 262 // sx1276?
cdupaty 0:d974bcee4f69 263 // digitalWrite(SX1272_RST, LOW);
cdupaty 0:d974bcee4f69 264 rst=0;
cdupaty 0:d974bcee4f69 265 wait_ms(100);
cdupaty 0:d974bcee4f69 266 // digitalWrite(SX1272_RST, HIGH);
cdupaty 0:d974bcee4f69 267 rst=1;
cdupaty 0:d974bcee4f69 268 wait_ms(100);
cdupaty 0:d974bcee4f69 269 version = readRegister(REG_VERSION);
cdupaty 0:d974bcee4f69 270 if (version == 0x12) {
cdupaty 0:d974bcee4f69 271 // sx1276
cdupaty 0:d974bcee4f69 272 printf("SX1276 detected, starting\n");
cdupaty 0:d974bcee4f69 273 _board = SX1276Chip;
cdupaty 0:d974bcee4f69 274 } else {
cdupaty 0:d974bcee4f69 275 printf("Unrecognized transceiver\n");
cdupaty 0:d974bcee4f69 276 }
cdupaty 0:d974bcee4f69 277 }
cdupaty 0:d974bcee4f69 278 // end from single_chan_pkt_fwd by Thomas Telkamp
cdupaty 0:d974bcee4f69 279
cdupaty 0:d974bcee4f69 280 // added by C. Pham
cdupaty 0:d974bcee4f69 281 RxChainCalibration();
cdupaty 0:d974bcee4f69 282
cdupaty 0:d974bcee4f69 283 setMaxCurrent(0x1B);
cdupaty 0:d974bcee4f69 284 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 285 printf("## Setting ON with maximum current supply ##");
cdupaty 0:d974bcee4f69 286 printf("\n");
cdupaty 0:d974bcee4f69 287 #endif
cdupaty 0:d974bcee4f69 288
cdupaty 0:d974bcee4f69 289 // set LoRa mode
cdupaty 0:d974bcee4f69 290 state = setLORA();
cdupaty 0:d974bcee4f69 291
cdupaty 0:d974bcee4f69 292 // Added by C. Pham for ToA computation
cdupaty 0:d974bcee4f69 293 getPreambleLength();
cdupaty 0:d974bcee4f69 294 #ifdef W_NET_KEY
cdupaty 0:d974bcee4f69 295 //#if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 296 printf("## SX1272 layer has net key##");
cdupaty 0:d974bcee4f69 297 //#endif
cdupaty 0:d974bcee4f69 298 #endif
cdupaty 0:d974bcee4f69 299
cdupaty 0:d974bcee4f69 300 #ifdef W_INITIALIZATION
cdupaty 0:d974bcee4f69 301 // CAUTION
cdupaty 0:d974bcee4f69 302 // doing initialization as proposed by Libelium seems not to work for the SX1276
cdupaty 0:d974bcee4f69 303 // so we decided to leave the default value of the SX127x, then configure the radio when
cdupaty 0:d974bcee4f69 304 // setting to LoRa mode
cdupaty 0:d974bcee4f69 305
cdupaty 0:d974bcee4f69 306 //Set initialization values
cdupaty 0:d974bcee4f69 307 writeRegister(0x0,0x0);
cdupaty 0:d974bcee4f69 308 // comment by C. Pham
cdupaty 0:d974bcee4f69 309 // still valid for SX1276
cdupaty 0:d974bcee4f69 310 writeRegister(0x1,0x81);
cdupaty 0:d974bcee4f69 311 // end
cdupaty 0:d974bcee4f69 312 writeRegister(0x2,0x1A);
cdupaty 0:d974bcee4f69 313 writeRegister(0x3,0xB);
cdupaty 0:d974bcee4f69 314 writeRegister(0x4,0x0);
cdupaty 0:d974bcee4f69 315 writeRegister(0x5,0x52);
cdupaty 0:d974bcee4f69 316 writeRegister(0x6,0xD8);
cdupaty 0:d974bcee4f69 317 writeRegister(0x7,0x99);
cdupaty 0:d974bcee4f69 318 writeRegister(0x8,0x99);
cdupaty 0:d974bcee4f69 319 // modified by C. Pham
cdupaty 0:d974bcee4f69 320 // added by C. Pham
cdupaty 0:d974bcee4f69 321 if (_board==SX1272Chip)
cdupaty 0:d974bcee4f69 322 // RFIO_pin RFU OutputPower
cdupaty 0:d974bcee4f69 323 // 0 000 0000
cdupaty 0:d974bcee4f69 324 writeRegister(0x9,0x0);
cdupaty 0:d974bcee4f69 325 else
cdupaty 0:d974bcee4f69 326 // RFO_pin MaxP OutputPower
cdupaty 0:d974bcee4f69 327 // 0 100 1111
cdupaty 0:d974bcee4f69 328 // set MaxPower to 0x4 and OutputPower to 0
cdupaty 0:d974bcee4f69 329 writeRegister(0x9,0x40);
cdupaty 0:d974bcee4f69 330
cdupaty 0:d974bcee4f69 331 writeRegister(0xA,0x9);
cdupaty 0:d974bcee4f69 332 writeRegister(0xB,0x3B);
cdupaty 0:d974bcee4f69 333
cdupaty 0:d974bcee4f69 334 // comment by C. Pham
cdupaty 0:d974bcee4f69 335 // still valid for SX1276
cdupaty 0:d974bcee4f69 336 writeRegister(0xC,0x23);
cdupaty 0:d974bcee4f69 337
cdupaty 0:d974bcee4f69 338 // REG_RX_CONFIG
cdupaty 0:d974bcee4f69 339 writeRegister(0xD,0x1);
cdupaty 0:d974bcee4f69 340
cdupaty 0:d974bcee4f69 341 writeRegister(0xE,0x80);
cdupaty 0:d974bcee4f69 342 writeRegister(0xF,0x0);
cdupaty 0:d974bcee4f69 343 writeRegister(0x10,0x0);
cdupaty 0:d974bcee4f69 344 writeRegister(0x11,0x0);
cdupaty 0:d974bcee4f69 345 writeRegister(0x12,0x0);
cdupaty 0:d974bcee4f69 346 writeRegister(0x13,0x0);
cdupaty 0:d974bcee4f69 347 writeRegister(0x14,0x0);
cdupaty 0:d974bcee4f69 348 writeRegister(0x15,0x0);
cdupaty 0:d974bcee4f69 349 writeRegister(0x16,0x0);
cdupaty 0:d974bcee4f69 350 writeRegister(0x17,0x0);
cdupaty 0:d974bcee4f69 351 writeRegister(0x18,0x10);
cdupaty 0:d974bcee4f69 352 writeRegister(0x19,0x0);
cdupaty 0:d974bcee4f69 353 writeRegister(0x1A,0x0);
cdupaty 0:d974bcee4f69 354 writeRegister(0x1B,0x0);
cdupaty 0:d974bcee4f69 355 writeRegister(0x1C,0x0);
cdupaty 0:d974bcee4f69 356
cdupaty 0:d974bcee4f69 357 // added by C. Pham
cdupaty 0:d974bcee4f69 358 if (_board==SX1272Chip) {
cdupaty 0:d974bcee4f69 359 // comment by C. Pham
cdupaty 0:d974bcee4f69 360 // 0x4A = 01 001 0 1 0
cdupaty 0:d974bcee4f69 361 // BW=250 CR=4/5 ImplicitH_off RxPayloadCrcOn_on LowDataRateOptimize_off
cdupaty 0:d974bcee4f69 362 writeRegister(0x1D,0x4A);
cdupaty 0:d974bcee4f69 363 // 1001 0 1 11
cdupaty 0:d974bcee4f69 364 // SF=9 TxContinuous_off AgcAutoOn SymbTimeOut
cdupaty 0:d974bcee4f69 365 writeRegister(0x1E,0x97);
cdupaty 0:d974bcee4f69 366 }
cdupaty 0:d974bcee4f69 367 else {
cdupaty 0:d974bcee4f69 368 // 1000 001 0
cdupaty 0:d974bcee4f69 369 // BW=250 CR=4/5 ImplicitH_off
cdupaty 0:d974bcee4f69 370 writeRegister(0x1D,0x82);
cdupaty 0:d974bcee4f69 371 // 1001 0 1 11
cdupaty 0:d974bcee4f69 372 // SF=9 TxContinuous_off RxPayloadCrcOn_on SymbTimeOut
cdupaty 0:d974bcee4f69 373 writeRegister(0x1E,0x97);
cdupaty 0:d974bcee4f69 374 }
cdupaty 0:d974bcee4f69 375 // end
cdupaty 0:d974bcee4f69 376
cdupaty 0:d974bcee4f69 377 writeRegister(0x1F,0xFF);
cdupaty 0:d974bcee4f69 378 writeRegister(0x20,0x0);
cdupaty 0:d974bcee4f69 379 writeRegister(0x21,0x8);
cdupaty 0:d974bcee4f69 380 writeRegister(0x22,0xFF);
cdupaty 0:d974bcee4f69 381 writeRegister(0x23,0xFF);
cdupaty 0:d974bcee4f69 382 writeRegister(0x24,0x0);
cdupaty 0:d974bcee4f69 383 writeRegister(0x25,0x0);
cdupaty 0:d974bcee4f69 384
cdupaty 0:d974bcee4f69 385 // added by C. Pham
cdupaty 0:d974bcee4f69 386 if (_board==SX1272Chip)
cdupaty 0:d974bcee4f69 387 writeRegister(0x26,0x0);
cdupaty 0:d974bcee4f69 388 else
cdupaty 0:d974bcee4f69 389 // 0000 0 1 00
cdupaty 0:d974bcee4f69 390 // reserved LowDataRateOptimize_off AgcAutoOn reserved
cdupaty 0:d974bcee4f69 391 writeRegister(0x26,0x04);
cdupaty 0:d974bcee4f69 392
cdupaty 0:d974bcee4f69 393 // REG_SYNC_CONFIG
cdupaty 0:d974bcee4f69 394 writeRegister(0x27,0x0);
cdupaty 0:d974bcee4f69 395
cdupaty 0:d974bcee4f69 396 writeRegister(0x28,0x0);
cdupaty 0:d974bcee4f69 397 writeRegister(0x29,0x0);
cdupaty 0:d974bcee4f69 398 writeRegister(0x2A,0x0);
cdupaty 0:d974bcee4f69 399 writeRegister(0x2B,0x0);
cdupaty 0:d974bcee4f69 400 writeRegister(0x2C,0x0);
cdupaty 0:d974bcee4f69 401 writeRegister(0x2D,0x50);
cdupaty 0:d974bcee4f69 402 writeRegister(0x2E,0x14);
cdupaty 0:d974bcee4f69 403 writeRegister(0x2F,0x40);
cdupaty 0:d974bcee4f69 404 writeRegister(0x30,0x0);
cdupaty 0:d974bcee4f69 405 writeRegister(0x31,0x3);
cdupaty 0:d974bcee4f69 406 writeRegister(0x32,0x5);
cdupaty 0:d974bcee4f69 407 writeRegister(0x33,0x27);
cdupaty 0:d974bcee4f69 408 writeRegister(0x34,0x1C);
cdupaty 0:d974bcee4f69 409 writeRegister(0x35,0xA);
cdupaty 0:d974bcee4f69 410 writeRegister(0x36,0x0);
cdupaty 0:d974bcee4f69 411 writeRegister(0x37,0xA);
cdupaty 0:d974bcee4f69 412 writeRegister(0x38,0x42);
cdupaty 0:d974bcee4f69 413 writeRegister(0x39,0x12);
cdupaty 0:d974bcee4f69 414 //writeRegister(0x3A,0x65);
cdupaty 0:d974bcee4f69 415 //writeRegister(0x3B,0x1D);
cdupaty 0:d974bcee4f69 416 //writeRegister(0x3C,0x1);
cdupaty 0:d974bcee4f69 417 //writeRegister(0x3D,0xA1);
cdupaty 0:d974bcee4f69 418 //writeRegister(0x3E,0x0);
cdupaty 0:d974bcee4f69 419 //writeRegister(0x3F,0x0);
cdupaty 0:d974bcee4f69 420 //writeRegister(0x40,0x0);
cdupaty 0:d974bcee4f69 421 //writeRegister(0x41,0x0);
cdupaty 0:d974bcee4f69 422 // commented by C. Pham
cdupaty 0:d974bcee4f69 423 // since now we handle also the SX1276
cdupaty 0:d974bcee4f69 424 //writeRegister(0x42,0x22);
cdupaty 0:d974bcee4f69 425 #endif
cdupaty 0:d974bcee4f69 426 // added by C. Pham
cdupaty 0:d974bcee4f69 427 // default sync word for non-LoRaWAN
cdupaty 0:d974bcee4f69 428 setSyncWord(_defaultSyncWord);
cdupaty 0:d974bcee4f69 429 getSyncWord();
cdupaty 0:d974bcee4f69 430 _defaultSyncWord=_syncWord;
cdupaty 0:d974bcee4f69 431
cdupaty 0:d974bcee4f69 432 #ifdef LIMIT_TOA
cdupaty 0:d974bcee4f69 433 uint16_t remainingToA=limitToA();
cdupaty 0:d974bcee4f69 434 printf("## Limit ToA ON ##");
cdupaty 0:d974bcee4f69 435 printf("cycle begins at ");
cdupaty 0:d974bcee4f69 436 Serial.print(_startToAcycle);
cdupaty 0:d974bcee4f69 437 printf(" cycle ends at ");
cdupaty 0:d974bcee4f69 438 Serial.print(_endToAcycle);
cdupaty 0:d974bcee4f69 439 printf(" remaining ToA is ");
cdupaty 0:d974bcee4f69 440 Serial.print(remainingToA);
cdupaty 0:d974bcee4f69 441 printf("\n");
cdupaty 0:d974bcee4f69 442 #endif
cdupaty 0:d974bcee4f69 443 //end
cdupaty 0:d974bcee4f69 444
cdupaty 0:d974bcee4f69 445 return state;
cdupaty 0:d974bcee4f69 446 }
cdupaty 0:d974bcee4f69 447
cdupaty 0:d974bcee4f69 448 /*
cdupaty 0:d974bcee4f69 449 Function: Sets the module OFF.
cdupaty 0:d974bcee4f69 450 Returns: Nothing
cdupaty 0:d974bcee4f69 451 */
cdupaty 0:d974bcee4f69 452 void SX1272::OFF()
cdupaty 0:d974bcee4f69 453 {
cdupaty 0:d974bcee4f69 454 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 455 printf("\n");
cdupaty 0:d974bcee4f69 456 printf("Starting 'OFF'\n");
cdupaty 0:d974bcee4f69 457 #endif
cdupaty 0:d974bcee4f69 458
cdupaty 0:d974bcee4f69 459 // ajoute par C.Dupaty
cdupaty 0:d974bcee4f69 460 //SPI.end();
cdupaty 0:d974bcee4f69 461
cdupaty 0:d974bcee4f69 462 // Powering the module
cdupaty 0:d974bcee4f69 463 // pinMode(SX1272_SS,OUTPUT);
cdupaty 0:d974bcee4f69 464 // digitalWrite(SX1272_SS,LOW);
cdupaty 0:d974bcee4f69 465 ss=0; // ????? !!!!!!!!!!!!!!!!!
cdupaty 0:d974bcee4f69 466 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 467 printf("## Setting OFF ##");
cdupaty 0:d974bcee4f69 468 printf("\n");
cdupaty 0:d974bcee4f69 469 #endif
cdupaty 0:d974bcee4f69 470 }
cdupaty 0:d974bcee4f69 471
cdupaty 0:d974bcee4f69 472 /*
cdupaty 0:d974bcee4f69 473 Function: Reads the indicated register.
cdupaty 0:d974bcee4f69 474 Returns: The content of the register
cdupaty 0:d974bcee4f69 475 Parameters:
cdupaty 0:d974bcee4f69 476 address: address register to read from
cdupaty 0:d974bcee4f69 477 */
cdupaty 0:d974bcee4f69 478 byte SX1272::readRegister(byte address)
cdupaty 0:d974bcee4f69 479 {
cdupaty 0:d974bcee4f69 480 byte value = 0x00;
cdupaty 0:d974bcee4f69 481
cdupaty 0:d974bcee4f69 482 //digitalWrite(SX1272_SS,LOW);
cdupaty 0:d974bcee4f69 483 ss=0;
cdupaty 0:d974bcee4f69 484 bitClear(address, 7); // Bit 7 cleared to write in registers
cdupaty 0:d974bcee4f69 485 // SPI.transfer(address);
cdupaty 0:d974bcee4f69 486 spi.write(address);
cdupaty 0:d974bcee4f69 487 //value = SPI.transfer(0x00);
cdupaty 0:d974bcee4f69 488 value = spi.write(0x00);
cdupaty 0:d974bcee4f69 489 //digitalWrite(SX1272_SS,HIGH);
cdupaty 0:d974bcee4f69 490 ss=1;
cdupaty 0:d974bcee4f69 491
cdupaty 0:d974bcee4f69 492 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 493 printf("## Reading: ");
cdupaty 0:d974bcee4f69 494 printf("Register 0x%02X : 0x%02X\n",address,value);
cdupaty 0:d974bcee4f69 495 // Serial.print(address, HEX);
cdupaty 0:d974bcee4f69 496 // printf(": ");
cdupaty 0:d974bcee4f69 497 // Serial.print(value, HEX);
cdupaty 0:d974bcee4f69 498 // printf("\n");
cdupaty 0:d974bcee4f69 499 #endif
cdupaty 0:d974bcee4f69 500
cdupaty 0:d974bcee4f69 501 return value;
cdupaty 0:d974bcee4f69 502 }
cdupaty 0:d974bcee4f69 503
cdupaty 0:d974bcee4f69 504 /*
cdupaty 0:d974bcee4f69 505 Function: Writes on the indicated register.
cdupaty 0:d974bcee4f69 506 Returns: Nothing
cdupaty 0:d974bcee4f69 507 Parameters:
cdupaty 0:d974bcee4f69 508 address: address register to write in
cdupaty 0:d974bcee4f69 509 data : value to write in the register
cdupaty 0:d974bcee4f69 510 */
cdupaty 0:d974bcee4f69 511 void SX1272::writeRegister(byte address, byte data)
cdupaty 0:d974bcee4f69 512 {
cdupaty 0:d974bcee4f69 513 //digitalWrite(SX1272_SS,LOW);
cdupaty 0:d974bcee4f69 514 ss=0;
cdupaty 0:d974bcee4f69 515 bitSet(address, 7); // Bit 7 set to read from registers
cdupaty 0:d974bcee4f69 516 //SPI.transfer(address);
cdupaty 0:d974bcee4f69 517 //SPI.transfer(data);
cdupaty 0:d974bcee4f69 518 spi.write(address);
cdupaty 0:d974bcee4f69 519 spi.write(data);
cdupaty 0:d974bcee4f69 520 // digitalWrite(SX1272_SS,HIGH);
cdupaty 0:d974bcee4f69 521 ss=1;
cdupaty 0:d974bcee4f69 522
cdupaty 0:d974bcee4f69 523 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 524 printf("## Writing: Register ");
cdupaty 0:d974bcee4f69 525 bitClear(address, 7);
cdupaty 0:d974bcee4f69 526 printf("0x%02X : 0x%02X\n",address,data);
cdupaty 0:d974bcee4f69 527 // Serial.print(address, HEX);
cdupaty 0:d974bcee4f69 528 // printf(": ");
cdupaty 0:d974bcee4f69 529 // Serial.print(data, HEX);
cdupaty 0:d974bcee4f69 530 // printf("\n");
cdupaty 0:d974bcee4f69 531 #endif
cdupaty 0:d974bcee4f69 532
cdupaty 0:d974bcee4f69 533 }
cdupaty 0:d974bcee4f69 534
cdupaty 0:d974bcee4f69 535 /*
cdupaty 0:d974bcee4f69 536 Function: Clears the interruption flags
cdupaty 0:d974bcee4f69 537 Returns: Nothing
cdupaty 0:d974bcee4f69 538 */
cdupaty 0:d974bcee4f69 539 void SX1272::clearFlags()
cdupaty 0:d974bcee4f69 540 {
cdupaty 0:d974bcee4f69 541 byte st0;
cdupaty 0:d974bcee4f69 542
cdupaty 0:d974bcee4f69 543 st0 = readRegister(REG_OP_MODE); // Save the previous status
cdupaty 0:d974bcee4f69 544
cdupaty 0:d974bcee4f69 545 if( _modem == LORA )
cdupaty 0:d974bcee4f69 546 { // LoRa mode
cdupaty 0:d974bcee4f69 547 writeRegister(REG_OP_MODE, LORA_STANDBY_MODE); // Stdby mode to write in registers
cdupaty 0:d974bcee4f69 548 writeRegister(REG_IRQ_FLAGS, 0xFF); // LoRa mode flags register
cdupaty 0:d974bcee4f69 549 writeRegister(REG_OP_MODE, st0); // Getting back to previous status
cdupaty 0:d974bcee4f69 550 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 551 printf("## LoRa flags cleared ##\n");
cdupaty 0:d974bcee4f69 552 #endif
cdupaty 0:d974bcee4f69 553 }
cdupaty 0:d974bcee4f69 554 else
cdupaty 0:d974bcee4f69 555 { // FSK mode
cdupaty 0:d974bcee4f69 556 writeRegister(REG_OP_MODE, FSK_STANDBY_MODE); // Stdby mode to write in registers
cdupaty 0:d974bcee4f69 557 writeRegister(REG_IRQ_FLAGS1, 0xFF); // FSK mode flags1 register
cdupaty 0:d974bcee4f69 558 writeRegister(REG_IRQ_FLAGS2, 0xFF); // FSK mode flags2 register
cdupaty 0:d974bcee4f69 559 writeRegister(REG_OP_MODE, st0); // Getting back to previous status
cdupaty 0:d974bcee4f69 560 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 561 printf("## FSK flags cleared ##");
cdupaty 0:d974bcee4f69 562 #endif
cdupaty 0:d974bcee4f69 563 }
cdupaty 0:d974bcee4f69 564 }
cdupaty 0:d974bcee4f69 565
cdupaty 0:d974bcee4f69 566 /*
cdupaty 0:d974bcee4f69 567 Function: Sets the module in LoRa mode.
cdupaty 0:d974bcee4f69 568 Returns: Integer that determines if there has been any error
cdupaty 0:d974bcee4f69 569 state = 2 --> The command has not been executed
cdupaty 0:d974bcee4f69 570 state = 1 --> There has been an error while executing the command
cdupaty 0:d974bcee4f69 571 state = 0 --> The command has been executed with no errors
cdupaty 0:d974bcee4f69 572 */
cdupaty 0:d974bcee4f69 573 uint8_t SX1272::setLORA()
cdupaty 0:d974bcee4f69 574 {
cdupaty 0:d974bcee4f69 575 uint8_t state = 2;
cdupaty 0:d974bcee4f69 576 byte st0;
cdupaty 0:d974bcee4f69 577
cdupaty 0:d974bcee4f69 578 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 579 printf("\n");
cdupaty 0:d974bcee4f69 580 printf("Starting 'setLORA'\n");
cdupaty 0:d974bcee4f69 581 #endif
cdupaty 0:d974bcee4f69 582
cdupaty 0:d974bcee4f69 583 // modified by C. Pham
cdupaty 0:d974bcee4f69 584 uint8_t retry=0;
cdupaty 0:d974bcee4f69 585
cdupaty 0:d974bcee4f69 586 do {
cdupaty 0:d974bcee4f69 587 wait_ms(200);
cdupaty 0:d974bcee4f69 588 writeRegister(REG_OP_MODE, FSK_SLEEP_MODE); // Sleep mode (mandatory to set LoRa mode)
cdupaty 0:d974bcee4f69 589 writeRegister(REG_OP_MODE, LORA_SLEEP_MODE); // LoRa sleep mode
cdupaty 0:d974bcee4f69 590 writeRegister(REG_OP_MODE, LORA_STANDBY_MODE);
cdupaty 0:d974bcee4f69 591 wait_ms(50+retry*10);
cdupaty 0:d974bcee4f69 592 st0 = readRegister(REG_OP_MODE);
cdupaty 0:d974bcee4f69 593 printf("...");
cdupaty 0:d974bcee4f69 594
cdupaty 0:d974bcee4f69 595 if ((retry % 2)==0)
cdupaty 0:d974bcee4f69 596 if (retry==20)
cdupaty 0:d974bcee4f69 597 retry=0;
cdupaty 0:d974bcee4f69 598 else
cdupaty 0:d974bcee4f69 599 retry++;
cdupaty 0:d974bcee4f69 600 /*
cdupaty 0:d974bcee4f69 601 if (st0!=LORA_STANDBY_MODE) {
cdupaty 0:d974bcee4f69 602 pinMode(SX1272_RST,OUTPUT);
cdupaty 0:d974bcee4f69 603 digitalWrite(SX1272_RST,HIGH);
cdupaty 0:d974bcee4f69 604 wait_ms(100);
cdupaty 0:d974bcee4f69 605 digitalWrite(SX1272_RST,LOW);
cdupaty 0:d974bcee4f69 606 }
cdupaty 0:d974bcee4f69 607 */
cdupaty 0:d974bcee4f69 608
cdupaty 0:d974bcee4f69 609 } while (st0!=LORA_STANDBY_MODE); // LoRa standby mode
cdupaty 0:d974bcee4f69 610
cdupaty 0:d974bcee4f69 611 if( st0 == LORA_STANDBY_MODE)
cdupaty 0:d974bcee4f69 612 { // LoRa mode
cdupaty 0:d974bcee4f69 613 _modem = LORA;
cdupaty 0:d974bcee4f69 614 state = 0;
cdupaty 0:d974bcee4f69 615 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 616 printf("## LoRa set with success ##");
cdupaty 0:d974bcee4f69 617 printf("\n");
cdupaty 0:d974bcee4f69 618 #endif
cdupaty 0:d974bcee4f69 619 }
cdupaty 0:d974bcee4f69 620 else
cdupaty 0:d974bcee4f69 621 { // FSK mode
cdupaty 0:d974bcee4f69 622 _modem = FSK;
cdupaty 0:d974bcee4f69 623 state = 1;
cdupaty 0:d974bcee4f69 624 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 625 printf("** There has been an error while setting LoRa **");
cdupaty 0:d974bcee4f69 626 printf("\n");
cdupaty 0:d974bcee4f69 627 #endif
cdupaty 0:d974bcee4f69 628 }
cdupaty 0:d974bcee4f69 629 return state;
cdupaty 0:d974bcee4f69 630 }
cdupaty 0:d974bcee4f69 631
cdupaty 0:d974bcee4f69 632 /*
cdupaty 0:d974bcee4f69 633 Function: Sets the module in FSK mode.
cdupaty 0:d974bcee4f69 634 Returns: Integer that determines if there has been any error
cdupaty 0:d974bcee4f69 635 state = 2 --> The command has not been executed
cdupaty 0:d974bcee4f69 636 state = 1 --> There has been an error while executing the command
cdupaty 0:d974bcee4f69 637 state = 0 --> The command has been executed with no errors
cdupaty 0:d974bcee4f69 638 */
cdupaty 0:d974bcee4f69 639 uint8_t SX1272::setFSK()
cdupaty 0:d974bcee4f69 640 {
cdupaty 0:d974bcee4f69 641 uint8_t state = 2;
cdupaty 0:d974bcee4f69 642 byte st0;
cdupaty 0:d974bcee4f69 643 byte config1;
cdupaty 0:d974bcee4f69 644
cdupaty 0:d974bcee4f69 645 if (_board==SX1276Chip)
cdupaty 0:d974bcee4f69 646 printf("Warning: FSK has not been tested on SX1276!");
cdupaty 0:d974bcee4f69 647
cdupaty 0:d974bcee4f69 648 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 649 printf("\n");
cdupaty 0:d974bcee4f69 650 printf("Starting 'setFSK'\n");
cdupaty 0:d974bcee4f69 651 #endif
cdupaty 0:d974bcee4f69 652
cdupaty 0:d974bcee4f69 653 writeRegister(REG_OP_MODE, FSK_SLEEP_MODE); // Sleep mode (mandatory to change mode)
cdupaty 0:d974bcee4f69 654 writeRegister(REG_OP_MODE, FSK_STANDBY_MODE); // FSK standby mode
cdupaty 0:d974bcee4f69 655 config1 = readRegister(REG_PACKET_CONFIG1);
cdupaty 0:d974bcee4f69 656 config1 = config1 & 0B01111101; // clears bits 8 and 1 from REG_PACKET_CONFIG1
cdupaty 0:d974bcee4f69 657 config1 = config1 | 0B00000100; // sets bit 2 from REG_PACKET_CONFIG1
cdupaty 0:d974bcee4f69 658 writeRegister(REG_PACKET_CONFIG1,config1); // AddressFiltering = NodeAddress + BroadcastAddress
cdupaty 0:d974bcee4f69 659 writeRegister(REG_FIFO_THRESH, 0x80); // condition to start packet tx
cdupaty 0:d974bcee4f69 660 config1 = readRegister(REG_SYNC_CONFIG);
cdupaty 0:d974bcee4f69 661 config1 = config1 & 0B00111111;
cdupaty 0:d974bcee4f69 662 writeRegister(REG_SYNC_CONFIG,config1);
cdupaty 0:d974bcee4f69 663
cdupaty 0:d974bcee4f69 664 wait_ms(100);
cdupaty 0:d974bcee4f69 665
cdupaty 0:d974bcee4f69 666 st0 = readRegister(REG_OP_MODE); // Reading config mode
cdupaty 0:d974bcee4f69 667 if( st0 == FSK_STANDBY_MODE )
cdupaty 0:d974bcee4f69 668 { // FSK mode
cdupaty 0:d974bcee4f69 669 _modem = FSK;
cdupaty 0:d974bcee4f69 670 state = 0;
cdupaty 0:d974bcee4f69 671 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 672 printf("## FSK set with success ##");
cdupaty 0:d974bcee4f69 673 printf("\n");
cdupaty 0:d974bcee4f69 674 #endif
cdupaty 0:d974bcee4f69 675 }
cdupaty 0:d974bcee4f69 676 else
cdupaty 0:d974bcee4f69 677 { // LoRa mode
cdupaty 0:d974bcee4f69 678 _modem = LORA;
cdupaty 0:d974bcee4f69 679 state = 1;
cdupaty 0:d974bcee4f69 680 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 681 printf("** There has been an error while setting FSK **");
cdupaty 0:d974bcee4f69 682 printf("\n");
cdupaty 0:d974bcee4f69 683 #endif
cdupaty 0:d974bcee4f69 684 }
cdupaty 0:d974bcee4f69 685 return state;
cdupaty 0:d974bcee4f69 686 }
cdupaty 0:d974bcee4f69 687
cdupaty 0:d974bcee4f69 688 /*
cdupaty 0:d974bcee4f69 689 Function: Gets the bandwidth, coding rate and spreading factor of the LoRa modulation.
cdupaty 0:d974bcee4f69 690 Returns: Integer that determines if there has been any error
cdupaty 0:d974bcee4f69 691 state = 2 --> The command has not been executed
cdupaty 0:d974bcee4f69 692 state = 1 --> There has been an error while executing the command
cdupaty 0:d974bcee4f69 693 state = 0 --> The command has been executed with no errors
cdupaty 0:d974bcee4f69 694 */
cdupaty 0:d974bcee4f69 695 uint8_t SX1272::getMode()
cdupaty 0:d974bcee4f69 696 {
cdupaty 0:d974bcee4f69 697 byte st0;
cdupaty 0:d974bcee4f69 698 int8_t state = 2;
cdupaty 0:d974bcee4f69 699 byte value = 0x00;
cdupaty 0:d974bcee4f69 700
cdupaty 0:d974bcee4f69 701 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 702 printf("\n");
cdupaty 0:d974bcee4f69 703 printf("Starting 'getMode'\n");
cdupaty 0:d974bcee4f69 704 #endif
cdupaty 0:d974bcee4f69 705
cdupaty 0:d974bcee4f69 706 st0 = readRegister(REG_OP_MODE); // Save the previous status
cdupaty 0:d974bcee4f69 707 if( _modem == FSK )
cdupaty 0:d974bcee4f69 708 {
cdupaty 0:d974bcee4f69 709 setLORA(); // Setting LoRa mode
cdupaty 0:d974bcee4f69 710 }
cdupaty 0:d974bcee4f69 711 value = readRegister(REG_MODEM_CONFIG1);
cdupaty 0:d974bcee4f69 712 // added by C. Pham
cdupaty 0:d974bcee4f69 713 if (_board==SX1272Chip) {
cdupaty 0:d974bcee4f69 714 _bandwidth = (value >> 6); // Storing 2 MSB from REG_MODEM_CONFIG1 (=_bandwidth)
cdupaty 0:d974bcee4f69 715 // added by C. Pham
cdupaty 0:d974bcee4f69 716 // convert to common bandwidth values used by both SX1272 and SX1276
cdupaty 0:d974bcee4f69 717 _bandwidth += 7;
cdupaty 0:d974bcee4f69 718 }
cdupaty 0:d974bcee4f69 719 else
cdupaty 0:d974bcee4f69 720 _bandwidth = (value >> 4); // Storing 4 MSB from REG_MODEM_CONFIG1 (=_bandwidth)
cdupaty 0:d974bcee4f69 721
cdupaty 0:d974bcee4f69 722 if (_board==SX1272Chip)
cdupaty 0:d974bcee4f69 723 _codingRate = (value >> 3) & 0x07; // Storing third, forth and fifth bits from
cdupaty 0:d974bcee4f69 724 else
cdupaty 0:d974bcee4f69 725 _codingRate = (value >> 1) & 0x07; // Storing 3-1 bits REG_MODEM_CONFIG1 (=_codingRate)
cdupaty 0:d974bcee4f69 726
cdupaty 0:d974bcee4f69 727 value = readRegister(REG_MODEM_CONFIG2);
cdupaty 0:d974bcee4f69 728 _spreadingFactor = (value >> 4) & 0x0F; // Storing 4 MSB from REG_MODEM_CONFIG2 (=_spreadingFactor)
cdupaty 0:d974bcee4f69 729 state = 1;
cdupaty 0:d974bcee4f69 730
cdupaty 0:d974bcee4f69 731 if( isBW(_bandwidth) ) // Checking available values for:
cdupaty 0:d974bcee4f69 732 { // _bandwidth
cdupaty 0:d974bcee4f69 733 if( isCR(_codingRate) ) // _codingRate
cdupaty 0:d974bcee4f69 734 { // _spreadingFactor
cdupaty 0:d974bcee4f69 735 if( isSF(_spreadingFactor) )
cdupaty 0:d974bcee4f69 736 {
cdupaty 0:d974bcee4f69 737 state = 0;
cdupaty 0:d974bcee4f69 738 }
cdupaty 0:d974bcee4f69 739 }
cdupaty 0:d974bcee4f69 740 }
cdupaty 0:d974bcee4f69 741
cdupaty 0:d974bcee4f69 742 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 743 printf("## Parameters from configuration mode are:");
cdupaty 0:d974bcee4f69 744 printf("Bandwidth: %X\n",_bandwidth);
cdupaty 0:d974bcee4f69 745 // Serial.print(_bandwidth, HEX);
cdupaty 0:d974bcee4f69 746 // printf("\n");
cdupaty 0:d974bcee4f69 747 printf("\t Coding Rate: %X\n",_codingRate);
cdupaty 0:d974bcee4f69 748 // Serial.print(_codingRate, HEX);
cdupaty 0:d974bcee4f69 749 // printf("\n");
cdupaty 0:d974bcee4f69 750 printf("\t Spreading Factor: %X\n",_spreadingFactor);
cdupaty 0:d974bcee4f69 751 // Serial.print(_spreadingFactor, HEX);
cdupaty 0:d974bcee4f69 752 printf(" ##");
cdupaty 0:d974bcee4f69 753 printf("\n");
cdupaty 0:d974bcee4f69 754 #endif
cdupaty 0:d974bcee4f69 755
cdupaty 0:d974bcee4f69 756 writeRegister(REG_OP_MODE, st0); // Getting back to previous status
cdupaty 0:d974bcee4f69 757 wait_ms(100);
cdupaty 0:d974bcee4f69 758 return state;
cdupaty 0:d974bcee4f69 759 }
cdupaty 0:d974bcee4f69 760
cdupaty 0:d974bcee4f69 761 /*
cdupaty 0:d974bcee4f69 762 Function: Sets the bandwidth, coding rate and spreading factor of the LoRa modulation.
cdupaty 0:d974bcee4f69 763 Returns: Integer that determines if there has been any error
cdupaty 0:d974bcee4f69 764 state = 2 --> The command has not been executed
cdupaty 0:d974bcee4f69 765 state = 1 --> There has been an error while executing the command
cdupaty 0:d974bcee4f69 766 state = 0 --> The command has been executed with no errors
cdupaty 0:d974bcee4f69 767 state = -1 --> Forbidden command for this protocol
cdupaty 0:d974bcee4f69 768 Parameters:
cdupaty 0:d974bcee4f69 769 mode: mode number to set the required BW, SF and CR of LoRa modem.
cdupaty 0:d974bcee4f69 770 */
cdupaty 0:d974bcee4f69 771 int8_t SX1272::setMode(uint8_t mode)
cdupaty 0:d974bcee4f69 772 {
cdupaty 0:d974bcee4f69 773 int8_t state = 2;
cdupaty 0:d974bcee4f69 774 byte st0;
cdupaty 0:d974bcee4f69 775 byte config1 = 0x00;
cdupaty 0:d974bcee4f69 776 byte config2 = 0x00;
cdupaty 0:d974bcee4f69 777
cdupaty 0:d974bcee4f69 778 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 779 printf("\n");
cdupaty 0:d974bcee4f69 780 printf("Starting 'setMode'\n");
cdupaty 0:d974bcee4f69 781 #endif
cdupaty 0:d974bcee4f69 782
cdupaty 0:d974bcee4f69 783 st0 = readRegister(REG_OP_MODE); // Save the previous status
cdupaty 0:d974bcee4f69 784
cdupaty 0:d974bcee4f69 785 if( _modem == FSK )
cdupaty 0:d974bcee4f69 786 {
cdupaty 0:d974bcee4f69 787 setLORA();
cdupaty 0:d974bcee4f69 788 }
cdupaty 0:d974bcee4f69 789 writeRegister(REG_OP_MODE, LORA_STANDBY_MODE); // LoRa standby mode
cdupaty 0:d974bcee4f69 790
cdupaty 0:d974bcee4f69 791 switch (mode)
cdupaty 0:d974bcee4f69 792 {
cdupaty 0:d974bcee4f69 793 // mode 1 (better reach, medium time on air)
cdupaty 0:d974bcee4f69 794 case 1:
cdupaty 0:d974bcee4f69 795 setCR(CR_5); // CR = 4/5
cdupaty 0:d974bcee4f69 796 setSF(SF_12); // SF = 12
cdupaty 0:d974bcee4f69 797 setBW(BW_125); // BW = 125 KHz
cdupaty 0:d974bcee4f69 798 break;
cdupaty 0:d974bcee4f69 799
cdupaty 0:d974bcee4f69 800 // mode 2 (medium reach, less time on air)
cdupaty 0:d974bcee4f69 801 case 2:
cdupaty 0:d974bcee4f69 802 setCR(CR_5); // CR = 4/5
cdupaty 0:d974bcee4f69 803 setSF(SF_12); // SF = 12
cdupaty 0:d974bcee4f69 804 setBW(BW_250); // BW = 250 KHz
cdupaty 0:d974bcee4f69 805 break;
cdupaty 0:d974bcee4f69 806
cdupaty 0:d974bcee4f69 807 // mode 3 (worst reach, less time on air)
cdupaty 0:d974bcee4f69 808 case 3:
cdupaty 0:d974bcee4f69 809 setCR(CR_5); // CR = 4/5
cdupaty 0:d974bcee4f69 810 setSF(SF_10); // SF = 10
cdupaty 0:d974bcee4f69 811 setBW(BW_125); // BW = 125 KHz
cdupaty 0:d974bcee4f69 812 break;
cdupaty 0:d974bcee4f69 813
cdupaty 0:d974bcee4f69 814 // mode 4 (better reach, low time on air)
cdupaty 0:d974bcee4f69 815 case 4:
cdupaty 0:d974bcee4f69 816 setCR(CR_5); // CR = 4/5
cdupaty 0:d974bcee4f69 817 setSF(SF_12); // SF = 12
cdupaty 0:d974bcee4f69 818 setBW(BW_500); // BW = 500 KHz
cdupaty 0:d974bcee4f69 819 break;
cdupaty 0:d974bcee4f69 820
cdupaty 0:d974bcee4f69 821 // mode 5 (better reach, medium time on air)
cdupaty 0:d974bcee4f69 822 case 5:
cdupaty 0:d974bcee4f69 823 setCR(CR_5); // CR = 4/5
cdupaty 0:d974bcee4f69 824 setSF(SF_10); // SF = 10
cdupaty 0:d974bcee4f69 825 setBW(BW_250); // BW = 250 KHz
cdupaty 0:d974bcee4f69 826 break;
cdupaty 0:d974bcee4f69 827
cdupaty 0:d974bcee4f69 828 // mode 6 (better reach, worst time-on-air)
cdupaty 0:d974bcee4f69 829 case 6:
cdupaty 0:d974bcee4f69 830 setCR(CR_5); // CR = 4/5
cdupaty 0:d974bcee4f69 831 setSF(SF_11); // SF = 11
cdupaty 0:d974bcee4f69 832 setBW(BW_500); // BW = 500 KHz
cdupaty 0:d974bcee4f69 833 break;
cdupaty 0:d974bcee4f69 834
cdupaty 0:d974bcee4f69 835 // mode 7 (medium-high reach, medium-low time-on-air)
cdupaty 0:d974bcee4f69 836 case 7:
cdupaty 0:d974bcee4f69 837 setCR(CR_5); // CR = 4/5
cdupaty 0:d974bcee4f69 838 setSF(SF_9); // SF = 9
cdupaty 0:d974bcee4f69 839 setBW(BW_250); // BW = 250 KHz
cdupaty 0:d974bcee4f69 840 break;
cdupaty 0:d974bcee4f69 841
cdupaty 0:d974bcee4f69 842 // mode 8 (medium reach, medium time-on-air)
cdupaty 0:d974bcee4f69 843 case 8:
cdupaty 0:d974bcee4f69 844 setCR(CR_5); // CR = 4/5
cdupaty 0:d974bcee4f69 845 setSF(SF_9); // SF = 9
cdupaty 0:d974bcee4f69 846 setBW(BW_500); // BW = 500 KHz
cdupaty 0:d974bcee4f69 847 break;
cdupaty 0:d974bcee4f69 848
cdupaty 0:d974bcee4f69 849 // mode 9 (medium-low reach, medium-high time-on-air)
cdupaty 0:d974bcee4f69 850 case 9:
cdupaty 0:d974bcee4f69 851 setCR(CR_5); // CR = 4/5
cdupaty 0:d974bcee4f69 852 setSF(SF_8); // SF = 8
cdupaty 0:d974bcee4f69 853 setBW(BW_500); // BW = 500 KHz
cdupaty 0:d974bcee4f69 854 break;
cdupaty 0:d974bcee4f69 855
cdupaty 0:d974bcee4f69 856 // mode 10 (worst reach, less time_on_air)
cdupaty 0:d974bcee4f69 857 case 10:
cdupaty 0:d974bcee4f69 858 setCR(CR_5); // CR = 4/5
cdupaty 0:d974bcee4f69 859 setSF(SF_7); // SF = 7
cdupaty 0:d974bcee4f69 860 setBW(BW_500); // BW = 500 KHz
cdupaty 0:d974bcee4f69 861 break;
cdupaty 0:d974bcee4f69 862
cdupaty 0:d974bcee4f69 863 // added by C. Pham
cdupaty 0:d974bcee4f69 864 // test for LoRaWAN channel
cdupaty 0:d974bcee4f69 865 case 11:
cdupaty 0:d974bcee4f69 866 setCR(CR_5); // CR = 4/5
cdupaty 0:d974bcee4f69 867 setSF(SF_12); // SF = 12
cdupaty 0:d974bcee4f69 868 setBW(BW_125); // BW = 125 KHz
cdupaty 0:d974bcee4f69 869 // set the sync word to the LoRaWAN sync word which is 0x34
cdupaty 0:d974bcee4f69 870 setSyncWord(0x34);
cdupaty 0:d974bcee4f69 871 printf("** Using sync word of 0x%X\n",_syncWord);
cdupaty 0:d974bcee4f69 872 // Serial.println(_syncWord, HEX);
cdupaty 0:d974bcee4f69 873 break;
cdupaty 0:d974bcee4f69 874
cdupaty 0:d974bcee4f69 875 default: state = -1; // The indicated mode doesn't exist
cdupaty 0:d974bcee4f69 876
cdupaty 0:d974bcee4f69 877 };
cdupaty 0:d974bcee4f69 878
cdupaty 0:d974bcee4f69 879 if( state == -1 ) // if state = -1, don't change its value
cdupaty 0:d974bcee4f69 880 {
cdupaty 0:d974bcee4f69 881 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 882 printf("** The indicated mode doesn't exist, ");
cdupaty 0:d974bcee4f69 883 printf("please select from 1 to 10 **");
cdupaty 0:d974bcee4f69 884 #endif
cdupaty 0:d974bcee4f69 885 }
cdupaty 0:d974bcee4f69 886 else
cdupaty 0:d974bcee4f69 887 {
cdupaty 0:d974bcee4f69 888 state = 1;
cdupaty 0:d974bcee4f69 889 config1 = readRegister(REG_MODEM_CONFIG1);
cdupaty 0:d974bcee4f69 890 switch (mode)
cdupaty 0:d974bcee4f69 891 { // Different way to check for each mode:
cdupaty 0:d974bcee4f69 892 // (config1 >> 3) ---> take out bits 7-3 from REG_MODEM_CONFIG1 (=_bandwidth & _codingRate together)
cdupaty 0:d974bcee4f69 893 // (config2 >> 4) ---> take out bits 7-4 from REG_MODEM_CONFIG2 (=_spreadingFactor)
cdupaty 0:d974bcee4f69 894
cdupaty 0:d974bcee4f69 895 // mode 1: BW = 125 KHz, CR = 4/5, SF = 12.
cdupaty 0:d974bcee4f69 896 case 1:
cdupaty 0:d974bcee4f69 897
cdupaty 0:d974bcee4f69 898 //modified by C. Pham
cdupaty 0:d974bcee4f69 899 if (_board==SX1272Chip) {
cdupaty 0:d974bcee4f69 900 //////////////////////////////////////////////possible pb sur config1 qui vaut 0
cdupaty 0:d974bcee4f69 901 if( (config1 >> 3) == 0x01 )
cdupaty 0:d974bcee4f69 902 state=0;
cdupaty 0:d974bcee4f69 903 }
cdupaty 0:d974bcee4f69 904 else {
cdupaty 0:d974bcee4f69 905 // (config1 >> 1) ---> take out bits 7-1 from REG_MODEM_CONFIG1 (=_bandwidth & _codingRate together)
cdupaty 0:d974bcee4f69 906 if( (config1 >> 1) == 0x39 )
cdupaty 0:d974bcee4f69 907 state=0;
cdupaty 0:d974bcee4f69 908 }
cdupaty 0:d974bcee4f69 909
cdupaty 0:d974bcee4f69 910 if( state==0) {
cdupaty 0:d974bcee4f69 911 state = 1;
cdupaty 0:d974bcee4f69 912 config2 = readRegister(REG_MODEM_CONFIG2);
cdupaty 0:d974bcee4f69 913
cdupaty 0:d974bcee4f69 914 if( (config2 >> 4) == SF_12 )
cdupaty 0:d974bcee4f69 915 {
cdupaty 0:d974bcee4f69 916 state = 0;
cdupaty 0:d974bcee4f69 917 }
cdupaty 0:d974bcee4f69 918 }
cdupaty 0:d974bcee4f69 919 break;
cdupaty 0:d974bcee4f69 920
cdupaty 0:d974bcee4f69 921
cdupaty 0:d974bcee4f69 922 // mode 2: BW = 250 KHz, CR = 4/5, SF = 12.
cdupaty 0:d974bcee4f69 923 case 2:
cdupaty 0:d974bcee4f69 924
cdupaty 0:d974bcee4f69 925 //modified by C. Pham
cdupaty 0:d974bcee4f69 926 if (_board==SX1272Chip) {
cdupaty 0:d974bcee4f69 927 if( (config1 >> 3) == 0x09 )
cdupaty 0:d974bcee4f69 928 state=0;
cdupaty 0:d974bcee4f69 929 }
cdupaty 0:d974bcee4f69 930 else {
cdupaty 0:d974bcee4f69 931 // (config1 >> 1) ---> take out bits 7-1 from REG_MODEM_CONFIG1 (=_bandwidth & _codingRate together)
cdupaty 0:d974bcee4f69 932 if( (config1 >> 1) == 0x41 )
cdupaty 0:d974bcee4f69 933 state=0;
cdupaty 0:d974bcee4f69 934 }
cdupaty 0:d974bcee4f69 935
cdupaty 0:d974bcee4f69 936 if( state==0) {
cdupaty 0:d974bcee4f69 937 state = 1;
cdupaty 0:d974bcee4f69 938 config2 = readRegister(REG_MODEM_CONFIG2);
cdupaty 0:d974bcee4f69 939
cdupaty 0:d974bcee4f69 940 if( (config2 >> 4) == SF_12 )
cdupaty 0:d974bcee4f69 941 {
cdupaty 0:d974bcee4f69 942 state = 0;
cdupaty 0:d974bcee4f69 943 }
cdupaty 0:d974bcee4f69 944 }
cdupaty 0:d974bcee4f69 945 break;
cdupaty 0:d974bcee4f69 946
cdupaty 0:d974bcee4f69 947 // mode 3: BW = 125 KHz, CR = 4/5, SF = 10.
cdupaty 0:d974bcee4f69 948 case 3:
cdupaty 0:d974bcee4f69 949
cdupaty 0:d974bcee4f69 950 //modified by C. Pham
cdupaty 0:d974bcee4f69 951 if (_board==SX1272Chip) {
cdupaty 0:d974bcee4f69 952 if( (config1 >> 3) == 0x01 )
cdupaty 0:d974bcee4f69 953 state=0;
cdupaty 0:d974bcee4f69 954 }
cdupaty 0:d974bcee4f69 955 else {
cdupaty 0:d974bcee4f69 956 // (config1 >> 1) ---> take out bits 7-1 from REG_MODEM_CONFIG1 (=_bandwidth & _codingRate together)
cdupaty 0:d974bcee4f69 957 if( (config1 >> 1) == 0x39 )
cdupaty 0:d974bcee4f69 958 state=0;
cdupaty 0:d974bcee4f69 959 }
cdupaty 0:d974bcee4f69 960
cdupaty 0:d974bcee4f69 961 if( state==0) {
cdupaty 0:d974bcee4f69 962 state = 1;
cdupaty 0:d974bcee4f69 963 config2 = readRegister(REG_MODEM_CONFIG2);
cdupaty 0:d974bcee4f69 964
cdupaty 0:d974bcee4f69 965 if( (config2 >> 4) == SF_10 )
cdupaty 0:d974bcee4f69 966 {
cdupaty 0:d974bcee4f69 967 state = 0;
cdupaty 0:d974bcee4f69 968 }
cdupaty 0:d974bcee4f69 969 }
cdupaty 0:d974bcee4f69 970 break;
cdupaty 0:d974bcee4f69 971
cdupaty 0:d974bcee4f69 972 // mode 4: BW = 500 KHz, CR = 4/5, SF = 12.
cdupaty 0:d974bcee4f69 973 case 4:
cdupaty 0:d974bcee4f69 974
cdupaty 0:d974bcee4f69 975 //modified by C. Pham
cdupaty 0:d974bcee4f69 976 if (_board==SX1272Chip) {
cdupaty 0:d974bcee4f69 977 if( (config1 >> 3) == 0x11 )
cdupaty 0:d974bcee4f69 978 state=0;
cdupaty 0:d974bcee4f69 979 }
cdupaty 0:d974bcee4f69 980 else {
cdupaty 0:d974bcee4f69 981 // (config1 >> 1) ---> take out bits 7-1 from REG_MODEM_CONFIG1 (=_bandwidth & _codingRate together)
cdupaty 0:d974bcee4f69 982 if( (config1 >> 1) == 0x49 )
cdupaty 0:d974bcee4f69 983 state=0;
cdupaty 0:d974bcee4f69 984 }
cdupaty 0:d974bcee4f69 985
cdupaty 0:d974bcee4f69 986 if( state==0) {
cdupaty 0:d974bcee4f69 987 state = 1;
cdupaty 0:d974bcee4f69 988 config2 = readRegister(REG_MODEM_CONFIG2);
cdupaty 0:d974bcee4f69 989
cdupaty 0:d974bcee4f69 990 if( (config2 >> 4) == SF_12 )
cdupaty 0:d974bcee4f69 991 {
cdupaty 0:d974bcee4f69 992 state = 0;
cdupaty 0:d974bcee4f69 993 }
cdupaty 0:d974bcee4f69 994 }
cdupaty 0:d974bcee4f69 995 break;
cdupaty 0:d974bcee4f69 996
cdupaty 0:d974bcee4f69 997 // mode 5: BW = 250 KHz, CR = 4/5, SF = 10.
cdupaty 0:d974bcee4f69 998 case 5:
cdupaty 0:d974bcee4f69 999
cdupaty 0:d974bcee4f69 1000 //modified by C. Pham
cdupaty 0:d974bcee4f69 1001 if (_board==SX1272Chip) {
cdupaty 0:d974bcee4f69 1002 if( (config1 >> 3) == 0x09 )
cdupaty 0:d974bcee4f69 1003 state=0;
cdupaty 0:d974bcee4f69 1004 }
cdupaty 0:d974bcee4f69 1005 else {
cdupaty 0:d974bcee4f69 1006 // (config1 >> 1) ---> take out bits 7-1 from REG_MODEM_CONFIG1 (=_bandwidth & _codingRate together)
cdupaty 0:d974bcee4f69 1007 if( (config1 >> 1) == 0x41 )
cdupaty 0:d974bcee4f69 1008 state=0;
cdupaty 0:d974bcee4f69 1009 }
cdupaty 0:d974bcee4f69 1010
cdupaty 0:d974bcee4f69 1011 if( state==0) {
cdupaty 0:d974bcee4f69 1012 state = 1;
cdupaty 0:d974bcee4f69 1013 config2 = readRegister(REG_MODEM_CONFIG2);
cdupaty 0:d974bcee4f69 1014
cdupaty 0:d974bcee4f69 1015 if( (config2 >> 4) == SF_10 )
cdupaty 0:d974bcee4f69 1016 {
cdupaty 0:d974bcee4f69 1017 state = 0;
cdupaty 0:d974bcee4f69 1018 }
cdupaty 0:d974bcee4f69 1019 }
cdupaty 0:d974bcee4f69 1020 break;
cdupaty 0:d974bcee4f69 1021
cdupaty 0:d974bcee4f69 1022 // mode 6: BW = 500 KHz, CR = 4/5, SF = 11.
cdupaty 0:d974bcee4f69 1023 case 6:
cdupaty 0:d974bcee4f69 1024
cdupaty 0:d974bcee4f69 1025 //modified by C. Pham
cdupaty 0:d974bcee4f69 1026 if (_board==SX1272Chip) {
cdupaty 0:d974bcee4f69 1027 if( (config1 >> 3) == 0x11 )
cdupaty 0:d974bcee4f69 1028 state=0;
cdupaty 0:d974bcee4f69 1029 }
cdupaty 0:d974bcee4f69 1030 else {
cdupaty 0:d974bcee4f69 1031 // (config1 >> 1) ---> take out bits 7-1 from REG_MODEM_CONFIG1 (=_bandwidth & _codingRate together)
cdupaty 0:d974bcee4f69 1032 if( (config1 >> 1) == 0x49 )
cdupaty 0:d974bcee4f69 1033 state=0;
cdupaty 0:d974bcee4f69 1034 }
cdupaty 0:d974bcee4f69 1035
cdupaty 0:d974bcee4f69 1036 if( state==0) {
cdupaty 0:d974bcee4f69 1037 state = 1;
cdupaty 0:d974bcee4f69 1038 config2 = readRegister(REG_MODEM_CONFIG2);
cdupaty 0:d974bcee4f69 1039
cdupaty 0:d974bcee4f69 1040 if( (config2 >> 4) == SF_11 )
cdupaty 0:d974bcee4f69 1041 {
cdupaty 0:d974bcee4f69 1042 state = 0;
cdupaty 0:d974bcee4f69 1043 }
cdupaty 0:d974bcee4f69 1044 }
cdupaty 0:d974bcee4f69 1045 break;
cdupaty 0:d974bcee4f69 1046
cdupaty 0:d974bcee4f69 1047 // mode 7: BW = 250 KHz, CR = 4/5, SF = 9.
cdupaty 0:d974bcee4f69 1048 case 7:
cdupaty 0:d974bcee4f69 1049
cdupaty 0:d974bcee4f69 1050 //modified by C. Pham
cdupaty 0:d974bcee4f69 1051 if (_board==SX1272Chip) {
cdupaty 0:d974bcee4f69 1052 if( (config1 >> 3) == 0x09 )
cdupaty 0:d974bcee4f69 1053 state=0;
cdupaty 0:d974bcee4f69 1054 }
cdupaty 0:d974bcee4f69 1055 else {
cdupaty 0:d974bcee4f69 1056 // (config1 >> 1) ---> take out bits 7-1 from REG_MODEM_CONFIG1 (=_bandwidth & _codingRate together)
cdupaty 0:d974bcee4f69 1057 if( (config1 >> 1) == 0x41 )
cdupaty 0:d974bcee4f69 1058 state=0;
cdupaty 0:d974bcee4f69 1059 }
cdupaty 0:d974bcee4f69 1060
cdupaty 0:d974bcee4f69 1061 if( state==0) {
cdupaty 0:d974bcee4f69 1062 state = 1;
cdupaty 0:d974bcee4f69 1063 config2 = readRegister(REG_MODEM_CONFIG2);
cdupaty 0:d974bcee4f69 1064
cdupaty 0:d974bcee4f69 1065 if( (config2 >> 4) == SF_9 )
cdupaty 0:d974bcee4f69 1066 {
cdupaty 0:d974bcee4f69 1067 state = 0;
cdupaty 0:d974bcee4f69 1068 }
cdupaty 0:d974bcee4f69 1069 }
cdupaty 0:d974bcee4f69 1070 break;
cdupaty 0:d974bcee4f69 1071
cdupaty 0:d974bcee4f69 1072 // mode 8: BW = 500 KHz, CR = 4/5, SF = 9.
cdupaty 0:d974bcee4f69 1073 case 8:
cdupaty 0:d974bcee4f69 1074
cdupaty 0:d974bcee4f69 1075 //modified by C. Pham
cdupaty 0:d974bcee4f69 1076 if (_board==SX1272Chip) {
cdupaty 0:d974bcee4f69 1077 if( (config1 >> 3) == 0x11 )
cdupaty 0:d974bcee4f69 1078 state=0;
cdupaty 0:d974bcee4f69 1079 }
cdupaty 0:d974bcee4f69 1080 else {
cdupaty 0:d974bcee4f69 1081 // (config1 >> 1) ---> take out bits 7-1 from REG_MODEM_CONFIG1 (=_bandwidth & _codingRate together)
cdupaty 0:d974bcee4f69 1082 if( (config1 >> 1) == 0x49 )
cdupaty 0:d974bcee4f69 1083 state=0;
cdupaty 0:d974bcee4f69 1084 }
cdupaty 0:d974bcee4f69 1085
cdupaty 0:d974bcee4f69 1086 if( state==0) {
cdupaty 0:d974bcee4f69 1087 state = 1;
cdupaty 0:d974bcee4f69 1088 config2 = readRegister(REG_MODEM_CONFIG2);
cdupaty 0:d974bcee4f69 1089
cdupaty 0:d974bcee4f69 1090 if( (config2 >> 4) == SF_9 )
cdupaty 0:d974bcee4f69 1091 {
cdupaty 0:d974bcee4f69 1092 state = 0;
cdupaty 0:d974bcee4f69 1093 }
cdupaty 0:d974bcee4f69 1094 }
cdupaty 0:d974bcee4f69 1095 break;
cdupaty 0:d974bcee4f69 1096
cdupaty 0:d974bcee4f69 1097 // mode 9: BW = 500 KHz, CR = 4/5, SF = 8.
cdupaty 0:d974bcee4f69 1098 case 9:
cdupaty 0:d974bcee4f69 1099
cdupaty 0:d974bcee4f69 1100 //modified by C. Pham
cdupaty 0:d974bcee4f69 1101 if (_board==SX1272Chip) {
cdupaty 0:d974bcee4f69 1102 if( (config1 >> 3) == 0x11 )
cdupaty 0:d974bcee4f69 1103 state=0;
cdupaty 0:d974bcee4f69 1104 }
cdupaty 0:d974bcee4f69 1105 else {
cdupaty 0:d974bcee4f69 1106 // (config1 >> 1) ---> take out bits 7-1 from REG_MODEM_CONFIG1 (=_bandwidth & _codingRate together)
cdupaty 0:d974bcee4f69 1107 if( (config1 >> 1) == 0x49 )
cdupaty 0:d974bcee4f69 1108 state=0;
cdupaty 0:d974bcee4f69 1109 }
cdupaty 0:d974bcee4f69 1110
cdupaty 0:d974bcee4f69 1111 if( state==0) {
cdupaty 0:d974bcee4f69 1112 state = 1;
cdupaty 0:d974bcee4f69 1113 config2 = readRegister(REG_MODEM_CONFIG2);
cdupaty 0:d974bcee4f69 1114
cdupaty 0:d974bcee4f69 1115 if( (config2 >> 4) == SF_8 )
cdupaty 0:d974bcee4f69 1116 {
cdupaty 0:d974bcee4f69 1117 state = 0;
cdupaty 0:d974bcee4f69 1118 }
cdupaty 0:d974bcee4f69 1119 }
cdupaty 0:d974bcee4f69 1120 break;
cdupaty 0:d974bcee4f69 1121
cdupaty 0:d974bcee4f69 1122 // mode 10: BW = 500 KHz, CR = 4/5, SF = 7.
cdupaty 0:d974bcee4f69 1123 case 10:
cdupaty 0:d974bcee4f69 1124
cdupaty 0:d974bcee4f69 1125 //modified by C. Pham
cdupaty 0:d974bcee4f69 1126 if (_board==SX1272Chip) {
cdupaty 0:d974bcee4f69 1127 if( (config1 >> 3) == 0x11 )
cdupaty 0:d974bcee4f69 1128 state=0;
cdupaty 0:d974bcee4f69 1129 }
cdupaty 0:d974bcee4f69 1130 else {
cdupaty 0:d974bcee4f69 1131 // (config1 >> 1) ---> take out bits 7-1 from REG_MODEM_CONFIG1 (=_bandwidth & _codingRate together)
cdupaty 0:d974bcee4f69 1132 if( (config1 >> 1) == 0x49 )
cdupaty 0:d974bcee4f69 1133 state=0;
cdupaty 0:d974bcee4f69 1134 }
cdupaty 0:d974bcee4f69 1135
cdupaty 0:d974bcee4f69 1136 if( state==0) {
cdupaty 0:d974bcee4f69 1137 state = 1;
cdupaty 0:d974bcee4f69 1138 config2 = readRegister(REG_MODEM_CONFIG2);
cdupaty 0:d974bcee4f69 1139
cdupaty 0:d974bcee4f69 1140 if( (config2 >> 4) == SF_7 )
cdupaty 0:d974bcee4f69 1141 {
cdupaty 0:d974bcee4f69 1142 state = 0;
cdupaty 0:d974bcee4f69 1143 }
cdupaty 0:d974bcee4f69 1144 }
cdupaty 0:d974bcee4f69 1145 break;
cdupaty 0:d974bcee4f69 1146
cdupaty 0:d974bcee4f69 1147 // added by C. Pham
cdupaty 0:d974bcee4f69 1148 // test of LoRaWAN channel
cdupaty 0:d974bcee4f69 1149 // mode 11: BW = 125 KHz, CR = 4/5, SF = 12.
cdupaty 0:d974bcee4f69 1150 case 11:
cdupaty 0:d974bcee4f69 1151
cdupaty 0:d974bcee4f69 1152 //modified by C. Pham
cdupaty 0:d974bcee4f69 1153 if (_board==SX1272Chip) {
cdupaty 0:d974bcee4f69 1154 if( (config1 >> 3) == 0x01 )
cdupaty 0:d974bcee4f69 1155 state=0;
cdupaty 0:d974bcee4f69 1156 }
cdupaty 0:d974bcee4f69 1157 else {
cdupaty 0:d974bcee4f69 1158 // (config1 >> 1) ---> take out bits 7-1 from REG_MODEM_CONFIG1 (=_bandwidth & _codingRate together)
cdupaty 0:d974bcee4f69 1159 if( (config1 >> 1) == 0x39 )
cdupaty 0:d974bcee4f69 1160 state=0;
cdupaty 0:d974bcee4f69 1161 }
cdupaty 0:d974bcee4f69 1162
cdupaty 0:d974bcee4f69 1163 if( state==0) {
cdupaty 0:d974bcee4f69 1164 state = 1;
cdupaty 0:d974bcee4f69 1165 config2 = readRegister(REG_MODEM_CONFIG2);
cdupaty 0:d974bcee4f69 1166
cdupaty 0:d974bcee4f69 1167 if( (config2 >> 4) == SF_12 )
cdupaty 0:d974bcee4f69 1168 {
cdupaty 0:d974bcee4f69 1169 state = 0;
cdupaty 0:d974bcee4f69 1170 }
cdupaty 0:d974bcee4f69 1171 }
cdupaty 0:d974bcee4f69 1172 break;
cdupaty 0:d974bcee4f69 1173 }// end switch
cdupaty 0:d974bcee4f69 1174
cdupaty 0:d974bcee4f69 1175 if (mode!=11) {
cdupaty 0:d974bcee4f69 1176 setSyncWord(_defaultSyncWord);
cdupaty 0:d974bcee4f69 1177 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 1178 printf("*** Using sync word of 0x%X\n",_defaultSyncWord);
cdupaty 0:d974bcee4f69 1179 // Serial.println(_defaultSyncWord, HEX);
cdupaty 0:d974bcee4f69 1180 #endif
cdupaty 0:d974bcee4f69 1181 }
cdupaty 0:d974bcee4f69 1182 }
cdupaty 0:d974bcee4f69 1183 // added by C. Pham
cdupaty 0:d974bcee4f69 1184 if (state == 0)
cdupaty 0:d974bcee4f69 1185 _loraMode=mode;
cdupaty 0:d974bcee4f69 1186
cdupaty 0:d974bcee4f69 1187 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 1188
cdupaty 0:d974bcee4f69 1189 if( state == 0 )
cdupaty 0:d974bcee4f69 1190 {
cdupaty 0:d974bcee4f69 1191 printf("## Mode %d ",mode);
cdupaty 0:d974bcee4f69 1192 // Serial.print(mode, DEC);
cdupaty 0:d974bcee4f69 1193 printf(" configured with success ##");
cdupaty 0:d974bcee4f69 1194 }
cdupaty 0:d974bcee4f69 1195 else
cdupaty 0:d974bcee4f69 1196 {
cdupaty 0:d974bcee4f69 1197 printf("** There has been an error while configuring mode %d ",mode);
cdupaty 0:d974bcee4f69 1198 // Serial.print(mode, DEC);
cdupaty 0:d974bcee4f69 1199 printf(". **\n");
cdupaty 0:d974bcee4f69 1200 }
cdupaty 0:d974bcee4f69 1201 #endif
cdupaty 0:d974bcee4f69 1202
cdupaty 0:d974bcee4f69 1203 writeRegister(REG_OP_MODE, st0); // Getting back to previous status
cdupaty 0:d974bcee4f69 1204 wait_ms(100);
cdupaty 0:d974bcee4f69 1205 return state;
cdupaty 0:d974bcee4f69 1206 }
cdupaty 0:d974bcee4f69 1207
cdupaty 0:d974bcee4f69 1208 /*
cdupaty 0:d974bcee4f69 1209 Function: Indicates if module is configured in implicit or explicit header mode.
cdupaty 0:d974bcee4f69 1210 Returns: Integer that determines if there has been any error
cdupaty 0:d974bcee4f69 1211 state = 2 --> The command has not been executed
cdupaty 0:d974bcee4f69 1212 state = 1 --> There has been an error while executing the command
cdupaty 0:d974bcee4f69 1213 state = 0 --> The command has been executed with no errors
cdupaty 0:d974bcee4f69 1214 */
cdupaty 0:d974bcee4f69 1215 uint8_t SX1272::getHeader()
cdupaty 0:d974bcee4f69 1216 {
cdupaty 0:d974bcee4f69 1217 int8_t state = 2;
cdupaty 0:d974bcee4f69 1218
cdupaty 0:d974bcee4f69 1219 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 1220 printf("\n");
cdupaty 0:d974bcee4f69 1221 printf("Starting 'getHeader'\n");
cdupaty 0:d974bcee4f69 1222 #endif
cdupaty 0:d974bcee4f69 1223
cdupaty 0:d974bcee4f69 1224 // added by C. Pham
cdupaty 0:d974bcee4f69 1225 uint8_t theHeaderBit;
cdupaty 0:d974bcee4f69 1226
cdupaty 0:d974bcee4f69 1227 if (_board==SX1272Chip)
cdupaty 0:d974bcee4f69 1228 theHeaderBit=2;
cdupaty 0:d974bcee4f69 1229 else
cdupaty 0:d974bcee4f69 1230 theHeaderBit=0;
cdupaty 0:d974bcee4f69 1231
cdupaty 0:d974bcee4f69 1232 // take out bit 2 from REG_MODEM_CONFIG1 indicates ImplicitHeaderModeOn
cdupaty 0:d974bcee4f69 1233 if( bitRead(REG_MODEM_CONFIG1, theHeaderBit) == 0 )
cdupaty 0:d974bcee4f69 1234 { // explicit header mode (ON)
cdupaty 0:d974bcee4f69 1235 _header = HEADER_ON;
cdupaty 0:d974bcee4f69 1236 state = 1;
cdupaty 0:d974bcee4f69 1237 }
cdupaty 0:d974bcee4f69 1238 else
cdupaty 0:d974bcee4f69 1239 { // implicit header mode (OFF)
cdupaty 0:d974bcee4f69 1240 _header = HEADER_OFF;
cdupaty 0:d974bcee4f69 1241 state = 1;
cdupaty 0:d974bcee4f69 1242 }
cdupaty 0:d974bcee4f69 1243
cdupaty 0:d974bcee4f69 1244 state = 0;
cdupaty 0:d974bcee4f69 1245
cdupaty 0:d974bcee4f69 1246 if( _modem == FSK )
cdupaty 0:d974bcee4f69 1247 { // header is not available in FSK mode
cdupaty 0:d974bcee4f69 1248 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 1249 printf("## Notice that FSK mode packets hasn't header ##");
cdupaty 0:d974bcee4f69 1250 printf("\n");
cdupaty 0:d974bcee4f69 1251 #endif
cdupaty 0:d974bcee4f69 1252 }
cdupaty 0:d974bcee4f69 1253 else
cdupaty 0:d974bcee4f69 1254 { // header in LoRa mode
cdupaty 0:d974bcee4f69 1255 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 1256 printf("## Header is ");
cdupaty 0:d974bcee4f69 1257 if( _header == HEADER_ON )
cdupaty 0:d974bcee4f69 1258 {
cdupaty 0:d974bcee4f69 1259 printf("in explicit header mode ##");
cdupaty 0:d974bcee4f69 1260 }
cdupaty 0:d974bcee4f69 1261 else
cdupaty 0:d974bcee4f69 1262 {
cdupaty 0:d974bcee4f69 1263 printf("in implicit header mode ##");
cdupaty 0:d974bcee4f69 1264 }
cdupaty 0:d974bcee4f69 1265 printf("\n");
cdupaty 0:d974bcee4f69 1266 #endif
cdupaty 0:d974bcee4f69 1267 }
cdupaty 0:d974bcee4f69 1268 return state;
cdupaty 0:d974bcee4f69 1269 }
cdupaty 0:d974bcee4f69 1270
cdupaty 0:d974bcee4f69 1271 /*
cdupaty 0:d974bcee4f69 1272 Function: Sets the module in explicit header mode (header is sent).
cdupaty 0:d974bcee4f69 1273 Returns: Integer that determines if there has been any error
cdupaty 0:d974bcee4f69 1274 state = 2 --> The command has not been executed
cdupaty 0:d974bcee4f69 1275 state = 1 --> There has been an error while executing the command
cdupaty 0:d974bcee4f69 1276 state = 0 --> The command has been executed with no errors
cdupaty 0:d974bcee4f69 1277 state = -1 --> Forbidden command for this protocol
cdupaty 0:d974bcee4f69 1278 */
cdupaty 0:d974bcee4f69 1279 int8_t SX1272::setHeaderON()
cdupaty 0:d974bcee4f69 1280 {
cdupaty 0:d974bcee4f69 1281 int8_t state = 2;
cdupaty 0:d974bcee4f69 1282 byte config1;
cdupaty 0:d974bcee4f69 1283
cdupaty 0:d974bcee4f69 1284 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 1285 printf("\n");
cdupaty 0:d974bcee4f69 1286 printf("Starting 'setHeaderON'\n");
cdupaty 0:d974bcee4f69 1287 #endif
cdupaty 0:d974bcee4f69 1288
cdupaty 0:d974bcee4f69 1289 if( _modem == FSK )
cdupaty 0:d974bcee4f69 1290 {
cdupaty 0:d974bcee4f69 1291 state = -1; // header is not available in FSK mode
cdupaty 0:d974bcee4f69 1292 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 1293 printf("## FSK mode packets hasn't header ##");
cdupaty 0:d974bcee4f69 1294 printf("\n");
cdupaty 0:d974bcee4f69 1295 #endif
cdupaty 0:d974bcee4f69 1296 }
cdupaty 0:d974bcee4f69 1297 else
cdupaty 0:d974bcee4f69 1298 {
cdupaty 0:d974bcee4f69 1299 config1 = readRegister(REG_MODEM_CONFIG1); // Save config1 to modify only the header bit
cdupaty 0:d974bcee4f69 1300 if( _spreadingFactor == 6 )
cdupaty 0:d974bcee4f69 1301 {
cdupaty 0:d974bcee4f69 1302 state = -1; // Mandatory headerOFF with SF = 6
cdupaty 0:d974bcee4f69 1303 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 1304 printf("## Mandatory implicit header mode with spreading factor = 6 ##");
cdupaty 0:d974bcee4f69 1305 #endif
cdupaty 0:d974bcee4f69 1306 }
cdupaty 0:d974bcee4f69 1307 else
cdupaty 0:d974bcee4f69 1308 {
cdupaty 0:d974bcee4f69 1309 // added by C. Pham
cdupaty 0:d974bcee4f69 1310 if (_board==SX1272Chip)
cdupaty 0:d974bcee4f69 1311 config1 = config1 & 0B11111011; // clears bit 2 from config1 = headerON
cdupaty 0:d974bcee4f69 1312 else
cdupaty 0:d974bcee4f69 1313 config1 = config1 & 0B11111110; // clears bit 0 from config1 = headerON
cdupaty 0:d974bcee4f69 1314
cdupaty 0:d974bcee4f69 1315 writeRegister(REG_MODEM_CONFIG1,config1); // Update config1
cdupaty 0:d974bcee4f69 1316 }
cdupaty 0:d974bcee4f69 1317
cdupaty 0:d974bcee4f69 1318 // added by C. Pham
cdupaty 0:d974bcee4f69 1319 uint8_t theHeaderBit;
cdupaty 0:d974bcee4f69 1320
cdupaty 0:d974bcee4f69 1321 if (_board==SX1272Chip)
cdupaty 0:d974bcee4f69 1322 theHeaderBit=2;
cdupaty 0:d974bcee4f69 1323 else
cdupaty 0:d974bcee4f69 1324 theHeaderBit=0;
cdupaty 0:d974bcee4f69 1325
cdupaty 0:d974bcee4f69 1326 if( _spreadingFactor != 6 )
cdupaty 0:d974bcee4f69 1327 { // checking headerON taking out bit 2 from REG_MODEM_CONFIG1
cdupaty 0:d974bcee4f69 1328 config1 = readRegister(REG_MODEM_CONFIG1);
cdupaty 0:d974bcee4f69 1329 // modified by C. Pham
cdupaty 0:d974bcee4f69 1330 if( bitRead(config1, theHeaderBit) == HEADER_ON )
cdupaty 0:d974bcee4f69 1331 {
cdupaty 0:d974bcee4f69 1332 state = 0;
cdupaty 0:d974bcee4f69 1333 _header = HEADER_ON;
cdupaty 0:d974bcee4f69 1334 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 1335 printf("## Header has been activated ##");
cdupaty 0:d974bcee4f69 1336 printf("\n");
cdupaty 0:d974bcee4f69 1337 #endif
cdupaty 0:d974bcee4f69 1338 }
cdupaty 0:d974bcee4f69 1339 else
cdupaty 0:d974bcee4f69 1340 {
cdupaty 0:d974bcee4f69 1341 state = 1;
cdupaty 0:d974bcee4f69 1342 }
cdupaty 0:d974bcee4f69 1343 }
cdupaty 0:d974bcee4f69 1344 // modifie par C.Dupaty
cdupaty 0:d974bcee4f69 1345 //return state;
cdupaty 0:d974bcee4f69 1346 }
cdupaty 0:d974bcee4f69 1347 return state;
cdupaty 0:d974bcee4f69 1348 }
cdupaty 0:d974bcee4f69 1349
cdupaty 0:d974bcee4f69 1350 /*
cdupaty 0:d974bcee4f69 1351 Function: Sets the module in implicit header mode (header is not sent).
cdupaty 0:d974bcee4f69 1352 Returns: Integer that determines if there has been any error
cdupaty 0:d974bcee4f69 1353 state = 2 --> The command has not been executed
cdupaty 0:d974bcee4f69 1354 state = 1 --> There has been an error while executing the command
cdupaty 0:d974bcee4f69 1355 state = 0 --> The command has been executed with no errors
cdupaty 0:d974bcee4f69 1356 state = -1 --> Forbidden command for this protocol
cdupaty 0:d974bcee4f69 1357 */
cdupaty 0:d974bcee4f69 1358 int8_t SX1272::setHeaderOFF()
cdupaty 0:d974bcee4f69 1359 {
cdupaty 0:d974bcee4f69 1360 int8_t state = 2;
cdupaty 0:d974bcee4f69 1361 byte config1;
cdupaty 0:d974bcee4f69 1362
cdupaty 0:d974bcee4f69 1363 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 1364 printf("\n");
cdupaty 0:d974bcee4f69 1365 printf("Starting 'setHeaderOFF'\n");
cdupaty 0:d974bcee4f69 1366 #endif
cdupaty 0:d974bcee4f69 1367
cdupaty 0:d974bcee4f69 1368 if( _modem == FSK )
cdupaty 0:d974bcee4f69 1369 { // header is not available in FSK mode
cdupaty 0:d974bcee4f69 1370 state = -1;
cdupaty 0:d974bcee4f69 1371 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 1372 printf("## Notice that FSK mode packets hasn't header ##");
cdupaty 0:d974bcee4f69 1373 printf("\n");
cdupaty 0:d974bcee4f69 1374 #endif
cdupaty 0:d974bcee4f69 1375 }
cdupaty 0:d974bcee4f69 1376 else
cdupaty 0:d974bcee4f69 1377 {
cdupaty 0:d974bcee4f69 1378 config1 = readRegister(REG_MODEM_CONFIG1); // Save config1 to modify only the header bit
cdupaty 0:d974bcee4f69 1379
cdupaty 0:d974bcee4f69 1380 // modified by C. Pham
cdupaty 0:d974bcee4f69 1381 if (_board==SX1272Chip)
cdupaty 0:d974bcee4f69 1382 config1 = config1 | 0B00000100; // sets bit 2 from REG_MODEM_CONFIG1 = headerOFF
cdupaty 0:d974bcee4f69 1383 else
cdupaty 0:d974bcee4f69 1384 config1 = config1 | 0B00000001; // sets bit 0 from REG_MODEM_CONFIG1 = headerOFF
cdupaty 0:d974bcee4f69 1385
cdupaty 0:d974bcee4f69 1386 writeRegister(REG_MODEM_CONFIG1,config1); // Update config1
cdupaty 0:d974bcee4f69 1387
cdupaty 0:d974bcee4f69 1388 config1 = readRegister(REG_MODEM_CONFIG1);
cdupaty 0:d974bcee4f69 1389
cdupaty 0:d974bcee4f69 1390 // added by C. Pham
cdupaty 0:d974bcee4f69 1391 uint8_t theHeaderBit;
cdupaty 0:d974bcee4f69 1392
cdupaty 0:d974bcee4f69 1393 if (_board==SX1272Chip)
cdupaty 0:d974bcee4f69 1394 theHeaderBit=2;
cdupaty 0:d974bcee4f69 1395 else
cdupaty 0:d974bcee4f69 1396 theHeaderBit=0;
cdupaty 0:d974bcee4f69 1397
cdupaty 0:d974bcee4f69 1398 if( bitRead(config1, theHeaderBit) == HEADER_OFF )
cdupaty 0:d974bcee4f69 1399 { // checking headerOFF taking out bit 2 from REG_MODEM_CONFIG1
cdupaty 0:d974bcee4f69 1400 state = 0;
cdupaty 0:d974bcee4f69 1401 _header = HEADER_OFF;
cdupaty 0:d974bcee4f69 1402
cdupaty 0:d974bcee4f69 1403 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 1404 printf("## Header has been desactivated ##");
cdupaty 0:d974bcee4f69 1405 printf("\n");
cdupaty 0:d974bcee4f69 1406 #endif
cdupaty 0:d974bcee4f69 1407 }
cdupaty 0:d974bcee4f69 1408 else
cdupaty 0:d974bcee4f69 1409 {
cdupaty 0:d974bcee4f69 1410 state = 1;
cdupaty 0:d974bcee4f69 1411 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 1412 printf("** Header hasn't been desactivated ##");
cdupaty 0:d974bcee4f69 1413 printf("\n");
cdupaty 0:d974bcee4f69 1414 #endif
cdupaty 0:d974bcee4f69 1415 }
cdupaty 0:d974bcee4f69 1416 }
cdupaty 0:d974bcee4f69 1417 return state;
cdupaty 0:d974bcee4f69 1418 }
cdupaty 0:d974bcee4f69 1419
cdupaty 0:d974bcee4f69 1420 /*
cdupaty 0:d974bcee4f69 1421 Function: Indicates if module is configured with or without checking CRC.
cdupaty 0:d974bcee4f69 1422 Returns: Integer that determines if there has been any error
cdupaty 0:d974bcee4f69 1423 state = 2 --> The command has not been executed
cdupaty 0:d974bcee4f69 1424 state = 1 --> There has been an error while executing the command
cdupaty 0:d974bcee4f69 1425 state = 0 --> The command has been executed with no errors
cdupaty 0:d974bcee4f69 1426 */
cdupaty 0:d974bcee4f69 1427 uint8_t SX1272::getCRC()
cdupaty 0:d974bcee4f69 1428 {
cdupaty 0:d974bcee4f69 1429 int8_t state = 2;
cdupaty 0:d974bcee4f69 1430 byte value;
cdupaty 0:d974bcee4f69 1431
cdupaty 0:d974bcee4f69 1432 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 1433 printf("\n");
cdupaty 0:d974bcee4f69 1434 printf("Starting 'getCRC'\n");
cdupaty 0:d974bcee4f69 1435 #endif
cdupaty 0:d974bcee4f69 1436
cdupaty 0:d974bcee4f69 1437 if( _modem == LORA )
cdupaty 0:d974bcee4f69 1438 { // LoRa mode
cdupaty 0:d974bcee4f69 1439
cdupaty 0:d974bcee4f69 1440 // added by C. Pham
cdupaty 0:d974bcee4f69 1441 uint8_t theRegister;
cdupaty 0:d974bcee4f69 1442 uint8_t theCrcBit;
cdupaty 0:d974bcee4f69 1443
cdupaty 0:d974bcee4f69 1444 if (_board==SX1272Chip) {
cdupaty 0:d974bcee4f69 1445 theRegister=REG_MODEM_CONFIG1;
cdupaty 0:d974bcee4f69 1446 theCrcBit=1;
cdupaty 0:d974bcee4f69 1447 }
cdupaty 0:d974bcee4f69 1448 else {
cdupaty 0:d974bcee4f69 1449 theRegister=REG_MODEM_CONFIG2;
cdupaty 0:d974bcee4f69 1450 theCrcBit=2;
cdupaty 0:d974bcee4f69 1451 }
cdupaty 0:d974bcee4f69 1452
cdupaty 0:d974bcee4f69 1453 // take out bit 1 from REG_MODEM_CONFIG1 indicates RxPayloadCrcOn
cdupaty 0:d974bcee4f69 1454 value = readRegister(theRegister);
cdupaty 0:d974bcee4f69 1455 if( bitRead(value, theCrcBit) == CRC_OFF )
cdupaty 0:d974bcee4f69 1456 { // CRCoff
cdupaty 0:d974bcee4f69 1457 _CRC = CRC_OFF;
cdupaty 0:d974bcee4f69 1458 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 1459 printf("## CRC is desactivated ##");
cdupaty 0:d974bcee4f69 1460 printf("\n");
cdupaty 0:d974bcee4f69 1461 #endif
cdupaty 0:d974bcee4f69 1462 state = 0;
cdupaty 0:d974bcee4f69 1463 }
cdupaty 0:d974bcee4f69 1464 else
cdupaty 0:d974bcee4f69 1465 { // CRCon
cdupaty 0:d974bcee4f69 1466 _CRC = CRC_ON;
cdupaty 0:d974bcee4f69 1467 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 1468 printf("## CRC is activated ##");
cdupaty 0:d974bcee4f69 1469 printf("\n");
cdupaty 0:d974bcee4f69 1470 #endif
cdupaty 0:d974bcee4f69 1471 state = 0;
cdupaty 0:d974bcee4f69 1472 }
cdupaty 0:d974bcee4f69 1473 }
cdupaty 0:d974bcee4f69 1474 else
cdupaty 0:d974bcee4f69 1475 { // FSK mode
cdupaty 0:d974bcee4f69 1476
cdupaty 0:d974bcee4f69 1477 // take out bit 2 from REG_PACKET_CONFIG1 indicates CrcOn
cdupaty 0:d974bcee4f69 1478 value = readRegister(REG_PACKET_CONFIG1);
cdupaty 0:d974bcee4f69 1479 if( bitRead(value, 4) == CRC_OFF )
cdupaty 0:d974bcee4f69 1480 { // CRCoff
cdupaty 0:d974bcee4f69 1481 _CRC = CRC_OFF;
cdupaty 0:d974bcee4f69 1482 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 1483 printf("## CRC is desactivated ##");
cdupaty 0:d974bcee4f69 1484 printf("\n");
cdupaty 0:d974bcee4f69 1485 #endif
cdupaty 0:d974bcee4f69 1486 state = 0;
cdupaty 0:d974bcee4f69 1487 }
cdupaty 0:d974bcee4f69 1488 else
cdupaty 0:d974bcee4f69 1489 { // CRCon
cdupaty 0:d974bcee4f69 1490 _CRC = CRC_ON;
cdupaty 0:d974bcee4f69 1491 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 1492 printf("## CRC is activated ##");
cdupaty 0:d974bcee4f69 1493 printf("\n");
cdupaty 0:d974bcee4f69 1494 #endif
cdupaty 0:d974bcee4f69 1495 state = 0;
cdupaty 0:d974bcee4f69 1496 }
cdupaty 0:d974bcee4f69 1497 }
cdupaty 0:d974bcee4f69 1498 if( state != 0 )
cdupaty 0:d974bcee4f69 1499 {
cdupaty 0:d974bcee4f69 1500 state = 1;
cdupaty 0:d974bcee4f69 1501 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 1502 printf("** There has been an error while getting configured CRC **");
cdupaty 0:d974bcee4f69 1503 printf("\n");
cdupaty 0:d974bcee4f69 1504 #endif
cdupaty 0:d974bcee4f69 1505 }
cdupaty 0:d974bcee4f69 1506 return state;
cdupaty 0:d974bcee4f69 1507 }
cdupaty 0:d974bcee4f69 1508
cdupaty 0:d974bcee4f69 1509 /*
cdupaty 0:d974bcee4f69 1510 Function: Sets the module with CRC on.
cdupaty 0:d974bcee4f69 1511 Returns: Integer that determines if there has been any error
cdupaty 0:d974bcee4f69 1512 state = 2 --> The command has not been executed
cdupaty 0:d974bcee4f69 1513 state = 1 --> There has been an error while executing the command
cdupaty 0:d974bcee4f69 1514 state = 0 --> The command has been executed with no errors
cdupaty 0:d974bcee4f69 1515 */
cdupaty 0:d974bcee4f69 1516 uint8_t SX1272::setCRC_ON()
cdupaty 0:d974bcee4f69 1517 {
cdupaty 0:d974bcee4f69 1518 uint8_t state = 2;
cdupaty 0:d974bcee4f69 1519 byte config1;
cdupaty 0:d974bcee4f69 1520
cdupaty 0:d974bcee4f69 1521 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 1522 printf("\n");
cdupaty 0:d974bcee4f69 1523 printf("Starting 'setCRC_ON'\n");
cdupaty 0:d974bcee4f69 1524 #endif
cdupaty 0:d974bcee4f69 1525
cdupaty 0:d974bcee4f69 1526 if( _modem == LORA )
cdupaty 0:d974bcee4f69 1527 { // LORA mode
cdupaty 0:d974bcee4f69 1528
cdupaty 0:d974bcee4f69 1529 // added by C. Pham
cdupaty 0:d974bcee4f69 1530 uint8_t theRegister;
cdupaty 0:d974bcee4f69 1531 uint8_t theCrcBit;
cdupaty 0:d974bcee4f69 1532
cdupaty 0:d974bcee4f69 1533 if (_board==SX1272Chip) {
cdupaty 0:d974bcee4f69 1534 theRegister=REG_MODEM_CONFIG1;
cdupaty 0:d974bcee4f69 1535 theCrcBit=1;
cdupaty 0:d974bcee4f69 1536 }
cdupaty 0:d974bcee4f69 1537 else {
cdupaty 0:d974bcee4f69 1538 theRegister=REG_MODEM_CONFIG2;
cdupaty 0:d974bcee4f69 1539 theCrcBit=2;
cdupaty 0:d974bcee4f69 1540 }
cdupaty 0:d974bcee4f69 1541
cdupaty 0:d974bcee4f69 1542 config1 = readRegister(theRegister); // Save config1 to modify only the CRC bit
cdupaty 0:d974bcee4f69 1543
cdupaty 0:d974bcee4f69 1544 if (_board==SX1272Chip)
cdupaty 0:d974bcee4f69 1545 config1 = config1 | 0B00000010; // sets bit 1 from REG_MODEM_CONFIG1 = CRC_ON
cdupaty 0:d974bcee4f69 1546 else
cdupaty 0:d974bcee4f69 1547 config1 = config1 | 0B00000100; // sets bit 2 from REG_MODEM_CONFIG2 = CRC_ON
cdupaty 0:d974bcee4f69 1548
cdupaty 0:d974bcee4f69 1549 writeRegister(theRegister,config1);
cdupaty 0:d974bcee4f69 1550
cdupaty 0:d974bcee4f69 1551 state = 1;
cdupaty 0:d974bcee4f69 1552
cdupaty 0:d974bcee4f69 1553 config1 = readRegister(theRegister);
cdupaty 0:d974bcee4f69 1554
cdupaty 0:d974bcee4f69 1555 if( bitRead(config1, theCrcBit) == CRC_ON )
cdupaty 0:d974bcee4f69 1556 { // take out bit 1 from REG_MODEM_CONFIG1 indicates RxPayloadCrcOn
cdupaty 0:d974bcee4f69 1557 state = 0;
cdupaty 0:d974bcee4f69 1558 _CRC = CRC_ON;
cdupaty 0:d974bcee4f69 1559 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 1560 printf("## CRC has been activated ##");
cdupaty 0:d974bcee4f69 1561 printf("\n");
cdupaty 0:d974bcee4f69 1562 #endif
cdupaty 0:d974bcee4f69 1563 }
cdupaty 0:d974bcee4f69 1564 }
cdupaty 0:d974bcee4f69 1565 else
cdupaty 0:d974bcee4f69 1566 { // FSK mode
cdupaty 0:d974bcee4f69 1567 config1 = readRegister(REG_PACKET_CONFIG1); // Save config1 to modify only the CRC bit
cdupaty 0:d974bcee4f69 1568 config1 = config1 | 0B00010000; // set bit 4 and 3 from REG_MODEM_CONFIG1 = CRC_ON
cdupaty 0:d974bcee4f69 1569 writeRegister(REG_PACKET_CONFIG1,config1);
cdupaty 0:d974bcee4f69 1570
cdupaty 0:d974bcee4f69 1571 state = 1;
cdupaty 0:d974bcee4f69 1572
cdupaty 0:d974bcee4f69 1573 config1 = readRegister(REG_PACKET_CONFIG1);
cdupaty 0:d974bcee4f69 1574 if( bitRead(config1, 4) == CRC_ON )
cdupaty 0:d974bcee4f69 1575 { // take out bit 4 from REG_PACKET_CONFIG1 indicates CrcOn
cdupaty 0:d974bcee4f69 1576 state = 0;
cdupaty 0:d974bcee4f69 1577 _CRC = CRC_ON;
cdupaty 0:d974bcee4f69 1578 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 1579 printf("## CRC has been activated ##");
cdupaty 0:d974bcee4f69 1580 printf("\n");
cdupaty 0:d974bcee4f69 1581 #endif
cdupaty 0:d974bcee4f69 1582 }
cdupaty 0:d974bcee4f69 1583 }
cdupaty 0:d974bcee4f69 1584 if( state != 0 )
cdupaty 0:d974bcee4f69 1585 {
cdupaty 0:d974bcee4f69 1586 state = 1;
cdupaty 0:d974bcee4f69 1587 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 1588 printf("** There has been an error while setting CRC ON **");
cdupaty 0:d974bcee4f69 1589 printf("\n");
cdupaty 0:d974bcee4f69 1590 #endif
cdupaty 0:d974bcee4f69 1591 }
cdupaty 0:d974bcee4f69 1592 return state;
cdupaty 0:d974bcee4f69 1593 }
cdupaty 0:d974bcee4f69 1594
cdupaty 0:d974bcee4f69 1595 /*
cdupaty 0:d974bcee4f69 1596 Function: Sets the module with CRC off.
cdupaty 0:d974bcee4f69 1597 Returns: Integer that determines if there has been any error
cdupaty 0:d974bcee4f69 1598 state = 2 --> The command has not been executed
cdupaty 0:d974bcee4f69 1599 state = 1 --> There has been an error while executing the command
cdupaty 0:d974bcee4f69 1600 state = 0 --> The command has been executed with no errors
cdupaty 0:d974bcee4f69 1601 */
cdupaty 0:d974bcee4f69 1602 uint8_t SX1272::setCRC_OFF()
cdupaty 0:d974bcee4f69 1603 {
cdupaty 0:d974bcee4f69 1604 int8_t state = 2;
cdupaty 0:d974bcee4f69 1605 byte config1;
cdupaty 0:d974bcee4f69 1606
cdupaty 0:d974bcee4f69 1607 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 1608 printf("\n");
cdupaty 0:d974bcee4f69 1609 printf("Starting 'setCRC_OFF'\n");
cdupaty 0:d974bcee4f69 1610 #endif
cdupaty 0:d974bcee4f69 1611
cdupaty 0:d974bcee4f69 1612 if( _modem == LORA )
cdupaty 0:d974bcee4f69 1613 { // LORA mode
cdupaty 0:d974bcee4f69 1614
cdupaty 0:d974bcee4f69 1615 // added by C. Pham
cdupaty 0:d974bcee4f69 1616 uint8_t theRegister;
cdupaty 0:d974bcee4f69 1617 uint8_t theCrcBit;
cdupaty 0:d974bcee4f69 1618
cdupaty 0:d974bcee4f69 1619 if (_board==SX1272Chip) {
cdupaty 0:d974bcee4f69 1620 theRegister=REG_MODEM_CONFIG1;
cdupaty 0:d974bcee4f69 1621 theCrcBit=1;
cdupaty 0:d974bcee4f69 1622 }
cdupaty 0:d974bcee4f69 1623 else {
cdupaty 0:d974bcee4f69 1624 theRegister=REG_MODEM_CONFIG2;
cdupaty 0:d974bcee4f69 1625 theCrcBit=2;
cdupaty 0:d974bcee4f69 1626 }
cdupaty 0:d974bcee4f69 1627
cdupaty 0:d974bcee4f69 1628 config1 = readRegister(theRegister); // Save config1 to modify only the CRC bit
cdupaty 0:d974bcee4f69 1629 if (_board==SX1272Chip)
cdupaty 0:d974bcee4f69 1630 config1 = config1 & 0B11111101; // clears bit 1 from config1 = CRC_OFF
cdupaty 0:d974bcee4f69 1631 else
cdupaty 0:d974bcee4f69 1632 config1 = config1 & 0B11111011; // clears bit 2 from config1 = CRC_OFF
cdupaty 0:d974bcee4f69 1633
cdupaty 0:d974bcee4f69 1634 writeRegister(theRegister,config1);
cdupaty 0:d974bcee4f69 1635
cdupaty 0:d974bcee4f69 1636 config1 = readRegister(theRegister);
cdupaty 0:d974bcee4f69 1637 if( (bitRead(config1, theCrcBit)) == CRC_OFF )
cdupaty 0:d974bcee4f69 1638 { // take out bit 1 from REG_MODEM_CONFIG1 indicates RxPayloadCrcOn
cdupaty 0:d974bcee4f69 1639 state = 0;
cdupaty 0:d974bcee4f69 1640 _CRC = CRC_OFF;
cdupaty 0:d974bcee4f69 1641 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 1642 printf("## CRC has been desactivated ##");
cdupaty 0:d974bcee4f69 1643 printf("\n");
cdupaty 0:d974bcee4f69 1644 #endif
cdupaty 0:d974bcee4f69 1645 }
cdupaty 0:d974bcee4f69 1646 }
cdupaty 0:d974bcee4f69 1647 else
cdupaty 0:d974bcee4f69 1648 { // FSK mode
cdupaty 0:d974bcee4f69 1649 config1 = readRegister(REG_PACKET_CONFIG1); // Save config1 to modify only the CRC bit
cdupaty 0:d974bcee4f69 1650 config1 = config1 & 0B11101111; // clears bit 4 from config1 = CRC_OFF
cdupaty 0:d974bcee4f69 1651 writeRegister(REG_PACKET_CONFIG1,config1);
cdupaty 0:d974bcee4f69 1652
cdupaty 0:d974bcee4f69 1653 config1 = readRegister(REG_PACKET_CONFIG1);
cdupaty 0:d974bcee4f69 1654 if( bitRead(config1, 4) == CRC_OFF )
cdupaty 0:d974bcee4f69 1655 { // take out bit 4 from REG_PACKET_CONFIG1 indicates RxPayloadCrcOn
cdupaty 0:d974bcee4f69 1656 state = 0;
cdupaty 0:d974bcee4f69 1657 _CRC = CRC_OFF;
cdupaty 0:d974bcee4f69 1658 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 1659 printf("## CRC has been desactivated ##");
cdupaty 0:d974bcee4f69 1660 printf("\n");
cdupaty 0:d974bcee4f69 1661 #endif
cdupaty 0:d974bcee4f69 1662 }
cdupaty 0:d974bcee4f69 1663 }
cdupaty 0:d974bcee4f69 1664 if( state != 0 )
cdupaty 0:d974bcee4f69 1665 {
cdupaty 0:d974bcee4f69 1666 state = 1;
cdupaty 0:d974bcee4f69 1667 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 1668 printf("** There has been an error while setting CRC OFF **");
cdupaty 0:d974bcee4f69 1669 printf("\n");
cdupaty 0:d974bcee4f69 1670 #endif
cdupaty 0:d974bcee4f69 1671 }
cdupaty 0:d974bcee4f69 1672 return state;
cdupaty 0:d974bcee4f69 1673 }
cdupaty 0:d974bcee4f69 1674
cdupaty 0:d974bcee4f69 1675 /*
cdupaty 0:d974bcee4f69 1676 Function: Checks if SF is a valid value.
cdupaty 0:d974bcee4f69 1677 Returns: Boolean that's 'true' if the SF value exists and
cdupaty 0:d974bcee4f69 1678 it's 'false' if the SF value does not exist.
cdupaty 0:d974bcee4f69 1679 Parameters:
cdupaty 0:d974bcee4f69 1680 spr: spreading factor value to check.
cdupaty 0:d974bcee4f69 1681 */
cdupaty 0:d974bcee4f69 1682 boolean SX1272::isSF(uint8_t spr)
cdupaty 0:d974bcee4f69 1683 {
cdupaty 0:d974bcee4f69 1684 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 1685 printf("\n");
cdupaty 0:d974bcee4f69 1686 printf("Starting 'isSF'\n");
cdupaty 0:d974bcee4f69 1687 #endif
cdupaty 0:d974bcee4f69 1688
cdupaty 0:d974bcee4f69 1689 // Checking available values for _spreadingFactor
cdupaty 0:d974bcee4f69 1690 switch(spr)
cdupaty 0:d974bcee4f69 1691 {
cdupaty 0:d974bcee4f69 1692 case SF_6:
cdupaty 0:d974bcee4f69 1693 case SF_7:
cdupaty 0:d974bcee4f69 1694 case SF_8:
cdupaty 0:d974bcee4f69 1695 case SF_9:
cdupaty 0:d974bcee4f69 1696 case SF_10:
cdupaty 0:d974bcee4f69 1697 case SF_11:
cdupaty 0:d974bcee4f69 1698 case SF_12:
cdupaty 0:d974bcee4f69 1699 return true;
cdupaty 0:d974bcee4f69 1700 //break;
cdupaty 0:d974bcee4f69 1701
cdupaty 0:d974bcee4f69 1702 default:
cdupaty 0:d974bcee4f69 1703 return false;
cdupaty 0:d974bcee4f69 1704 }
cdupaty 0:d974bcee4f69 1705 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 1706 printf("## Finished 'isSF' ##");
cdupaty 0:d974bcee4f69 1707 printf("\n");
cdupaty 0:d974bcee4f69 1708 #endif
cdupaty 0:d974bcee4f69 1709 }
cdupaty 0:d974bcee4f69 1710
cdupaty 0:d974bcee4f69 1711 /*
cdupaty 0:d974bcee4f69 1712 Function: Gets the SF within the module is configured.
cdupaty 0:d974bcee4f69 1713 Returns: Integer that determines if there has been any error
cdupaty 0:d974bcee4f69 1714 state = 2 --> The command has not been executed
cdupaty 0:d974bcee4f69 1715 state = 1 --> There has been an error while executing the command
cdupaty 0:d974bcee4f69 1716 state = 0 --> The command has been executed with no errors
cdupaty 0:d974bcee4f69 1717 state = -1 --> Forbidden command for this protocol
cdupaty 0:d974bcee4f69 1718 */
cdupaty 0:d974bcee4f69 1719 int8_t SX1272::getSF()
cdupaty 0:d974bcee4f69 1720 {
cdupaty 0:d974bcee4f69 1721 int8_t state = 2;
cdupaty 0:d974bcee4f69 1722 byte config2;
cdupaty 0:d974bcee4f69 1723
cdupaty 0:d974bcee4f69 1724 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 1725 printf("\n");
cdupaty 0:d974bcee4f69 1726 printf("Starting 'getSF'\n");
cdupaty 0:d974bcee4f69 1727 #endif
cdupaty 0:d974bcee4f69 1728
cdupaty 0:d974bcee4f69 1729 if( _modem == FSK )
cdupaty 0:d974bcee4f69 1730 {
cdupaty 0:d974bcee4f69 1731 state = -1; // SF is not available in FSK mode
cdupaty 0:d974bcee4f69 1732 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 1733 printf("** FSK mode hasn't spreading factor **");
cdupaty 0:d974bcee4f69 1734 printf("\n");
cdupaty 0:d974bcee4f69 1735 #endif
cdupaty 0:d974bcee4f69 1736 }
cdupaty 0:d974bcee4f69 1737 else
cdupaty 0:d974bcee4f69 1738 {
cdupaty 0:d974bcee4f69 1739 // take out bits 7-4 from REG_MODEM_CONFIG2 indicates _spreadingFactor
cdupaty 0:d974bcee4f69 1740 config2 = (readRegister(REG_MODEM_CONFIG2)) >> 4;
cdupaty 0:d974bcee4f69 1741 _spreadingFactor = config2;
cdupaty 0:d974bcee4f69 1742 state = 1;
cdupaty 0:d974bcee4f69 1743
cdupaty 0:d974bcee4f69 1744 if( (config2 == _spreadingFactor) && isSF(_spreadingFactor) )
cdupaty 0:d974bcee4f69 1745 {
cdupaty 0:d974bcee4f69 1746 state = 0;
cdupaty 0:d974bcee4f69 1747 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 1748 printf("## Spreading factor is %X",_spreadingFactor);
cdupaty 0:d974bcee4f69 1749 // Serial.print(_spreadingFactor,HEX);
cdupaty 0:d974bcee4f69 1750 printf(" ##");
cdupaty 0:d974bcee4f69 1751 printf("\n");
cdupaty 0:d974bcee4f69 1752 #endif
cdupaty 0:d974bcee4f69 1753 }
cdupaty 0:d974bcee4f69 1754 }
cdupaty 0:d974bcee4f69 1755 return state;
cdupaty 0:d974bcee4f69 1756 }
cdupaty 0:d974bcee4f69 1757
cdupaty 0:d974bcee4f69 1758 /*
cdupaty 0:d974bcee4f69 1759 Function: Sets the indicated SF in the module.
cdupaty 0:d974bcee4f69 1760 Returns: Integer that determines if there has been any error
cdupaty 0:d974bcee4f69 1761 state = 2 --> The command has not been executed
cdupaty 0:d974bcee4f69 1762 state = 1 --> There has been an error while executing the command
cdupaty 0:d974bcee4f69 1763 state = 0 --> The command has been executed with no errors
cdupaty 0:d974bcee4f69 1764 Parameters:
cdupaty 0:d974bcee4f69 1765 spr: spreading factor value to set in LoRa modem configuration.
cdupaty 0:d974bcee4f69 1766 */
cdupaty 0:d974bcee4f69 1767 uint8_t SX1272::setSF(uint8_t spr)
cdupaty 0:d974bcee4f69 1768 {
cdupaty 0:d974bcee4f69 1769 byte st0;
cdupaty 0:d974bcee4f69 1770 int8_t state = 2;
cdupaty 0:d974bcee4f69 1771 byte config1;
cdupaty 0:d974bcee4f69 1772 byte config2;
cdupaty 0:d974bcee4f69 1773
cdupaty 0:d974bcee4f69 1774 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 1775 printf("\n");
cdupaty 0:d974bcee4f69 1776 printf("Starting 'setSF'\n");
cdupaty 0:d974bcee4f69 1777 #endif
cdupaty 0:d974bcee4f69 1778
cdupaty 0:d974bcee4f69 1779 st0 = readRegister(REG_OP_MODE); // Save the previous status
cdupaty 0:d974bcee4f69 1780
cdupaty 0:d974bcee4f69 1781 if( _modem == FSK )
cdupaty 0:d974bcee4f69 1782 {
cdupaty 0:d974bcee4f69 1783 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 1784 printf("## Notice that FSK hasn't Spreading Factor parameter, ");
cdupaty 0:d974bcee4f69 1785 printf("so you are configuring it in LoRa mode ##");
cdupaty 0:d974bcee4f69 1786 #endif
cdupaty 0:d974bcee4f69 1787 state = setLORA(); // Setting LoRa mode
cdupaty 0:d974bcee4f69 1788 }
cdupaty 0:d974bcee4f69 1789 else
cdupaty 0:d974bcee4f69 1790 { // LoRa mode
cdupaty 0:d974bcee4f69 1791 writeRegister(REG_OP_MODE, LORA_STANDBY_MODE); // LoRa standby mode
cdupaty 0:d974bcee4f69 1792 config2 = (readRegister(REG_MODEM_CONFIG2)); // Save config2 to modify SF value (bits 7-4)
cdupaty 0:d974bcee4f69 1793 switch(spr)
cdupaty 0:d974bcee4f69 1794 {
cdupaty 0:d974bcee4f69 1795 case SF_6: config2 = config2 & 0B01101111; // clears bits 7 & 4 from REG_MODEM_CONFIG2
cdupaty 0:d974bcee4f69 1796 config2 = config2 | 0B01100000; // sets bits 6 & 5 from REG_MODEM_CONFIG2
cdupaty 0:d974bcee4f69 1797 setHeaderOFF(); // Mandatory headerOFF with SF = 6
cdupaty 0:d974bcee4f69 1798 break;
cdupaty 0:d974bcee4f69 1799 case SF_7: config2 = config2 & 0B01111111; // clears bits 7 from REG_MODEM_CONFIG2
cdupaty 0:d974bcee4f69 1800 config2 = config2 | 0B01110000; // sets bits 6, 5 & 4
cdupaty 0:d974bcee4f69 1801 break;
cdupaty 0:d974bcee4f69 1802 case SF_8: config2 = config2 & 0B10001111; // clears bits 6, 5 & 4 from REG_MODEM_CONFIG2
cdupaty 0:d974bcee4f69 1803 config2 = config2 | 0B10000000; // sets bit 7 from REG_MODEM_CONFIG2
cdupaty 0:d974bcee4f69 1804 break;
cdupaty 0:d974bcee4f69 1805 case SF_9: config2 = config2 & 0B10011111; // clears bits 6, 5 & 4 from REG_MODEM_CONFIG2
cdupaty 0:d974bcee4f69 1806 config2 = config2 | 0B10010000; // sets bits 7 & 4 from REG_MODEM_CONFIG2
cdupaty 0:d974bcee4f69 1807 break;
cdupaty 0:d974bcee4f69 1808 case SF_10: config2 = config2 & 0B10101111; // clears bits 6 & 4 from REG_MODEM_CONFIG2
cdupaty 0:d974bcee4f69 1809 config2 = config2 | 0B10100000; // sets bits 7 & 5 from REG_MODEM_CONFIG2
cdupaty 0:d974bcee4f69 1810 break;
cdupaty 0:d974bcee4f69 1811 case SF_11: config2 = config2 & 0B10111111; // clears bit 6 from REG_MODEM_CONFIG2
cdupaty 0:d974bcee4f69 1812 config2 = config2 | 0B10110000; // sets bits 7, 5 & 4 from REG_MODEM_CONFIG2
cdupaty 0:d974bcee4f69 1813 getBW();
cdupaty 0:d974bcee4f69 1814
cdupaty 0:d974bcee4f69 1815 // modified by C. Pham
cdupaty 0:d974bcee4f69 1816 if( _bandwidth == BW_125)
cdupaty 0:d974bcee4f69 1817 { // LowDataRateOptimize (Mandatory with SF_11 if BW_125)
cdupaty 0:d974bcee4f69 1818 if (_board==SX1272Chip) {
cdupaty 0:d974bcee4f69 1819 config1 = (readRegister(REG_MODEM_CONFIG1)); // Save config1 to modify only the LowDataRateOptimize
cdupaty 0:d974bcee4f69 1820 config1 = config1 | 0B00000001;
cdupaty 0:d974bcee4f69 1821 writeRegister(REG_MODEM_CONFIG1,config1);
cdupaty 0:d974bcee4f69 1822 }
cdupaty 0:d974bcee4f69 1823 else {
cdupaty 0:d974bcee4f69 1824 byte config3=readRegister(REG_MODEM_CONFIG3);
cdupaty 0:d974bcee4f69 1825 config3 = config3 | 0B00001000;
cdupaty 0:d974bcee4f69 1826 writeRegister(REG_MODEM_CONFIG3,config3);
cdupaty 0:d974bcee4f69 1827 }
cdupaty 0:d974bcee4f69 1828 }
cdupaty 0:d974bcee4f69 1829 break;
cdupaty 0:d974bcee4f69 1830 case SF_12: config2 = config2 & 0B11001111; // clears bits 5 & 4 from REG_MODEM_CONFIG2
cdupaty 0:d974bcee4f69 1831 config2 = config2 | 0B11000000; // sets bits 7 & 6 from REG_MODEM_CONFIG2
cdupaty 0:d974bcee4f69 1832 if( _bandwidth == BW_125)
cdupaty 0:d974bcee4f69 1833 { // LowDataRateOptimize (Mandatory with SF_12 if BW_125)
cdupaty 0:d974bcee4f69 1834 // modified by C. Pham
cdupaty 0:d974bcee4f69 1835 if (_board==SX1272Chip) {
cdupaty 0:d974bcee4f69 1836 config1 = (readRegister(REG_MODEM_CONFIG1)); // Save config1 to modify only the LowDataRateOptimize
cdupaty 0:d974bcee4f69 1837 config1 = config1 | 0B00000001;
cdupaty 0:d974bcee4f69 1838 writeRegister(REG_MODEM_CONFIG1,config1);
cdupaty 0:d974bcee4f69 1839 }
cdupaty 0:d974bcee4f69 1840 else {
cdupaty 0:d974bcee4f69 1841 byte config3=readRegister(REG_MODEM_CONFIG3);
cdupaty 0:d974bcee4f69 1842 config3 = config3 | 0B00001000;
cdupaty 0:d974bcee4f69 1843 writeRegister(REG_MODEM_CONFIG3,config3);
cdupaty 0:d974bcee4f69 1844 }
cdupaty 0:d974bcee4f69 1845 }
cdupaty 0:d974bcee4f69 1846 break;
cdupaty 0:d974bcee4f69 1847 }
cdupaty 0:d974bcee4f69 1848
cdupaty 0:d974bcee4f69 1849 // Check if it is neccesary to set special settings for SF=6
cdupaty 0:d974bcee4f69 1850 if( spr == SF_6 )
cdupaty 0:d974bcee4f69 1851 {
cdupaty 0:d974bcee4f69 1852 // Mandatory headerOFF with SF = 6 (Implicit mode)
cdupaty 0:d974bcee4f69 1853 setHeaderOFF();
cdupaty 0:d974bcee4f69 1854
cdupaty 0:d974bcee4f69 1855 // Set the bit field DetectionOptimize of
cdupaty 0:d974bcee4f69 1856 // register RegLoRaDetectOptimize to value "0b101".
cdupaty 0:d974bcee4f69 1857 writeRegister(REG_DETECT_OPTIMIZE, 0x05);
cdupaty 0:d974bcee4f69 1858
cdupaty 0:d974bcee4f69 1859 // Write 0x0C in the register RegDetectionThreshold.
cdupaty 0:d974bcee4f69 1860 writeRegister(REG_DETECTION_THRESHOLD, 0x0C);
cdupaty 0:d974bcee4f69 1861 }
cdupaty 0:d974bcee4f69 1862 else
cdupaty 0:d974bcee4f69 1863 {
cdupaty 0:d974bcee4f69 1864 // added by C. Pham
cdupaty 0:d974bcee4f69 1865 setHeaderON();
cdupaty 0:d974bcee4f69 1866
cdupaty 0:d974bcee4f69 1867 // LoRa detection Optimize: 0x03 --> SF7 to SF12
cdupaty 0:d974bcee4f69 1868 writeRegister(REG_DETECT_OPTIMIZE, 0x03);
cdupaty 0:d974bcee4f69 1869
cdupaty 0:d974bcee4f69 1870 // LoRa detection threshold: 0x0A --> SF7 to SF12
cdupaty 0:d974bcee4f69 1871 writeRegister(REG_DETECTION_THRESHOLD, 0x0A);
cdupaty 0:d974bcee4f69 1872 }
cdupaty 0:d974bcee4f69 1873
cdupaty 0:d974bcee4f69 1874 // added by C. Pham
cdupaty 0:d974bcee4f69 1875 if (_board==SX1272Chip) {
cdupaty 0:d974bcee4f69 1876 // comment by C. Pham
cdupaty 0:d974bcee4f69 1877 // bit 9:8 of SymbTimeout are then 11
cdupaty 0:d974bcee4f69 1878 // single_chan_pkt_fwd uses 00 and then 00001000
cdupaty 0:d974bcee4f69 1879 // why?
cdupaty 0:d974bcee4f69 1880 // sets bit 2-0 (AgcAutoOn and SymbTimout) for any SF value
cdupaty 0:d974bcee4f69 1881 //config2 = config2 | 0B00000111;
cdupaty 0:d974bcee4f69 1882 // modified by C. Pham
cdupaty 0:d974bcee4f69 1883 config2 = config2 | 0B00000100;
cdupaty 0:d974bcee4f69 1884 writeRegister(REG_MODEM_CONFIG1, config1); // Update config1
cdupaty 0:d974bcee4f69 1885 }
cdupaty 0:d974bcee4f69 1886 else {
cdupaty 0:d974bcee4f69 1887 // set the AgcAutoOn in bit 2 of REG_MODEM_CONFIG3
cdupaty 0:d974bcee4f69 1888 uint8_t config3 = (readRegister(REG_MODEM_CONFIG3));
cdupaty 0:d974bcee4f69 1889 config3=config3 | 0B00000100;
cdupaty 0:d974bcee4f69 1890 writeRegister(REG_MODEM_CONFIG3, config3);
cdupaty 0:d974bcee4f69 1891 }
cdupaty 0:d974bcee4f69 1892
cdupaty 0:d974bcee4f69 1893 // here we write the new SF
cdupaty 0:d974bcee4f69 1894 writeRegister(REG_MODEM_CONFIG2, config2); // Update config2
cdupaty 0:d974bcee4f69 1895
cdupaty 0:d974bcee4f69 1896 wait_ms(100);
cdupaty 0:d974bcee4f69 1897
cdupaty 0:d974bcee4f69 1898 // added by C. Pham
cdupaty 0:d974bcee4f69 1899 byte configAgc;
cdupaty 0:d974bcee4f69 1900 uint8_t theLDRBit;
cdupaty 0:d974bcee4f69 1901
cdupaty 0:d974bcee4f69 1902 if (_board==SX1272Chip) {
cdupaty 0:d974bcee4f69 1903 config1 = (readRegister(REG_MODEM_CONFIG1)); // Save config1 to check update
cdupaty 0:d974bcee4f69 1904 config2 = (readRegister(REG_MODEM_CONFIG2)); // Save config2 to check update
cdupaty 0:d974bcee4f69 1905 // comment by C. Pham
cdupaty 0:d974bcee4f69 1906 // (config2 >> 4) ---> take out bits 7-4 from REG_MODEM_CONFIG2 (=_spreadingFactor)
cdupaty 0:d974bcee4f69 1907 // bitRead(config1, 0) ---> take out bits 1 from config1 (=LowDataRateOptimize)
cdupaty 0:d974bcee4f69 1908 // config2 is only for the AgcAutoOn
cdupaty 0:d974bcee4f69 1909 configAgc=config2;
cdupaty 0:d974bcee4f69 1910 theLDRBit=0;
cdupaty 0:d974bcee4f69 1911 }
cdupaty 0:d974bcee4f69 1912 else {
cdupaty 0:d974bcee4f69 1913 config1 = (readRegister(REG_MODEM_CONFIG3)); // Save config1 to check update
cdupaty 0:d974bcee4f69 1914 config2 = (readRegister(REG_MODEM_CONFIG2));
cdupaty 0:d974bcee4f69 1915 // LowDataRateOptimize is in REG_MODEM_CONFIG3
cdupaty 0:d974bcee4f69 1916 // AgcAutoOn is in REG_MODEM_CONFIG3
cdupaty 0:d974bcee4f69 1917 configAgc=config1;
cdupaty 0:d974bcee4f69 1918 theLDRBit=3;
cdupaty 0:d974bcee4f69 1919 }
cdupaty 0:d974bcee4f69 1920
cdupaty 0:d974bcee4f69 1921
cdupaty 0:d974bcee4f69 1922 switch(spr)
cdupaty 0:d974bcee4f69 1923 {
cdupaty 0:d974bcee4f69 1924 case SF_6: if( ((config2 >> 4) == spr)
cdupaty 0:d974bcee4f69 1925 && (bitRead(configAgc, 2) == 1)
cdupaty 0:d974bcee4f69 1926 && (_header == HEADER_OFF))
cdupaty 0:d974bcee4f69 1927 {
cdupaty 0:d974bcee4f69 1928 state = 0;
cdupaty 0:d974bcee4f69 1929 }
cdupaty 0:d974bcee4f69 1930 break;
cdupaty 0:d974bcee4f69 1931 case SF_7: if( ((config2 >> 4) == 0x07)
cdupaty 0:d974bcee4f69 1932 && (bitRead(configAgc, 2) == 1))
cdupaty 0:d974bcee4f69 1933 {
cdupaty 0:d974bcee4f69 1934 state = 0;
cdupaty 0:d974bcee4f69 1935 }
cdupaty 0:d974bcee4f69 1936 break;
cdupaty 0:d974bcee4f69 1937 case SF_8: if( ((config2 >> 4) == 0x08)
cdupaty 0:d974bcee4f69 1938 && (bitRead(configAgc, 2) == 1))
cdupaty 0:d974bcee4f69 1939 {
cdupaty 0:d974bcee4f69 1940 state = 0;
cdupaty 0:d974bcee4f69 1941 }
cdupaty 0:d974bcee4f69 1942 break;
cdupaty 0:d974bcee4f69 1943 case SF_9: if( ((config2 >> 4) == 0x09)
cdupaty 0:d974bcee4f69 1944 && (bitRead(configAgc, 2) == 1))
cdupaty 0:d974bcee4f69 1945 {
cdupaty 0:d974bcee4f69 1946 state = 0;
cdupaty 0:d974bcee4f69 1947 }
cdupaty 0:d974bcee4f69 1948 break;
cdupaty 0:d974bcee4f69 1949 case SF_10: if( ((config2 >> 4) == 0x0A)
cdupaty 0:d974bcee4f69 1950 && (bitRead(configAgc, 2) == 1))
cdupaty 0:d974bcee4f69 1951 {
cdupaty 0:d974bcee4f69 1952 state = 0;
cdupaty 0:d974bcee4f69 1953 }
cdupaty 0:d974bcee4f69 1954 break;
cdupaty 0:d974bcee4f69 1955 case SF_11: if( ((config2 >> 4) == 0x0B)
cdupaty 0:d974bcee4f69 1956 && (bitRead(configAgc, 2) == 1)
cdupaty 0:d974bcee4f69 1957 && (bitRead(config1, theLDRBit) == 1))
cdupaty 0:d974bcee4f69 1958 {
cdupaty 0:d974bcee4f69 1959 state = 0;
cdupaty 0:d974bcee4f69 1960 }
cdupaty 0:d974bcee4f69 1961 break;
cdupaty 0:d974bcee4f69 1962 case SF_12: if( ((config2 >> 4) == 0x0C)
cdupaty 0:d974bcee4f69 1963 && (bitRead(configAgc, 2) == 1)
cdupaty 0:d974bcee4f69 1964 && (bitRead(config1, theLDRBit) == 1))
cdupaty 0:d974bcee4f69 1965 {
cdupaty 0:d974bcee4f69 1966 state = 0;
cdupaty 0:d974bcee4f69 1967 }
cdupaty 0:d974bcee4f69 1968 break;
cdupaty 0:d974bcee4f69 1969 default: state = 1;
cdupaty 0:d974bcee4f69 1970 }
cdupaty 0:d974bcee4f69 1971 }
cdupaty 0:d974bcee4f69 1972
cdupaty 0:d974bcee4f69 1973 writeRegister(REG_OP_MODE, st0); // Getting back to previous status
cdupaty 0:d974bcee4f69 1974 wait_ms(100);
cdupaty 0:d974bcee4f69 1975
cdupaty 0:d974bcee4f69 1976 if( isSF(spr) )
cdupaty 0:d974bcee4f69 1977 { // Checking available value for _spreadingFactor
cdupaty 0:d974bcee4f69 1978 state = 0;
cdupaty 0:d974bcee4f69 1979 _spreadingFactor = spr;
cdupaty 0:d974bcee4f69 1980 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 1981 printf("## Spreading factor %d ",_spreadingFactor);
cdupaty 0:d974bcee4f69 1982 // Serial.print(_spreadingFactor, DEC);
cdupaty 0:d974bcee4f69 1983 printf(" has been successfully set ##");
cdupaty 0:d974bcee4f69 1984 printf("\n");
cdupaty 0:d974bcee4f69 1985 #endif
cdupaty 0:d974bcee4f69 1986 }
cdupaty 0:d974bcee4f69 1987 else
cdupaty 0:d974bcee4f69 1988 {
cdupaty 0:d974bcee4f69 1989 if( state != 0 )
cdupaty 0:d974bcee4f69 1990 {
cdupaty 0:d974bcee4f69 1991 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 1992 printf("** There has been an error while setting the spreading factor **");
cdupaty 0:d974bcee4f69 1993 printf("\n");
cdupaty 0:d974bcee4f69 1994 #endif
cdupaty 0:d974bcee4f69 1995 }
cdupaty 0:d974bcee4f69 1996 }
cdupaty 0:d974bcee4f69 1997 return state;
cdupaty 0:d974bcee4f69 1998 }
cdupaty 0:d974bcee4f69 1999
cdupaty 0:d974bcee4f69 2000 /*
cdupaty 0:d974bcee4f69 2001 Function: Checks if BW is a valid value.
cdupaty 0:d974bcee4f69 2002 Returns: Boolean that's 'true' if the BW value exists and
cdupaty 0:d974bcee4f69 2003 it's 'false' if the BW value does not exist.
cdupaty 0:d974bcee4f69 2004 Parameters:
cdupaty 0:d974bcee4f69 2005 band: bandwidth value to check.
cdupaty 0:d974bcee4f69 2006 */
cdupaty 0:d974bcee4f69 2007 boolean SX1272::isBW(uint16_t band)
cdupaty 0:d974bcee4f69 2008 {
cdupaty 0:d974bcee4f69 2009 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 2010 printf("\n");
cdupaty 0:d974bcee4f69 2011 printf("Starting 'isBW'\n");
cdupaty 0:d974bcee4f69 2012 #endif
cdupaty 0:d974bcee4f69 2013
cdupaty 0:d974bcee4f69 2014 // Checking available values for _bandwidth
cdupaty 0:d974bcee4f69 2015 // added by C. Pham
cdupaty 0:d974bcee4f69 2016 if (_board==SX1272Chip) {
cdupaty 0:d974bcee4f69 2017 switch(band)
cdupaty 0:d974bcee4f69 2018 {
cdupaty 0:d974bcee4f69 2019 case BW_125:
cdupaty 0:d974bcee4f69 2020 case BW_250:
cdupaty 0:d974bcee4f69 2021 case BW_500:
cdupaty 0:d974bcee4f69 2022 return true;
cdupaty 0:d974bcee4f69 2023 //break;
cdupaty 0:d974bcee4f69 2024
cdupaty 0:d974bcee4f69 2025 default:
cdupaty 0:d974bcee4f69 2026 return false;
cdupaty 0:d974bcee4f69 2027 }
cdupaty 0:d974bcee4f69 2028 }
cdupaty 0:d974bcee4f69 2029 else {
cdupaty 0:d974bcee4f69 2030 switch(band)
cdupaty 0:d974bcee4f69 2031 {
cdupaty 0:d974bcee4f69 2032 case BW_7_8:
cdupaty 0:d974bcee4f69 2033 case BW_10_4:
cdupaty 0:d974bcee4f69 2034 case BW_15_6:
cdupaty 0:d974bcee4f69 2035 case BW_20_8:
cdupaty 0:d974bcee4f69 2036 case BW_31_25:
cdupaty 0:d974bcee4f69 2037 case BW_41_7:
cdupaty 0:d974bcee4f69 2038 case BW_62_5:
cdupaty 0:d974bcee4f69 2039 case BW_125:
cdupaty 0:d974bcee4f69 2040 case BW_250:
cdupaty 0:d974bcee4f69 2041 case BW_500:
cdupaty 0:d974bcee4f69 2042 return true;
cdupaty 0:d974bcee4f69 2043 //break;
cdupaty 0:d974bcee4f69 2044
cdupaty 0:d974bcee4f69 2045 default:
cdupaty 0:d974bcee4f69 2046 return false;
cdupaty 0:d974bcee4f69 2047 }
cdupaty 0:d974bcee4f69 2048 }
cdupaty 0:d974bcee4f69 2049
cdupaty 0:d974bcee4f69 2050 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 2051 printf("## Finished 'isBW' ##");
cdupaty 0:d974bcee4f69 2052 printf("\n");
cdupaty 0:d974bcee4f69 2053 #endif
cdupaty 0:d974bcee4f69 2054 }
cdupaty 0:d974bcee4f69 2055
cdupaty 0:d974bcee4f69 2056 /*
cdupaty 0:d974bcee4f69 2057 Function: Gets the BW within the module is configured.
cdupaty 0:d974bcee4f69 2058 Returns: Integer that determines if there has been any error
cdupaty 0:d974bcee4f69 2059 state = 2 --> The command has not been executed
cdupaty 0:d974bcee4f69 2060 state = 1 --> There has been an error while executing the command
cdupaty 0:d974bcee4f69 2061 state = 0 --> The command has been executed with no errors
cdupaty 0:d974bcee4f69 2062 state = -1 --> Forbidden command for this protocol
cdupaty 0:d974bcee4f69 2063 */
cdupaty 0:d974bcee4f69 2064 int8_t SX1272::getBW()
cdupaty 0:d974bcee4f69 2065 {
cdupaty 0:d974bcee4f69 2066 int8_t state = 2;
cdupaty 0:d974bcee4f69 2067 byte config1;
cdupaty 0:d974bcee4f69 2068
cdupaty 0:d974bcee4f69 2069 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 2070 printf("\n");
cdupaty 0:d974bcee4f69 2071 printf("Starting 'getBW'\n");
cdupaty 0:d974bcee4f69 2072 #endif
cdupaty 0:d974bcee4f69 2073
cdupaty 0:d974bcee4f69 2074 if( _modem == FSK )
cdupaty 0:d974bcee4f69 2075 {
cdupaty 0:d974bcee4f69 2076 state = -1; // BW is not available in FSK mode
cdupaty 0:d974bcee4f69 2077 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 2078 printf("** FSK mode hasn't bandwidth **");
cdupaty 0:d974bcee4f69 2079 printf("\n");
cdupaty 0:d974bcee4f69 2080 #endif
cdupaty 0:d974bcee4f69 2081 }
cdupaty 0:d974bcee4f69 2082 else
cdupaty 0:d974bcee4f69 2083 {
cdupaty 0:d974bcee4f69 2084 // added by C. Pham
cdupaty 0:d974bcee4f69 2085 if (_board==SX1272Chip) {
cdupaty 0:d974bcee4f69 2086 // take out bits 7-6 from REG_MODEM_CONFIG1 indicates _bandwidth
cdupaty 0:d974bcee4f69 2087 config1 = (readRegister(REG_MODEM_CONFIG1)) >> 6;
cdupaty 0:d974bcee4f69 2088 }
cdupaty 0:d974bcee4f69 2089 else {
cdupaty 0:d974bcee4f69 2090 // take out bits 7-4 from REG_MODEM_CONFIG1 indicates _bandwidth
cdupaty 0:d974bcee4f69 2091 config1 = (readRegister(REG_MODEM_CONFIG1)) >> 4;
cdupaty 0:d974bcee4f69 2092 }
cdupaty 0:d974bcee4f69 2093
cdupaty 0:d974bcee4f69 2094 _bandwidth = config1;
cdupaty 0:d974bcee4f69 2095
cdupaty 0:d974bcee4f69 2096 if( (config1 == _bandwidth) && isBW(_bandwidth) )
cdupaty 0:d974bcee4f69 2097 {
cdupaty 0:d974bcee4f69 2098 state = 0;
cdupaty 0:d974bcee4f69 2099 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 2100 printf("## Bandwidth is %X ",_bandwidth);
cdupaty 0:d974bcee4f69 2101 // Serial.print(_bandwidth,HEX);
cdupaty 0:d974bcee4f69 2102 printf(" ##");
cdupaty 0:d974bcee4f69 2103 printf("\n");
cdupaty 0:d974bcee4f69 2104 #endif
cdupaty 0:d974bcee4f69 2105 }
cdupaty 0:d974bcee4f69 2106 else
cdupaty 0:d974bcee4f69 2107 {
cdupaty 0:d974bcee4f69 2108 state = 1;
cdupaty 0:d974bcee4f69 2109 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 2110 printf("** There has been an error while getting bandwidth **");
cdupaty 0:d974bcee4f69 2111 printf("\n");
cdupaty 0:d974bcee4f69 2112 #endif
cdupaty 0:d974bcee4f69 2113 }
cdupaty 0:d974bcee4f69 2114 }
cdupaty 0:d974bcee4f69 2115 return state;
cdupaty 0:d974bcee4f69 2116 }
cdupaty 0:d974bcee4f69 2117
cdupaty 0:d974bcee4f69 2118 /*
cdupaty 0:d974bcee4f69 2119 Function: Sets the indicated BW in the module.
cdupaty 0:d974bcee4f69 2120 Returns: Integer that determines if there has been any error
cdupaty 0:d974bcee4f69 2121 state = 2 --> The command has not been executed
cdupaty 0:d974bcee4f69 2122 state = 1 --> There has been an error while executing the command
cdupaty 0:d974bcee4f69 2123 state = 0 --> The command has been executed with no errors
cdupaty 0:d974bcee4f69 2124 Parameters:
cdupaty 0:d974bcee4f69 2125 band: bandwith value to set in LoRa modem configuration.
cdupaty 0:d974bcee4f69 2126 */
cdupaty 0:d974bcee4f69 2127 int8_t SX1272::setBW(uint16_t band)
cdupaty 0:d974bcee4f69 2128 {
cdupaty 0:d974bcee4f69 2129 byte st0;
cdupaty 0:d974bcee4f69 2130 int8_t state = 2;
cdupaty 0:d974bcee4f69 2131 byte config1;
cdupaty 0:d974bcee4f69 2132
cdupaty 0:d974bcee4f69 2133 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 2134 printf("\n");
cdupaty 0:d974bcee4f69 2135 printf("Starting 'setBW'\n");
cdupaty 0:d974bcee4f69 2136 #endif
cdupaty 0:d974bcee4f69 2137
cdupaty 0:d974bcee4f69 2138 if(!isBW(band) )
cdupaty 0:d974bcee4f69 2139 {
cdupaty 0:d974bcee4f69 2140 state = 1;
cdupaty 0:d974bcee4f69 2141 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 2142 printf("** Bandwidth %X ",band);
cdupaty 0:d974bcee4f69 2143 // Serial.print(band, HEX);
cdupaty 0:d974bcee4f69 2144 printf(" is not a correct value **");
cdupaty 0:d974bcee4f69 2145 printf("\n");
cdupaty 0:d974bcee4f69 2146 #endif
cdupaty 0:d974bcee4f69 2147 return state;
cdupaty 0:d974bcee4f69 2148 }
cdupaty 0:d974bcee4f69 2149
cdupaty 0:d974bcee4f69 2150 st0 = readRegister(REG_OP_MODE); // Save the previous status
cdupaty 0:d974bcee4f69 2151
cdupaty 0:d974bcee4f69 2152 if( _modem == FSK )
cdupaty 0:d974bcee4f69 2153 {
cdupaty 0:d974bcee4f69 2154 #if (SX1272_debug_mode > 1)
cdupaty 0:d974bcee4f69 2155 printf("## Notice that FSK hasn't Bandwidth parameter, ");
cdupaty 0:d974bcee4f69 2156 printf("so you are configuring it in LoRa mode ##");
cdupaty 0:d974bcee4f69 2157 #endif
cdupaty 0:d974bcee4f69 2158 state = setLORA();
cdupaty 0:d974bcee4f69 2159 }
cdupaty 0:d974bcee4f69 2160 writeRegister(REG_OP_MODE, LORA_STANDBY_MODE); // LoRa standby mode
cdupaty 0:d974bcee4f69 2161 config1 = (readRegister(REG_MODEM_CONFIG1)); // Save config1 to modify only the BW
cdupaty 0:d974bcee4f69 2162
cdupaty 0:d974bcee4f69 2163 // added by C. Pham for SX1276
cdupaty 0:d974bcee4f69 2164 if (_board==SX1272Chip) {
cdupaty 0:d974bcee4f69 2165 switch(band)
cdupaty 0:d974bcee4f69 2166 {
cdupaty 0:d974bcee4f69 2167 case BW_125: config1 = config1 & 0B00111111; // clears bits 7 & 6 from REG_MODEM_CONFIG1
cdupaty 0:d974bcee4f69 2168 getSF();
cdupaty 0:d974bcee4f69 2169 if( _spreadingFactor == 11 )
cdupaty 0:d974bcee4f69 2170 { // LowDataRateOptimize (Mandatory with BW_125 if SF_11)
cdupaty 0:d974bcee4f69 2171 config1 = config1 | 0B00000001;
cdupaty 0:d974bcee4f69 2172 }
cdupaty 0:d974bcee4f69 2173 if( _spreadingFactor == 12 )
cdupaty 0:d974bcee4f69 2174 { // LowDataRateOptimize (Mandatory with BW_125 if SF_12)
cdupaty 0:d974bcee4f69 2175 config1 = config1 | 0B00000001;
cdupaty 0:d974bcee4f69 2176 }
cdupaty 0:d974bcee4f69 2177 break;
cdupaty 0:d974bcee4f69 2178 case BW_250: config1 = config1 & 0B01111111; // clears bit 7 from REG_MODEM_CONFIG1
cdupaty 0:d974bcee4f69 2179 config1 = config1 | 0B01000000; // sets bit 6 from REG_MODEM_CONFIG1
cdupaty 0:d974bcee4f69 2180 break;
cdupaty 0:d974bcee4f69 2181 case BW_500: config1 = config1 & 0B10111111; //clears bit 6 from REG_MODEM_CONFIG1
cdupaty 0:d974bcee4f69 2182 config1 = config1 | 0B10000000; //sets bit 7 from REG_MODEM_CONFIG1
cdupaty 0:d974bcee4f69 2183 break;
cdupaty 0:d974bcee4f69 2184 }
cdupaty 0:d974bcee4f69 2185 }
cdupaty 0:d974bcee4f69 2186 else {
cdupaty 0:d974bcee4f69 2187 // SX1276
cdupaty 0:d974bcee4f69 2188 config1 = config1 & 0B00001111; // clears bits 7 - 4 from REG_MODEM_CONFIG1
cdupaty 0:d974bcee4f69 2189 switch(band)
cdupaty 0:d974bcee4f69 2190 {
cdupaty 0:d974bcee4f69 2191 case BW_125:
cdupaty 0:d974bcee4f69 2192 // 0111
cdupaty 0:d974bcee4f69 2193 config1 = config1 | 0B01110000;
cdupaty 0:d974bcee4f69 2194 getSF();
cdupaty 0:d974bcee4f69 2195 if( _spreadingFactor == 11 || _spreadingFactor == 12)
cdupaty 0:d974bcee4f69 2196 { // LowDataRateOptimize (Mandatory with BW_125 if SF_11 or SF_12)
cdupaty 0:d974bcee4f69 2197 byte config3=readRegister(REG_MODEM_CONFIG3);
cdupaty 0:d974bcee4f69 2198 config3 = config3 | 0B00001000;
cdupaty 0:d974bcee4f69 2199 writeRegister(REG_MODEM_CONFIG3,config3);
cdupaty 0:d974bcee4f69 2200 }
cdupaty 0:d974bcee4f69 2201 break;
cdupaty 0:d974bcee4f69 2202 case BW_250:
cdupaty 0:d974bcee4f69 2203 // 1000
cdupaty 0:d974bcee4f69 2204 config1 = config1 | 0B10000000;
cdupaty 0:d974bcee4f69 2205 break;
cdupaty 0:d974bcee4f69 2206 case BW_500:
cdupaty 0:d974bcee4f69 2207 // 1001
cdupaty 0:d974bcee4f69 2208 config1 = config1 | 0B10010000;
cdupaty 0:d974bcee4f69 2209 break;
cdupaty 0:d974bcee4f69 2210 }
cdupaty 0:d974bcee4f69 2211 }
cdupaty 0:d974bcee4f69 2212 // end
cdupaty 0:d974bcee4f69 2213
cdupaty 0:d974bcee4f69 2214 writeRegister(REG_MODEM_CONFIG1,config1); // Update config1
cdupaty 0:d974bcee4f69 2215
cdupaty 0:d974bcee4f69 2216 wait_ms(100);
cdupaty 0:d974bcee4f69 2217
cdupaty 0:d974bcee4f69 2218 config1 = (readRegister(REG_MODEM_CONFIG1));
cdupaty 0:d974bcee4f69 2219
cdupaty 0:d974bcee4f69 2220 // added by C. Pham
cdupaty 0:d974bcee4f69 2221 if (_board==SX1272Chip) {
cdupaty 0:d974bcee4f69 2222 // (config1 >> 6) ---> take out bits 7-6 from REG_MODEM_CONFIG1 (=_bandwidth)
cdupaty 0:d974bcee4f69 2223 switch(band)
cdupaty 0:d974bcee4f69 2224 {
cdupaty 0:d974bcee4f69 2225 case BW_125: if( (config1 >> 6) == SX1272_BW_125 )
cdupaty 0:d974bcee4f69 2226 {
cdupaty 0:d974bcee4f69 2227 state = 0;
cdupaty 0:d974bcee4f69 2228 if( _spreadingFactor == 11 )
cdupaty 0:d974bcee4f69 2229 {
cdupaty 0:d974bcee4f69 2230 if( bitRead(config1, 0) == 1 )
cdupaty 0:d974bcee4f69 2231 { // LowDataRateOptimize
cdupaty 0:d974bcee4f69 2232 state = 0;
cdupaty 0:d974bcee4f69 2233 }
cdupaty 0:d974bcee4f69 2234 else
cdupaty 0:d974bcee4f69 2235 {
cdupaty 0:d974bcee4f69 2236 state = 1;
cdupaty 0:d974bcee4f69 2237 }
cdupaty 0:d974bcee4f69 2238 }
cdupaty 0:d974bcee4f69 2239 if( _spreadingFactor == 12 )
cdupaty 0:d974bcee4f69 2240 {
cdupaty 0:d974bcee4f69 2241 if( bitRead(config1, 0) == 1 )
cdupaty 0:d974bcee4f69 2242 { // LowDataRateOptimize
cdupaty 0:d974bcee4f69 2243 state = 0;
cdupaty 0:d974bcee4f69 2244 }
cdupaty 0:d974bcee4f69 2245 else
cdupaty 0:d974bcee4f69 2246 {
cdupaty 0:d974bcee4f69 2247 state = 1;
cdupaty 0:d974bcee4f69 2248 }
cdupaty 0:d974bcee4f69 2249 }
cdupaty 0:d974bcee4f69 2250 }
cdupaty 0:d974bcee4f69 2251 break;
cdupaty 0:d974bcee4f69 2252 case BW_250: if( (config1 >> 6) == SX1272_BW_250 )
cdupaty 0:d974bcee4f69 2253 {
cdupaty 0:d974bcee4f69 2254 state = 0;
cdupaty 0:d974bcee4f69 2255 }
cdupaty 0:d974bcee4f69 2256 break;
cdupaty 0:d974bcee4f69 2257 case BW_500: if( (config1 >> 6) == SX1272_BW_500 )
cdupaty 0:d974bcee4f69 2258 {
cdupaty 0:d974bcee4f69 2259 state = 0;
cdupaty 0:d974bcee4f69 2260 }
cdupaty 0:d974bcee4f69 2261 break;
cdupaty 0:d974bcee4f69 2262 }
cdupaty 0:d974bcee4f69 2263 }
cdupaty 0:d974bcee4f69 2264 else {
cdupaty 0:d974bcee4f69 2265 // (config1 >> 4) ---> take out bits 7-4 from REG_MODEM_CONFIG1 (=_bandwidth)
cdupaty 0:d974bcee4f69 2266 switch(band)
cdupaty 0:d974bcee4f69 2267 {
cdupaty 0:d974bcee4f69 2268 case BW_125: if( (config1 >> 4) == BW_125 )
cdupaty 0:d974bcee4f69 2269 {
cdupaty 0:d974bcee4f69 2270 state = 0;
cdupaty 0:d974bcee4f69 2271
cdupaty 0:d974bcee4f69 2272 byte config3 = (readRegister(REG_MODEM_CONFIG3));
cdupaty 0:d974bcee4f69 2273
cdupaty 0:d974bcee4f69 2274 if( _spreadingFactor == 11 )
cdupaty 0:d974bcee4f69 2275 {
cdupaty 0:d974bcee4f69 2276 if( bitRead(config3, 3) == 1 )
cdupaty 0:d974bcee4f69 2277 { // LowDataRateOptimize