RF24.cpp

00001 /*
00002  Copyright (C) 2011 J. Coliz <maniacbug@ymail.com>
00003 
00004  This program is free software; you can redistribute it and/or
00005  modify it under the terms of the GNU General Public License
00006  version 2 as published by the Free Software Foundation.
00007  */
00008  
00009 /*
00010  * Mbed support added by Akash Vibhute <akash.roboticist@gmail.com>
00011  * Porting completed on Nov/05/2015
00012  *
00013  * Updated 1: Synced with TMRh20's RF24 library on Nov/04/2015 from https://github.com/TMRh20
00014  * Updated 2: Synced with TMRh20's RF24 library on Apr/18/2015 from https://github.com/TMRh20
00015  *
00016  */
00017  
00018 #include "nRF24L01.h"
00019 #include "RF24_config.h"
00020 #include "RF24.h"
00021 
00022 /****************************************************************************/
00023 
00024 void RF24::csn(bool mode)
00025 {
00026 
00027     csn_pin = mode;
00028     
00029 }
00030 
00031 /****************************************************************************/
00032 
00033 void RF24::ce(bool level)
00034 {
00035   ce_pin = level;
00036   
00037 }
00038 
00039 /****************************************************************************/
00040 
00041   inline void RF24::beginTransaction() {
00042     csn(LOW);
00043     
00044   }
00045 
00046 /****************************************************************************/
00047 
00048   inline void RF24::endTransaction() {
00049     csn(HIGH);
00050 
00051   }
00052 
00053 /****************************************************************************/
00054 
00055 uint8_t RF24::read_register(uint8_t reg, uint8_t* buf, uint8_t len)
00056 {
00057   uint8_t status;
00058 
00059 
00060   beginTransaction();
00061   status = spi.write( R_REGISTER | ( REGISTER_MASK & reg ) );
00062   while ( len-- ){
00063     *buf++ = spi.write(0xff);
00064   }
00065   endTransaction();
00066 
00067 
00068 
00069   return status;
00070 }
00071 
00072 /****************************************************************************/
00073 
00074 uint8_t RF24::read_register(uint8_t reg)
00075 {
00076   uint8_t result;  
00077 
00078   beginTransaction();
00079   spi.write( R_REGISTER | ( REGISTER_MASK & reg ) );
00080   result = spi.write(0xff);
00081   endTransaction();
00082 
00083 
00084 
00085   return result;
00086 }
00087 
00088 /****************************************************************************/
00089 
00090 uint8_t RF24::write_register(uint8_t reg, const uint8_t* buf, uint8_t len)
00091 {
00092   uint8_t status;  
00093 
00094   beginTransaction();
00095   status = spi.write( W_REGISTER | ( REGISTER_MASK & reg ) );
00096   while ( len-- )
00097     spi.write(*buf++);
00098   endTransaction();
00099 
00100   
00101   
00102   return status;
00103 }
00104 
00105 /****************************************************************************/
00106 
00107 uint8_t RF24::write_register(uint8_t reg, uint8_t value)
00108 {
00109   uint8_t status;
00110 
00111   IF_SERIAL_DEBUG(printf_P(PSTR("write_register(%02x,%02x)\r\n"),reg,value));
00112 
00113   
00114   
00115   beginTransaction();
00116   status = spi.write( W_REGISTER | ( REGISTER_MASK & reg ) );
00117   spi.write(value);
00118   endTransaction();
00119 
00120   
00121 
00122   return status;
00123 }
00124 
00125 /****************************************************************************/
00126 
00127 uint8_t RF24::write_payload(const void* buf, uint8_t data_len, const uint8_t writeType)
00128 {
00129   uint8_t status;
00130   const uint8_t* current = reinterpret_cast<const uint8_t*>(buf);
00131 
00132    data_len = rf24_min(data_len, payload_size);
00133    uint8_t blank_len = dynamic_payloads_enabled ? 0 : payload_size - data_len;
00134   
00135   //printf("[Writing %u bytes %u blanks]",data_len,blank_len);
00136   IF_SERIAL_DEBUG( printf("[Writing %u bytes %u blanks]\n",data_len,blank_len); );
00137   
00138  
00139   beginTransaction();
00140   status = spi.write( writeType );
00141   while ( data_len-- ) {
00142     spi.write(*current++);
00143   }
00144   while ( blank_len-- ) {
00145     spi.write(0);
00146   }  
00147   endTransaction();
00148 
00149   
00150 
00151   return status;
00152 }
00153 
00154 /****************************************************************************/
00155 
00156 uint8_t RF24::read_payload(void* buf, uint8_t data_len)
00157 {
00158   uint8_t status;
00159   uint8_t* current = reinterpret_cast<uint8_t*>(buf);
00160 
00161   if(data_len > payload_size) data_len = payload_size;
00162   uint8_t blank_len = dynamic_payloads_enabled ? 0 : payload_size - data_len;
00163   
00164   //printf("[Reading %u bytes %u blanks]",data_len,blank_len);
00165 
00166   IF_SERIAL_DEBUG( printf("[Reading %u bytes %u blanks]\n",data_len,blank_len); );
00167   
00168   beginTransaction();
00169   status = spi.write( R_RX_PAYLOAD );
00170   while ( data_len-- ) {
00171     *current++ = spi.write(0xFF);
00172   }
00173   while ( blank_len-- ) {
00174     spi.write(0xff);
00175   }
00176   endTransaction();
00177 
00178   
00179 
00180   return status;
00181 }
00182 
00183 /****************************************************************************/
00184 
00185 uint8_t RF24::flush_rx(void)
00186 {
00187   return spiTrans( FLUSH_RX );
00188 }
00189 
00190 /****************************************************************************/
00191 
00192 uint8_t RF24::flush_tx(void)
00193 {
00194   return spiTrans( FLUSH_TX );
00195 }
00196 
00197 /****************************************************************************/
00198 
00199 uint8_t RF24::spiTrans(uint8_t cmd){
00200 
00201   uint8_t status;
00202   
00203   beginTransaction();
00204   status = spi.write( cmd );
00205   endTransaction();
00206   
00207   return status;
00208 }
00209 
00210 /****************************************************************************/
00211 
00212 uint8_t RF24::get_status(void)
00213 {
00214   return spiTrans(NOP);
00215 }
00216 
00217 /****************************************************************************/
00218 #if !defined (MINIMAL)
00219 void RF24::print_status(uint8_t status)
00220 {
00221   printf_P(PSTR("STATUS\t\t = 0x%02x RX_DR=%x TX_DS=%x MAX_RT=%x RX_P_NO=%x TX_FULL=%x\r\n"),
00222            status,
00223            (status & _BV(RX_DR))?1:0,
00224            (status & _BV(TX_DS))?1:0,
00225            (status & _BV(MAX_RT))?1:0,
00226            ((status >> RX_P_NO) & 0b111),
00227            (status & _BV(TX_FULL))?1:0
00228           );
00229 }
00230 
00231 /****************************************************************************/
00232 
00233 void RF24::print_observe_tx(uint8_t value)
00234 {
00235   printf_P(PSTR("OBSERVE_TX=%02x: POLS_CNT=%x ARC_CNT=%x\r\n"),
00236            value,
00237            (value >> PLOS_CNT) & 0b1111,
00238            (value >> ARC_CNT) & 0b1111
00239           );
00240 }
00241 
00242 /****************************************************************************/
00243 
00244 void RF24::print_byte_register(const char* name, uint8_t reg, uint8_t qty)
00245 {
00246   //char extra_tab = strlen_P(name) < 8 ? '\t' : 0;
00247   //printf_P(PSTR(PRIPSTR"\t%c ="),name,extra_tab);
00248   
00249   
00250   
00251     printf_P(PSTR(PRIPSTR"\t ="),name);
00252   
00253   while (qty--)
00254     printf_P(PSTR(" 0x%02x"),read_register(reg++));
00255   printf_P(PSTR("\r\n"));
00256 }
00257 
00258 /****************************************************************************/
00259 
00260 void RF24::print_address_register(const char* name, uint8_t reg, uint8_t qty)
00261 {
00262 
00263   
00264   
00265   
00266     printf_P(PSTR(PRIPSTR"\t ="),name);
00267   
00268   while (qty--)
00269   {
00270     uint8_t buffer[addr_width];
00271     read_register(reg++,buffer,sizeof buffer);
00272 
00273     printf_P(PSTR(" 0x"));
00274     uint8_t* bufptr = buffer + sizeof buffer;
00275     while( --bufptr >= buffer )
00276       printf_P(PSTR("%02x"),*bufptr);
00277   }
00278 
00279   printf_P(PSTR("\r\n"));
00280 }
00281 #endif
00282 /****************************************************************************/
00283 RF24::RF24(PinName mosi, PinName miso, PinName sck, PinName _cepin, PinName _csnpin):
00284   spi(mosi, miso, sck), ce_pin(_cepin), csn_pin(_csnpin), p_variant(true),
00285   payload_size(32), dynamic_payloads_enabled(false), addr_width(5)
00286 {
00287   pipe0_reading_address[0]=0;
00288   
00289   //spi.frequency(10000000/5);     // 2Mbit, 1/5th the maximum transfer rate for the spi bus
00290   spi.frequency(10000000);
00291   //spi.format(8,0);               // 8-bit, ClockPhase = 0, ClockPolarity = 0
00292   spi.format(8,0);               
00293   wait_ms(10);
00294 }
00295 
00296 
00297 
00298 
00299 
00300 
00301 
00302 
00303 /****************************************************************************/
00304 
00305 void RF24::setChannel(uint8_t channel)
00306 {
00307   const uint8_t max_channel = 125;
00308   write_register(RF_CH,rf24_min(channel,max_channel));
00309 }
00310 
00311 uint8_t RF24::getChannel()
00312 {
00313   
00314   return read_register(RF_CH);
00315 }
00316 /****************************************************************************/
00317 
00318 void RF24::setPayloadSize(uint8_t size)
00319 {
00320   payload_size = rf24_min(size,32);
00321 }
00322 
00323 /****************************************************************************/
00324 
00325 uint8_t RF24::getPayloadSize(void)
00326 {
00327   return payload_size;
00328 }
00329 
00330 /****************************************************************************/
00331 
00332 #if !defined (MINIMAL)
00333 
00334 static const char rf24_datarate_e_str_0[] PROGMEM = "1MBPS";
00335 static const char rf24_datarate_e_str_1[] PROGMEM = "2MBPS";
00336 static const char rf24_datarate_e_str_2[] PROGMEM = "250KBPS";
00337 static const char * const rf24_datarate_e_str_P[] PROGMEM = {
00338   rf24_datarate_e_str_0,
00339   rf24_datarate_e_str_1,
00340   rf24_datarate_e_str_2,
00341 };
00342 static const char rf24_model_e_str_0[] PROGMEM = "nRF24L01";
00343 static const char rf24_model_e_str_1[] PROGMEM = "nRF24L01+";
00344 static const char * const rf24_model_e_str_P[] PROGMEM = {
00345   rf24_model_e_str_0,
00346   rf24_model_e_str_1,
00347 };
00348 static const char rf24_crclength_e_str_0[] PROGMEM = "Disabled";
00349 static const char rf24_crclength_e_str_1[] PROGMEM = "8 bits";
00350 static const char rf24_crclength_e_str_2[] PROGMEM = "16 bits" ;
00351 static const char * const rf24_crclength_e_str_P[] PROGMEM = {
00352   rf24_crclength_e_str_0,
00353   rf24_crclength_e_str_1,
00354   rf24_crclength_e_str_2,
00355 };
00356 static const char rf24_pa_dbm_e_str_0[] PROGMEM = "PA_MIN";
00357 static const char rf24_pa_dbm_e_str_1[] PROGMEM = "PA_LOW";
00358 static const char rf24_pa_dbm_e_str_2[] PROGMEM = "PA_HIGH";
00359 static const char rf24_pa_dbm_e_str_3[] PROGMEM = "PA_MAX";
00360 static const char * const rf24_pa_dbm_e_str_P[] PROGMEM = {
00361   rf24_pa_dbm_e_str_0,
00362   rf24_pa_dbm_e_str_1,
00363   rf24_pa_dbm_e_str_2,
00364   rf24_pa_dbm_e_str_3,
00365 };
00366 
00367 
00368 
00369 
00370 void RF24::printDetails(void)
00371 {
00372   print_status(get_status());
00373 
00374   print_address_register(PSTR("RX_ADDR_P0-1"),RX_ADDR_P0,2);
00375   print_byte_register(PSTR("RX_ADDR_P2-5"),RX_ADDR_P2,4);
00376   print_address_register(PSTR("TX_ADDR\t"),TX_ADDR);
00377 
00378   print_byte_register(PSTR("RX_PW_P0-6"),RX_PW_P0,6);
00379   print_byte_register(PSTR("EN_AA\t"),EN_AA);
00380   print_byte_register(PSTR("EN_RXADDR"),EN_RXADDR);
00381   print_byte_register(PSTR("RF_CH\t"),RF_CH);
00382   print_byte_register(PSTR("RF_SETUP"),RF_SETUP);
00383   print_byte_register(PSTR("CONFIG\t"),NRF_CONFIG);
00384   print_byte_register(PSTR("DYNPD/FEATURE"),DYNPD,2);
00385 
00386   printf_P(PSTR("Data Rate\t = " PRIPSTR "\r\n"),pgm_read_word(&rf24_datarate_e_str_P[getDataRate()]));
00387   printf_P(PSTR("Model\t\t = " PRIPSTR "\r\n"),pgm_read_word(&rf24_model_e_str_P[isPVariant()]));
00388   printf_P(PSTR("CRC Length\t = " PRIPSTR "\r\n"),pgm_read_word(&rf24_crclength_e_str_P[getCRCLength()]));
00389   printf_P(PSTR("PA Power\t = " PRIPSTR "\r\n"),  pgm_read_word(&rf24_pa_dbm_e_str_P[getPALevel()]));
00390 
00391 }
00392 
00393 #endif
00394 /****************************************************************************/
00395 
00396 bool RF24::begin(void)
00397 {
00398 
00399   uint8_t setup=0;
00400 
00401     mainTimer.start();
00402   
00403     ce(LOW);
00404     csn(HIGH);
00405 
00406     wait_ms(100);
00407 
00408 
00409   // Must allow the radio time to settle else configuration bits will not necessarily stick.
00410   // This is actually only required following power up but some settling time also appears to
00411   // be required after resets too. For full coverage, we'll always assume the worst.
00412   // Enabling 16b CRC is by far the most obvious case if the wrong timing is used - or skipped.
00413   // Technically we require 4.5ms + 14us as a worst case. We'll just call it 5ms for good measure.
00414   // WARNING: Delay is based on P-variant whereby non-P *may* require different timing.
00415   wait_ms( 5 ) ;
00416 
00417   // Reset NRF_CONFIG and enable 16-bit CRC.
00418   write_register( NRF_CONFIG, 0b00001100 ) ;
00419 
00420   // Set 1500uS (minimum for 32B payload in ESB@250KBPS) timeouts, to make testing a little easier
00421   // WARNING: If this is ever lowered, either 250KBS mode with AA is broken or maximum packet
00422   // sizes must never be used. See documentation for a more complete explanation.
00423   setRetries(5,15);
00424 
00425   // Reset value is MAX
00426   //setPALevel( RF24_PA_MAX ) ;
00427 
00428   // check for connected module and if this is a p nRF24l01 variant
00429   //
00430   if( setDataRate( RF24_250KBPS ) )
00431   {
00432     p_variant = true ;
00433   }
00434   setup = read_register(RF_SETUP);
00435   /*if( setup == 0b00001110 )     // register default for nRF24L01P
00436   {
00437     p_variant = true ;
00438   }*/
00439   
00440   // Then set the data rate to the slowest (and most reliable) speed supported by all
00441   // hardware.
00442   //setDataRate( RF24_1MBPS ) ;
00443   setDataRate( RF24_2MBPS ) ;
00444 
00445   // Initialize CRC and request 2-byte (16bit) CRC
00446   //setCRCLength( RF24_CRC_16 ) ;
00447 
00448   // Disable dynamic payloads, to match dynamic_payloads_enabled setting - Reset value is 0
00449   toggle_features();
00450   write_register(FEATURE,0 );
00451   write_register(DYNPD,0);
00452 
00453   // Reset current status
00454   // Notice reset and flush is the last thing we do
00455   write_register(NRF_STATUS,_BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) );
00456 
00457   // Set up default configuration.  Callers can always change it later.
00458   // This channel should be universally safe and not bleed over into adjacent
00459   // spectrum.
00460   setChannel(76);
00461 
00462   // Flush buffers
00463   flush_rx();
00464   flush_tx();
00465 
00466   powerUp(); //Power up by default when begin() is called
00467 
00468   // Enable PTX, do not write CE high so radio will remain in standby I mode ( 130us max to transition to RX or TX instead of 1500us from powerUp )
00469   // PTX should use only 22uA of power
00470   write_register(NRF_CONFIG, ( read_register(NRF_CONFIG) ) & ~_BV(PRIM_RX) );
00471     //printDetails();
00472   // if setup is 0 or ff then there was no response from module
00473   return ( setup != 0 && setup != 0xff );
00474 }
00475 
00476 /****************************************************************************/
00477 
00478 void RF24::startListening(void)
00479 {
00480  
00481  
00482  
00483   write_register(NRF_CONFIG, read_register(NRF_CONFIG) | _BV(PRIM_RX));
00484   write_register(NRF_STATUS, _BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) );
00485   ce(HIGH);
00486   // Restore the pipe0 adddress, if exists
00487   if (pipe0_reading_address[0] > 0){
00488     write_register(RX_ADDR_P0, pipe0_reading_address, addr_width);  
00489   }else{
00490     closeReadingPipe(0);
00491   }
00492 
00493   // Flush buffers
00494   //flush_rx();
00495   if(read_register(FEATURE) & _BV(EN_ACK_PAY)){
00496     flush_tx();
00497   }
00498 
00499   // Go!
00500   //delayMicroseconds(100);
00501 }
00502 
00503 /****************************************************************************/
00504 static const uint8_t child_pipe_enable[] PROGMEM =
00505 {
00506   ERX_P0, ERX_P1, ERX_P2, ERX_P3, ERX_P4, ERX_P5
00507 };
00508 
00509 void RF24::stopListening(void)
00510 {  
00511   ce(LOW);
00512 
00513   wait_us(txRxDelay);
00514   
00515   if(read_register(FEATURE) & _BV(EN_ACK_PAY)){
00516     wait_us(txRxDelay); //200
00517     flush_tx();
00518   }
00519   //flush_rx();
00520   write_register(NRF_CONFIG, ( read_register(NRF_CONFIG) ) & ~_BV(PRIM_RX) );
00521  
00522   
00523   
00524   
00525   
00526   
00527   
00528   
00529   write_register(EN_RXADDR,read_register(EN_RXADDR) | _BV(pgm_read_byte(&child_pipe_enable[0]))); // Enable RX on pipe0
00530   
00531   //delayMicroseconds(100);
00532 
00533 }
00534 
00535 /****************************************************************************/
00536 
00537 void RF24::powerDown(void)
00538 {
00539   ce(LOW); // Guarantee CE is low on powerDown
00540   write_register(NRF_CONFIG,read_register(NRF_CONFIG) & ~_BV(PWR_UP));
00541 }
00542 
00543 /****************************************************************************/
00544 
00545 //Power up now. Radio will not power down unless instructed by MCU for config changes etc.
00546 void RF24::powerUp(void)
00547 {
00548    uint8_t cfg = read_register(NRF_CONFIG);
00549 
00550    // if not powered up then power up and wait for the radio to initialize
00551    if (!(cfg & _BV(PWR_UP))){
00552       write_register(NRF_CONFIG, cfg | _BV(PWR_UP));
00553 
00554       // For nRF24L01+ to go from power down mode to TX or RX mode it must first pass through stand-by mode.
00555       // There must be a delay of Tpd2stby (see Table 16.) after the nRF24L01+ leaves power down mode before
00556       // the CEis set high. - Tpd2stby can be up to 5ms per the 1.0 datasheet
00557       wait_ms(5);
00558    }
00559 }
00560 
00561 /******************************************************************/
00562 #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
00563 void RF24::errNotify(){
00564     #if defined (SERIAL_DEBUG) || defined (RF24_LINUX)
00565       printf_P(PSTR("RF24 HARDWARE FAIL: Radio not responding, verify pin connections, wiring, etc.\r\n"));
00566     #endif
00567     #if defined (FAILURE_HANDLING)
00568     failureDetected = 1;
00569     #else
00570     wait_ms(5000);
00571     #endif
00572 }
00573 #endif
00574 /******************************************************************/
00575 
00576 //Similar to the previous write, clears the interrupt flags
00577 bool RF24::write( const void* buf, uint8_t len, const bool multicast )
00578 {
00579     //Start Writing
00580     startFastWrite(buf,len,multicast);
00581 
00582     //Wait until complete or failed
00583     #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
00584         uint32_t timer = mainTimer.read_ms();
00585     #endif 
00586     
00587     while( ! ( get_status()  & ( _BV(TX_DS) | _BV(MAX_RT) ))) { 
00588         #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
00589             if(mainTimer.read_ms() - timer > 95){           
00590                 errNotify();
00591                 #if defined (FAILURE_HANDLING)
00592                   return 0;     
00593                 #else
00594                   wait_ms(100);
00595                 #endif
00596             }
00597         #endif
00598     }
00599     
00600     ce(LOW);
00601 
00602     uint8_t status = write_register(NRF_STATUS,_BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) );
00603 
00604   //Max retries exceeded
00605   if( status & _BV(MAX_RT)){
00606     flush_tx(); //Only going to be 1 packet int the FIFO at a time using this method, so just flush
00607     return 0;
00608   }
00609     //TX OK 1 or 0
00610   return 1;
00611 }
00612 
00613 bool RF24::write( const void* buf, uint8_t len ){
00614     return write(buf,len,0);
00615 }
00616 /****************************************************************************/
00617 
00618 //For general use, the interrupt flags are not important to clear
00619 bool RF24::writeBlocking( const void* buf, uint8_t len, uint32_t timeout )
00620 {
00621     //Block until the FIFO is NOT full.
00622     //Keep track of the MAX retries and set auto-retry if seeing failures
00623     //This way the FIFO will fill up and allow blocking until packets go through
00624     //The radio will auto-clear everything in the FIFO as long as CE remains high
00625 
00626     uint32_t timer = mainTimer.read_ms();                             //Get the time that the payload transmission started
00627 
00628     while( ( get_status()  & ( _BV(TX_FULL) ))) {         //Blocking only if FIFO is full. This will loop and block until TX is successful or timeout
00629 
00630         if( get_status() & _BV(MAX_RT)){                      //If MAX Retries have been reached
00631             reUseTX();                                        //Set re-transmit and clear the MAX_RT interrupt flag
00632             if(mainTimer.read_ms() - timer > timeout){ return 0; }        //If this payload has exceeded the user-defined timeout, exit and return 0
00633         }
00634         #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
00635             if(mainTimer.read_ms() - timer > (timeout+95) ){            
00636                 errNotify();
00637                 #if defined (FAILURE_HANDLING)
00638                 return 0;           
00639                 #endif              
00640             }
00641         #endif
00642 
00643     }
00644 
00645     //Start Writing
00646     startFastWrite(buf,len,0);                                //Write the payload if a buffer is clear
00647 
00648     return 1;                                                 //Return 1 to indicate successful transmission
00649 }
00650 
00651 /****************************************************************************/
00652 
00653 void RF24::reUseTX(){
00654         write_register(NRF_STATUS,_BV(MAX_RT) );              //Clear max retry flag
00655         spiTrans( REUSE_TX_PL );
00656         ce(LOW);                                          //Re-Transfer packet
00657         ce(HIGH);
00658 }
00659 
00660 /****************************************************************************/
00661 
00662 bool RF24::writeFast( const void* buf, uint8_t len, const bool multicast )
00663 {
00664     //Block until the FIFO is NOT full.
00665     //Keep track of the MAX retries and set auto-retry if seeing failures
00666     //Return 0 so the user can control the retrys and set a timer or failure counter if required
00667     //The radio will auto-clear everything in the FIFO as long as CE remains high
00668 
00669     #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
00670         uint32_t timer = mainTimer.read_ms();
00671     #endif
00672     
00673     while( ( get_status()  & ( _BV(TX_FULL) ))) {             //Blocking only if FIFO is full. This will loop and block until TX is successful or fail
00674 
00675         if( get_status() & _BV(MAX_RT)){
00676             //reUseTX();                                          //Set re-transmit
00677             write_register(NRF_STATUS,_BV(MAX_RT) );              //Clear max retry flag
00678             return 0;                                         //Return 0. The previous payload has been retransmitted
00679                                                               //From the user perspective, if you get a 0, just keep trying to send the same payload
00680         }
00681         #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
00682             if(mainTimer.read_ms() - timer > 95 ){          
00683                 errNotify();
00684                 #if defined (FAILURE_HANDLING)
00685                 return 0;                           
00686                 #endif
00687             }
00688         #endif
00689     }
00690              //Start Writing
00691     startFastWrite(buf,len,multicast);
00692 
00693     return 1;
00694 }
00695 
00696 bool RF24::writeFast( const void* buf, uint8_t len ){
00697     return writeFast(buf,len,0);
00698 }
00699 
00700 /****************************************************************************/
00701 
00702 //Per the documentation, we want to set PTX Mode when not listening. Then all we do is write data and set CE high
00703 //In this mode, if we can keep the FIFO buffers loaded, packets will transmit immediately (no 130us delay)
00704 //Otherwise we enter Standby-II mode, which is still faster than standby mode
00705 //Also, we remove the need to keep writing the config register over and over and delaying for 150 us each time if sending a stream of data
00706 
00707 void RF24::startFastWrite( const void* buf, uint8_t len, const bool multicast, bool startTx){ //TMRh20
00708 
00709     //write_payload( buf,len);
00710     write_payload( buf, len,multicast ? W_TX_PAYLOAD_NO_ACK : W_TX_PAYLOAD ) ;
00711     if(startTx){
00712         ce(HIGH);
00713     }
00714 
00715 }
00716 
00717 /****************************************************************************/
00718 
00719 //Added the original startWrite back in so users can still use interrupts, ack payloads, etc
00720 //Allows the library to pass all tests
00721 void RF24::startWrite( const void* buf, uint8_t len, const bool multicast ){
00722 
00723   // Send the payload
00724 
00725   //write_payload( buf, len );
00726   write_payload( buf, len,multicast? W_TX_PAYLOAD_NO_ACK : W_TX_PAYLOAD ) ;
00727   ce(HIGH);
00728   
00729   wait_us(10);
00730   
00731   ce(LOW);
00732 
00733 
00734 }
00735 
00736 /****************************************************************************/
00737 
00738 bool RF24::rxFifoFull(){
00739     return read_register(FIFO_STATUS) & _BV(RX_FULL);
00740 }
00741 /****************************************************************************/
00742 
00743 bool RF24::txStandBy(){
00744 
00745     #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
00746         uint32_t timeout = mainTimer.read_ms();
00747     #endif
00748     while( ! (read_register(FIFO_STATUS) & _BV(TX_EMPTY)) ){
00749         if( get_status() & _BV(MAX_RT)){
00750             write_register(NRF_STATUS,_BV(MAX_RT) );
00751             ce(LOW);
00752             flush_tx();    //Non blocking, flush the data
00753             return 0;
00754         }
00755         #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
00756             if( mainTimer.read_ms() - timeout > 95){
00757                 errNotify();
00758                 #if defined (FAILURE_HANDLING)
00759                 return 0;   
00760                 #endif
00761             }
00762         #endif
00763     }
00764 
00765     ce(LOW);               //Set STANDBY-I mode
00766     return 1;
00767 }
00768 
00769 /****************************************************************************/
00770 
00771 bool RF24::txStandBy(uint32_t timeout, bool startTx){
00772 
00773     if(startTx){
00774       stopListening();
00775       ce(HIGH);
00776     }
00777     uint32_t start = mainTimer.read_ms();
00778 
00779     while( ! (read_register(FIFO_STATUS) & _BV(TX_EMPTY)) ){
00780         if( get_status() & _BV(MAX_RT)){
00781             write_register(NRF_STATUS,_BV(MAX_RT) );
00782                 ce(LOW);                                          //Set re-transmit
00783                 ce(HIGH);
00784                 if(mainTimer.read_ms() - start >= timeout){
00785                     ce(LOW); flush_tx(); return 0;
00786                 }
00787         }
00788         #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
00789             if( mainTimer.read_ms() - start > (timeout+95)){
00790                 errNotify();
00791                 #if defined (FAILURE_HANDLING)
00792                 return 0;   
00793                 #endif
00794             }
00795         #endif
00796     }
00797 
00798     
00799     ce(LOW);                   //Set STANDBY-I mode
00800     return 1;
00801 
00802 }
00803 
00804 /****************************************************************************/
00805 
00806 void RF24::maskIRQ(bool tx, bool fail, bool rx){
00807 
00808     uint8_t config = read_register(NRF_CONFIG);
00809     /* clear the interrupt flags */
00810     config &= ~(1 << MASK_MAX_RT | 1 << MASK_TX_DS | 1 << MASK_RX_DR);
00811     /* set the specified interrupt flags */
00812     config |= fail << MASK_MAX_RT | tx << MASK_TX_DS | rx << MASK_RX_DR;
00813     write_register(NRF_CONFIG, config);
00814 }
00815 
00816 /****************************************************************************/
00817 
00818 uint8_t RF24::getDynamicPayloadSize(void)
00819 {
00820   uint8_t result = 0;
00821 
00822   
00823   
00824   
00825   
00826   
00827   
00828   
00829   
00830   beginTransaction();
00831   spi.write( R_RX_PL_WID );
00832   result = spi.write(0xff);
00833   endTransaction();
00834   
00835 
00836   if(result > 32) { flush_rx(); wait_ms(2); return 0; }
00837   return result;
00838 }
00839 
00840 /****************************************************************************/
00841 
00842 bool RF24::available(void)
00843 {
00844   return available(NULL);
00845 }
00846 
00847 /****************************************************************************/
00848 
00849 bool RF24::available(uint8_t* pipe_num)
00850 {
00851   if (!( read_register(FIFO_STATUS) & _BV(RX_EMPTY) )){
00852 
00853     // If the caller wants the pipe number, include that
00854     if ( pipe_num ){
00855       uint8_t status = get_status();
00856       *pipe_num = ( status >> RX_P_NO ) & 0b111;
00857     }
00858     return 1;
00859   }
00860 
00861 
00862   return 0;
00863 
00864 
00865 }
00866 
00867 /****************************************************************************/
00868 
00869 void RF24::read( void* buf, uint8_t len ){
00870 
00871   // Fetch the payload
00872   read_payload( buf, len );
00873 
00874   //Clear the two possible interrupt flags with one command
00875   write_register(NRF_STATUS,_BV(RX_DR) | _BV(MAX_RT) | _BV(TX_DS) );
00876 
00877 }
00878 
00879 /****************************************************************************/
00880 
00881 void RF24::whatHappened(bool& tx_ok,bool& tx_fail,bool& rx_ready)
00882 {
00883   // Read the status & reset the status in one easy call
00884   // Or is that such a good idea?
00885   uint8_t status = write_register(NRF_STATUS,_BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) );
00886 
00887   // Report to the user what happened
00888   tx_ok = status & _BV(TX_DS);
00889   tx_fail = status & _BV(MAX_RT);
00890   rx_ready = status & _BV(RX_DR);
00891 }
00892 
00893 /****************************************************************************/
00894 
00895 void RF24::openWritingPipe(uint64_t value)
00896 {
00897   // Note that AVR 8-bit uC's store this LSB first, and the NRF24L01(+)
00898   // expects it LSB first too, so we're good.
00899 
00900   write_register(RX_ADDR_P0, reinterpret_cast<uint8_t*>(&value), addr_width);
00901   write_register(TX_ADDR, reinterpret_cast<uint8_t*>(&value), addr_width);
00902   
00903   
00904   //const uint8_t max_payload_size = 32;
00905   //write_register(RX_PW_P0,rf24_min(payload_size,max_payload_size));
00906   write_register(RX_PW_P0,payload_size);
00907 }
00908 
00909 /****************************************************************************/
00910 void RF24::openWritingPipe(const uint8_t *address)
00911 {
00912   // Note that AVR 8-bit uC's store this LSB first, and the NRF24L01(+)
00913   // expects it LSB first too, so we're good.
00914 
00915   write_register(RX_ADDR_P0,address, addr_width);
00916   write_register(TX_ADDR, address, addr_width);
00917 
00918   //const uint8_t max_payload_size = 32;
00919   //write_register(RX_PW_P0,rf24_min(payload_size,max_payload_size));
00920   write_register(RX_PW_P0,payload_size);
00921 }
00922 
00923 /****************************************************************************/
00924 static const uint8_t child_pipe[] PROGMEM =
00925 {
00926   RX_ADDR_P0, RX_ADDR_P1, RX_ADDR_P2, RX_ADDR_P3, RX_ADDR_P4, RX_ADDR_P5
00927 };
00928 static const uint8_t child_payload_size[] PROGMEM =
00929 {
00930   RX_PW_P0, RX_PW_P1, RX_PW_P2, RX_PW_P3, RX_PW_P4, RX_PW_P5
00931 };
00932 
00933 
00934 void RF24::openReadingPipe(uint8_t child, uint64_t address)
00935 {
00936   // If this is pipe 0, cache the address.  This is needed because
00937   // openWritingPipe() will overwrite the pipe 0 address, so
00938   // startListening() will have to restore it.
00939   if (child == 0){
00940     memcpy(pipe0_reading_address,&address,addr_width);
00941   }
00942 
00943   if (child <= 6)
00944   {
00945     // For pipes 2-5, only write the LSB
00946     if ( child < 2 )
00947       write_register(pgm_read_byte(&child_pipe[child]), reinterpret_cast<const uint8_t*>(&address), addr_width);
00948     else
00949       write_register(pgm_read_byte(&child_pipe[child]), reinterpret_cast<const uint8_t*>(&address), 1);
00950 
00951     write_register(pgm_read_byte(&child_payload_size[child]),payload_size);
00952 
00953     // Note it would be more efficient to set all of the bits for all open
00954     // pipes at once.  However, I thought it would make the calling code
00955     // more simple to do it this way.
00956     write_register(EN_RXADDR,read_register(EN_RXADDR) | _BV(pgm_read_byte(&child_pipe_enable[child])));
00957   }
00958 }
00959 
00960 /****************************************************************************/
00961 void RF24::setAddressWidth(uint8_t a_width){
00962 
00963     if(a_width -= 2){
00964         write_register(SETUP_AW,a_width%4);
00965         addr_width = (a_width%4) + 2;
00966     }
00967 
00968 }
00969 
00970 /****************************************************************************/
00971 
00972 void RF24::openReadingPipe(uint8_t child, const uint8_t *address)
00973 {
00974   // If this is pipe 0, cache the address.  This is needed because
00975   // openWritingPipe() will overwrite the pipe 0 address, so
00976   // startListening() will have to restore it.
00977   if (child == 0){
00978     memcpy(pipe0_reading_address,address,addr_width);
00979   }
00980   if (child <= 6)
00981   {
00982     // For pipes 2-5, only write the LSB
00983     if ( child < 2 ){
00984       write_register(pgm_read_byte(&child_pipe[child]), address, addr_width);
00985     }else{
00986       write_register(pgm_read_byte(&child_pipe[child]), address, 1);
00987     }
00988     write_register(pgm_read_byte(&child_payload_size[child]),payload_size);
00989 
00990     // Note it would be more efficient to set all of the bits for all open
00991     // pipes at once.  However, I thought it would make the calling code
00992     // more simple to do it this way.
00993     write_register(EN_RXADDR,read_register(EN_RXADDR) | _BV(pgm_read_byte(&child_pipe_enable[child])));
00994 
00995   }
00996 }
00997 
00998 /****************************************************************************/
00999 
01000 void RF24::closeReadingPipe( uint8_t pipe )
01001 {
01002   write_register(EN_RXADDR,read_register(EN_RXADDR) & ~_BV(pgm_read_byte(&child_pipe_enable[pipe])));
01003 }
01004 
01005 /****************************************************************************/
01006 
01007 void RF24::toggle_features(void)
01008 {
01009     beginTransaction();
01010     spi.write( ACTIVATE );
01011     spi.write( 0x73 );
01012     endTransaction();
01013 }
01014 
01015 /****************************************************************************/
01016 
01017 void RF24::enableDynamicPayloads(void)
01018 {
01019   // Enable dynamic payload throughout the system
01020 
01021     //toggle_features();
01022     write_register(FEATURE,read_register(FEATURE) | _BV(EN_DPL) );
01023 
01024 
01025   IF_SERIAL_DEBUG(printf("FEATURE=%i\r\n",read_register(FEATURE)));
01026 
01027   // Enable dynamic payload on all pipes
01028   //
01029   // Not sure the use case of only having dynamic payload on certain
01030   // pipes, so the library does not support it.
01031   write_register(DYNPD,read_register(DYNPD) | _BV(DPL_P5) | _BV(DPL_P4) | _BV(DPL_P3) | _BV(DPL_P2) | _BV(DPL_P1) | _BV(DPL_P0));
01032 
01033   dynamic_payloads_enabled = true;
01034 }
01035 
01036 /****************************************************************************/
01037 
01038 void RF24::enableAckPayload(void)
01039 {
01040   //
01041   // enable ack payload and dynamic payload features
01042   //
01043 
01044     //toggle_features();
01045     write_register(FEATURE,read_register(FEATURE) | _BV(EN_ACK_PAY) | _BV(EN_DPL) );
01046 
01047   IF_SERIAL_DEBUG(printf("FEATURE=%i\r\n",read_register(FEATURE)));
01048 
01049   //
01050   // Enable dynamic payload on pipes 0 & 1
01051   //
01052 
01053   write_register(DYNPD,read_register(DYNPD) | _BV(DPL_P1) | _BV(DPL_P0));
01054   dynamic_payloads_enabled = true;
01055 }
01056 
01057 /****************************************************************************/
01058 
01059 void RF24::enableDynamicAck(void){
01060   //
01061   // enable dynamic ack features
01062   //
01063     //toggle_features();
01064     write_register(FEATURE,read_register(FEATURE) | _BV(EN_DYN_ACK) );
01065 
01066   IF_SERIAL_DEBUG(printf("FEATURE=%i\r\n",read_register(FEATURE)));
01067 
01068 
01069 }
01070 
01071 /****************************************************************************/
01072 
01073 void RF24::writeAckPayload(uint8_t pipe, const void* buf, uint8_t len)
01074 {
01075   const uint8_t* current = reinterpret_cast<const uint8_t*>(buf);
01076 
01077   uint8_t data_len = rf24_min(len,32);
01078 
01079   
01080   
01081   
01082   
01083   
01084   
01085   
01086   
01087   
01088   
01089   
01090   
01091   beginTransaction();
01092   spi.write(W_ACK_PAYLOAD | ( pipe & 0b111 ) );
01093 
01094   while ( data_len-- )
01095     spi.write(*current++);
01096   endTransaction();
01097     
01098    
01099 
01100 }
01101 
01102 /****************************************************************************/
01103 
01104 bool RF24::isAckPayloadAvailable(void)
01105 {
01106   return ! (read_register(FIFO_STATUS) & _BV(RX_EMPTY));
01107 }
01108 
01109 /****************************************************************************/
01110 
01111 bool RF24::isPVariant(void)
01112 {
01113   return p_variant ;
01114 }
01115 
01116 /****************************************************************************/
01117 
01118 void RF24::setAutoAck(bool enable)
01119 {
01120   if ( enable )
01121     write_register(EN_AA, 0b111111);
01122   else
01123     write_register(EN_AA, 0);
01124 }
01125 
01126 /****************************************************************************/
01127 
01128 void RF24::setAutoAck( uint8_t pipe, bool enable )
01129 {
01130   if ( pipe <= 6 )
01131   {
01132     uint8_t en_aa = read_register( EN_AA ) ;
01133     if( enable )
01134     {
01135       en_aa |= _BV(pipe) ;
01136     }
01137     else
01138     {
01139       en_aa &= ~_BV(pipe) ;
01140     }
01141     write_register( EN_AA, en_aa ) ;
01142   }
01143 }
01144 
01145 /****************************************************************************/
01146 
01147 bool RF24::testCarrier(void)
01148 {
01149   return ( read_register(CD) & 1 );
01150 }
01151 
01152 /****************************************************************************/
01153 
01154 bool RF24::testRPD(void)
01155 {
01156   return ( read_register(RPD) & 1 ) ;
01157 }
01158 
01159 /****************************************************************************/
01160 
01161 void RF24::setPALevel(uint8_t level)
01162 {
01163 
01164   uint8_t setup = read_register(RF_SETUP) & 0b11111000;
01165 
01166   if(level > 3){                        // If invalid level, go to max PA
01167       level = (RF24_PA_MAX << 1) + 1;       // +1 to support the SI24R1 chip extra bit
01168   }else{
01169       level = (level << 1) + 1;         // Else set level as requested
01170   }
01171 
01172 
01173   write_register( RF_SETUP, setup |= level ) ;  // Write it to the chip
01174 }
01175 
01176 /****************************************************************************/
01177 
01178 uint8_t RF24::getPALevel(void)
01179 {
01180 
01181   return (read_register(RF_SETUP) & (_BV(RF_PWR_LOW) | _BV(RF_PWR_HIGH))) >> 1 ;
01182 }
01183 
01184 /****************************************************************************/
01185 
01186 bool RF24::setDataRate(rf24_datarate_e speed)
01187 {
01188   bool result = false;
01189   uint8_t setup = read_register(RF_SETUP) ;
01190 
01191   // HIGH and LOW '00' is 1Mbs - our default
01192   setup &= ~(_BV(RF_DR_LOW) | _BV(RF_DR_HIGH)) ;
01193   
01194   
01195   
01196   
01197     txRxDelay=85;
01198 
01199   if( speed == RF24_250KBPS )
01200   {
01201     // Must set the RF_DR_LOW to 1; RF_DR_HIGH (used to be RF_DR) is already 0
01202     // Making it '10'.
01203     setup |= _BV( RF_DR_LOW ) ;
01204  
01205  
01206  
01207     txRxDelay=155;
01208 
01209   }
01210   else
01211   {
01212     // Set 2Mbs, RF_DR (RF_DR_HIGH) is set 1
01213     // Making it '01'
01214     if ( speed == RF24_2MBPS )
01215     {
01216       setup |= _BV(RF_DR_HIGH);
01217       
01218       
01219       //txRxDelay=65;
01220       txRxDelay=15; //mbed works fine with this latency
01221       
01222     }
01223   }
01224   write_register(RF_SETUP,setup);
01225 
01226   // Verify our result
01227   if ( read_register(RF_SETUP) == setup )
01228   {
01229     result = true;
01230   }
01231   return result;
01232 }
01233 
01234 /****************************************************************************/
01235 
01236 rf24_datarate_e RF24::getDataRate( void )
01237 {
01238   rf24_datarate_e result ;
01239   uint8_t dr = read_register(RF_SETUP) & (_BV(RF_DR_LOW) | _BV(RF_DR_HIGH));
01240 
01241   // switch uses RAM (evil!)
01242   // Order matters in our case below
01243   if ( dr == _BV(RF_DR_LOW) )
01244   {
01245     // '10' = 250KBPS
01246     result = RF24_250KBPS ;
01247   }
01248   else if ( dr == _BV(RF_DR_HIGH) )
01249   {
01250     // '01' = 2MBPS
01251     result = RF24_2MBPS ;
01252   }
01253   else
01254   {
01255     // '00' = 1MBPS
01256     result = RF24_1MBPS ;
01257   }
01258   return result ;
01259 }
01260 
01261 /****************************************************************************/
01262 
01263 void RF24::setCRCLength(rf24_crclength_e length)
01264 {
01265   uint8_t config = read_register(NRF_CONFIG) & ~( _BV(CRCO) | _BV(EN_CRC)) ;
01266 
01267   // switch uses RAM (evil!)
01268   if ( length == RF24_CRC_DISABLED )
01269   {
01270     // Do nothing, we turned it off above.
01271   }
01272   else if ( length == RF24_CRC_8 )
01273   {
01274     config |= _BV(EN_CRC);
01275   }
01276   else
01277   {
01278     config |= _BV(EN_CRC);
01279     config |= _BV( CRCO );
01280   }
01281   write_register( NRF_CONFIG, config ) ;
01282 }
01283 
01284 /****************************************************************************/
01285 
01286 rf24_crclength_e RF24::getCRCLength(void)
01287 {
01288   rf24_crclength_e result = RF24_CRC_DISABLED;
01289   
01290   uint8_t config = read_register(NRF_CONFIG) & ( _BV(CRCO) | _BV(EN_CRC)) ;
01291   uint8_t AA = read_register(EN_AA);
01292   
01293   if ( config & _BV(EN_CRC ) || AA)
01294   {
01295     if ( config & _BV(CRCO) )
01296       result = RF24_CRC_16;
01297     else
01298       result = RF24_CRC_8;
01299   }
01300 
01301   return result;
01302 }
01303 
01304 /****************************************************************************/
01305 
01306 void RF24::disableCRC( void )
01307 {
01308   uint8_t disable = read_register(NRF_CONFIG) & ~_BV(EN_CRC) ;
01309   write_register( NRF_CONFIG, disable ) ;
01310 }
01311 
01312 /****************************************************************************/
01313 void RF24::setRetries(uint8_t delay, uint8_t count)
01314 {
01315  write_register(SETUP_RETR,(delay&0xf)<<ARD | (count&0xf)<<ARC);
01316 }
01317 
01318 /****************************************************************************/
01319 bool RF24::isChipConnected()
01320 {
01321   uint8_t setup = read_register(SETUP_AW);
01322   if(setup >= 1 && setup <= 3) return true;
01323 
01324   return false;
01325 }