BA
/
SerialCom
Important changes to repositories hosted on mbed.com
Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.
To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.
It is also possible to export all your personal repositories from the account settings page.
Fork of
OmniWheels
by 
Gustav Atmel
mbed-os/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_clk.c@1:9c5af431a1f1, 2018-05-01 (annotated)
- Committer:
- gustavatmel
- Date:
- Tue May 01 15:47:08 2018 +0000
- Revision:
- 1:9c5af431a1f1
sdf
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| gustavatmel | 1:9c5af431a1f1 | 1 | /**************************************************************************//** |
| gustavatmel | 1:9c5af431a1f1 | 2 | * @file clk.c |
| gustavatmel | 1:9c5af431a1f1 | 3 | * @version V1.00 |
| gustavatmel | 1:9c5af431a1f1 | 4 | * $Revision: 35 $ |
| gustavatmel | 1:9c5af431a1f1 | 5 | * $Date: 16/03/04 3:42p $ |
| gustavatmel | 1:9c5af431a1f1 | 6 | * @brief NUC472/NUC442 CLK driver source file |
| gustavatmel | 1:9c5af431a1f1 | 7 | * |
| gustavatmel | 1:9c5af431a1f1 | 8 | * @note |
| gustavatmel | 1:9c5af431a1f1 | 9 | * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved. |
| gustavatmel | 1:9c5af431a1f1 | 10 | *****************************************************************************/ |
| gustavatmel | 1:9c5af431a1f1 | 11 | |
| gustavatmel | 1:9c5af431a1f1 | 12 | #include "NUC472_442.h" |
| gustavatmel | 1:9c5af431a1f1 | 13 | /** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver |
| gustavatmel | 1:9c5af431a1f1 | 14 | @{ |
| gustavatmel | 1:9c5af431a1f1 | 15 | */ |
| gustavatmel | 1:9c5af431a1f1 | 16 | |
| gustavatmel | 1:9c5af431a1f1 | 17 | /** @addtogroup NUC472_442_CLK_Driver CLK Driver |
| gustavatmel | 1:9c5af431a1f1 | 18 | @{ |
| gustavatmel | 1:9c5af431a1f1 | 19 | */ |
| gustavatmel | 1:9c5af431a1f1 | 20 | |
| gustavatmel | 1:9c5af431a1f1 | 21 | |
| gustavatmel | 1:9c5af431a1f1 | 22 | /** @addtogroup NUC472_442_CLK_EXPORTED_FUNCTIONS CLK Exported Functions |
| gustavatmel | 1:9c5af431a1f1 | 23 | @{ |
| gustavatmel | 1:9c5af431a1f1 | 24 | */ |
| gustavatmel | 1:9c5af431a1f1 | 25 | |
| gustavatmel | 1:9c5af431a1f1 | 26 | |
| gustavatmel | 1:9c5af431a1f1 | 27 | /** |
| gustavatmel | 1:9c5af431a1f1 | 28 | * @brief Disable frequency output function |
| gustavatmel | 1:9c5af431a1f1 | 29 | * @return None |
| gustavatmel | 1:9c5af431a1f1 | 30 | * @details This function disable frequency output function. |
| gustavatmel | 1:9c5af431a1f1 | 31 | */ |
| gustavatmel | 1:9c5af431a1f1 | 32 | void CLK_DisableCKO(void) |
| gustavatmel | 1:9c5af431a1f1 | 33 | { |
| gustavatmel | 1:9c5af431a1f1 | 34 | /* Disable CKO clock source */ |
| gustavatmel | 1:9c5af431a1f1 | 35 | CLK->APBCLK0 &= (~CLK_APBCLK0_CLKOCKEN_Msk); |
| gustavatmel | 1:9c5af431a1f1 | 36 | } |
| gustavatmel | 1:9c5af431a1f1 | 37 | |
| gustavatmel | 1:9c5af431a1f1 | 38 | /** |
| gustavatmel | 1:9c5af431a1f1 | 39 | * @brief This function enable frequency divider module clock, |
| gustavatmel | 1:9c5af431a1f1 | 40 | * enable frequency divider clock function and configure frequency divider. |
| gustavatmel | 1:9c5af431a1f1 | 41 | * @param[in] u32ClkSrc is frequency divider function clock source |
| gustavatmel | 1:9c5af431a1f1 | 42 | * - \ref CLK_CLKSEL1_CLKOSEL_HXT |
| gustavatmel | 1:9c5af431a1f1 | 43 | * - \ref CLK_CLKSEL1_CLKOSEL_LXT |
| gustavatmel | 1:9c5af431a1f1 | 44 | * - \ref CLK_CLKSEL1_CLKOSEL_HCLK |
| gustavatmel | 1:9c5af431a1f1 | 45 | * - \ref CLK_CLKSEL1_CLKOSEL_HIRC |
| gustavatmel | 1:9c5af431a1f1 | 46 | * @param[in] u32ClkDiv is system reset source |
| gustavatmel | 1:9c5af431a1f1 | 47 | * @param[in] u32ClkDivBy1En is frequency divided by one enable. |
| gustavatmel | 1:9c5af431a1f1 | 48 | * @return None |
| gustavatmel | 1:9c5af431a1f1 | 49 | * |
| gustavatmel | 1:9c5af431a1f1 | 50 | * @details Output selected clock to CKO. The output clock frequency is divided by u32ClkDiv. |
| gustavatmel | 1:9c5af431a1f1 | 51 | * The formula is: |
| gustavatmel | 1:9c5af431a1f1 | 52 | * CKO frequency = (Clock source frequency) / 2^(u32ClkDiv + 1) |
| gustavatmel | 1:9c5af431a1f1 | 53 | * This function is just used to set CKO clock. |
| gustavatmel | 1:9c5af431a1f1 | 54 | * User must enable I/O for CKO clock output pin by themselves. |
| gustavatmel | 1:9c5af431a1f1 | 55 | */ |
| gustavatmel | 1:9c5af431a1f1 | 56 | void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En) |
| gustavatmel | 1:9c5af431a1f1 | 57 | { |
| gustavatmel | 1:9c5af431a1f1 | 58 | /* CKO = clock source / 2^(u32ClkDiv + 1) */ |
| gustavatmel | 1:9c5af431a1f1 | 59 | CLK->CLKOCTL = CLK_CLKOCTL_CLKOEN_Msk | u32ClkDiv | u32ClkDivBy1En<<CLK_CLKOCTL_DIV1EN_Pos; |
| gustavatmel | 1:9c5af431a1f1 | 60 | |
| gustavatmel | 1:9c5af431a1f1 | 61 | /* Enable CKO clock source */ |
| gustavatmel | 1:9c5af431a1f1 | 62 | CLK->APBCLK0 |= CLK_APBCLK0_CLKOCKEN_Msk; |
| gustavatmel | 1:9c5af431a1f1 | 63 | |
| gustavatmel | 1:9c5af431a1f1 | 64 | /* Select CKO clock source */ |
| gustavatmel | 1:9c5af431a1f1 | 65 | CLK->CLKSEL1 = (CLK->CLKSEL1 & (~CLK_CLKSEL1_CLKOSEL_Msk)) | u32ClkSrc; |
| gustavatmel | 1:9c5af431a1f1 | 66 | } |
| gustavatmel | 1:9c5af431a1f1 | 67 | |
| gustavatmel | 1:9c5af431a1f1 | 68 | /** |
| gustavatmel | 1:9c5af431a1f1 | 69 | * @brief Enter to Power-down mode |
| gustavatmel | 1:9c5af431a1f1 | 70 | * @return None |
| gustavatmel | 1:9c5af431a1f1 | 71 | * @details This function let system enter to Power-down mode. |
| gustavatmel | 1:9c5af431a1f1 | 72 | */ |
| gustavatmel | 1:9c5af431a1f1 | 73 | void CLK_PowerDown(void) |
| gustavatmel | 1:9c5af431a1f1 | 74 | { |
| gustavatmel | 1:9c5af431a1f1 | 75 | SCB->SCR = SCB_SCR_SLEEPDEEP_Msk; |
| gustavatmel | 1:9c5af431a1f1 | 76 | CLK->PWRCTL |= (CLK_PWRCTL_PDEN_Msk | CLK_PWRCTL_PDWKDLY_Msk ); |
| gustavatmel | 1:9c5af431a1f1 | 77 | __WFI(); |
| gustavatmel | 1:9c5af431a1f1 | 78 | } |
| gustavatmel | 1:9c5af431a1f1 | 79 | |
| gustavatmel | 1:9c5af431a1f1 | 80 | /** |
| gustavatmel | 1:9c5af431a1f1 | 81 | * @brief Enter to Idle mode. |
| gustavatmel | 1:9c5af431a1f1 | 82 | * @return None |
| gustavatmel | 1:9c5af431a1f1 | 83 | * @details This function let system enter to Idle mode. |
| gustavatmel | 1:9c5af431a1f1 | 84 | */ |
| gustavatmel | 1:9c5af431a1f1 | 85 | void CLK_Idle(void) |
| gustavatmel | 1:9c5af431a1f1 | 86 | { |
| gustavatmel | 1:9c5af431a1f1 | 87 | /* Set the processor uses sleep as its low power mode */ |
| gustavatmel | 1:9c5af431a1f1 | 88 | SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; |
| gustavatmel | 1:9c5af431a1f1 | 89 | |
| gustavatmel | 1:9c5af431a1f1 | 90 | /* Set chip in idle mode because of WFI command */ |
| gustavatmel | 1:9c5af431a1f1 | 91 | CLK->PWRCTL &= ~(CLK_PWRCTL_PDEN_Msk ); |
| gustavatmel | 1:9c5af431a1f1 | 92 | |
| gustavatmel | 1:9c5af431a1f1 | 93 | /* Chip enter idle mode after CPU run WFI instruction */ |
| gustavatmel | 1:9c5af431a1f1 | 94 | __WFI(); |
| gustavatmel | 1:9c5af431a1f1 | 95 | } |
| gustavatmel | 1:9c5af431a1f1 | 96 | |
| gustavatmel | 1:9c5af431a1f1 | 97 | |
| gustavatmel | 1:9c5af431a1f1 | 98 | /** |
| gustavatmel | 1:9c5af431a1f1 | 99 | * @brief This function get PCLK frequency. The frequency unit is Hz. |
| gustavatmel | 1:9c5af431a1f1 | 100 | * @return PCLK frequency |
| gustavatmel | 1:9c5af431a1f1 | 101 | */ |
| gustavatmel | 1:9c5af431a1f1 | 102 | uint32_t CLK_GetPCLKFreq(void) |
| gustavatmel | 1:9c5af431a1f1 | 103 | { |
| gustavatmel | 1:9c5af431a1f1 | 104 | SystemCoreClockUpdate(); |
| gustavatmel | 1:9c5af431a1f1 | 105 | if(CLK->CLKSEL0 & CLK_CLKSEL0_PCLKSEL_Msk) |
| gustavatmel | 1:9c5af431a1f1 | 106 | return SystemCoreClock/2; |
| gustavatmel | 1:9c5af431a1f1 | 107 | else |
| gustavatmel | 1:9c5af431a1f1 | 108 | return SystemCoreClock; |
| gustavatmel | 1:9c5af431a1f1 | 109 | } |
| gustavatmel | 1:9c5af431a1f1 | 110 | |
| gustavatmel | 1:9c5af431a1f1 | 111 | /** |
| gustavatmel | 1:9c5af431a1f1 | 112 | * @brief Get external high speed crystal clock frequency |
| gustavatmel | 1:9c5af431a1f1 | 113 | * @return External high frequency crystal frequency |
| gustavatmel | 1:9c5af431a1f1 | 114 | * @details This function get external high frequency crystal frequency. The frequency unit is Hz. |
| gustavatmel | 1:9c5af431a1f1 | 115 | */ |
| gustavatmel | 1:9c5af431a1f1 | 116 | uint32_t CLK_GetHXTFreq(void) |
| gustavatmel | 1:9c5af431a1f1 | 117 | { |
| gustavatmel | 1:9c5af431a1f1 | 118 | if(CLK->PWRCTL & CLK_PWRCTL_HXTEN_Msk ) |
| gustavatmel | 1:9c5af431a1f1 | 119 | return __HXT; |
| gustavatmel | 1:9c5af431a1f1 | 120 | else |
| gustavatmel | 1:9c5af431a1f1 | 121 | return 0; |
| gustavatmel | 1:9c5af431a1f1 | 122 | } |
| gustavatmel | 1:9c5af431a1f1 | 123 | |
| gustavatmel | 1:9c5af431a1f1 | 124 | /** |
| gustavatmel | 1:9c5af431a1f1 | 125 | * @brief Get external low speed crystal clock frequency |
| gustavatmel | 1:9c5af431a1f1 | 126 | * @return External low speed crystal clock frequency |
| gustavatmel | 1:9c5af431a1f1 | 127 | * @details This function get external low frequency crystal frequency. The frequency unit is Hz. |
| gustavatmel | 1:9c5af431a1f1 | 128 | */ |
| gustavatmel | 1:9c5af431a1f1 | 129 | uint32_t CLK_GetLXTFreq(void) |
| gustavatmel | 1:9c5af431a1f1 | 130 | { |
| gustavatmel | 1:9c5af431a1f1 | 131 | if(CLK->PWRCTL & CLK_PWRCTL_LXTEN_Msk ) |
| gustavatmel | 1:9c5af431a1f1 | 132 | return __LXT; |
| gustavatmel | 1:9c5af431a1f1 | 133 | else |
| gustavatmel | 1:9c5af431a1f1 | 134 | return 0; |
| gustavatmel | 1:9c5af431a1f1 | 135 | } |
| gustavatmel | 1:9c5af431a1f1 | 136 | |
| gustavatmel | 1:9c5af431a1f1 | 137 | |
| gustavatmel | 1:9c5af431a1f1 | 138 | /** |
| gustavatmel | 1:9c5af431a1f1 | 139 | * @brief Get HCLK frequency |
| gustavatmel | 1:9c5af431a1f1 | 140 | * @return HCLK frequency |
| gustavatmel | 1:9c5af431a1f1 | 141 | * @details This function get HCLK frequency. The frequency unit is Hz. |
| gustavatmel | 1:9c5af431a1f1 | 142 | */ |
| gustavatmel | 1:9c5af431a1f1 | 143 | uint32_t CLK_GetHCLKFreq(void) |
| gustavatmel | 1:9c5af431a1f1 | 144 | { |
| gustavatmel | 1:9c5af431a1f1 | 145 | SystemCoreClockUpdate(); |
| gustavatmel | 1:9c5af431a1f1 | 146 | return SystemCoreClock; |
| gustavatmel | 1:9c5af431a1f1 | 147 | } |
| gustavatmel | 1:9c5af431a1f1 | 148 | |
| gustavatmel | 1:9c5af431a1f1 | 149 | /** |
| gustavatmel | 1:9c5af431a1f1 | 150 | * @brief Get CPU frequency |
| gustavatmel | 1:9c5af431a1f1 | 151 | * @return CPU frequency |
| gustavatmel | 1:9c5af431a1f1 | 152 | * @details This function get CPU frequency. The frequency unit is Hz. |
| gustavatmel | 1:9c5af431a1f1 | 153 | */ |
| gustavatmel | 1:9c5af431a1f1 | 154 | uint32_t CLK_GetCPUFreq(void) |
| gustavatmel | 1:9c5af431a1f1 | 155 | { |
| gustavatmel | 1:9c5af431a1f1 | 156 | SystemCoreClockUpdate(); |
| gustavatmel | 1:9c5af431a1f1 | 157 | return SystemCoreClock; |
| gustavatmel | 1:9c5af431a1f1 | 158 | } |
| gustavatmel | 1:9c5af431a1f1 | 159 | |
| gustavatmel | 1:9c5af431a1f1 | 160 | /** |
| gustavatmel | 1:9c5af431a1f1 | 161 | * @brief This function get PLL frequency. The frequency unit is Hz. |
| gustavatmel | 1:9c5af431a1f1 | 162 | * @return PLL frequency |
| gustavatmel | 1:9c5af431a1f1 | 163 | */ |
| gustavatmel | 1:9c5af431a1f1 | 164 | uint32_t CLK_GetPLLClockFreq(void) |
| gustavatmel | 1:9c5af431a1f1 | 165 | { |
| gustavatmel | 1:9c5af431a1f1 | 166 | uint32_t u32Freq =0, u32PLLSrc; |
| gustavatmel | 1:9c5af431a1f1 | 167 | uint32_t u32NO,u32NF,u32NR,u32PllReg; |
| gustavatmel | 1:9c5af431a1f1 | 168 | |
| gustavatmel | 1:9c5af431a1f1 | 169 | u32PllReg = CLK->PLLCTL; |
| gustavatmel | 1:9c5af431a1f1 | 170 | |
| gustavatmel | 1:9c5af431a1f1 | 171 | if(u32PllReg & (CLK_PLLCTL_PD_Msk | CLK_PLLCTL_OE_Msk)) |
| gustavatmel | 1:9c5af431a1f1 | 172 | return 0; /* PLL is in power down mode or fix low */ |
| gustavatmel | 1:9c5af431a1f1 | 173 | |
| gustavatmel | 1:9c5af431a1f1 | 174 | if(u32PllReg & CLK_PLLCTL_PLLSRC_Msk) |
| gustavatmel | 1:9c5af431a1f1 | 175 | u32PLLSrc = __HIRC; |
| gustavatmel | 1:9c5af431a1f1 | 176 | else |
| gustavatmel | 1:9c5af431a1f1 | 177 | u32PLLSrc = __HXT; |
| gustavatmel | 1:9c5af431a1f1 | 178 | |
| gustavatmel | 1:9c5af431a1f1 | 179 | u32NO=(u32PllReg & CLK_PLLCTL_OUTDV_Msk)>>CLK_PLLCTL_OUTDV_Pos; |
| gustavatmel | 1:9c5af431a1f1 | 180 | switch(u32NO) { |
| gustavatmel | 1:9c5af431a1f1 | 181 | case 0: |
| gustavatmel | 1:9c5af431a1f1 | 182 | u32NO=1; |
| gustavatmel | 1:9c5af431a1f1 | 183 | break; |
| gustavatmel | 1:9c5af431a1f1 | 184 | case 1: |
| gustavatmel | 1:9c5af431a1f1 | 185 | case 2: |
| gustavatmel | 1:9c5af431a1f1 | 186 | u32NO=2; |
| gustavatmel | 1:9c5af431a1f1 | 187 | break; |
| gustavatmel | 1:9c5af431a1f1 | 188 | case 3: |
| gustavatmel | 1:9c5af431a1f1 | 189 | u32NO=4; |
| gustavatmel | 1:9c5af431a1f1 | 190 | break; |
| gustavatmel | 1:9c5af431a1f1 | 191 | } |
| gustavatmel | 1:9c5af431a1f1 | 192 | |
| gustavatmel | 1:9c5af431a1f1 | 193 | u32NF = (u32PllReg & CLK_PLLCTL_FBDIV_Msk) + 2; |
| gustavatmel | 1:9c5af431a1f1 | 194 | u32NR = ( (u32PllReg & CLK_PLLCTL_INDIV_Msk)>>CLK_PLLCTL_INDIV_Pos ) + 2; |
| gustavatmel | 1:9c5af431a1f1 | 195 | |
| gustavatmel | 1:9c5af431a1f1 | 196 | /* u32PLLSrc is shifted 2 bits to avoid overflow */ |
| gustavatmel | 1:9c5af431a1f1 | 197 | u32Freq = (((u32PLLSrc >> 2) * u32NF) / (u32NR * u32NO) << 2); |
| gustavatmel | 1:9c5af431a1f1 | 198 | return u32Freq; |
| gustavatmel | 1:9c5af431a1f1 | 199 | } |
| gustavatmel | 1:9c5af431a1f1 | 200 | |
| gustavatmel | 1:9c5af431a1f1 | 201 | /** |
| gustavatmel | 1:9c5af431a1f1 | 202 | * @brief Set HCLK frequency |
| gustavatmel | 1:9c5af431a1f1 | 203 | * @param[in] u32Hclk is HCLK frequency |
| gustavatmel | 1:9c5af431a1f1 | 204 | * @return HCLK frequency |
| gustavatmel | 1:9c5af431a1f1 | 205 | * @details This function set HCLK frequency. The frequency unit is Hz. The range of u32Hclk is 24 MHz ~ 96 MHz. |
| gustavatmel | 1:9c5af431a1f1 | 206 | */ |
| gustavatmel | 1:9c5af431a1f1 | 207 | uint32_t CLK_SetCoreClock(uint32_t u32Hclk) |
| gustavatmel | 1:9c5af431a1f1 | 208 | { |
| gustavatmel | 1:9c5af431a1f1 | 209 | uint32_t u32ClkSrc,u32NR, u32NF,u32Register; |
| gustavatmel | 1:9c5af431a1f1 | 210 | u32ClkSrc = CLK->CLKSEL0 & CLK_CLKSEL0_HCLKSEL_Msk; |
| gustavatmel | 1:9c5af431a1f1 | 211 | |
| gustavatmel | 1:9c5af431a1f1 | 212 | if(u32Hclk < FREQ_24MHZ) |
| gustavatmel | 1:9c5af431a1f1 | 213 | u32Hclk =FREQ_24MHZ; |
| gustavatmel | 1:9c5af431a1f1 | 214 | |
| gustavatmel | 1:9c5af431a1f1 | 215 | if(CLK->PWRCTL & CLK_PWRCTL_HXTEN_Msk) { |
| gustavatmel | 1:9c5af431a1f1 | 216 | u32Register = 0<<CLK_PLLCTL_PLLSRC_Pos; |
| gustavatmel | 1:9c5af431a1f1 | 217 | u32ClkSrc = __HXT; |
| gustavatmel | 1:9c5af431a1f1 | 218 | } else { |
| gustavatmel | 1:9c5af431a1f1 | 219 | u32Register = 1<<CLK_PLLCTL_PLLSRC_Pos; |
| gustavatmel | 1:9c5af431a1f1 | 220 | u32ClkSrc = __HIRC; |
| gustavatmel | 1:9c5af431a1f1 | 221 | } |
| gustavatmel | 1:9c5af431a1f1 | 222 | |
| gustavatmel | 1:9c5af431a1f1 | 223 | if(u32Hclk<FREQ_50MHZ) { |
| gustavatmel | 1:9c5af431a1f1 | 224 | u32Hclk <<=2; |
| gustavatmel | 1:9c5af431a1f1 | 225 | u32Register |= (0x3<<CLK_PLLCTL_OUTDV_Pos); |
| gustavatmel | 1:9c5af431a1f1 | 226 | } else { |
| gustavatmel | 1:9c5af431a1f1 | 227 | u32Hclk <<=1; |
| gustavatmel | 1:9c5af431a1f1 | 228 | u32Register |= (0x1<<CLK_PLLCTL_OUTDV_Pos); |
| gustavatmel | 1:9c5af431a1f1 | 229 | } |
| gustavatmel | 1:9c5af431a1f1 | 230 | u32NF = u32Hclk / 1000000; |
| gustavatmel | 1:9c5af431a1f1 | 231 | u32NR = u32ClkSrc / 1000000; |
| gustavatmel | 1:9c5af431a1f1 | 232 | while( u32NR>(0xF+2) || u32NF>(0xFF+2) ) { |
| gustavatmel | 1:9c5af431a1f1 | 233 | u32NR = u32NR>>1; |
| gustavatmel | 1:9c5af431a1f1 | 234 | u32NF = u32NF>>1; |
| gustavatmel | 1:9c5af431a1f1 | 235 | } |
| gustavatmel | 1:9c5af431a1f1 | 236 | CLK->PLLCTL = u32Register | ((u32NR - 2)<<9) | (u32NF - 2) ; |
| gustavatmel | 1:9c5af431a1f1 | 237 | CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk); |
| gustavatmel | 1:9c5af431a1f1 | 238 | |
| gustavatmel | 1:9c5af431a1f1 | 239 | CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL,CLK_CLKDIV0_HCLK(1)); |
| gustavatmel | 1:9c5af431a1f1 | 240 | |
| gustavatmel | 1:9c5af431a1f1 | 241 | /* Update System Core Clock */ |
| gustavatmel | 1:9c5af431a1f1 | 242 | SystemCoreClockUpdate(); |
| gustavatmel | 1:9c5af431a1f1 | 243 | |
| gustavatmel | 1:9c5af431a1f1 | 244 | return SystemCoreClock; |
| gustavatmel | 1:9c5af431a1f1 | 245 | } |
| gustavatmel | 1:9c5af431a1f1 | 246 | |
| gustavatmel | 1:9c5af431a1f1 | 247 | /** |
| gustavatmel | 1:9c5af431a1f1 | 248 | * @brief This function set HCLK clock source and HCLK clock divider |
| gustavatmel | 1:9c5af431a1f1 | 249 | * @param[in] u32ClkSrc is HCLK clock source. Including : |
| gustavatmel | 1:9c5af431a1f1 | 250 | * - \ref CLK_CLKSEL0_HCLKSEL_HXT |
| gustavatmel | 1:9c5af431a1f1 | 251 | * - \ref CLK_CLKSEL0_HCLKSEL_LXT |
| gustavatmel | 1:9c5af431a1f1 | 252 | * - \ref CLK_CLKSEL0_HCLKSEL_PLL |
| gustavatmel | 1:9c5af431a1f1 | 253 | * - \ref CLK_CLKSEL0_HCLKSEL_LIRC |
| gustavatmel | 1:9c5af431a1f1 | 254 | * - \ref CLK_CLKSEL0_HCLKSEL_HIRC |
| gustavatmel | 1:9c5af431a1f1 | 255 | * @param[in] u32ClkDiv is HCLK clock divider. Including : |
| gustavatmel | 1:9c5af431a1f1 | 256 | * - \ref CLK_CLKDIV0_HCLK(x) |
| gustavatmel | 1:9c5af431a1f1 | 257 | * @return None |
| gustavatmel | 1:9c5af431a1f1 | 258 | */ |
| gustavatmel | 1:9c5af431a1f1 | 259 | void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv) |
| gustavatmel | 1:9c5af431a1f1 | 260 | { |
| gustavatmel | 1:9c5af431a1f1 | 261 | CLK->CLKDIV0 = (CLK->CLKDIV0 & ~CLK_CLKDIV0_HCLKDIV_Msk) | u32ClkDiv; |
| gustavatmel | 1:9c5af431a1f1 | 262 | CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_HCLKSEL_Msk) | u32ClkSrc; |
| gustavatmel | 1:9c5af431a1f1 | 263 | SystemCoreClockUpdate(); |
| gustavatmel | 1:9c5af431a1f1 | 264 | } |
| gustavatmel | 1:9c5af431a1f1 | 265 | |
| gustavatmel | 1:9c5af431a1f1 | 266 | /** |
| gustavatmel | 1:9c5af431a1f1 | 267 | * @brief This function set selected module clock source and module clock divider |
| gustavatmel | 1:9c5af431a1f1 | 268 | * @param[in] u32ModuleIdx is module index. |
| gustavatmel | 1:9c5af431a1f1 | 269 | * @param[in] u32ClkSrc is module clock source. |
| gustavatmel | 1:9c5af431a1f1 | 270 | * @param[in] u32ClkDiv is module clock divider. |
| gustavatmel | 1:9c5af431a1f1 | 271 | * @return None |
| gustavatmel | 1:9c5af431a1f1 | 272 | * @details Valid parameter combinations listed in following table: |
| gustavatmel | 1:9c5af431a1f1 | 273 | * |
| gustavatmel | 1:9c5af431a1f1 | 274 | * |Module index |Clock source |Divider | |
| gustavatmel | 1:9c5af431a1f1 | 275 | * | :------------------- | :------------------------------- | :------------------------- | |
| gustavatmel | 1:9c5af431a1f1 | 276 | * |\ref PDMA_MODULE | x | x | |
| gustavatmel | 1:9c5af431a1f1 | 277 | * |\ref ISP_MODULE | x | x | |
| gustavatmel | 1:9c5af431a1f1 | 278 | * |\ref EBI_MODULE | x | x | |
| gustavatmel | 1:9c5af431a1f1 | 279 | * |\ref USBH_MODULE |\ref CLK_CLKSEL0_USBHSEL_PLL |\ref CLK_CLKDIV0_USB(x) | |
| gustavatmel | 1:9c5af431a1f1 | 280 | * |\ref USBH_MODULE |\ref CLK_CLKSEL0_USBHSEL_PLL2 |\ref CLK_CLKDIV0_USB(x) | |
| gustavatmel | 1:9c5af431a1f1 | 281 | * |\ref EMAC_MODULE | x |\ref CLK_CLKDIV3_EMAC(x) | |
| gustavatmel | 1:9c5af431a1f1 | 282 | * |\ref SDH_MODULE |\ref CLK_CLKSEL0_SDHSEL_HXT |\ref CLK_CLKDIV0_SDH(x) | |
| gustavatmel | 1:9c5af431a1f1 | 283 | * |\ref SDH_MODULE |\ref CLK_CLKSEL0_SDHSEL_PLL |\ref CLK_CLKDIV0_SDH(x) | |
| gustavatmel | 1:9c5af431a1f1 | 284 | * |\ref SDH_MODULE |\ref CLK_CLKSEL0_SDHSEL_HCLK |\ref CLK_CLKDIV0_SDH(x) | |
| gustavatmel | 1:9c5af431a1f1 | 285 | * |\ref SDH_MODULE |\ref CLK_CLKSEL0_SDHSEL_HIRC |\ref CLK_CLKDIV0_SDH(x) | |
| gustavatmel | 1:9c5af431a1f1 | 286 | * |\ref CRC_MODULE | x | x | |
| gustavatmel | 1:9c5af431a1f1 | 287 | * |\ref CAP_MODULE |\ref CLK_CLKSEL0_CAPSEL_HXT |\ref CLK_CLKDIV3_CAP(x) | |
| gustavatmel | 1:9c5af431a1f1 | 288 | * |\ref CAP_MODULE |\ref CLK_CLKSEL0_CAPSEL_PLL2 |\ref CLK_CLKDIV3_CAP(x) | |
| gustavatmel | 1:9c5af431a1f1 | 289 | * |\ref CAP_MODULE |\ref CLK_CLKSEL0_CAPSEL_HCLK |\ref CLK_CLKDIV3_CAP(x) | |
| gustavatmel | 1:9c5af431a1f1 | 290 | * |\ref CAP_MODULE |\ref CLK_CLKSEL0_CAPSEL_HIRC |\ref CLK_CLKDIV3_CAP(x) | |
| gustavatmel | 1:9c5af431a1f1 | 291 | * |\ref SEN_MODULE | x | x | |
| gustavatmel | 1:9c5af431a1f1 | 292 | * |\ref USBD_MODULE | x | x | |
| gustavatmel | 1:9c5af431a1f1 | 293 | * |\ref CRPT_MODULE | x | x | |
| gustavatmel | 1:9c5af431a1f1 | 294 | * |\ref ECAP1_MODULE | x | x | |
| gustavatmel | 1:9c5af431a1f1 | 295 | * |\ref ECAP0_MODULE | x | x | |
| gustavatmel | 1:9c5af431a1f1 | 296 | * |\ref EADC_MODULE |\ref CLK_CLKSEL1_ADCSEL_HXT |\ref CLK_CLKDIV0_ADC(x) | |
| gustavatmel | 1:9c5af431a1f1 | 297 | * |\ref EADC_MODULE |\ref CLK_CLKSEL1_ADCSEL_PLL |\ref CLK_CLKDIV0_ADC(x) | |
| gustavatmel | 1:9c5af431a1f1 | 298 | * |\ref EADC_MODULE |\ref CLK_CLKSEL1_ADCSEL_PCLK |\ref CLK_CLKDIV0_ADC(x) | |
| gustavatmel | 1:9c5af431a1f1 | 299 | * |\ref EADC_MODULE |\ref CLK_CLKSEL1_ADCSEL_HIRC |\ref CLK_CLKDIV0_ADC(x) | |
| gustavatmel | 1:9c5af431a1f1 | 300 | * |\ref OPA_MODULE | x | x | |
| gustavatmel | 1:9c5af431a1f1 | 301 | * |\ref QEI1_MODULE | x | x | |
| gustavatmel | 1:9c5af431a1f1 | 302 | * |\ref QEI0_MODULE | x | x | |
| gustavatmel | 1:9c5af431a1f1 | 303 | * |\ref PWM1CH45_MODULE |\ref CLK_CLKSEL2_PWM1CH45SEL_HXT | x | |
| gustavatmel | 1:9c5af431a1f1 | 304 | * |\ref PWM1CH45_MODULE |\ref CLK_CLKSEL2_PWM1CH45SEL_LXT | x | |
| gustavatmel | 1:9c5af431a1f1 | 305 | * |\ref PWM1CH45_MODULE |\ref CLK_CLKSEL2_PWM1CH45SEL_PCLK | x | |
| gustavatmel | 1:9c5af431a1f1 | 306 | * |\ref PWM1CH45_MODULE |\ref CLK_CLKSEL2_PWM1CH45SEL_LIRC | x | |
| gustavatmel | 1:9c5af431a1f1 | 307 | * |\ref PWM1CH45_MODULE |\ref CLK_CLKSEL2_PWM1CH45SEL_HIRC | x | |
| gustavatmel | 1:9c5af431a1f1 | 308 | * |\ref PWM1CH23_MODULE |\ref CLK_CLKSEL2_PWM1CH23SEL_HXT | x | |
| gustavatmel | 1:9c5af431a1f1 | 309 | * |\ref PWM1CH23_MODULE |\ref CLK_CLKSEL2_PWM1CH23SEL_LXT | x | |
| gustavatmel | 1:9c5af431a1f1 | 310 | * |\ref PWM1CH23_MODULE |\ref CLK_CLKSEL2_PWM1CH23SEL_PCLK | x | |
| gustavatmel | 1:9c5af431a1f1 | 311 | * |\ref PWM1CH23_MODULE |\ref CLK_CLKSEL2_PWM1CH23SEL_LIRC | x | |
| gustavatmel | 1:9c5af431a1f1 | 312 | * |\ref PWM1CH23_MODULE |\ref CLK_CLKSEL2_PWM1CH23SEL_HIRC | x | |
| gustavatmel | 1:9c5af431a1f1 | 313 | * |\ref PWM1CH01_MODULE |\ref CLK_CLKSEL2_PWM1CH01SEL_HXT | x | |
| gustavatmel | 1:9c5af431a1f1 | 314 | * |\ref PWM1CH01_MODULE |\ref CLK_CLKSEL2_PWM1CH01SEL_LXT | x | |
| gustavatmel | 1:9c5af431a1f1 | 315 | * |\ref PWM1CH01_MODULE |\ref CLK_CLKSEL2_PWM1CH01SEL_PCLK | x | |
| gustavatmel | 1:9c5af431a1f1 | 316 | * |\ref PWM1CH01_MODULE |\ref CLK_CLKSEL2_PWM1CH01SEL_LIRC | x | |
| gustavatmel | 1:9c5af431a1f1 | 317 | * |\ref PWM1CH01_MODULE |\ref CLK_CLKSEL2_PWM1CH01SEL_HIRC | x | |
| gustavatmel | 1:9c5af431a1f1 | 318 | * |\ref PWM0CH45_MODULE |\ref CLK_CLKSEL2_PWM0CH45SEL_HXT | x | |
| gustavatmel | 1:9c5af431a1f1 | 319 | * |\ref PWM0CH45_MODULE |\ref CLK_CLKSEL2_PWM0CH45SEL_LXT | x | |
| gustavatmel | 1:9c5af431a1f1 | 320 | * |\ref PWM0CH45_MODULE |\ref CLK_CLKSEL2_PWM0CH45SEL_PCLK | x | |
| gustavatmel | 1:9c5af431a1f1 | 321 | * |\ref PWM0CH45_MODULE |\ref CLK_CLKSEL2_PWM0CH45SEL_LIRC | x | |
| gustavatmel | 1:9c5af431a1f1 | 322 | * |\ref PWM0CH45_MODULE |\ref CLK_CLKSEL2_PWM0CH45SEL_HIRC | x | |
| gustavatmel | 1:9c5af431a1f1 | 323 | * |\ref PWM0CH23_MODULE |\ref CLK_CLKSEL2_PWM0CH23SEL_HXT | x | |
| gustavatmel | 1:9c5af431a1f1 | 324 | * |\ref PWM0CH23_MODULE |\ref CLK_CLKSEL2_PWM0CH23SEL_LXT | x | |
| gustavatmel | 1:9c5af431a1f1 | 325 | * |\ref PWM0CH23_MODULE |\ref CLK_CLKSEL2_PWM0CH23SEL_PCLK | x | |
| gustavatmel | 1:9c5af431a1f1 | 326 | * |\ref PWM0CH23_MODULE |\ref CLK_CLKSEL2_PWM0CH23SEL_LIRC | x | |
| gustavatmel | 1:9c5af431a1f1 | 327 | * |\ref PWM0CH23_MODULE |\ref CLK_CLKSEL2_PWM0CH23SEL_HIRC | x | |
| gustavatmel | 1:9c5af431a1f1 | 328 | * |\ref PWM0CH01_MODULE |\ref CLK_CLKSEL2_PWM0CH01SEL_HXT | x | |
| gustavatmel | 1:9c5af431a1f1 | 329 | * |\ref PWM0CH01_MODULE |\ref CLK_CLKSEL2_PWM0CH01SEL_LXT | x | |
| gustavatmel | 1:9c5af431a1f1 | 330 | * |\ref PWM0CH01_MODULE |\ref CLK_CLKSEL2_PWM0CH01SEL_PCLK | x | |
| gustavatmel | 1:9c5af431a1f1 | 331 | * |\ref PWM0CH01_MODULE |\ref CLK_CLKSEL2_PWM0CH01SEL_LIRC | x | |
| gustavatmel | 1:9c5af431a1f1 | 332 | * |\ref PWM0CH01_MODULE |\ref CLK_CLKSEL2_PWM0CH01SEL_HIRC | x | |
| gustavatmel | 1:9c5af431a1f1 | 333 | * |\ref I2C4_MODULE | x | x | |
| gustavatmel | 1:9c5af431a1f1 | 334 | * |\ref SC5_MODULE | x | x | |
| gustavatmel | 1:9c5af431a1f1 | 335 | * |\ref SC4_MODULE | x | x | |
| gustavatmel | 1:9c5af431a1f1 | 336 | * |\ref SC3_MODULE | x | x | |
| gustavatmel | 1:9c5af431a1f1 | 337 | * |\ref SC2_MODULE | x | x | |
| gustavatmel | 1:9c5af431a1f1 | 338 | * |\ref SC5_MODULE |\ref CLK_CLKSEL3_SC5SEL_HXT |\ref CLK_CLKDIV2_SC5(x) | |
| gustavatmel | 1:9c5af431a1f1 | 339 | * |\ref SC5_MODULE |\ref CLK_CLKSEL3_SC5SEL_PLL |\ref CLK_CLKDIV2_SC5(x) | |
| gustavatmel | 1:9c5af431a1f1 | 340 | * |\ref SC5_MODULE |\ref CLK_CLKSEL3_SC5SEL_PCLK |\ref CLK_CLKDIV2_SC5(x) | |
| gustavatmel | 1:9c5af431a1f1 | 341 | * |\ref SC5_MODULE |\ref CLK_CLKSEL3_SC5SEL_HIRC |\ref CLK_CLKDIV2_SC5(x) | |
| gustavatmel | 1:9c5af431a1f1 | 342 | * |\ref SC4_MODULE |\ref CLK_CLKSEL3_SC4SEL_HXT |\ref CLK_CLKDIV2_SC4(x) | |
| gustavatmel | 1:9c5af431a1f1 | 343 | * |\ref SC4_MODULE |\ref CLK_CLKSEL3_SC4SEL_PLL |\ref CLK_CLKDIV2_SC4(x) | |
| gustavatmel | 1:9c5af431a1f1 | 344 | * |\ref SC4_MODULE |\ref CLK_CLKSEL3_SC4SEL_PCLK |\ref CLK_CLKDIV2_SC4(x) | |
| gustavatmel | 1:9c5af431a1f1 | 345 | * |\ref SC4_MODULE |\ref CLK_CLKSEL3_SC4SEL_HIRC |\ref CLK_CLKDIV2_SC4(x) | |
| gustavatmel | 1:9c5af431a1f1 | 346 | * |\ref SC3_MODULE |\ref CLK_CLKSEL3_SC3SEL_HXT |\ref CLK_CLKDIV1_SC3(x) | |
| gustavatmel | 1:9c5af431a1f1 | 347 | * |\ref SC3_MODULE |\ref CLK_CLKSEL3_SC3SEL_PLL |\ref CLK_CLKDIV1_SC3(x) | |
| gustavatmel | 1:9c5af431a1f1 | 348 | * |\ref SC3_MODULE |\ref CLK_CLKSEL3_SC3SEL_PCLK |\ref CLK_CLKDIV1_SC3(x) | |
| gustavatmel | 1:9c5af431a1f1 | 349 | * |\ref SC3_MODULE |\ref CLK_CLKSEL3_SC3SEL_HIRC |\ref CLK_CLKDIV1_SC3(x) | |
| gustavatmel | 1:9c5af431a1f1 | 350 | * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_HXT |\ref CLK_CLKDIV1_SC2(x) | |
| gustavatmel | 1:9c5af431a1f1 | 351 | * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_PLL |\ref CLK_CLKDIV1_SC2(x) | |
| gustavatmel | 1:9c5af431a1f1 | 352 | * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_PCLK |\ref CLK_CLKDIV1_SC2(x) | |
| gustavatmel | 1:9c5af431a1f1 | 353 | * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_HIRC |\ref CLK_CLKDIV1_SC2(x) | |
| gustavatmel | 1:9c5af431a1f1 | 354 | * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_HXT |\ref CLK_CLKDIV1_SC1(x) | |
| gustavatmel | 1:9c5af431a1f1 | 355 | * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_PLL |\ref CLK_CLKDIV1_SC1(x) | |
| gustavatmel | 1:9c5af431a1f1 | 356 | * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_PCLK |\ref CLK_CLKDIV1_SC1(x) | |
| gustavatmel | 1:9c5af431a1f1 | 357 | * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_HIRC |\ref CLK_CLKDIV1_SC1(x) | |
| gustavatmel | 1:9c5af431a1f1 | 358 | * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_HXT |\ref CLK_CLKDIV1_SC0(x) | |
| gustavatmel | 1:9c5af431a1f1 | 359 | * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_PLL |\ref CLK_CLKDIV1_SC0(x) | |
| gustavatmel | 1:9c5af431a1f1 | 360 | * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_PCLK |\ref CLK_CLKDIV1_SC0(x) | |
| gustavatmel | 1:9c5af431a1f1 | 361 | * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_HIRC |\ref CLK_CLKDIV1_SC0(x) | |
| gustavatmel | 1:9c5af431a1f1 | 362 | * |\ref PS2_MODULE |\ref CLK_CLKSEL3_I2S1SEL_HXT | x | |
| gustavatmel | 1:9c5af431a1f1 | 363 | * |\ref I2S1_MODULE |\ref CLK_CLKSEL3_I2S1SEL_HXT | x | |
| gustavatmel | 1:9c5af431a1f1 | 364 | * |\ref I2S1_MODULE |\ref CLK_CLKSEL3_I2S1SEL_PLL | x | |
| gustavatmel | 1:9c5af431a1f1 | 365 | * |\ref I2S1_MODULE |\ref CLK_CLKSEL3_I2S1SEL_PCLK | x | |
| gustavatmel | 1:9c5af431a1f1 | 366 | * |\ref I2S1_MODULE |\ref CLK_CLKSEL3_I2S1SEL_HIRC | x | |
| gustavatmel | 1:9c5af431a1f1 | 367 | * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_HXT | x | |
| gustavatmel | 1:9c5af431a1f1 | 368 | * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_PLL | x | |
| gustavatmel | 1:9c5af431a1f1 | 369 | * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_PCLK | x | |
| gustavatmel | 1:9c5af431a1f1 | 370 | * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_HIRC | x | |
| gustavatmel | 1:9c5af431a1f1 | 371 | * |\ref ADC_MODULE |\ref CLK_CLKSEL1_ADCSEL_HXT |\ref CLK_CLKDIV0_ADC(x) | |
| gustavatmel | 1:9c5af431a1f1 | 372 | * |\ref ADC_MODULE |\ref CLK_CLKSEL1_ADCSEL_PLL |\ref CLK_CLKDIV0_ADC(x) | |
| gustavatmel | 1:9c5af431a1f1 | 373 | * |\ref ADC_MODULE |\ref CLK_CLKSEL1_ADCSEL_PCLK |\ref CLK_CLKDIV0_ADC(x) | |
| gustavatmel | 1:9c5af431a1f1 | 374 | * |\ref ADC_MODULE |\ref CLK_CLKSEL1_ADCSEL_HIRC |\ref CLK_CLKDIV0_ADC(x) | |
| gustavatmel | 1:9c5af431a1f1 | 375 | * |\ref OTG_MODULE | x | x | |
| gustavatmel | 1:9c5af431a1f1 | 376 | * |\ref CAN1_MODULE | x | x | |
| gustavatmel | 1:9c5af431a1f1 | 377 | * |\ref CAN0_MODULE | x | x | |
| gustavatmel | 1:9c5af431a1f1 | 378 | * |\ref UART5_MODULE |\ref CLK_CLKSEL1_UARTSEL_HXT |\ref CLK_CLKDIV0_UART(x) | |
| gustavatmel | 1:9c5af431a1f1 | 379 | * |\ref UART5_MODULE |\ref CLK_CLKSEL1_UARTSEL_PLL |\ref CLK_CLKDIV0_UART(x) | |
| gustavatmel | 1:9c5af431a1f1 | 380 | * |\ref UART5_MODULE |\ref CLK_CLKSEL1_UARTSEL_HIRC |\ref CLK_CLKDIV0_UART(x) | |
| gustavatmel | 1:9c5af431a1f1 | 381 | * |\ref UART4_MODULE |\ref CLK_CLKSEL1_UARTSEL_HXT |\ref CLK_CLKDIV0_UART(x) | |
| gustavatmel | 1:9c5af431a1f1 | 382 | * |\ref UART4_MODULE |\ref CLK_CLKSEL1_UARTSEL_PLL |\ref CLK_CLKDIV0_UART(x) | |
| gustavatmel | 1:9c5af431a1f1 | 383 | * |\ref UART4_MODULE |\ref CLK_CLKSEL1_UARTSEL_HIRC |\ref CLK_CLKDIV0_UART(x) | |
| gustavatmel | 1:9c5af431a1f1 | 384 | * |\ref UART3_MODULE |\ref CLK_CLKSEL1_UARTSEL_HXT |\ref CLK_CLKDIV0_UART(x) | |
| gustavatmel | 1:9c5af431a1f1 | 385 | * |\ref UART3_MODULE |\ref CLK_CLKSEL1_UARTSEL_PLL |\ref CLK_CLKDIV0_UART(x) | |
| gustavatmel | 1:9c5af431a1f1 | 386 | * |\ref UART3_MODULE |\ref CLK_CLKSEL1_UARTSEL_HIRC |\ref CLK_CLKDIV0_UART(x) | |
| gustavatmel | 1:9c5af431a1f1 | 387 | * |\ref UART2_MODULE |\ref CLK_CLKSEL1_UARTSEL_HXT |\ref CLK_CLKDIV0_UART(x) | |
| gustavatmel | 1:9c5af431a1f1 | 388 | * |\ref UART2_MODULE |\ref CLK_CLKSEL1_UARTSEL_PLL |\ref CLK_CLKDIV0_UART(x) | |
| gustavatmel | 1:9c5af431a1f1 | 389 | * |\ref UART2_MODULE |\ref CLK_CLKSEL1_UARTSEL_HIRC |\ref CLK_CLKDIV0_UART(x) | |
| gustavatmel | 1:9c5af431a1f1 | 390 | * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UARTSEL_HXT |\ref CLK_CLKDIV0_UART(x) | |
| gustavatmel | 1:9c5af431a1f1 | 391 | * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UARTSEL_PLL |\ref CLK_CLKDIV0_UART(x) | |
| gustavatmel | 1:9c5af431a1f1 | 392 | * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UARTSEL_HIRC |\ref CLK_CLKDIV0_UART(x) | |
| gustavatmel | 1:9c5af431a1f1 | 393 | * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UARTSEL_HXT |\ref CLK_CLKDIV0_UART(x) | |
| gustavatmel | 1:9c5af431a1f1 | 394 | * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UARTSEL_PLL |\ref CLK_CLKDIV0_UART(x) | |
| gustavatmel | 1:9c5af431a1f1 | 395 | * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UARTSEL_HIRC |\ref CLK_CLKDIV0_UART(x) | |
| gustavatmel | 1:9c5af431a1f1 | 396 | * |\ref SPI3_MODULE |\ref CLK_CLKSEL1_SPI3SEL_PLL | x | |
| gustavatmel | 1:9c5af431a1f1 | 397 | * |\ref SPI3_MODULE |\ref CLK_CLKSEL1_SPI3SEL_PCLK | x | |
| gustavatmel | 1:9c5af431a1f1 | 398 | * |\ref SPI2_MODULE |\ref CLK_CLKSEL1_SPI2SEL_PLL | x | |
| gustavatmel | 1:9c5af431a1f1 | 399 | * |\ref SPI2_MODULE |\ref CLK_CLKSEL1_SPI2SEL_PCLK | x | |
| gustavatmel | 1:9c5af431a1f1 | 400 | * |\ref SPI1_MODULE |\ref CLK_CLKSEL1_SPI1SEL_PLL | x | |
| gustavatmel | 1:9c5af431a1f1 | 401 | * |\ref SPI1_MODULE |\ref CLK_CLKSEL1_SPI1SEL_PCLK | x | |
| gustavatmel | 1:9c5af431a1f1 | 402 | * |\ref SPI0_MODULE |\ref CLK_CLKSEL1_SPI0SEL_PLL | x | |
| gustavatmel | 1:9c5af431a1f1 | 403 | * |\ref SPI0_MODULE |\ref CLK_CLKSEL1_SPI0SEL_PCLK | x | |
| gustavatmel | 1:9c5af431a1f1 | 404 | * |\ref I2C3_MODULE | x | x | |
| gustavatmel | 1:9c5af431a1f1 | 405 | * |\ref I2C2_MODULE | x | x | |
| gustavatmel | 1:9c5af431a1f1 | 406 | * |\ref I2C1_MODULE | x | x | |
| gustavatmel | 1:9c5af431a1f1 | 407 | * |\ref I2C0_MODULE | x | x | |
| gustavatmel | 1:9c5af431a1f1 | 408 | * |\ref ACMP_MODULE | x | x | |
| gustavatmel | 1:9c5af431a1f1 | 409 | * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HXT | x | |
| gustavatmel | 1:9c5af431a1f1 | 410 | * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_LXT | x | |
| gustavatmel | 1:9c5af431a1f1 | 411 | * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HCLK | x | |
| gustavatmel | 1:9c5af431a1f1 | 412 | * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HIRC | x | |
| gustavatmel | 1:9c5af431a1f1 | 413 | * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_HXT | x | |
| gustavatmel | 1:9c5af431a1f1 | 414 | * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_LXT | x | |
| gustavatmel | 1:9c5af431a1f1 | 415 | * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_PCLK | x | |
| gustavatmel | 1:9c5af431a1f1 | 416 | * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_LIRC | x | |
| gustavatmel | 1:9c5af431a1f1 | 417 | * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_EXT | x | |
| gustavatmel | 1:9c5af431a1f1 | 418 | * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_HIRC | x | |
| gustavatmel | 1:9c5af431a1f1 | 419 | * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_HXT | x | |
| gustavatmel | 1:9c5af431a1f1 | 420 | * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_LXT | x | |
| gustavatmel | 1:9c5af431a1f1 | 421 | * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_PCLK | x | |
| gustavatmel | 1:9c5af431a1f1 | 422 | * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_LIRC | x | |
| gustavatmel | 1:9c5af431a1f1 | 423 | * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_EXT | x | |
| gustavatmel | 1:9c5af431a1f1 | 424 | * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_HIRC | x | |
| gustavatmel | 1:9c5af431a1f1 | 425 | * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_HXT | x | |
| gustavatmel | 1:9c5af431a1f1 | 426 | * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_LXT | x | |
| gustavatmel | 1:9c5af431a1f1 | 427 | * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_PCLK | x | |
| gustavatmel | 1:9c5af431a1f1 | 428 | * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_LIRC | x | |
| gustavatmel | 1:9c5af431a1f1 | 429 | * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_EXT | x | |
| gustavatmel | 1:9c5af431a1f1 | 430 | * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_HIRC | x | |
| gustavatmel | 1:9c5af431a1f1 | 431 | * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_HXT | x | |
| gustavatmel | 1:9c5af431a1f1 | 432 | * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_LXT | x | |
| gustavatmel | 1:9c5af431a1f1 | 433 | * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_PCLK | x | |
| gustavatmel | 1:9c5af431a1f1 | 434 | * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_LIRC | x | |
| gustavatmel | 1:9c5af431a1f1 | 435 | * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_EXT | x | |
| gustavatmel | 1:9c5af431a1f1 | 436 | * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_HIRC | x | |
| gustavatmel | 1:9c5af431a1f1 | 437 | * |\ref RTC_MODULE | x | x | |
| gustavatmel | 1:9c5af431a1f1 | 438 | * |\ref WWDT_MODULE |\ref CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048 | x | |
| gustavatmel | 1:9c5af431a1f1 | 439 | * |\ref WWDT_MODULE |\ref CLK_CLKSEL1_WWDTSEL_LIRC | x | |
| gustavatmel | 1:9c5af431a1f1 | 440 | * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_LXT | x | |
| gustavatmel | 1:9c5af431a1f1 | 441 | * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 | x | |
| gustavatmel | 1:9c5af431a1f1 | 442 | * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_LIRC | x | |
| gustavatmel | 1:9c5af431a1f1 | 443 | * |
| gustavatmel | 1:9c5af431a1f1 | 444 | */ |
| gustavatmel | 1:9c5af431a1f1 | 445 | |
| gustavatmel | 1:9c5af431a1f1 | 446 | void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv) |
| gustavatmel | 1:9c5af431a1f1 | 447 | { |
| gustavatmel | 1:9c5af431a1f1 | 448 | uint32_t u32tmp=0,u32sel=0,u32div=0; |
| gustavatmel | 1:9c5af431a1f1 | 449 | |
| gustavatmel | 1:9c5af431a1f1 | 450 | if(MODULE_CLKDIV_Msk(u32ModuleIdx)!=MODULE_NoMsk) { |
| gustavatmel | 1:9c5af431a1f1 | 451 | u32div =(uint32_t)&CLK->CLKDIV0+((MODULE_CLKDIV(u32ModuleIdx))*4); |
| gustavatmel | 1:9c5af431a1f1 | 452 | u32tmp = *(volatile uint32_t *)(u32div); |
| gustavatmel | 1:9c5af431a1f1 | 453 | u32tmp = ( u32tmp & ~(MODULE_CLKDIV_Msk(u32ModuleIdx)<<MODULE_CLKDIV_Pos(u32ModuleIdx)) ) | u32ClkDiv; |
| gustavatmel | 1:9c5af431a1f1 | 454 | *(volatile uint32_t *)(u32div) = u32tmp; |
| gustavatmel | 1:9c5af431a1f1 | 455 | } |
| gustavatmel | 1:9c5af431a1f1 | 456 | |
| gustavatmel | 1:9c5af431a1f1 | 457 | if(MODULE_CLKSEL_Msk(u32ModuleIdx)!=MODULE_NoMsk) { |
| gustavatmel | 1:9c5af431a1f1 | 458 | u32sel = (uint32_t)&CLK->CLKSEL0+((MODULE_CLKSEL(u32ModuleIdx))*4); |
| gustavatmel | 1:9c5af431a1f1 | 459 | u32tmp = *(volatile uint32_t *)(u32sel); |
| gustavatmel | 1:9c5af431a1f1 | 460 | u32tmp = ( u32tmp & ~(MODULE_CLKSEL_Msk(u32ModuleIdx)<<MODULE_CLKSEL_Pos(u32ModuleIdx)) ) | u32ClkSrc; |
| gustavatmel | 1:9c5af431a1f1 | 461 | *(volatile uint32_t *)(u32sel) = u32tmp; |
| gustavatmel | 1:9c5af431a1f1 | 462 | } |
| gustavatmel | 1:9c5af431a1f1 | 463 | } |
| gustavatmel | 1:9c5af431a1f1 | 464 | |
| gustavatmel | 1:9c5af431a1f1 | 465 | /** |
| gustavatmel | 1:9c5af431a1f1 | 466 | * @brief This function enable clock source |
| gustavatmel | 1:9c5af431a1f1 | 467 | * @param u32ClkMask is clock source mask. Including: |
| gustavatmel | 1:9c5af431a1f1 | 468 | * - \ref CLK_PWRCTL_HXTEN_Msk |
| gustavatmel | 1:9c5af431a1f1 | 469 | * - \ref CLK_PWRCTL_LXTEN_Msk |
| gustavatmel | 1:9c5af431a1f1 | 470 | * - \ref CLK_PWRCTL_HIRCEN_Msk |
| gustavatmel | 1:9c5af431a1f1 | 471 | * - \ref CLK_PWRCTL_LIRCEN_Msk |
| gustavatmel | 1:9c5af431a1f1 | 472 | * @return None |
| gustavatmel | 1:9c5af431a1f1 | 473 | */ |
| gustavatmel | 1:9c5af431a1f1 | 474 | void CLK_EnableXtalRC(uint32_t u32ClkMask) |
| gustavatmel | 1:9c5af431a1f1 | 475 | { |
| gustavatmel | 1:9c5af431a1f1 | 476 | CLK->PWRCTL |= u32ClkMask; |
| gustavatmel | 1:9c5af431a1f1 | 477 | } |
| gustavatmel | 1:9c5af431a1f1 | 478 | |
| gustavatmel | 1:9c5af431a1f1 | 479 | /** |
| gustavatmel | 1:9c5af431a1f1 | 480 | * @brief This function disable clock source |
| gustavatmel | 1:9c5af431a1f1 | 481 | * @param u32ClkMask is clock source mask. Including: |
| gustavatmel | 1:9c5af431a1f1 | 482 | * - \ref CLK_PWRCTL_HXTEN_Msk |
| gustavatmel | 1:9c5af431a1f1 | 483 | * - \ref CLK_PWRCTL_LXTEN_Msk |
| gustavatmel | 1:9c5af431a1f1 | 484 | * - \ref CLK_PWRCTL_HIRCEN_Msk |
| gustavatmel | 1:9c5af431a1f1 | 485 | * - \ref CLK_PWRCTL_LIRCEN_Msk |
| gustavatmel | 1:9c5af431a1f1 | 486 | * @return None |
| gustavatmel | 1:9c5af431a1f1 | 487 | */ |
| gustavatmel | 1:9c5af431a1f1 | 488 | void CLK_DisableXtalRC(uint32_t u32ClkMask) |
| gustavatmel | 1:9c5af431a1f1 | 489 | { |
| gustavatmel | 1:9c5af431a1f1 | 490 | CLK->PWRCTL &= ~u32ClkMask; |
| gustavatmel | 1:9c5af431a1f1 | 491 | } |
| gustavatmel | 1:9c5af431a1f1 | 492 | |
| gustavatmel | 1:9c5af431a1f1 | 493 | /** |
| gustavatmel | 1:9c5af431a1f1 | 494 | * @brief This function enable module clock |
| gustavatmel | 1:9c5af431a1f1 | 495 | * @param[in] u32ModuleIdx is module index. Including : |
| gustavatmel | 1:9c5af431a1f1 | 496 | * - \ref PDMA_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 497 | * - \ref ISP_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 498 | * - \ref EBI_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 499 | * - \ref USBH_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 500 | * - \ref EMAC_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 501 | * - \ref SDH_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 502 | * - \ref CRC_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 503 | * - \ref CAP_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 504 | * - \ref USBD_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 505 | * - \ref CRPT_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 506 | * - \ref WDT_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 507 | * - \ref WWDT_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 508 | * - \ref RTC_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 509 | * - \ref TMR0_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 510 | * - \ref TMR1_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 511 | * - \ref TMR2_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 512 | * - \ref TMR3_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 513 | * - \ref CLKO_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 514 | * - \ref ACMP_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 515 | * - \ref I2C0_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 516 | * - \ref I2C1_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 517 | * - \ref I2C2_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 518 | * - \ref I2C3_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 519 | * - \ref SPI0_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 520 | * - \ref SPI1_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 521 | * - \ref SPI2_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 522 | * - \ref SPI3_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 523 | * - \ref UART0_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 524 | * - \ref UART1_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 525 | * - \ref UART2_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 526 | * - \ref UART3_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 527 | * - \ref UART4_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 528 | * - \ref UART5_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 529 | * - \ref CAN0_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 530 | * - \ref CAN1_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 531 | * - \ref OTG_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 532 | * - \ref ADC_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 533 | * - \ref I2S0_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 534 | * - \ref I2S1_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 535 | * - \ref PS2_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 536 | * - \ref SC0_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 537 | * - \ref SC1_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 538 | * - \ref SC2_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 539 | * - \ref SC3_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 540 | * - \ref SC4_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 541 | * - \ref SC5_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 542 | * - \ref I2C4_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 543 | * - \ref PWM0CH01_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 544 | * - \ref PWM0CH23_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 545 | * - \ref PWM0CH45_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 546 | * - \ref PWM1CH01_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 547 | * - \ref PWM1CH23_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 548 | * - \ref PWM1CH45_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 549 | * - \ref QEI0_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 550 | * - \ref QEI1_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 551 | * - \ref ECAP0_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 552 | * - \ref ECAP1_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 553 | * - \ref EPWM0_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 554 | * - \ref EPWM1_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 555 | * - \ref OPA_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 556 | * - \ref EADC_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 557 | * @return None |
| gustavatmel | 1:9c5af431a1f1 | 558 | */ |
| gustavatmel | 1:9c5af431a1f1 | 559 | void CLK_EnableModuleClock(uint32_t u32ModuleIdx) |
| gustavatmel | 1:9c5af431a1f1 | 560 | { |
| gustavatmel | 1:9c5af431a1f1 | 561 | *(volatile uint32_t *)((uint32_t)&CLK->AHBCLK+(MODULE_APBCLK(u32ModuleIdx)*4)) |= 1<<MODULE_IP_EN_Pos(u32ModuleIdx); |
| gustavatmel | 1:9c5af431a1f1 | 562 | } |
| gustavatmel | 1:9c5af431a1f1 | 563 | |
| gustavatmel | 1:9c5af431a1f1 | 564 | /** |
| gustavatmel | 1:9c5af431a1f1 | 565 | * @brief This function disable module clock |
| gustavatmel | 1:9c5af431a1f1 | 566 | * @param[in] u32ModuleIdx is module index. Including : |
| gustavatmel | 1:9c5af431a1f1 | 567 | * - \ref PDMA_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 568 | * - \ref ISP_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 569 | * - \ref EBI_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 570 | * - \ref USBH_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 571 | * - \ref EMAC_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 572 | * - \ref SDH_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 573 | * - \ref CRC_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 574 | * - \ref CAP_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 575 | * - \ref USBD_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 576 | * - \ref CRPT_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 577 | * - \ref WDT_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 578 | * - \ref WWDT_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 579 | * - \ref RTC_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 580 | * - \ref TMR0_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 581 | * - \ref TMR1_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 582 | * - \ref TMR2_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 583 | * - \ref TMR3_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 584 | * - \ref CLKO_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 585 | * - \ref ACMP_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 586 | * - \ref I2C0_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 587 | * - \ref I2C1_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 588 | * - \ref I2C2_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 589 | * - \ref I2C3_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 590 | * - \ref SPI0_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 591 | * - \ref SPI1_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 592 | * - \ref SPI2_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 593 | * - \ref SPI3_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 594 | * - \ref UART0_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 595 | * - \ref UART1_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 596 | * - \ref UART2_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 597 | * - \ref UART3_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 598 | * - \ref UART4_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 599 | * - \ref UART5_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 600 | * - \ref CAN0_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 601 | * - \ref CAN1_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 602 | * - \ref OTG_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 603 | * - \ref ADC_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 604 | * - \ref I2S0_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 605 | * - \ref I2S1_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 606 | * - \ref PS2_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 607 | * - \ref SC0_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 608 | * - \ref SC1_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 609 | * - \ref SC2_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 610 | * - \ref SC3_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 611 | * - \ref SC4_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 612 | * - \ref SC5_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 613 | * - \ref I2C4_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 614 | * - \ref PWM0CH01_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 615 | * - \ref PWM0CH23_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 616 | * - \ref PWM0CH45_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 617 | * - \ref PWM1CH01_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 618 | * - \ref PWM1CH23_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 619 | * - \ref PWM1CH45_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 620 | * - \ref QEI0_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 621 | * - \ref QEI1_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 622 | * - \ref ECAP0_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 623 | * - \ref ECAP1_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 624 | * - \ref EPWM0_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 625 | * - \ref EPWM1_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 626 | * - \ref OPA_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 627 | * - \ref EADC_MODULE |
| gustavatmel | 1:9c5af431a1f1 | 628 | * @return None |
| gustavatmel | 1:9c5af431a1f1 | 629 | */ |
| gustavatmel | 1:9c5af431a1f1 | 630 | void CLK_DisableModuleClock(uint32_t u32ModuleIdx) |
| gustavatmel | 1:9c5af431a1f1 | 631 | { |
| gustavatmel | 1:9c5af431a1f1 | 632 | *(volatile uint32_t *)((uint32_t)&CLK->AHBCLK+(MODULE_APBCLK(u32ModuleIdx)*4)) &= ~(1<<MODULE_IP_EN_Pos(u32ModuleIdx)); |
| gustavatmel | 1:9c5af431a1f1 | 633 | } |
| gustavatmel | 1:9c5af431a1f1 | 634 | |
| gustavatmel | 1:9c5af431a1f1 | 635 | /** |
| gustavatmel | 1:9c5af431a1f1 | 636 | * @brief This function set PLL frequency |
| gustavatmel | 1:9c5af431a1f1 | 637 | * @param[in] u32PllClkSrc is PLL clock source. Including : |
| gustavatmel | 1:9c5af431a1f1 | 638 | * - \ref CLK_PLLCTL_PLLSRC_HIRC |
| gustavatmel | 1:9c5af431a1f1 | 639 | * - \ref CLK_PLLCTL_PLLSRC_HXT |
| gustavatmel | 1:9c5af431a1f1 | 640 | * @param[in] u32PllFreq is PLL frequency |
| gustavatmel | 1:9c5af431a1f1 | 641 | * @return None |
| gustavatmel | 1:9c5af431a1f1 | 642 | */ |
| gustavatmel | 1:9c5af431a1f1 | 643 | uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq) |
| gustavatmel | 1:9c5af431a1f1 | 644 | { |
| gustavatmel | 1:9c5af431a1f1 | 645 | uint32_t u32PllSrcClk, u32NR, u32NF, u32NO, u32CLK_SRC; |
| gustavatmel | 1:9c5af431a1f1 | 646 | uint32_t u32Tmp, u32Tmp2, u32Tmp3, u32Min, u32MinNF, u32MinNR; |
| gustavatmel | 1:9c5af431a1f1 | 647 | |
| gustavatmel | 1:9c5af431a1f1 | 648 | /* Disable PLL first to avoid unstable when setting PLL */ |
| gustavatmel | 1:9c5af431a1f1 | 649 | CLK_DisablePLL(); |
| gustavatmel | 1:9c5af431a1f1 | 650 | |
| gustavatmel | 1:9c5af431a1f1 | 651 | /* PLL source clock is from HXT */ |
| gustavatmel | 1:9c5af431a1f1 | 652 | if(u32PllClkSrc == CLK_PLLCTL_PLLSRC_HXT) { |
| gustavatmel | 1:9c5af431a1f1 | 653 | /* Enable HXT clock */ |
| gustavatmel | 1:9c5af431a1f1 | 654 | CLK->PWRCTL |= CLK_PWRCTL_HXTEN_Msk; |
| gustavatmel | 1:9c5af431a1f1 | 655 | |
| gustavatmel | 1:9c5af431a1f1 | 656 | /* Wait for HXT clock ready */ |
| gustavatmel | 1:9c5af431a1f1 | 657 | CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk); |
| gustavatmel | 1:9c5af431a1f1 | 658 | |
| gustavatmel | 1:9c5af431a1f1 | 659 | /* Select PLL source clock from HXT */ |
| gustavatmel | 1:9c5af431a1f1 | 660 | u32CLK_SRC = CLK_PLLCTL_PLLSRC_HXT; |
| gustavatmel | 1:9c5af431a1f1 | 661 | u32PllSrcClk = __HXT; |
| gustavatmel | 1:9c5af431a1f1 | 662 | |
| gustavatmel | 1:9c5af431a1f1 | 663 | /* u32NR start from 2 */ |
| gustavatmel | 1:9c5af431a1f1 | 664 | u32NR = 2; |
| gustavatmel | 1:9c5af431a1f1 | 665 | } |
| gustavatmel | 1:9c5af431a1f1 | 666 | |
| gustavatmel | 1:9c5af431a1f1 | 667 | /* PLL source clock is from HIRC */ |
| gustavatmel | 1:9c5af431a1f1 | 668 | else { |
| gustavatmel | 1:9c5af431a1f1 | 669 | /* Enable HIRC clock */ |
| gustavatmel | 1:9c5af431a1f1 | 670 | CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk; |
| gustavatmel | 1:9c5af431a1f1 | 671 | |
| gustavatmel | 1:9c5af431a1f1 | 672 | /* Wait for HIRC clock ready */ |
| gustavatmel | 1:9c5af431a1f1 | 673 | CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk); |
| gustavatmel | 1:9c5af431a1f1 | 674 | |
| gustavatmel | 1:9c5af431a1f1 | 675 | /* Select PLL source clock from HIRC */ |
| gustavatmel | 1:9c5af431a1f1 | 676 | u32CLK_SRC = CLK_PLLCTL_PLLSRC_HIRC; |
| gustavatmel | 1:9c5af431a1f1 | 677 | u32PllSrcClk = __HIRC; |
| gustavatmel | 1:9c5af431a1f1 | 678 | |
| gustavatmel | 1:9c5af431a1f1 | 679 | /* u32NR start from 4 when FIN = 22.1184MHz to avoid calculation overflow */ |
| gustavatmel | 1:9c5af431a1f1 | 680 | u32NR = 4; |
| gustavatmel | 1:9c5af431a1f1 | 681 | } |
| gustavatmel | 1:9c5af431a1f1 | 682 | |
| gustavatmel | 1:9c5af431a1f1 | 683 | /* Select "NO" according to request frequency */ |
| gustavatmel | 1:9c5af431a1f1 | 684 | if((u32PllFreq <= FREQ_500MHZ) && (u32PllFreq > FREQ_250MHZ)) { |
| gustavatmel | 1:9c5af431a1f1 | 685 | u32NO = 0; |
| gustavatmel | 1:9c5af431a1f1 | 686 | } else if((u32PllFreq <= FREQ_250MHZ) && (u32PllFreq > FREQ_125MHZ)) { |
| gustavatmel | 1:9c5af431a1f1 | 687 | u32NO = 1; |
| gustavatmel | 1:9c5af431a1f1 | 688 | u32PllFreq = u32PllFreq << 1; |
| gustavatmel | 1:9c5af431a1f1 | 689 | } else if((u32PllFreq <= FREQ_125MHZ) && (u32PllFreq >= FREQ_50MHZ)) { |
| gustavatmel | 1:9c5af431a1f1 | 690 | u32NO = 3; |
| gustavatmel | 1:9c5af431a1f1 | 691 | u32PllFreq = u32PllFreq << 2; |
| gustavatmel | 1:9c5af431a1f1 | 692 | } else { |
| gustavatmel | 1:9c5af431a1f1 | 693 | /* Wrong frequency request. Just return default setting. */ |
| gustavatmel | 1:9c5af431a1f1 | 694 | goto lexit; |
| gustavatmel | 1:9c5af431a1f1 | 695 | } |
| gustavatmel | 1:9c5af431a1f1 | 696 | |
| gustavatmel | 1:9c5af431a1f1 | 697 | /* Find best solution */ |
| gustavatmel | 1:9c5af431a1f1 | 698 | u32Min = (uint32_t) - 1; |
| gustavatmel | 1:9c5af431a1f1 | 699 | u32MinNR = 0; |
| gustavatmel | 1:9c5af431a1f1 | 700 | u32MinNF = 0; |
| gustavatmel | 1:9c5af431a1f1 | 701 | for(; u32NR <= 33; u32NR++) { |
| gustavatmel | 1:9c5af431a1f1 | 702 | u32Tmp = u32PllSrcClk / u32NR; |
| gustavatmel | 1:9c5af431a1f1 | 703 | if((u32Tmp > 1600000) && (u32Tmp < 16000000)) { |
| gustavatmel | 1:9c5af431a1f1 | 704 | for(u32NF = 2; u32NF <= 513; u32NF++) { |
| gustavatmel | 1:9c5af431a1f1 | 705 | u32Tmp2 = u32Tmp * u32NF; |
| gustavatmel | 1:9c5af431a1f1 | 706 | if((u32Tmp2 >= 200000000) && (u32Tmp2 <= 500000000)) { |
| gustavatmel | 1:9c5af431a1f1 | 707 | u32Tmp3 = (u32Tmp2 > u32PllFreq) ? u32Tmp2 - u32PllFreq : u32PllFreq - u32Tmp2; |
| gustavatmel | 1:9c5af431a1f1 | 708 | if(u32Tmp3 < u32Min) { |
| gustavatmel | 1:9c5af431a1f1 | 709 | u32Min = u32Tmp3; |
| gustavatmel | 1:9c5af431a1f1 | 710 | u32MinNR = u32NR; |
| gustavatmel | 1:9c5af431a1f1 | 711 | u32MinNF = u32NF; |
| gustavatmel | 1:9c5af431a1f1 | 712 | |
| gustavatmel | 1:9c5af431a1f1 | 713 | /* Break when get good results */ |
| gustavatmel | 1:9c5af431a1f1 | 714 | if(u32Min == 0) |
| gustavatmel | 1:9c5af431a1f1 | 715 | break; |
| gustavatmel | 1:9c5af431a1f1 | 716 | } |
| gustavatmel | 1:9c5af431a1f1 | 717 | } |
| gustavatmel | 1:9c5af431a1f1 | 718 | } |
| gustavatmel | 1:9c5af431a1f1 | 719 | } |
| gustavatmel | 1:9c5af431a1f1 | 720 | } |
| gustavatmel | 1:9c5af431a1f1 | 721 | |
| gustavatmel | 1:9c5af431a1f1 | 722 | /* Enable and apply new PLL setting. */ |
| gustavatmel | 1:9c5af431a1f1 | 723 | CLK->PLLCTL = u32CLK_SRC | (u32NO << 14) | ((u32MinNR - 2) << 9) | (u32MinNF - 2); |
| gustavatmel | 1:9c5af431a1f1 | 724 | |
| gustavatmel | 1:9c5af431a1f1 | 725 | /* Wait for PLL clock stable */ |
| gustavatmel | 1:9c5af431a1f1 | 726 | CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk); |
| gustavatmel | 1:9c5af431a1f1 | 727 | |
| gustavatmel | 1:9c5af431a1f1 | 728 | /* Return actual PLL output clock frequency */ |
| gustavatmel | 1:9c5af431a1f1 | 729 | return u32PllSrcClk / ((u32NO + 1) * u32MinNR) * u32MinNF; |
| gustavatmel | 1:9c5af431a1f1 | 730 | |
| gustavatmel | 1:9c5af431a1f1 | 731 | lexit: |
| gustavatmel | 1:9c5af431a1f1 | 732 | |
| gustavatmel | 1:9c5af431a1f1 | 733 | /* Apply default PLL setting and return */ |
| gustavatmel | 1:9c5af431a1f1 | 734 | if(u32PllClkSrc == CLK_PLLCTL_PLLSRC_HXT) |
| gustavatmel | 1:9c5af431a1f1 | 735 | CLK->PLLCTL = CLK_PLLCTL_84MHz_HXT; /* 84MHz */ |
| gustavatmel | 1:9c5af431a1f1 | 736 | else |
| gustavatmel | 1:9c5af431a1f1 | 737 | CLK->PLLCTL = CLK_PLLCTL_50MHz_HIRC; /* 50MHz */ |
| gustavatmel | 1:9c5af431a1f1 | 738 | |
| gustavatmel | 1:9c5af431a1f1 | 739 | /* Wait for PLL clock stable */ |
| gustavatmel | 1:9c5af431a1f1 | 740 | CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk); |
| gustavatmel | 1:9c5af431a1f1 | 741 | |
| gustavatmel | 1:9c5af431a1f1 | 742 | return CLK_GetPLLClockFreq(); |
| gustavatmel | 1:9c5af431a1f1 | 743 | } |
| gustavatmel | 1:9c5af431a1f1 | 744 | |
| gustavatmel | 1:9c5af431a1f1 | 745 | /** |
| gustavatmel | 1:9c5af431a1f1 | 746 | * @brief This function disable PLL |
| gustavatmel | 1:9c5af431a1f1 | 747 | * @return None |
| gustavatmel | 1:9c5af431a1f1 | 748 | */ |
| gustavatmel | 1:9c5af431a1f1 | 749 | void CLK_DisablePLL(void) |
| gustavatmel | 1:9c5af431a1f1 | 750 | { |
| gustavatmel | 1:9c5af431a1f1 | 751 | CLK->PLLCTL |= CLK_PLLCTL_PD_Msk; |
| gustavatmel | 1:9c5af431a1f1 | 752 | } |
| gustavatmel | 1:9c5af431a1f1 | 753 | |
| gustavatmel | 1:9c5af431a1f1 | 754 | /** |
| gustavatmel | 1:9c5af431a1f1 | 755 | * @brief This function set SysTick clock source |
| gustavatmel | 1:9c5af431a1f1 | 756 | * @param[in] u32ClkSrc is SysTick clock source. Including : |
| gustavatmel | 1:9c5af431a1f1 | 757 | * - \ref CLK_CLKSEL0_STCLKSEL_HXT |
| gustavatmel | 1:9c5af431a1f1 | 758 | * - \ref CLK_CLKSEL0_STCLKSEL_LXT |
| gustavatmel | 1:9c5af431a1f1 | 759 | * - \ref CLK_CLKSEL0_STCLKSEL_HXT_DIV2 |
| gustavatmel | 1:9c5af431a1f1 | 760 | * - \ref CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 |
| gustavatmel | 1:9c5af431a1f1 | 761 | * - \ref CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 |
| gustavatmel | 1:9c5af431a1f1 | 762 | * @return None |
| gustavatmel | 1:9c5af431a1f1 | 763 | */ |
| gustavatmel | 1:9c5af431a1f1 | 764 | void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc) |
| gustavatmel | 1:9c5af431a1f1 | 765 | { |
| gustavatmel | 1:9c5af431a1f1 | 766 | CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc ; |
| gustavatmel | 1:9c5af431a1f1 | 767 | } |
| gustavatmel | 1:9c5af431a1f1 | 768 | /** |
| gustavatmel | 1:9c5af431a1f1 | 769 | * @brief This function execute delay function. |
| gustavatmel | 1:9c5af431a1f1 | 770 | * @param[in] us Delay time. The Max value is 2^24 / CPU Clock(MHz). Ex: |
| gustavatmel | 1:9c5af431a1f1 | 771 | * 50MHz => 335544us, 48MHz => 349525us, 28MHz => 699050us ... |
| gustavatmel | 1:9c5af431a1f1 | 772 | * @return None |
| gustavatmel | 1:9c5af431a1f1 | 773 | * @details Use the SysTick to generate the delay time and the UNIT is in us. |
| gustavatmel | 1:9c5af431a1f1 | 774 | * The SysTick clock source is from HCLK, i.e the same as system core clock. |
| gustavatmel | 1:9c5af431a1f1 | 775 | */ |
| gustavatmel | 1:9c5af431a1f1 | 776 | void CLK_SysTickDelay(uint32_t us) |
| gustavatmel | 1:9c5af431a1f1 | 777 | { |
| gustavatmel | 1:9c5af431a1f1 | 778 | SysTick->LOAD = us * CyclesPerUs; |
| gustavatmel | 1:9c5af431a1f1 | 779 | SysTick->VAL = (0x00); |
| gustavatmel | 1:9c5af431a1f1 | 780 | SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk; |
| gustavatmel | 1:9c5af431a1f1 | 781 | |
| gustavatmel | 1:9c5af431a1f1 | 782 | /* Waiting for down-count to zero */ |
| gustavatmel | 1:9c5af431a1f1 | 783 | while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0); |
| gustavatmel | 1:9c5af431a1f1 | 784 | SysTick->CTRL = 0 ; |
| gustavatmel | 1:9c5af431a1f1 | 785 | } |
| gustavatmel | 1:9c5af431a1f1 | 786 | |
| gustavatmel | 1:9c5af431a1f1 | 787 | /** |
| gustavatmel | 1:9c5af431a1f1 | 788 | * @brief This function check selected clock source status |
| gustavatmel | 1:9c5af431a1f1 | 789 | * @param[in] u32ClkMask is selected clock source. Including |
| gustavatmel | 1:9c5af431a1f1 | 790 | * - \ref CLK_STATUS_CLKSFAIL_Msk |
| gustavatmel | 1:9c5af431a1f1 | 791 | * - \ref CLK_STATUS_HIRCSTB_Msk |
| gustavatmel | 1:9c5af431a1f1 | 792 | * - \ref CLK_STATUS_LIRCSTB_Msk |
| gustavatmel | 1:9c5af431a1f1 | 793 | * - \ref CLK_STATUS_PLLSTB_Msk |
| gustavatmel | 1:9c5af431a1f1 | 794 | * - \ref CLK_STATUS_LXTSTB_Msk |
| gustavatmel | 1:9c5af431a1f1 | 795 | * - \ref CLK_STATUS_HXTSTB_Msk |
| gustavatmel | 1:9c5af431a1f1 | 796 | * |
| gustavatmel | 1:9c5af431a1f1 | 797 | * @return 0 clock is not stable |
| gustavatmel | 1:9c5af431a1f1 | 798 | * 1 clock is stable |
| gustavatmel | 1:9c5af431a1f1 | 799 | * |
| gustavatmel | 1:9c5af431a1f1 | 800 | * @details To wait for clock ready by specified CLKSTATUS bit or timeout (~300ms) |
| gustavatmel | 1:9c5af431a1f1 | 801 | */ |
| gustavatmel | 1:9c5af431a1f1 | 802 | uint32_t CLK_WaitClockReady(uint32_t u32ClkMask) |
| gustavatmel | 1:9c5af431a1f1 | 803 | { |
| gustavatmel | 1:9c5af431a1f1 | 804 | int32_t i32TimeOutCnt = 2160000; |
| gustavatmel | 1:9c5af431a1f1 | 805 | |
| gustavatmel | 1:9c5af431a1f1 | 806 | while((CLK->STATUS & u32ClkMask) != u32ClkMask) { |
| gustavatmel | 1:9c5af431a1f1 | 807 | if(i32TimeOutCnt-- <= 0) |
| gustavatmel | 1:9c5af431a1f1 | 808 | return 0; |
| gustavatmel | 1:9c5af431a1f1 | 809 | } |
| gustavatmel | 1:9c5af431a1f1 | 810 | |
| gustavatmel | 1:9c5af431a1f1 | 811 | return 1; |
| gustavatmel | 1:9c5af431a1f1 | 812 | } |
| gustavatmel | 1:9c5af431a1f1 | 813 | |
| gustavatmel | 1:9c5af431a1f1 | 814 | /** |
| gustavatmel | 1:9c5af431a1f1 | 815 | * @brief Enable System Tick counter |
| gustavatmel | 1:9c5af431a1f1 | 816 | * @param[in] u32ClkSrc is System Tick clock source. Including: |
| gustavatmel | 1:9c5af431a1f1 | 817 | * - \ref CLK_CLKSEL0_STCLKSEL_HXT |
| gustavatmel | 1:9c5af431a1f1 | 818 | * - \ref CLK_CLKSEL0_STCLKSEL_LXT |
| gustavatmel | 1:9c5af431a1f1 | 819 | * - \ref CLK_CLKSEL0_STCLKSEL_HXT_DIV2 |
| gustavatmel | 1:9c5af431a1f1 | 820 | * - \ref CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 |
| gustavatmel | 1:9c5af431a1f1 | 821 | * - \ref CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 |
| gustavatmel | 1:9c5af431a1f1 | 822 | * - \ref CLK_CLKSEL0_STCLKSEL_HCLK |
| gustavatmel | 1:9c5af431a1f1 | 823 | * @param[in] u32Count is System Tick reload value. It could be 0~0xFFFFFF. |
| gustavatmel | 1:9c5af431a1f1 | 824 | * @return None |
| gustavatmel | 1:9c5af431a1f1 | 825 | * @details This function set System Tick clock source, reload value, enable System Tick counter and interrupt. \n |
| gustavatmel | 1:9c5af431a1f1 | 826 | * The register write-protection function should be disabled before using this function. |
| gustavatmel | 1:9c5af431a1f1 | 827 | */ |
| gustavatmel | 1:9c5af431a1f1 | 828 | void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count) |
| gustavatmel | 1:9c5af431a1f1 | 829 | { |
| gustavatmel | 1:9c5af431a1f1 | 830 | /* Set System Tick counter disabled */ |
| gustavatmel | 1:9c5af431a1f1 | 831 | SysTick->CTRL = 0; |
| gustavatmel | 1:9c5af431a1f1 | 832 | |
| gustavatmel | 1:9c5af431a1f1 | 833 | /* Set System Tick clock source */ |
| gustavatmel | 1:9c5af431a1f1 | 834 | if( u32ClkSrc == CLK_CLKSEL0_STCLKSEL_HCLK ) |
| gustavatmel | 1:9c5af431a1f1 | 835 | SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk; |
| gustavatmel | 1:9c5af431a1f1 | 836 | else |
| gustavatmel | 1:9c5af431a1f1 | 837 | CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc; |
| gustavatmel | 1:9c5af431a1f1 | 838 | |
| gustavatmel | 1:9c5af431a1f1 | 839 | /* Set System Tick reload value */ |
| gustavatmel | 1:9c5af431a1f1 | 840 | SysTick->LOAD = u32Count; |
| gustavatmel | 1:9c5af431a1f1 | 841 | |
| gustavatmel | 1:9c5af431a1f1 | 842 | /* Clear System Tick current value and counter flag */ |
| gustavatmel | 1:9c5af431a1f1 | 843 | SysTick->VAL = 0; |
| gustavatmel | 1:9c5af431a1f1 | 844 | |
| gustavatmel | 1:9c5af431a1f1 | 845 | /* Set System Tick interrupt enabled and counter enabled */ |
| gustavatmel | 1:9c5af431a1f1 | 846 | SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; |
| gustavatmel | 1:9c5af431a1f1 | 847 | } |
| gustavatmel | 1:9c5af431a1f1 | 848 | |
| gustavatmel | 1:9c5af431a1f1 | 849 | /** |
| gustavatmel | 1:9c5af431a1f1 | 850 | * @brief Disable System Tick counter |
| gustavatmel | 1:9c5af431a1f1 | 851 | * @param None |
| gustavatmel | 1:9c5af431a1f1 | 852 | * @return None |
| gustavatmel | 1:9c5af431a1f1 | 853 | * @details This function disable System Tick counter. |
| gustavatmel | 1:9c5af431a1f1 | 854 | */ |
| gustavatmel | 1:9c5af431a1f1 | 855 | void CLK_DisableSysTick(void) |
| gustavatmel | 1:9c5af431a1f1 | 856 | { |
| gustavatmel | 1:9c5af431a1f1 | 857 | /* Set System Tick counter disabled */ |
| gustavatmel | 1:9c5af431a1f1 | 858 | SysTick->CTRL = 0; |
| gustavatmel | 1:9c5af431a1f1 | 859 | } |
| gustavatmel | 1:9c5af431a1f1 | 860 | |
| gustavatmel | 1:9c5af431a1f1 | 861 | /*@}*/ /* end of group NUC472_442_CLK_EXPORTED_FUNCTIONS */ |
| gustavatmel | 1:9c5af431a1f1 | 862 | |
| gustavatmel | 1:9c5af431a1f1 | 863 | /*@}*/ /* end of group NUC472_442_CLK_Driver */ |
| gustavatmel | 1:9c5af431a1f1 | 864 | |
| gustavatmel | 1:9c5af431a1f1 | 865 | /*@}*/ /* end of group NUC472_442_Device_Driver */ |
| gustavatmel | 1:9c5af431a1f1 | 866 | |
| gustavatmel | 1:9c5af431a1f1 | 867 | /*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/ |
| gustavatmel | 1:9c5af431a1f1 | 868 |