BA / SerialCom

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

Fork of OmniWheels by Gustav Atmel

mbed-os/targets/TARGET_WIZNET/TARGET_W7500x/device/W7500x.h@2:798925c9e4a8, 2018-05-01 (annotated)

Committer:
gustavatmel
Date:
Tue May 01 15:55:34 2018 +0000
Revision:
2:798925c9e4a8
Parent:
1:9c5af431a1f1 
bluetooth

Who changed what in which revision?

UserRevisionLine numberNew contents of line
gustavatmel 1:9c5af431a1f1 1 /**************************************************************************//**
gustavatmel 1:9c5af431a1f1 2 * @file W7500x.h
gustavatmel 1:9c5af431a1f1 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File for
gustavatmel 1:9c5af431a1f1 4 * Device W7500x
gustavatmel 1:9c5af431a1f1 5 * @version V3.01
gustavatmel 1:9c5af431a1f1 6 * @date 06. March 2012
gustavatmel 1:9c5af431a1f1 7 *
gustavatmel 1:9c5af431a1f1 8 * @note
gustavatmel 1:9c5af431a1f1 9 * Copyright (C) 2010-2012 ARM Limited. All rights reserved.
gustavatmel 1:9c5af431a1f1 10 *
gustavatmel 1:9c5af431a1f1 11 * @par
gustavatmel 1:9c5af431a1f1 12 * ARM Limited (ARM) is supplying this software for use with Cortex-M
gustavatmel 1:9c5af431a1f1 13 * processor based microcontrollers. This file can be freely distributed
gustavatmel 1:9c5af431a1f1 14 * within development tools that are supporting such ARM based processors.
gustavatmel 1:9c5af431a1f1 15 *
gustavatmel 1:9c5af431a1f1 16 * @par
gustavatmel 1:9c5af431a1f1 17 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
gustavatmel 1:9c5af431a1f1 18 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
gustavatmel 1:9c5af431a1f1 19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
gustavatmel 1:9c5af431a1f1 20 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
gustavatmel 1:9c5af431a1f1 21 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
gustavatmel 1:9c5af431a1f1 22 *
gustavatmel 1:9c5af431a1f1 23 ******************************************************************************/
gustavatmel 1:9c5af431a1f1 24
gustavatmel 1:9c5af431a1f1 25
gustavatmel 1:9c5af431a1f1 26 #ifndef W7500x_H
gustavatmel 1:9c5af431a1f1 27 #define W7500x_H
gustavatmel 1:9c5af431a1f1 28
gustavatmel 1:9c5af431a1f1 29 #ifdef __cplusplus
gustavatmel 1:9c5af431a1f1 30 extern "C" {
gustavatmel 1:9c5af431a1f1 31 #endif
gustavatmel 1:9c5af431a1f1 32
gustavatmel 1:9c5af431a1f1 33 /** @addtogroup W7500x_Definitions W7500x Definitions
gustavatmel 1:9c5af431a1f1 34 This file defines all structures and symbols for W7500x:
gustavatmel 1:9c5af431a1f1 35 - registers and bitfields
gustavatmel 1:9c5af431a1f1 36 - peripheral base address
gustavatmel 1:9c5af431a1f1 37 - peripheral ID
gustavatmel 1:9c5af431a1f1 38 - Peripheral definitions
gustavatmel 1:9c5af431a1f1 39 @{
gustavatmel 1:9c5af431a1f1 40 */
gustavatmel 1:9c5af431a1f1 41
gustavatmel 1:9c5af431a1f1 42
gustavatmel 1:9c5af431a1f1 43 /******************************************************************************/
gustavatmel 1:9c5af431a1f1 44 /* Processor and Core Peripherals */
gustavatmel 1:9c5af431a1f1 45 /******************************************************************************/
gustavatmel 1:9c5af431a1f1 46 /** @addtogroup W7500x_CMSIS Device CMSIS Definitions
gustavatmel 1:9c5af431a1f1 47 Configuration of the Cortex-M0 Processor and Core Peripherals
gustavatmel 1:9c5af431a1f1 48 @{
gustavatmel 1:9c5af431a1f1 49 */
gustavatmel 1:9c5af431a1f1 50
gustavatmel 1:9c5af431a1f1 51 /*
gustavatmel 1:9c5af431a1f1 52 * ==========================================================================
gustavatmel 1:9c5af431a1f1 53 * ---------- Interrupt Number Definition -----------------------------------
gustavatmel 1:9c5af431a1f1 54 * ==========================================================================
gustavatmel 1:9c5af431a1f1 55 */
gustavatmel 1:9c5af431a1f1 56
gustavatmel 1:9c5af431a1f1 57 typedef enum IRQn
gustavatmel 1:9c5af431a1f1 58 {
gustavatmel 1:9c5af431a1f1 59 /****** Cortex-M0 Processor Exceptions Numbers **************************************************/
gustavatmel 1:9c5af431a1f1 60
gustavatmel 1:9c5af431a1f1 61 /* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M0 device */
gustavatmel 1:9c5af431a1f1 62 NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M0 Non Maskable Interrupt */
gustavatmel 1:9c5af431a1f1 63 HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
gustavatmel 1:9c5af431a1f1 64 SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
gustavatmel 1:9c5af431a1f1 65 PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
gustavatmel 1:9c5af431a1f1 66 SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
gustavatmel 1:9c5af431a1f1 67 /****** W7500x Specific Interrupt Numbers *********************************************************/
gustavatmel 1:9c5af431a1f1 68 SSP0_IRQn = 0, /*!< SSP 0 Interrupt */
gustavatmel 1:9c5af431a1f1 69 SSP1_IRQn = 1, /*!< SSP 1 Interrupt */
gustavatmel 1:9c5af431a1f1 70 UART0_IRQn = 2, /*!< UART 0 Interrupt */
gustavatmel 1:9c5af431a1f1 71 UART1_IRQn = 3, /*!< UART 1 Interrupt */
gustavatmel 1:9c5af431a1f1 72 UART2_IRQn = 4, /*!< UART 2 Interrupt */
gustavatmel 1:9c5af431a1f1 73 I2C0_IRQn = 5, /*!< I2C 0 Interrupt */
gustavatmel 1:9c5af431a1f1 74 I2C1_IRQn = 6, /*!< I2C 1 Interrupt */
gustavatmel 1:9c5af431a1f1 75 PORT0_IRQn = 7, /*!< Port 1 combined Interrupt */
gustavatmel 1:9c5af431a1f1 76 PORT1_IRQn = 8, /*!< Port 2 combined Interrupt */
gustavatmel 1:9c5af431a1f1 77 PORT2_IRQn = 9, /*!< Port 2 combined Interrupt */
gustavatmel 1:9c5af431a1f1 78 PORT3_IRQn = 10, /*!< Port 2 combined Interrupt */
gustavatmel 1:9c5af431a1f1 79 DMA_IRQn = 11, /*!< DMA combined Interrupt */
gustavatmel 1:9c5af431a1f1 80 DUALTIMER0_IRQn = 12, /*!< Dual Timer 0 Interrupt */
gustavatmel 1:9c5af431a1f1 81 DUALTIMER1_IRQn = 13, /*!< Dual Timer 1 Interrupt */
gustavatmel 1:9c5af431a1f1 82 PWM0_IRQn = 14, /*!< PWM 0 Interrupt */
gustavatmel 1:9c5af431a1f1 83 PWM1_IRQn = 15, /*!< PWM 1 Interrupt */
gustavatmel 1:9c5af431a1f1 84 PWM2_IRQn = 16, /*!< PWM 2 Interrupt */
gustavatmel 1:9c5af431a1f1 85 PWM3_IRQn = 17, /*!< PWM 3 Interrupt */
gustavatmel 1:9c5af431a1f1 86 PWM4_IRQn = 18, /*!< PWM 4 Interrupt */
gustavatmel 1:9c5af431a1f1 87 PWM5_IRQn = 19, /*!< PWM 5 Interrupt */
gustavatmel 1:9c5af431a1f1 88 PWM6_IRQn = 20, /*!< PWM 6 Interrupt */
gustavatmel 1:9c5af431a1f1 89 PWM7_IRQn = 21, /*!< PWM 7 Interrupt */
gustavatmel 1:9c5af431a1f1 90 RTC_IRQn = 22, /*!< RTC Interrupt */
gustavatmel 1:9c5af431a1f1 91 ADC_IRQn = 23, /*!< ADC Interrupt */
gustavatmel 1:9c5af431a1f1 92 WZTOE_IRQn = 24, /*!< WZTOE Interrupt */
gustavatmel 1:9c5af431a1f1 93 EXTI_IRQn = 25 /*!< EXTI Interrupt */
gustavatmel 1:9c5af431a1f1 94 } IRQn_Type;
gustavatmel 1:9c5af431a1f1 95
gustavatmel 1:9c5af431a1f1 96 /*
gustavatmel 1:9c5af431a1f1 97 * ==========================================================================
gustavatmel 1:9c5af431a1f1 98 * ----------- Processor and Core Peripheral Section ------------------------
gustavatmel 1:9c5af431a1f1 99 * ==========================================================================
gustavatmel 1:9c5af431a1f1 100 */
gustavatmel 1:9c5af431a1f1 101
gustavatmel 1:9c5af431a1f1 102 /* Configuration of the Cortex-M0 Processor and Core Peripherals */
gustavatmel 1:9c5af431a1f1 103 #define __CM0_REV 0x0000 /*!< Core Revision r0p0 */
gustavatmel 1:9c5af431a1f1 104 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
gustavatmel 1:9c5af431a1f1 105 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
gustavatmel 1:9c5af431a1f1 106 #define __MPU_PRESENT 0 /*!< MPU present or not */
gustavatmel 1:9c5af431a1f1 107
gustavatmel 1:9c5af431a1f1 108 /*@}*/ /* end of group W7500x_CMSIS */
gustavatmel 1:9c5af431a1f1 109
gustavatmel 1:9c5af431a1f1 110
gustavatmel 1:9c5af431a1f1 111 #include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
gustavatmel 1:9c5af431a1f1 112 #include "system_W7500x.h" /* W7500x System include file */
gustavatmel 1:9c5af431a1f1 113
gustavatmel 1:9c5af431a1f1 114
gustavatmel 1:9c5af431a1f1 115 /** @addtogroup Exported_types
gustavatmel 1:9c5af431a1f1 116 * @{
gustavatmel 1:9c5af431a1f1 117 */
gustavatmel 1:9c5af431a1f1 118
gustavatmel 1:9c5af431a1f1 119 typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
gustavatmel 1:9c5af431a1f1 120 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
gustavatmel 1:9c5af431a1f1 121 #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
gustavatmel 1:9c5af431a1f1 122
gustavatmel 1:9c5af431a1f1 123 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
gustavatmel 1:9c5af431a1f1 124
gustavatmel 1:9c5af431a1f1 125
gustavatmel 1:9c5af431a1f1 126
gustavatmel 1:9c5af431a1f1 127
gustavatmel 1:9c5af431a1f1 128 /**
gustavatmel 1:9c5af431a1f1 129 * @}
gustavatmel 1:9c5af431a1f1 130 */
gustavatmel 1:9c5af431a1f1 131
gustavatmel 1:9c5af431a1f1 132
gustavatmel 1:9c5af431a1f1 133
gustavatmel 1:9c5af431a1f1 134
gustavatmel 1:9c5af431a1f1 135 /** @addtogroup Peripheral_registers_structures
gustavatmel 1:9c5af431a1f1 136 * @{
gustavatmel 1:9c5af431a1f1 137 */
gustavatmel 1:9c5af431a1f1 138
gustavatmel 1:9c5af431a1f1 139 /**
gustavatmel 1:9c5af431a1f1 140 * @brief Clock Reset Generator
gustavatmel 1:9c5af431a1f1 141 */
gustavatmel 1:9c5af431a1f1 142 typedef struct
gustavatmel 1:9c5af431a1f1 143 {
gustavatmel 1:9c5af431a1f1 144 __IO uint32_t OSC_PDR; /*!< Oscillator power down register, Address offset : 0x00 */
gustavatmel 1:9c5af431a1f1 145 uint32_t RESERVED0[3];
gustavatmel 1:9c5af431a1f1 146 __IO uint32_t PLL_PDR; /*!< PLL power down register, Address offset : 0x10 */
gustavatmel 1:9c5af431a1f1 147 __IO uint32_t PLL_FCR; /*!< PLL frequency calculating register, Address offset : 0x14 */
gustavatmel 1:9c5af431a1f1 148 __IO uint32_t PLL_OER; /*!< PLL output enable register, Address offset : 0x18 */
gustavatmel 1:9c5af431a1f1 149 __IO uint32_t PLL_BPR; /*!< PLL bypass register, Address offset : 0x1c */
gustavatmel 1:9c5af431a1f1 150 __IO uint32_t PLL_IFSR; /*!< PLL input frequency select register, Address offset : 0x20 */
gustavatmel 1:9c5af431a1f1 151 uint32_t RESERVED1[3];
gustavatmel 1:9c5af431a1f1 152 __IO uint32_t FCLK_SSR; /*!< FCLK source select register, Address offset : 0x30 */
gustavatmel 1:9c5af431a1f1 153 __IO uint32_t FCLK_PVSR; /*!< FCLK prescale value select register, Address offset : 0x34 */
gustavatmel 1:9c5af431a1f1 154 uint32_t RESERVED2[2];
gustavatmel 1:9c5af431a1f1 155 __IO uint32_t SSPCLK_SSR; /*!< SSPCLK source select register, Address offset : 0x40 */
gustavatmel 1:9c5af431a1f1 156 __IO uint32_t SSPCLK_PVSR; /*!< SSPCLK prescale value select register, Address offset : 0x44 */
gustavatmel 1:9c5af431a1f1 157 uint32_t RESERVED3[6];
gustavatmel 1:9c5af431a1f1 158 __IO uint32_t ADCCLK_SSR; /*!< ADCCLK source select register, Address offset : 0x60 */
gustavatmel 1:9c5af431a1f1 159 __IO uint32_t ADCCLK_PVSR; /*!< ADCCLK prescale value select register, Address offset : 0x64 */
gustavatmel 1:9c5af431a1f1 160 uint32_t RESERVED4[2];
gustavatmel 1:9c5af431a1f1 161 __IO uint32_t TIMER0CLK_SSR; /*!< TIMER0CLK source select register, Address offset : 0x70 */
gustavatmel 1:9c5af431a1f1 162 __IO uint32_t TIMER0CLK_PVSR; /*!< TIMER0CLK prescale value select register, Address offset : 0x74 */
gustavatmel 1:9c5af431a1f1 163 uint32_t RESERVED5[2];
gustavatmel 1:9c5af431a1f1 164 __IO uint32_t TIMER1CLK_SSR; /*!< TIMER1CLK source select register, Address offset : 0x80 */
gustavatmel 1:9c5af431a1f1 165 __IO uint32_t TIMER1CLK_PVSR; /*!< TIMER1CLK prescale value select register, Address offset : 0x84 */
gustavatmel 1:9c5af431a1f1 166 uint32_t RESERVED6[10];
gustavatmel 1:9c5af431a1f1 167 __IO uint32_t PWM0CLK_SSR; /*!< PWM0CLK source select register, Address offset : 0xb0 */
gustavatmel 1:9c5af431a1f1 168 __IO uint32_t PWM0CLK_PVSR; /*!< PWM0CLK prescale value select register, Address offset : 0xb4 */
gustavatmel 1:9c5af431a1f1 169 uint32_t RESERVED7[2];
gustavatmel 1:9c5af431a1f1 170 __IO uint32_t PWM1CLK_SSR; /*!< PWM1CLK source select register, Address offset : 0xc0 */
gustavatmel 1:9c5af431a1f1 171 __IO uint32_t PWM1CLK_PVSR; /*!< PWM1CLK prescale value select register, Address offset : 0xc4 */
gustavatmel 1:9c5af431a1f1 172 uint32_t RESERVED8[2];
gustavatmel 1:9c5af431a1f1 173 __IO uint32_t PWM2CLK_SSR; /*!< PWM2CLK source select register, Address offset : 0xd0 */
gustavatmel 1:9c5af431a1f1 174 __IO uint32_t PWM2CLK_PVSR; /*!< PWM2CLK prescale value select register, Address offset : 0xd4 */
gustavatmel 1:9c5af431a1f1 175 uint32_t RESERVED9[2];
gustavatmel 1:9c5af431a1f1 176 __IO uint32_t PWM3CLK_SSR; /*!< PWM3CLK source select register, Address offset : 0xe0 */
gustavatmel 1:9c5af431a1f1 177 __IO uint32_t PWM3CLK_PVSR; /*!< PWM3CLK prescale value select register, Address offset : 0xe4 */
gustavatmel 1:9c5af431a1f1 178 uint32_t RESERVED10[2];
gustavatmel 1:9c5af431a1f1 179 __IO uint32_t PWM4CLK_SSR; /*!< PWM4CLK source select register, Address offset : 0xf0 */
gustavatmel 1:9c5af431a1f1 180 __IO uint32_t PWM4CLK_PVSR; /*!< PWM4CLK prescale value select register, Address offset : 0xf4 */
gustavatmel 1:9c5af431a1f1 181 uint32_t RESERVED11[2];
gustavatmel 1:9c5af431a1f1 182 __IO uint32_t PWM5CLK_SSR; /*!< PWM5CLK source select register, Address offset : 0x100 */
gustavatmel 1:9c5af431a1f1 183 __IO uint32_t PWM5LK_PVSR; /*!< PWM5CLK prescale value select register, Address offset : 0x104 */
gustavatmel 1:9c5af431a1f1 184 uint32_t RESERVED12[2];
gustavatmel 1:9c5af431a1f1 185 __IO uint32_t PWM6CLK_SSR; /*!< PWM6CLK source select register, Address offset : 0x110 */
gustavatmel 1:9c5af431a1f1 186 __IO uint32_t PWM6CLK_PVSR; /*!< PWM6CLK prescale value select register, Address offset : 0x114 */
gustavatmel 1:9c5af431a1f1 187 uint32_t RESERVED13[2];
gustavatmel 1:9c5af431a1f1 188 __IO uint32_t PWM7CLK_SSR; /*!< PWM7CLK source select register, Address offset : 0x120 */
gustavatmel 1:9c5af431a1f1 189 __IO uint32_t PWM7CLK_PVSR; /*!< PWM7CLK prescale value select register, Address offset : 0x124 */
gustavatmel 1:9c5af431a1f1 190 uint32_t RESERVED14[2];
gustavatmel 1:9c5af431a1f1 191 __IO uint32_t RTC_HS_SSR; /*!< RTC High Speed source select register, Address offset : 0x130 */
gustavatmel 1:9c5af431a1f1 192 __IO uint32_t RTC_HS_PVSR; /*!< RTC High Speed prescale value select register, Address offset : 0x134 */
gustavatmel 1:9c5af431a1f1 193 uint32_t RESERVED15;
gustavatmel 1:9c5af431a1f1 194 __IO uint32_t RTC_SSR; /*!< RTC source select register, Address offset : 0x13c */
gustavatmel 1:9c5af431a1f1 195
gustavatmel 1:9c5af431a1f1 196 __IO uint32_t WDOGCLK_HS_SSR; /*!< WDOGCLK High Speed source select register, Address offset : 0x140 */
gustavatmel 1:9c5af431a1f1 197 __IO uint32_t WDOGCLK_HS_PVSR; /*!< WDOGCLK High Speed prescale value select register, Address offset : 0x144 */
gustavatmel 1:9c5af431a1f1 198 uint32_t RESERVED16;
gustavatmel 1:9c5af431a1f1 199 __IO uint32_t WDOGCLK_SSR; /*!< WDOGCLK source select register, Address offset : 0x14c */
gustavatmel 1:9c5af431a1f1 200
gustavatmel 1:9c5af431a1f1 201 __IO uint32_t UARTCLK_SSR; /*!< UARTCLK source select register, Address offset : 0x150 */
gustavatmel 1:9c5af431a1f1 202 __IO uint32_t UARTCLK_PVSR; /*!< UARTCLK prescale value select register, Address offset : 0x154 */
gustavatmel 1:9c5af431a1f1 203 uint32_t RESERVED17[2];
gustavatmel 1:9c5af431a1f1 204 __IO uint32_t MIICLK_ECR; /*!< MII clock enable control register, Address offset : 0x160 */
gustavatmel 1:9c5af431a1f1 205 uint32_t RESERVED18[3];
gustavatmel 1:9c5af431a1f1 206 __IO uint32_t MONCLK_SSR; /*!< Monitoring clock source select I found Treasure was IoT Base Station in March.register, Address offset : 0x170 */
gustavatmel 1:9c5af431a1f1 207 }CRG_TypeDef;
gustavatmel 1:9c5af431a1f1 208
gustavatmel 1:9c5af431a1f1 209
gustavatmel 1:9c5af431a1f1 210 /**
gustavatmel 1:9c5af431a1f1 211 * @brief UART
gustavatmel 1:9c5af431a1f1 212 */
gustavatmel 1:9c5af431a1f1 213 typedef struct
gustavatmel 1:9c5af431a1f1 214 {
gustavatmel 1:9c5af431a1f1 215 __IO uint32_t DR; /*!< Data, Address offset : 0x00 */
gustavatmel 1:9c5af431a1f1 216 union {
gustavatmel 1:9c5af431a1f1 217 __I uint32_t RSR; /*!< Receive Status, Address offset : 0x04 */
gustavatmel 1:9c5af431a1f1 218 __O uint32_t ECR; /*!< Error Clear, Address offset : 0x04 */
gustavatmel 1:9c5af431a1f1 219 } STATUS;
gustavatmel 1:9c5af431a1f1 220 uint32_t RESERVED0[4];
gustavatmel 1:9c5af431a1f1 221 __IO uint32_t FR; /*!< Flags, Address offset : 0x18 */
gustavatmel 1:9c5af431a1f1 222 uint32_t RESERVED1;
gustavatmel 1:9c5af431a1f1 223 __IO uint32_t ILPR; /*!< IrDA Low-power Counter, Address offset : 0x20 */
gustavatmel 1:9c5af431a1f1 224 __IO uint32_t IBRD; /*!< Integer Baud Rate, Address offset : 0x24 */
gustavatmel 1:9c5af431a1f1 225 __IO uint32_t FBRD; /*!< Fractional Baud Rate, Address offset : 0x28 */
gustavatmel 1:9c5af431a1f1 226 __IO uint32_t LCR_H; /*!< Line Control, Address offset : 0x2C */
gustavatmel 1:9c5af431a1f1 227 __IO uint32_t CR; /*!< Control, Address offset : 0x30 */
gustavatmel 1:9c5af431a1f1 228 __IO uint32_t IFLS; /*!< Interrupt FIFO Level Select, Address offset : 0x34 */
gustavatmel 1:9c5af431a1f1 229 __IO uint32_t IMSC; /*!< Interrupt Mask Set / Clear, Address offset : 0x38 */
gustavatmel 1:9c5af431a1f1 230 __IO uint32_t RIS; /*!< Raw Interrupt Status , Address offset : 0x3C */
gustavatmel 1:9c5af431a1f1 231 __IO uint32_t MIS; /*!< Masked Interrupt Status , Address offset : 0x40 */
gustavatmel 1:9c5af431a1f1 232 __O uint32_t ICR; /*!< Interrupt Clear, Address offset : 0x44 */
gustavatmel 1:9c5af431a1f1 233 __IO uint32_t DMACR; /*!< DMA Control, Address offset : 0x48 */
gustavatmel 1:9c5af431a1f1 234 } UART_TypeDef;
gustavatmel 1:9c5af431a1f1 235
gustavatmel 1:9c5af431a1f1 236
gustavatmel 1:9c5af431a1f1 237 /**
gustavatmel 1:9c5af431a1f1 238 * @brief Simple UART
gustavatmel 1:9c5af431a1f1 239 */
gustavatmel 1:9c5af431a1f1 240 typedef struct
gustavatmel 1:9c5af431a1f1 241 {
gustavatmel 1:9c5af431a1f1 242 __IO uint32_t DATA; /*!< Offset: 0x000 Data Register (R/W) */
gustavatmel 1:9c5af431a1f1 243 __IO uint32_t STATE; /*!< Offset: 0x004 Status Register (R/W) */
gustavatmel 1:9c5af431a1f1 244 __IO uint32_t CTRL; /*!< Offset: 0x008 Control Register (R/W) */
gustavatmel 1:9c5af431a1f1 245 union {
gustavatmel 1:9c5af431a1f1 246 __I uint32_t STATUS; /*!< Offset: 0x00C Interrupt Status Register (R/ ) */
gustavatmel 1:9c5af431a1f1 247 __O uint32_t CLEAR; /*!< Offset: 0x00C Interrupt Clear Register ( /W) */
gustavatmel 1:9c5af431a1f1 248 }INT;
gustavatmel 1:9c5af431a1f1 249 __IO uint32_t BAUDDIV; /*!< Offset: 0x010 Baudrate Divider Register (R/W) */
gustavatmel 1:9c5af431a1f1 250
gustavatmel 1:9c5af431a1f1 251 } S_UART_TypeDef;
gustavatmel 1:9c5af431a1f1 252
gustavatmel 1:9c5af431a1f1 253 /**
gustavatmel 1:9c5af431a1f1 254 * @brief Analog Digital Converter
gustavatmel 1:9c5af431a1f1 255 */
gustavatmel 1:9c5af431a1f1 256
gustavatmel 1:9c5af431a1f1 257 typedef struct
gustavatmel 1:9c5af431a1f1 258 {
gustavatmel 1:9c5af431a1f1 259 __IO uint32_t ADC_CTR; /* ADC control register, Address offset : 0x000 */
gustavatmel 1:9c5af431a1f1 260 __IO uint32_t ADC_CHSEL; /* ADC channel select register, Address offset : 0x004 */
gustavatmel 1:9c5af431a1f1 261 __IO uint32_t ADC_START; /* ADC start register, Address offset : 0x008 */
gustavatmel 1:9c5af431a1f1 262 __I uint32_t ADC_DATA; /* ADC conversion data register, Address offset : 0x00c */
gustavatmel 1:9c5af431a1f1 263 __IO uint32_t ADC_INT; /* ADC interrupt register, Address offset : 0x010 */
gustavatmel 1:9c5af431a1f1 264 uint32_t RESERVED0[2];
gustavatmel 1:9c5af431a1f1 265 __IO uint32_t ADC_INTCLR; /* ADC interrupt clear register, Address offset : 0x01c */
gustavatmel 1:9c5af431a1f1 266 }ADC_TypeDef;
gustavatmel 1:9c5af431a1f1 267
gustavatmel 1:9c5af431a1f1 268 /**
gustavatmel 1:9c5af431a1f1 269 * @brief dualtimer
gustavatmel 1:9c5af431a1f1 270 */
gustavatmel 1:9c5af431a1f1 271 typedef struct
gustavatmel 1:9c5af431a1f1 272 {
gustavatmel 1:9c5af431a1f1 273 __IO uint32_t TimerLoad; // <h> Timer Load </h>
gustavatmel 1:9c5af431a1f1 274 __I uint32_t TimerValue; // <h> Timer Counter Current Value <r></h>
gustavatmel 1:9c5af431a1f1 275 __IO uint32_t TimerControl; // <h> Timer Control
gustavatmel 1:9c5af431a1f1 276 // <o.7> TimerEn: Timer Enable
gustavatmel 1:9c5af431a1f1 277 // <o.6> TimerMode: Timer Mode
gustavatmel 1:9c5af431a1f1 278 // <0=> Freerunning-mode
gustavatmel 1:9c5af431a1f1 279 // <1=> Periodic mode
gustavatmel 1:9c5af431a1f1 280 // <o.5> IntEnable: Interrupt Enable
gustavatmel 1:9c5af431a1f1 281 // <o.2..3> TimerPre: Timer Prescale
gustavatmel 1:9c5af431a1f1 282 // <0=> / 1
gustavatmel 1:9c5af431a1f1 283 // <1=> / 16
gustavatmel 1:9c5af431a1f1 284 // <2=> / 256
gustavatmel 1:9c5af431a1f1 285 // <3=> Undefined!
gustavatmel 1:9c5af431a1f1 286 // <o.1> TimerSize: Timer Size
gustavatmel 1:9c5af431a1f1 287 // <0=> 16-bit counter
gustavatmel 1:9c5af431a1f1 288 // <1=> 32-bit counter
gustavatmel 1:9c5af431a1f1 289 // <o.0> OneShot: One-shoot mode
gustavatmel 1:9c5af431a1f1 290 // <0=> Wrapping mode
gustavatmel 1:9c5af431a1f1 291 // <1=> One-shot mode
gustavatmel 1:9c5af431a1f1 292 // </h>
gustavatmel 1:9c5af431a1f1 293 __O uint32_t TimerIntClr; // <h> Timer Interrupt Clear <w></h>
gustavatmel 1:9c5af431a1f1 294 __I uint32_t TimerRIS; // <h> Timer Raw Interrupt Status <r></h>
gustavatmel 1:9c5af431a1f1 295 __I uint32_t TimerMIS; // <h> Timer Masked Interrupt Status <r></h>
gustavatmel 1:9c5af431a1f1 296 __IO uint32_t TimerBGLoad; // <h> Background Load Register </h>
gustavatmel 1:9c5af431a1f1 297 } DUALTIMER_TypeDef;
gustavatmel 1:9c5af431a1f1 298
gustavatmel 1:9c5af431a1f1 299 /**
gustavatmel 1:9c5af431a1f1 300 * @brief GPIO
gustavatmel 1:9c5af431a1f1 301 */
gustavatmel 1:9c5af431a1f1 302 typedef struct
gustavatmel 1:9c5af431a1f1 303 {
gustavatmel 1:9c5af431a1f1 304 __IO uint32_t DATA; /* DATA Register (R/W), offset : 0x000 */
gustavatmel 1:9c5af431a1f1 305 __IO uint32_t DATAOUT; /* Data Output Latch Register (R/W), offset : 0x004 */
gustavatmel 1:9c5af431a1f1 306 uint32_t RESERVED0[2];
gustavatmel 1:9c5af431a1f1 307 __IO uint32_t OUTENSET; /* Output Enable Set Register (R/W) offset : 0x010 */
gustavatmel 1:9c5af431a1f1 308 __IO uint32_t OUTENCLR; /* Output Enable Clear Register (R/W) offset : 0x014 */
gustavatmel 1:9c5af431a1f1 309 __IO uint32_t RESERVED1; /* Alternate Function Set Register (R/W) offset : 0x018 */
gustavatmel 1:9c5af431a1f1 310 __IO uint32_t RESERVED2; /* Alternate Function Clear Register (R/W) offset : 0x01C */
gustavatmel 1:9c5af431a1f1 311 __IO uint32_t INTENSET; /* Interrupt Enable Set Register (R/W) offset : 0x020 */
gustavatmel 1:9c5af431a1f1 312 __IO uint32_t INTENCLR; /* Interrupt Enable Clear Register (R/W) offset : 0x024 */
gustavatmel 1:9c5af431a1f1 313 __IO uint32_t INTTYPESET; /* Interrupt Type Set Register (R/W) offset : 0x028 */
gustavatmel 1:9c5af431a1f1 314 __IO uint32_t INTTYPECLR; /* Interrupt Type Clear Register (R/W) offset : 0x02C */
gustavatmel 1:9c5af431a1f1 315 __IO uint32_t INTPOLSET; /* Interrupt Polarity Set Register (R/W) offset : 0x030 */
gustavatmel 1:9c5af431a1f1 316 __IO uint32_t INTPOLCLR; /* Interrupt Polarity Clear Register (R/W) offset : 0x034 */
gustavatmel 1:9c5af431a1f1 317 union {
gustavatmel 1:9c5af431a1f1 318 __I uint32_t INTSTATUS; /* Interrupt Status Register (R/ ) offset : 0x038 */
gustavatmel 1:9c5af431a1f1 319 __O uint32_t INTCLEAR; /* Interrupt Clear Register ( /W) offset : 0x038 */
gustavatmel 1:9c5af431a1f1 320 }Interrupt;
gustavatmel 1:9c5af431a1f1 321 uint32_t RESERVED3[241];
gustavatmel 1:9c5af431a1f1 322 __IO uint32_t LB_MASKED[256]; /* Lower byte Masked Access Register (R/W) offset : 0x400 - 0x7FC */
gustavatmel 1:9c5af431a1f1 323 __IO uint32_t UB_MASKED[256]; /* Upper byte Masked Access Register (R/W) offset : 0x800 - 0xBFC */
gustavatmel 1:9c5af431a1f1 324 } GPIO_TypeDef;
gustavatmel 1:9c5af431a1f1 325
gustavatmel 1:9c5af431a1f1 326 typedef struct
gustavatmel 1:9c5af431a1f1 327 {
gustavatmel 1:9c5af431a1f1 328 __IO uint32_t Port[16]; /* Port_00, offset : 0x00 */
gustavatmel 1:9c5af431a1f1 329 /* Port_01, offset : 0x04 */
gustavatmel 1:9c5af431a1f1 330 /* Port_02, offset : 0x08 */
gustavatmel 1:9c5af431a1f1 331 /* Port_03, offset : 0x0C */
gustavatmel 1:9c5af431a1f1 332 /* Port_04, offset : 0x10 */
gustavatmel 1:9c5af431a1f1 333 /* Port_05, offset : 0x14 */
gustavatmel 1:9c5af431a1f1 334 /* Port_06, offset : 0x18 */
gustavatmel 1:9c5af431a1f1 335 /* Port_07, offset : 0x1C */
gustavatmel 1:9c5af431a1f1 336 /* Port_08, offset : 0x20 */
gustavatmel 1:9c5af431a1f1 337 /* Port_09, offset : 0x24 */
gustavatmel 1:9c5af431a1f1 338 /* Port_10, offset : 0x28 */
gustavatmel 1:9c5af431a1f1 339 /* Port_11, offset : 0x2C */
gustavatmel 1:9c5af431a1f1 340 /* Port_12, offset : 0x30 */
gustavatmel 1:9c5af431a1f1 341 /* Port_13, offset : 0x34 */
gustavatmel 1:9c5af431a1f1 342 /* Port_14, offset : 0x38 */
gustavatmel 1:9c5af431a1f1 343 /* Port_15, offset : 0x3C */
gustavatmel 1:9c5af431a1f1 344 } P_Port_Def;
gustavatmel 1:9c5af431a1f1 345
gustavatmel 1:9c5af431a1f1 346 typedef struct
gustavatmel 1:9c5af431a1f1 347 {
gustavatmel 1:9c5af431a1f1 348 __IO uint32_t Port[5]; /* Port_00, offset : 0x00 */
gustavatmel 1:9c5af431a1f1 349 /* Port_01, offset : 0x04 */
gustavatmel 1:9c5af431a1f1 350 /* Port_02, offset : 0x08 */
gustavatmel 1:9c5af431a1f1 351 /* Port_03, offset : 0x0C */
gustavatmel 1:9c5af431a1f1 352 /* Port_04, offset : 0x10 */
gustavatmel 1:9c5af431a1f1 353 } P_Port_D_Def;
gustavatmel 1:9c5af431a1f1 354
gustavatmel 1:9c5af431a1f1 355 /**
gustavatmel 1:9c5af431a1f1 356 * @brief I2C Register structure definition
gustavatmel 1:9c5af431a1f1 357 */
gustavatmel 1:9c5af431a1f1 358 typedef struct
gustavatmel 1:9c5af431a1f1 359 {
gustavatmel 1:9c5af431a1f1 360 __IO uint32_t PRER; //0x00
gustavatmel 1:9c5af431a1f1 361 __IO uint32_t CTR; //0x04
gustavatmel 1:9c5af431a1f1 362 __IO uint32_t CMDR; //0x08
gustavatmel 1:9c5af431a1f1 363 __I uint32_t SR; //0x0C
gustavatmel 1:9c5af431a1f1 364 __IO uint32_t TSR; //0x10
gustavatmel 1:9c5af431a1f1 365 __IO uint32_t SADDR; //0x14
gustavatmel 1:9c5af431a1f1 366 __IO uint32_t TXR; //0x18
gustavatmel 1:9c5af431a1f1 367 __I uint32_t RXR; //0x1C
gustavatmel 1:9c5af431a1f1 368 __I uint32_t ISR; //0x20
gustavatmel 1:9c5af431a1f1 369 __IO uint32_t ISCR; //0x24
gustavatmel 1:9c5af431a1f1 370 __IO uint32_t ISMR; //0x28
gustavatmel 1:9c5af431a1f1 371 }I2C_TypeDef;
gustavatmel 1:9c5af431a1f1 372
gustavatmel 1:9c5af431a1f1 373 /**
gustavatmel 1:9c5af431a1f1 374 * @brief PWM Register structure definition
gustavatmel 1:9c5af431a1f1 375 */
gustavatmel 1:9c5af431a1f1 376 typedef struct
gustavatmel 1:9c5af431a1f1 377 {
gustavatmel 1:9c5af431a1f1 378 __IO uint32_t IER; //Interrupt enable register
gustavatmel 1:9c5af431a1f1 379 // <7> IE7 : Channel 7 interrupt enable <R/W>
gustavatmel 1:9c5af431a1f1 380 // <6> IE6 : Channel 6 interrupt enable <R/W>
gustavatmel 1:9c5af431a1f1 381 // <5> IE5 : Channel 5 interrupt enable <R/W>
gustavatmel 1:9c5af431a1f1 382 // <4> IE4 : Channel 4 interrupt enable <R/W>
gustavatmel 1:9c5af431a1f1 383 // <3> IE3 : Channel 3 interrupt enable <R/W>
gustavatmel 1:9c5af431a1f1 384 // <2> IE2 : Channel 2 interrupt enable <R/W>
gustavatmel 1:9c5af431a1f1 385 // <1> IE1 : Channel 1 interrupt enable <R/W>
gustavatmel 1:9c5af431a1f1 386 // <0> IE0 : Channel 0 interrupt enable <R/W>
gustavatmel 1:9c5af431a1f1 387
gustavatmel 1:9c5af431a1f1 388 __IO uint32_t SSR; //Start Stop register
gustavatmel 1:9c5af431a1f1 389 // <7> SS7 : Channel 7 TC start or stop <R/W>
gustavatmel 1:9c5af431a1f1 390 // <6> SS6 : Channel 6 TC start or stop <R/W>
gustavatmel 1:9c5af431a1f1 391 // <5> SS5 : Channel 5 TC start or stop <R/W>
gustavatmel 1:9c5af431a1f1 392 // <4> SS4 : Channel 4 TC start or stop <R/W>
gustavatmel 1:9c5af431a1f1 393 // <3> SS3 : Channel 3 TC start or stop <R/W>
gustavatmel 1:9c5af431a1f1 394 // <2> SS2 : Channel 2 TC start or stop <R/W>
gustavatmel 1:9c5af431a1f1 395 // <1> SS1 : Channel 1 TC start or stop <R/W>
gustavatmel 1:9c5af431a1f1 396 // <0> SS0 : Channel 0 TC start or stop <R/W>
gustavatmel 1:9c5af431a1f1 397
gustavatmel 1:9c5af431a1f1 398 __IO uint32_t PSR; //Pause register
gustavatmel 1:9c5af431a1f1 399 // <7> PS7 : Channel 7 TC pasue <R/W>
gustavatmel 1:9c5af431a1f1 400 // <6> PS6 : Channel 6 TC pasue <R/W>
gustavatmel 1:9c5af431a1f1 401 // <5> PS5 : Channel 5 TC pasue <R/W>
gustavatmel 1:9c5af431a1f1 402 // <4> PS4 : Channel 4 TC pasue <R/W>
gustavatmel 1:9c5af431a1f1 403 // <3> PS3 : Channel 3 TC pasue <R/W>
gustavatmel 1:9c5af431a1f1 404 // <2> PS2 : Channel 2 TC pasue <R/W>
gustavatmel 1:9c5af431a1f1 405 // <1> PS1 : Channel 1 TC pasue <R/W>
gustavatmel 1:9c5af431a1f1 406 // <0> PS0 : Channel 0 TC pasue <R/W>
gustavatmel 1:9c5af431a1f1 407 } PWM_TypeDef;
gustavatmel 1:9c5af431a1f1 408
gustavatmel 1:9c5af431a1f1 409 typedef struct
gustavatmel 1:9c5af431a1f1 410 {
gustavatmel 1:9c5af431a1f1 411 __I uint32_t IR; //Interrupt register
gustavatmel 1:9c5af431a1f1 412 // <2> CI : Capture interrupt <R>
gustavatmel 1:9c5af431a1f1 413 // <1> OI : Overflow interrupt <R>
gustavatmel 1:9c5af431a1f1 414 // <0> MI : Match interrupt <R>
gustavatmel 1:9c5af431a1f1 415
gustavatmel 1:9c5af431a1f1 416 __IO uint32_t IER; //Interrupt enable register
gustavatmel 1:9c5af431a1f1 417 // <2> CIE : Capture interrupt enable <R/W>
gustavatmel 1:9c5af431a1f1 418 // <1> OIE : Overflow interrupt enable <R/W>
gustavatmel 1:9c5af431a1f1 419 // <0> MIE : Match interrupt enable <R/W>
gustavatmel 1:9c5af431a1f1 420
gustavatmel 1:9c5af431a1f1 421 __O uint32_t ICR; //Interrupt clear register
gustavatmel 1:9c5af431a1f1 422 // <2> CIC : Capture interrupt clear <W>
gustavatmel 1:9c5af431a1f1 423 // <1> OIC : Overflow interrupt clear <W>
gustavatmel 1:9c5af431a1f1 424 // <0> MIC : Match interrupt clear <W>
gustavatmel 1:9c5af431a1f1 425
gustavatmel 1:9c5af431a1f1 426 __I uint32_t TCR; //Timer/Counter register
gustavatmel 1:9c5af431a1f1 427 // <0..31> TCR : Timer/Counter register <R>
gustavatmel 1:9c5af431a1f1 428
gustavatmel 1:9c5af431a1f1 429 __I uint32_t PCR; //Prescale counter register
gustavatmel 1:9c5af431a1f1 430 // <0..5> PCR : Prescale Counter register <R>
gustavatmel 1:9c5af431a1f1 431
gustavatmel 1:9c5af431a1f1 432 __IO uint32_t PR; //Prescale register
gustavatmel 1:9c5af431a1f1 433 // <0..5> PR : prescale register <R/W>
gustavatmel 1:9c5af431a1f1 434
gustavatmel 1:9c5af431a1f1 435 __IO uint32_t MR; //Match register
gustavatmel 1:9c5af431a1f1 436 // <0..31> MR : Match register <R/W>
gustavatmel 1:9c5af431a1f1 437
gustavatmel 1:9c5af431a1f1 438 __IO uint32_t LR; //Limit register
gustavatmel 1:9c5af431a1f1 439 // <0..31> LR : Limit register <R/W>
gustavatmel 1:9c5af431a1f1 440 __IO uint32_t UDMR; //Up-Down mode register
gustavatmel 1:9c5af431a1f1 441 // <0> UDM : Up-down mode <R/W>
gustavatmel 1:9c5af431a1f1 442
gustavatmel 1:9c5af431a1f1 443 __IO uint32_t TCMR; //Timer/Counter mode register
gustavatmel 1:9c5af431a1f1 444 // <0> TCM : Timer/Counter mode <R/W>
gustavatmel 1:9c5af431a1f1 445
gustavatmel 1:9c5af431a1f1 446 __IO uint32_t PEEER; //PWM output enable and external input enable register
gustavatmel 1:9c5af431a1f1 447 // <0..1> PEEE : PWM output enable and external input enable <R/W>
gustavatmel 1:9c5af431a1f1 448
gustavatmel 1:9c5af431a1f1 449 __IO uint32_t CMR; //Capture mode register
gustavatmel 1:9c5af431a1f1 450 // <0> CM : Capture mode <R/W>
gustavatmel 1:9c5af431a1f1 451
gustavatmel 1:9c5af431a1f1 452 __IO uint32_t CR; //Capture register
gustavatmel 1:9c5af431a1f1 453 // <0..31> CR : Capture register <R>
gustavatmel 1:9c5af431a1f1 454
gustavatmel 1:9c5af431a1f1 455 __IO uint32_t PDMR; //Periodic mode register
gustavatmel 1:9c5af431a1f1 456 // <0> PDM : Periodic mode <R/W>
gustavatmel 1:9c5af431a1f1 457
gustavatmel 1:9c5af431a1f1 458 __IO uint32_t DZER; //Dead-zone enable register
gustavatmel 1:9c5af431a1f1 459 // <0> DZE : Dead-zone enable <R/W>
gustavatmel 1:9c5af431a1f1 460
gustavatmel 1:9c5af431a1f1 461 __IO uint32_t DZCR; //Dead-zone counter register
gustavatmel 1:9c5af431a1f1 462 // <0..9> DZC : Dead-zone counter <R/W>
gustavatmel 1:9c5af431a1f1 463 } PWM_CHn_TypeDef;
gustavatmel 1:9c5af431a1f1 464
gustavatmel 1:9c5af431a1f1 465 typedef struct
gustavatmel 1:9c5af431a1f1 466 {
gustavatmel 1:9c5af431a1f1 467 __IO uint32_t PWM_CHn_PR; //Prescale register
gustavatmel 1:9c5af431a1f1 468 // <0..5> PR : prescale register <R/W>
gustavatmel 1:9c5af431a1f1 469 __IO uint32_t PWM_CHn_MR; //Match register
gustavatmel 1:9c5af431a1f1 470 // <0..31> MR : Match register <R/W>
gustavatmel 1:9c5af431a1f1 471 __IO uint32_t PWM_CHn_LR; //Limit register
gustavatmel 1:9c5af431a1f1 472 // <0..31> LR : Limit register <R/W>
gustavatmel 1:9c5af431a1f1 473 __IO uint32_t PWM_CHn_UDMR; //Up-Down mode register
gustavatmel 1:9c5af431a1f1 474 // <0> UDM : Up-down mode <R/W>
gustavatmel 1:9c5af431a1f1 475 __IO uint32_t PWM_CHn_PDMR; //Periodic mode register
gustavatmel 1:9c5af431a1f1 476 // <0> PDM : Periodic mode <R/W>
gustavatmel 1:9c5af431a1f1 477 }PWM_TimerModeInitTypeDef;
gustavatmel 1:9c5af431a1f1 478
gustavatmel 1:9c5af431a1f1 479 typedef struct
gustavatmel 1:9c5af431a1f1 480 {
gustavatmel 1:9c5af431a1f1 481 __IO uint32_t PWM_CHn_PR; //Prescale register
gustavatmel 1:9c5af431a1f1 482 // <0..5> PR : prescale register <R/W>
gustavatmel 1:9c5af431a1f1 483 __IO uint32_t PWM_CHn_MR; //Match register
gustavatmel 1:9c5af431a1f1 484 // <0..31> MR : Match register <R/W>
gustavatmel 1:9c5af431a1f1 485 __IO uint32_t PWM_CHn_LR; //Limit register
gustavatmel 1:9c5af431a1f1 486 // <0..31> LR : Limit register <R/W>
gustavatmel 1:9c5af431a1f1 487 __IO uint32_t PWM_CHn_UDMR; //Up-Down mode register
gustavatmel 1:9c5af431a1f1 488 // <0> UDM : Up-down mode <R/W>
gustavatmel 1:9c5af431a1f1 489 __IO uint32_t PWM_CHn_PDMR; //Periodic mode register
gustavatmel 1:9c5af431a1f1 490 // <0> PDM : Peiodic mode <R/W>
gustavatmel 1:9c5af431a1f1 491 __IO uint32_t PWM_CHn_CMR; //Capture mode register
gustavatmel 1:9c5af431a1f1 492 // <0> CM : Capture mode <R/W>
gustavatmel 1:9c5af431a1f1 493 }PWM_CaptureModeInitTypeDef;
gustavatmel 1:9c5af431a1f1 494
gustavatmel 1:9c5af431a1f1 495 typedef struct
gustavatmel 1:9c5af431a1f1 496 {
gustavatmel 1:9c5af431a1f1 497 __IO uint32_t PWM_CHn_MR;
gustavatmel 1:9c5af431a1f1 498 __IO uint32_t PWM_CHn_LR;
gustavatmel 1:9c5af431a1f1 499 __IO uint32_t PWM_CHn_UDMR;
gustavatmel 1:9c5af431a1f1 500 __IO uint32_t PWM_CHn_PDMR;
gustavatmel 1:9c5af431a1f1 501 __IO uint32_t PWM_CHn_TCMR;
gustavatmel 1:9c5af431a1f1 502 }PWM_CounterModeInitTypeDef;
gustavatmel 1:9c5af431a1f1 503
gustavatmel 1:9c5af431a1f1 504
gustavatmel 1:9c5af431a1f1 505 /**
gustavatmel 1:9c5af431a1f1 506 * @brief Random Number generator
gustavatmel 1:9c5af431a1f1 507 */
gustavatmel 1:9c5af431a1f1 508 typedef struct
gustavatmel 1:9c5af431a1f1 509 {
gustavatmel 1:9c5af431a1f1 510 __IO uint32_t RNG_RUN; /* RNG run register, Address offset : 0x000 */
gustavatmel 1:9c5af431a1f1 511 __IO uint32_t RNG_SEED; /* RNG seed value register, Address offset : 0x004 */
gustavatmel 1:9c5af431a1f1 512 __IO uint32_t RNG_CLKSEL; /* RNG Clock source select register, Address offset : 0x008 */
gustavatmel 1:9c5af431a1f1 513 __IO uint32_t RNG_MODE; /* RNG MODE select register, Address offset : 0x00c */
gustavatmel 1:9c5af431a1f1 514 __I uint32_t RNG_RN; /* RNG random number value register, Address offset : 0x010 */
gustavatmel 1:9c5af431a1f1 515 __IO uint32_t RNG_POLY; /* RNG polynomial register, Address offset : 0x014 */
gustavatmel 1:9c5af431a1f1 516 }RNG_TypeDef;
gustavatmel 1:9c5af431a1f1 517
gustavatmel 1:9c5af431a1f1 518 /**
gustavatmel 1:9c5af431a1f1 519 * @brief Serial Peripheral Interface
gustavatmel 1:9c5af431a1f1 520 */
gustavatmel 1:9c5af431a1f1 521 typedef struct
gustavatmel 1:9c5af431a1f1 522 {
gustavatmel 1:9c5af431a1f1 523 __IO uint32_t CR0;
gustavatmel 1:9c5af431a1f1 524 __IO uint32_t CR1;
gustavatmel 1:9c5af431a1f1 525 __IO uint32_t DR;
gustavatmel 1:9c5af431a1f1 526 __IO uint32_t SR;
gustavatmel 1:9c5af431a1f1 527 __IO uint32_t CPSR;
gustavatmel 1:9c5af431a1f1 528 __IO uint32_t IMSC;
gustavatmel 1:9c5af431a1f1 529 __IO uint32_t RIS;
gustavatmel 1:9c5af431a1f1 530 __IO uint32_t MIS;
gustavatmel 1:9c5af431a1f1 531 __IO uint32_t ICR;
gustavatmel 1:9c5af431a1f1 532 __IO uint32_t DMACR;
gustavatmel 1:9c5af431a1f1 533 } SSP_TypeDef;
gustavatmel 1:9c5af431a1f1 534
gustavatmel 1:9c5af431a1f1 535 typedef struct
gustavatmel 1:9c5af431a1f1 536 {
gustavatmel 1:9c5af431a1f1 537 __IO uint32_t WatchdogLoad; // <h> Watchdog Load Register </h>
gustavatmel 1:9c5af431a1f1 538 __I uint32_t WatchdogValue; // <h> Watchdog Value Register </h>
gustavatmel 1:9c5af431a1f1 539 __IO uint32_t WatchdogControl; // <h> Watchdog Control Register
gustavatmel 1:9c5af431a1f1 540 // <o.1> RESEN: Reset enable
gustavatmel 1:9c5af431a1f1 541 // <o.0> INTEN: Interrupt enable
gustavatmel 1:9c5af431a1f1 542 // </h>
gustavatmel 1:9c5af431a1f1 543 __O uint32_t WatchdogIntClr; // <h> Watchdog Clear Interrupt Register </h>
gustavatmel 1:9c5af431a1f1 544 __I uint32_t WatchdogRIS; // <h> Watchdog Raw Interrupt Status Register </h>
gustavatmel 1:9c5af431a1f1 545 __I uint32_t WatchdogMIS; // <h> Watchdog Interrupt Status Register </h>
gustavatmel 1:9c5af431a1f1 546 uint32_t RESERVED[762];
gustavatmel 1:9c5af431a1f1 547 __IO uint32_t WatchdogLock; // <h> Watchdog Lock Register </h>
gustavatmel 1:9c5af431a1f1 548 }WATCHDOG_TypeDef;
gustavatmel 1:9c5af431a1f1 549
gustavatmel 1:9c5af431a1f1 550 /** @addtogroup Peripheral_memory_map
gustavatmel 1:9c5af431a1f1 551 * @{
gustavatmel 1:9c5af431a1f1 552 */
gustavatmel 1:9c5af431a1f1 553
gustavatmel 1:9c5af431a1f1 554 /* Peripheral and SRAM base address */
gustavatmel 1:9c5af431a1f1 555 #define W7500x_FLASH_BASE (0x00000000UL) /*!< (FLASH ) Base Address */
gustavatmel 1:9c5af431a1f1 556 #define W7500x_SRAM_BASE (0x20000000UL) /*!< (SRAM ) Base Address */
gustavatmel 1:9c5af431a1f1 557 #define W7500x_PERIPH_BASE (0x40000000UL) /*!< (Peripheral) Base Address */
gustavatmel 1:9c5af431a1f1 558
gustavatmel 1:9c5af431a1f1 559 #define W7500x_RAM_BASE (0x20000000UL)
gustavatmel 1:9c5af431a1f1 560 #define W7500x_APB1_BASE (0x40000000UL)
gustavatmel 1:9c5af431a1f1 561 #define W7500x_APB2_BASE (0x41000000UL)
gustavatmel 1:9c5af431a1f1 562 #define W7500x_AHB_BASE (0x42000000UL)
gustavatmel 1:9c5af431a1f1 563
gustavatmel 1:9c5af431a1f1 564 #define W7500x_UART0_BASE (W7500x_APB1_BASE + 0x0000C000UL)
gustavatmel 1:9c5af431a1f1 565 #define W7500x_UART1_BASE (W7500x_APB1_BASE + 0x0000D000UL)
gustavatmel 1:9c5af431a1f1 566 #define W7500x_UART2_BASE (W7500x_APB1_BASE + 0x00006000UL)
gustavatmel 1:9c5af431a1f1 567
gustavatmel 1:9c5af431a1f1 568 #define W7500x_CRG_BASE (W7500x_APB2_BASE + 0x00001000UL)
gustavatmel 1:9c5af431a1f1 569 #define W7500x_ADC_BASE (W7500x_APB2_BASE + 0x00000000UL)
gustavatmel 1:9c5af431a1f1 570
gustavatmel 1:9c5af431a1f1 571 #define W7500x_INFO_BGT (0x0003FDB8)
gustavatmel 1:9c5af431a1f1 572 #define W7500x_INFO_OSC (0x0003FDBC)
gustavatmel 1:9c5af431a1f1 573
gustavatmel 1:9c5af431a1f1 574 #define W7500x_TRIM_BGT (0x41001210)
gustavatmel 1:9c5af431a1f1 575 #define W7500x_TRIM_OSC (0x41001004)
gustavatmel 1:9c5af431a1f1 576
gustavatmel 1:9c5af431a1f1 577 #define W7500x_DUALTIMER0_BASE (W7500x_APB1_BASE + 0x00001000ul)
gustavatmel 1:9c5af431a1f1 578 #define W7500x_DUALTIMER1_BASE (W7500x_APB1_BASE + 0x00002000ul)
gustavatmel 1:9c5af431a1f1 579
gustavatmel 1:9c5af431a1f1 580 #define EXTI_Px_BASE (W7500x_APB2_BASE + 0x00002200UL)
gustavatmel 1:9c5af431a1f1 581
gustavatmel 1:9c5af431a1f1 582 #define GPIOA_BASE (W7500x_AHB_BASE + 0x00000000UL) // W7500x_AHB_BASE : 0x42000000UL
gustavatmel 1:9c5af431a1f1 583 #define GPIOB_BASE (W7500x_AHB_BASE + 0x01000000UL)
gustavatmel 1:9c5af431a1f1 584 #define GPIOC_BASE (W7500x_AHB_BASE + 0x02000000UL)
gustavatmel 1:9c5af431a1f1 585 #define GPIOD_BASE (W7500x_AHB_BASE + 0x03000000UL)
gustavatmel 1:9c5af431a1f1 586
gustavatmel 1:9c5af431a1f1 587 #define P_AFSR_BASE (W7500x_APB2_BASE + 0x00002000UL)
gustavatmel 1:9c5af431a1f1 588
gustavatmel 1:9c5af431a1f1 589 #define P_PCR_BASE (W7500x_APB2_BASE + 0x00003000UL)
gustavatmel 1:9c5af431a1f1 590
gustavatmel 1:9c5af431a1f1 591 #define I2C0_BASE (W7500x_APB1_BASE + 0x8000)
gustavatmel 1:9c5af431a1f1 592 #define I2C1_BASE (W7500x_APB1_BASE + 0x9000)
gustavatmel 1:9c5af431a1f1 593
gustavatmel 1:9c5af431a1f1 594 #define W7500x_PWM_BASE (W7500x_APB1_BASE + 0x00005000UL)
gustavatmel 1:9c5af431a1f1 595
gustavatmel 1:9c5af431a1f1 596 #define W7500x_RNG_BASE (W7500x_APB1_BASE + 0x00007000UL)
gustavatmel 1:9c5af431a1f1 597
gustavatmel 1:9c5af431a1f1 598 #define SSP0_BASE (0x4000A000)
gustavatmel 1:9c5af431a1f1 599 #define SSP1_BASE (0x4000B000)
gustavatmel 1:9c5af431a1f1 600
gustavatmel 1:9c5af431a1f1 601 #define W7500x_WATCHDOG_BASE (W7500x_APB1_BASE + 0x0000UL)
gustavatmel 1:9c5af431a1f1 602
gustavatmel 1:9c5af431a1f1 603 /**
gustavatmel 1:9c5af431a1f1 604 * @}
gustavatmel 1:9c5af431a1f1 605 */
gustavatmel 1:9c5af431a1f1 606
gustavatmel 1:9c5af431a1f1 607
gustavatmel 1:9c5af431a1f1 608 /** @addtogroup Peripheral_declaration
gustavatmel 1:9c5af431a1f1 609 * @{
gustavatmel 1:9c5af431a1f1 610 */
gustavatmel 1:9c5af431a1f1 611 #define CRG ((CRG_TypeDef *) W7500x_CRG_BASE)
gustavatmel 1:9c5af431a1f1 612
gustavatmel 1:9c5af431a1f1 613 #define UART0 ((UART_TypeDef *) W7500x_UART0_BASE)
gustavatmel 1:9c5af431a1f1 614 #define UART1 ((UART_TypeDef *) W7500x_UART1_BASE)
gustavatmel 1:9c5af431a1f1 615 #define UART2 ((S_UART_TypeDef *) W7500x_UART2_BASE)
gustavatmel 1:9c5af431a1f1 616
gustavatmel 1:9c5af431a1f1 617 #define ADC ((ADC_TypeDef *) W7500x_ADC_BASE)
gustavatmel 1:9c5af431a1f1 618
gustavatmel 1:9c5af431a1f1 619 #define DUALTIMER0_0 ((DUALTIMER_TypeDef *) (W7500x_DUALTIMER0_BASE) )
gustavatmel 1:9c5af431a1f1 620 #define DUALTIMER0_1 ((DUALTIMER_TypeDef *) (W7500x_DUALTIMER0_BASE + 0x20ul))
gustavatmel 1:9c5af431a1f1 621 #define DUALTIMER1_0 ((DUALTIMER_TypeDef *) (W7500x_DUALTIMER1_BASE) )
gustavatmel 1:9c5af431a1f1 622 #define DUALTIMER1_1 ((DUALTIMER_TypeDef *) (W7500x_DUALTIMER1_BASE + 0x20ul))
gustavatmel 1:9c5af431a1f1 623
gustavatmel 1:9c5af431a1f1 624 #define EXTI_PA ((P_Port_Def *) (EXTI_Px_BASE + 0x00000000UL)) /* PA_XX External interrupt Enable Register */
gustavatmel 1:9c5af431a1f1 625 #define EXTI_PB ((P_Port_Def *) (EXTI_Px_BASE + 0x00000040UL)) /* PB_XX External interrupt Enable Register */
gustavatmel 1:9c5af431a1f1 626 #define EXTI_PC ((P_Port_Def *) (EXTI_Px_BASE + 0x00000080UL)) /* PC_XX External interrupt Enable Register */
gustavatmel 1:9c5af431a1f1 627 #define EXTI_PD ((P_Port_D_Def *) (EXTI_Px_BASE + 0x000000C0UL)) /* PD_XX External interrupt Enable Register */
gustavatmel 1:9c5af431a1f1 628
gustavatmel 1:9c5af431a1f1 629 #define GPIOA ((GPIO_TypeDef *) (GPIOA_BASE) )
gustavatmel 1:9c5af431a1f1 630 #define GPIOB ((GPIO_TypeDef *) (GPIOB_BASE) )
gustavatmel 1:9c5af431a1f1 631 #define GPIOC ((GPIO_TypeDef *) (GPIOC_BASE) )
gustavatmel 1:9c5af431a1f1 632 #define GPIOD ((GPIO_TypeDef *) (GPIOD_BASE) )
gustavatmel 1:9c5af431a1f1 633
gustavatmel 1:9c5af431a1f1 634 #define PA_AFSR ((P_Port_Def *) (P_AFSR_BASE + 0x00000000UL)) /* PA_XX Pad Alternate Function Select Register */
gustavatmel 1:9c5af431a1f1 635 #define PB_AFSR ((P_Port_Def *) (P_AFSR_BASE + 0x00000040UL)) /* PB_XX Pad Alternate Function Select Register */
gustavatmel 1:9c5af431a1f1 636 #define PC_AFSR ((P_Port_Def *) (P_AFSR_BASE + 0x00000080UL)) /* PC_XX Pad Alternate Function Select Register */
gustavatmel 1:9c5af431a1f1 637 #define PD_AFSR ((P_Port_D_Def *) (P_AFSR_BASE + 0x000000C0UL)) /* PD_XX Pad Alternate Function Select Register */
gustavatmel 1:9c5af431a1f1 638
gustavatmel 1:9c5af431a1f1 639 #define PA_PCR ((P_Port_Def *) (P_PCR_BASE + 0x00000000UL)) /* PA_XX Pad Control Register */
gustavatmel 1:9c5af431a1f1 640 #define PB_PCR ((P_Port_Def *) (P_PCR_BASE + 0x00000040UL)) /* PB_XX Pad Control Register */
gustavatmel 1:9c5af431a1f1 641 #define PC_PCR ((P_Port_Def *) (P_PCR_BASE + 0x00000080UL)) /* PC_XX Pad Control Register */
gustavatmel 1:9c5af431a1f1 642 #define PD_PCR ((P_Port_D_Def *) (P_PCR_BASE + 0x000000C0UL)) /* PD_XX Pad Control Register */
gustavatmel 1:9c5af431a1f1 643
gustavatmel 1:9c5af431a1f1 644 #define I2C0 ((I2C_TypeDef *) I2C0_BASE)
gustavatmel 1:9c5af431a1f1 645 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
gustavatmel 1:9c5af431a1f1 646
gustavatmel 1:9c5af431a1f1 647
gustavatmel 1:9c5af431a1f1 648 #define TIMCLKEN0_0 *(uint32_t *)(W7500x_DUALTIMER0_BASE + 0x80ul)
gustavatmel 1:9c5af431a1f1 649 #define TIMCLKEN0_1 *(uint32_t *)(W7500x_DUALTIMER0_BASE + 0xA0ul)
gustavatmel 1:9c5af431a1f1 650 #define TIMCLKEN1_0 *(uint32_t *)(W7500x_DUALTIMER1_BASE + 0x80ul)
gustavatmel 1:9c5af431a1f1 651 #define TIMCLKEN1_1 *(uint32_t *)(W7500x_DUALTIMER1_BASE + 0xA0ul)
gustavatmel 1:9c5af431a1f1 652
gustavatmel 1:9c5af431a1f1 653 #define PWM ((PWM_TypeDef *) (W7500x_PWM_BASE + 0x800UL ))
gustavatmel 1:9c5af431a1f1 654 #define PWM_CH0 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE))
gustavatmel 1:9c5af431a1f1 655 #define PWM_CH1 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x100UL))
gustavatmel 1:9c5af431a1f1 656 #define PWM_CH2 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x200UL))
gustavatmel 1:9c5af431a1f1 657 #define PWM_CH3 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x300UL))
gustavatmel 1:9c5af431a1f1 658 #define PWM_CH4 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x400UL))
gustavatmel 1:9c5af431a1f1 659 #define PWM_CH5 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x500UL))
gustavatmel 1:9c5af431a1f1 660 #define PWM_CH6 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x600UL))
gustavatmel 1:9c5af431a1f1 661 #define PWM_CH7 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x700UL))
gustavatmel 1:9c5af431a1f1 662
gustavatmel 1:9c5af431a1f1 663 #define PWM_CH0_BASE (W7500x_PWM_BASE)
gustavatmel 1:9c5af431a1f1 664 #define PWM_CH1_BASE (W7500x_PWM_BASE + 0x100UL)
gustavatmel 1:9c5af431a1f1 665 #define PWM_CH2_BASE (W7500x_PWM_BASE + 0x200UL)
gustavatmel 1:9c5af431a1f1 666 #define PWM_CH3_BASE (W7500x_PWM_BASE + 0x300UL)
gustavatmel 1:9c5af431a1f1 667 #define PWM_CH4_BASE (W7500x_PWM_BASE + 0x400UL)
gustavatmel 1:9c5af431a1f1 668 #define PWM_CH5_BASE (W7500x_PWM_BASE + 0x500UL)
gustavatmel 1:9c5af431a1f1 669 #define PWM_CH6_BASE (W7500x_PWM_BASE + 0x600UL)
gustavatmel 1:9c5af431a1f1 670 #define PWM_CH7_BASE (W7500x_PWM_BASE + 0x700UL)
gustavatmel 1:9c5af431a1f1 671
gustavatmel 1:9c5af431a1f1 672 #define RNG ((RNG_TypeDef *) W7500x_RNG_BASE)
gustavatmel 1:9c5af431a1f1 673
gustavatmel 1:9c5af431a1f1 674 #define SSP0 ((SSP_TypeDef*) (SSP0_BASE))
gustavatmel 1:9c5af431a1f1 675 #define SSP1 ((SSP_TypeDef*) (SSP1_BASE))
gustavatmel 1:9c5af431a1f1 676
gustavatmel 1:9c5af431a1f1 677 #define WATCHDOG ((WATCHDOG_TypeDef *) W7500x_WATCHDOG_BASE)
gustavatmel 1:9c5af431a1f1 678
gustavatmel 1:9c5af431a1f1 679 /**
gustavatmel 1:9c5af431a1f1 680 * @}
gustavatmel 1:9c5af431a1f1 681 */
gustavatmel 1:9c5af431a1f1 682
gustavatmel 1:9c5af431a1f1 683
gustavatmel 1:9c5af431a1f1 684
gustavatmel 1:9c5af431a1f1 685 /******************************************************************************/
gustavatmel 1:9c5af431a1f1 686 /* */
gustavatmel 1:9c5af431a1f1 687 /* Clock Reset Generator */
gustavatmel 1:9c5af431a1f1 688 /* */
gustavatmel 1:9c5af431a1f1 689 /******************************************************************************/
gustavatmel 1:9c5af431a1f1 690 /**************** Bit definition for CRG_OSC_PDR **************************/
gustavatmel 1:9c5af431a1f1 691 #define CRG_OSC_PDR_NRMLOP (0x0ul) // Normal Operation
gustavatmel 1:9c5af431a1f1 692 #define CRG_OSC_PDR_PD (0x1ul) // Power Down
gustavatmel 1:9c5af431a1f1 693 /**************** Bit definition for CRG_PLL_PDR **************************/
gustavatmel 1:9c5af431a1f1 694 #define CRG_PLL_PDR_PD (0x0ul) // Power Down
gustavatmel 1:9c5af431a1f1 695 #define CRG_PLL_PDR_NRMLOP (0x1ul) // Normal Operation
gustavatmel 1:9c5af431a1f1 696 /**************** Bit definition for CRG_PLL_FCR **************************/
gustavatmel 1:9c5af431a1f1 697 //ToDo
gustavatmel 1:9c5af431a1f1 698 /**************** Bit definition for CRG_PLL_OER **************************/
gustavatmel 1:9c5af431a1f1 699 #define CRG_PLL_OER_DIS (0x0ul) // Clock out is disable
gustavatmel 1:9c5af431a1f1 700 #define CRG_PLL_OER_EN (0x1ul) // Clock out is enable
gustavatmel 1:9c5af431a1f1 701 /**************** Bit definition for CRG_PLL_BPR **************************/
gustavatmel 1:9c5af431a1f1 702 #define CRG_PLL_BPR_DIS (0x0ul) // Bypass disable. Normal operation
gustavatmel 1:9c5af431a1f1 703 #define CRG_PLL_BPR_EN (0x1ul) // Bypass enable. Clock will be set to external clock
gustavatmel 1:9c5af431a1f1 704 /**************** Bit definition for CRG_PLL_IFSR **************************/
gustavatmel 1:9c5af431a1f1 705 #define CRG_PLL_IFSR_RCLK (0x0ul) // Internal 8MHz RC oscillator clock(RCLK)
gustavatmel 1:9c5af431a1f1 706 #define CRG_PLL_IFSR_OCLK (0x1ul) // External oscillator clock (OCLK, 8MHz ~ 24MHz)
gustavatmel 1:9c5af431a1f1 707 /**************** Bit definition for CRG_FCLK_SSR **************************/
gustavatmel 1:9c5af431a1f1 708 #define CRG_FCLK_SSR_MCLK (0x01ul) // 00,01 Output clock of PLL(MCLK)
gustavatmel 1:9c5af431a1f1 709 #define CRG_FCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
gustavatmel 1:9c5af431a1f1 710 #define CRG_FCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
gustavatmel 1:9c5af431a1f1 711 /**************** Bit definition for CRG_FCLK_PVSR **************************/
gustavatmel 1:9c5af431a1f1 712 #define CRG_FCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
gustavatmel 1:9c5af431a1f1 713 #define CRG_FCLK_PVSR_DIV2 (0x01ul) // 1/2
gustavatmel 1:9c5af431a1f1 714 #define CRG_FCLK_PVSR_DIV4 (0x02ul) // 1/4
gustavatmel 1:9c5af431a1f1 715 #define CRG_FCLK_PVSR_DIV8 (0x03ul) // 1/8
gustavatmel 1:9c5af431a1f1 716 /**************** Bit definition for CRG_SSPCLK_SSR **************************/
gustavatmel 1:9c5af431a1f1 717 #define CRG_SSPCLK_SSR_DIS (0x00ul) // Disable clock
gustavatmel 1:9c5af431a1f1 718 #define CRG_SSPCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
gustavatmel 1:9c5af431a1f1 719 #define CRG_SSPCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
gustavatmel 1:9c5af431a1f1 720 #define CRG_SSPCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
gustavatmel 1:9c5af431a1f1 721 /**************** Bit definition for CRG_SSPCLK_PVSR **************************/
gustavatmel 1:9c5af431a1f1 722 #define CRG_SSPCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
gustavatmel 1:9c5af431a1f1 723 #define CRG_SSPCLK_PVSR_DIV2 (0x01ul) // 1/2
gustavatmel 1:9c5af431a1f1 724 #define CRG_SSPCLK_PVSR_DIV4 (0x02ul) // 1/4
gustavatmel 1:9c5af431a1f1 725 #define CRG_SSPCLK_PVSR_DIV8 (0x03ul) // 1/8
gustavatmel 1:9c5af431a1f1 726 /**************** Bit definition for CRG_ADCCLK_SSR **************************/
gustavatmel 1:9c5af431a1f1 727 #define CRG_ADCCLK_SSR_DIS (0x00ul) // Disable clock
gustavatmel 1:9c5af431a1f1 728 #define CRG_ADCCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
gustavatmel 1:9c5af431a1f1 729 #define CRG_ADCCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
gustavatmel 1:9c5af431a1f1 730 #define CRG_ADCCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
gustavatmel 1:9c5af431a1f1 731 /**************** Bit definition for CRG_ADCCLK_PVSR **************************/
gustavatmel 1:9c5af431a1f1 732 #define CRG_ADCCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
gustavatmel 1:9c5af431a1f1 733 #define CRG_ADCCLK_PVSR_DIV2 (0x01ul) // 1/2
gustavatmel 1:9c5af431a1f1 734 #define CRG_ADCCLK_PVSR_DIV4 (0x02ul) // 1/4
gustavatmel 1:9c5af431a1f1 735 #define CRG_ADCCLK_PVSR_DIV8 (0x03ul) // 1/8
gustavatmel 1:9c5af431a1f1 736 /**************** Bit definition for CRG_TIMER0/1CLK_SSR **************************/
gustavatmel 1:9c5af431a1f1 737 #define CRG_TIMERCLK_SSR_DIS (0x00ul) // Disable clock
gustavatmel 1:9c5af431a1f1 738 #define CRG_TIMERCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
gustavatmel 1:9c5af431a1f1 739 #define CRG_TIMERCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
gustavatmel 1:9c5af431a1f1 740 #define CRG_TIMERCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
gustavatmel 1:9c5af431a1f1 741 /**************** Bit definition for CRG_TIMER0/1CLK_PVSR **************************/
gustavatmel 1:9c5af431a1f1 742 #define CRG_TIMERCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
gustavatmel 1:9c5af431a1f1 743 #define CRG_TIMERCLK_PVSR_DIV2 (0x01ul) // 1/2
gustavatmel 1:9c5af431a1f1 744 #define CRG_TIMERCLK_PVSR_DIV4 (0x02ul) // 1/4
gustavatmel 1:9c5af431a1f1 745 #define CRG_TIMERCLK_PVSR_DIV8 (0x03ul) // 1/8
gustavatmel 1:9c5af431a1f1 746 #define CRG_TIMERCLK_PVSR_DIV16 (0x04ul) // 1/16
gustavatmel 1:9c5af431a1f1 747 #define CRG_TIMERCLK_PVSR_DIV32 (0x05ul) // 1/32
gustavatmel 1:9c5af431a1f1 748 #define CRG_TIMERCLK_PVSR_DIV64 (0x06ul) // 1/64
gustavatmel 1:9c5af431a1f1 749 #define CRG_TIMERCLK_PVSR_DIV128 (0x07ul) // 1/128
gustavatmel 1:9c5af431a1f1 750 /**************** Bit definition for CRG_PWMnCLK_SSR **************************/
gustavatmel 1:9c5af431a1f1 751 #define CRG_PWMCLK_SSR_DIS (0x00ul) // Disable clock
gustavatmel 1:9c5af431a1f1 752 #define CRG_PWMCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
gustavatmel 1:9c5af431a1f1 753 #define CRG_PWMCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
gustavatmel 1:9c5af431a1f1 754 #define CRG_PWMCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
gustavatmel 1:9c5af431a1f1 755 /**************** Bit definition for CRG_PWMnCLK_PVSR **************************/
gustavatmel 1:9c5af431a1f1 756 #define CRG_PWMCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
gustavatmel 1:9c5af431a1f1 757 #define CRG_PWMCLK_PVSR_DIV2 (0x01ul) // 1/2
gustavatmel 1:9c5af431a1f1 758 #define CRG_PWMCLK_PVSR_DIV4 (0x02ul) // 1/4
gustavatmel 1:9c5af431a1f1 759 #define CRG_PWMCLK_PVSR_DIV8 (0x03ul) // 1/8
gustavatmel 1:9c5af431a1f1 760 #define CRG_PWMCLK_PVSR_DIV16 (0x04ul) // 1/16
gustavatmel 1:9c5af431a1f1 761 #define CRG_PWMCLK_PVSR_DIV32 (0x05ul) // 1/32
gustavatmel 1:9c5af431a1f1 762 #define CRG_PWMCLK_PVSR_DIV64 (0x06ul) // 1/64
gustavatmel 1:9c5af431a1f1 763 #define CRG_PWMCLK_PVSR_DIV128 (0x07ul) // 1/128
gustavatmel 1:9c5af431a1f1 764 /**************** Bit definition for CRG_RTC_HS_SSR **************************/
gustavatmel 1:9c5af431a1f1 765 #define CRG_RTC_HS_SSR_DIS (0x00ul) // Disable clock
gustavatmel 1:9c5af431a1f1 766 #define CRG_RTC_HS_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
gustavatmel 1:9c5af431a1f1 767 #define CRG_RTC_HS_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
gustavatmel 1:9c5af431a1f1 768 #define CRG_RTC_HS_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
gustavatmel 1:9c5af431a1f1 769 /**************** Bit definition for CRG_RTC_HS_PVSR **************************/
gustavatmel 1:9c5af431a1f1 770 #define CRG_RTC_HS_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
gustavatmel 1:9c5af431a1f1 771 #define CRG_RTC_HS_PVSR_DIV2 (0x01ul) // 1/2
gustavatmel 1:9c5af431a1f1 772 #define CRG_RTC_HS_PVSR_DIV4 (0x02ul) // 1/4
gustavatmel 1:9c5af431a1f1 773 #define CRG_RTC_HS_PVSR_DIV8 (0x03ul) // 1/8
gustavatmel 1:9c5af431a1f1 774 #define CRG_RTC_HS_PVSR_DIV16 (0x04ul) // 1/16
gustavatmel 1:9c5af431a1f1 775 #define CRG_RTC_HS_PVSR_DIV32 (0x05ul) // 1/32
gustavatmel 1:9c5af431a1f1 776 #define CRG_RTC_HS_PVSR_DIV64 (0x06ul) // 1/64
gustavatmel 1:9c5af431a1f1 777 #define CRG_RTC_HS_PVSR_DIV128 (0x07ul) // 1/128
gustavatmel 1:9c5af431a1f1 778 /**************** Bit definition for CRG_RTC_SSR **************************/
gustavatmel 1:9c5af431a1f1 779 #define CRG_RTC_SSR_HS (0x00ul) // RTCCLK HS(High Speed clock)
gustavatmel 1:9c5af431a1f1 780 #define CRG_RTC_SSR_LW (0x01ul) // 32K_OSC_CLK(Low Speed external oscillator clock)
gustavatmel 1:9c5af431a1f1 781 /**************** Bit definition for CRG_WDOGCLK_HS_SSR **************************/
gustavatmel 1:9c5af431a1f1 782 #define CRG_WDOGCLK_HS_SSR_DIS (0x00ul) // Disable clock
gustavatmel 1:9c5af431a1f1 783 #define CRG_WDOGCLK_HS_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
gustavatmel 1:9c5af431a1f1 784 #define CRG_WDOGCLK_HS_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
gustavatmel 1:9c5af431a1f1 785 #define CRG_WDOGCLK_HS_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
gustavatmel 1:9c5af431a1f1 786 /**************** Bit definition for CRG_WDOGCLK_HS_PVSR **************************/
gustavatmel 1:9c5af431a1f1 787 #define CRG_WDOGCLK_HS_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
gustavatmel 1:9c5af431a1f1 788 #define CRG_WDOGCLK_HS_PVSR_DIV2 (0x01ul) // 1/2
gustavatmel 1:9c5af431a1f1 789 #define CRG_WDOGCLK_HS_PVSR_DIV4 (0x02ul) // 1/4
gustavatmel 1:9c5af431a1f1 790 #define CRG_WDOGCLK_HS_PVSR_DIV8 (0x03ul) // 1/8
gustavatmel 1:9c5af431a1f1 791 #define CRG_WDOGCLK_HS_PVSR_DIV16 (0x04ul) // 1/16
gustavatmel 1:9c5af431a1f1 792 #define CRG_WDOGCLK_HS_PVSR_DIV32 (0x05ul) // 1/32
gustavatmel 1:9c5af431a1f1 793 #define CRG_WDOGCLK_HS_PVSR_DIV64 (0x06ul) // 1/64
gustavatmel 1:9c5af431a1f1 794 #define CRG_WDOGCLK_HS_PVSR_DIV128 (0x07ul) // 1/128
gustavatmel 1:9c5af431a1f1 795 /**************** Bit definition for CRG_WDOGCLK_SSR **************************/
gustavatmel 1:9c5af431a1f1 796 #define CRG_WDOGCLK_SSR_HS (0x00ul) // RTCCLK HS(High Speed clock)
gustavatmel 1:9c5af431a1f1 797 #define CRG_WDOGCLK_SSR_LW (0x01ul) // 32K_OSC_CLK(Low Speed external oscillator clock)
gustavatmel 1:9c5af431a1f1 798 /**************** Bit definition for CRG_UARTCLK_SSR **************************/
gustavatmel 1:9c5af431a1f1 799 #define CRG_UARTCLK_SSR_DIS (0x00ul) // Disable clock
gustavatmel 1:9c5af431a1f1 800 #define CRG_UARTCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
gustavatmel 1:9c5af431a1f1 801 #define CRG_UARTCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
gustavatmel 1:9c5af431a1f1 802 #define CRG_UARTCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
gustavatmel 1:9c5af431a1f1 803 /**************** Bit definition for CRG_UARTCLK_PVSR **************************/
gustavatmel 1:9c5af431a1f1 804 #define CRG_UARTCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
gustavatmel 1:9c5af431a1f1 805 #define CRG_UARTCLK_PVSR_DIV2 (0x01ul) // 1/2
gustavatmel 1:9c5af431a1f1 806 #define CRG_UARTCLK_PVSR_DIV4 (0x02ul) // 1/4
gustavatmel 1:9c5af431a1f1 807 #define CRG_UARTCLK_PVSR_DIV8 (0x03ul) // 1/8
gustavatmel 1:9c5af431a1f1 808 /**************** Bit definition for CRG_MIICLK_ECR **************************/
gustavatmel 1:9c5af431a1f1 809 #define CRG_MIICLK_ECR_EN_RXCLK (0x01ul << 0) // Enable MII_RCK and MII_RCK_N
gustavatmel 1:9c5af431a1f1 810 #define CRG_MIICLK_ECR_EN_TXCLK (0x01ul << 1) // Enable MII_TCK and MII_TCK_N
gustavatmel 1:9c5af431a1f1 811 /**************** Bit definition for CRG_MONCLK_SSR **************************/
gustavatmel 1:9c5af431a1f1 812 #define CRG_MONCLK_SSR_MCLK (0x00ul) // PLL output clock (MCLK)
gustavatmel 1:9c5af431a1f1 813 #define CRG_MONCLK_SSR_FCLK (0x01ul) // FCLK
gustavatmel 1:9c5af431a1f1 814 #define CRG_MONCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
gustavatmel 1:9c5af431a1f1 815 #define CRG_MONCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
gustavatmel 1:9c5af431a1f1 816 #define CRG_MONCLK_SSR_ADCCLK (0x04ul) // ADCCLK
gustavatmel 1:9c5af431a1f1 817 #define CRG_MONCLK_SSR_SSPCLK (0x05ul) // SSPCLK
gustavatmel 1:9c5af431a1f1 818 #define CRG_MONCLK_SSR_TIMCLK0 (0x06ul) // TIMCLK0
gustavatmel 1:9c5af431a1f1 819 #define CRG_MONCLK_SSR_TIMCLK1 (0x07ul) // TIMCLK1
gustavatmel 1:9c5af431a1f1 820 #define CRG_MONCLK_SSR_PWMCLK0 (0x08ul) // PWMCLK0
gustavatmel 1:9c5af431a1f1 821 #define CRG_MONCLK_SSR_PWMCLK1 (0x09ul) // PWMCLK1
gustavatmel 1:9c5af431a1f1 822 #define CRG_MONCLK_SSR_PWMCLK2 (0x0Aul) // PWMCLK2
gustavatmel 1:9c5af431a1f1 823 #define CRG_MONCLK_SSR_PWMCLK3 (0x0Bul) // PWMCLK3
gustavatmel 1:9c5af431a1f1 824 #define CRG_MONCLK_SSR_PWMCLK4 (0x0Cul) // PWMCLK4
gustavatmel 1:9c5af431a1f1 825 #define CRG_MONCLK_SSR_PWMCLK5 (0x0Dul) // PWMCLK5
gustavatmel 1:9c5af431a1f1 826 #define CRG_MONCLK_SSR_PWMCLK6 (0x0Eul) // PWMCLK6
gustavatmel 1:9c5af431a1f1 827 #define CRG_MONCLK_SSR_PWMCLK7 (0x0Ful) // PWMCLK7
gustavatmel 1:9c5af431a1f1 828 #define CRG_MONCLK_SSR_UARTCLK (0x10ul) // UARTCLK
gustavatmel 1:9c5af431a1f1 829 #define CRG_MONCLK_SSR_MII_RXCLK (0x11ul) // MII_RXCLK
gustavatmel 1:9c5af431a1f1 830 #define CRG_MONCLK_SSR_MII_TXCLK (0x12ul) // MII_TXCLK
gustavatmel 1:9c5af431a1f1 831 #define CRG_MONCLK_SSR_RTCCLK (0x13ul) // RTCCLK
gustavatmel 1:9c5af431a1f1 832
gustavatmel 1:9c5af431a1f1 833 /******************************************************************************/
gustavatmel 1:9c5af431a1f1 834 /* */
gustavatmel 1:9c5af431a1f1 835 /* UART */
gustavatmel 1:9c5af431a1f1 836 /* */
gustavatmel 1:9c5af431a1f1 837 /******************************************************************************/
gustavatmel 1:9c5af431a1f1 838 /****************** Bit definition for UART Data(UARTDR) register *************************/
gustavatmel 1:9c5af431a1f1 839 #define UART_DR_OE (0x01ul << 11) // Overrun Error
gustavatmel 1:9c5af431a1f1 840 #define UART_DR_BE (0x01ul << 10) // Break Error
gustavatmel 1:9c5af431a1f1 841 #define UART_DR_PE (0x01ul << 9) // Parity Error
gustavatmel 1:9c5af431a1f1 842 #define UART_DR_FE (0x01ul << 8) // Framing Error
gustavatmel 1:9c5af431a1f1 843 //#define UART_DR_DR // ToDo
gustavatmel 1:9c5af431a1f1 844 /***************** Bit definition for UART Receive Status(UARTRSR) register ***************/
gustavatmel 1:9c5af431a1f1 845 #define UARTR_SR_OE (0x01ul << 3) // Overrun Error
gustavatmel 1:9c5af431a1f1 846 #define UARTR_SR_BE (0x01ul << 2) // Break Error
gustavatmel 1:9c5af431a1f1 847 #define UARTR_SR_PE (0x01ul << 1) // Parity Error
gustavatmel 1:9c5af431a1f1 848 #define UARTR_SR_FE (0x01ul << 0) // Framing Error
gustavatmel 1:9c5af431a1f1 849 /***************** Bit definition for UART Error Clear(UARTECR) register ******************/
gustavatmel 1:9c5af431a1f1 850 #define UARTE_CR_OE (0x01ul << 3) // Overrun Error
gustavatmel 1:9c5af431a1f1 851 #define UARTE_CR_BE (0x01ul << 2) // Break Error
gustavatmel 1:9c5af431a1f1 852 #define UARTE_CR_PE (0x01ul << 1) // Parity Error
gustavatmel 1:9c5af431a1f1 853 #define UARTE_CR_FE (0x01ul << 0) // Framing Error
gustavatmel 1:9c5af431a1f1 854 /****************** Bit definition for UART Flags(UARTFR) register ************************/
gustavatmel 1:9c5af431a1f1 855 #define UART_FR_RI (0x01ul << 8) // Ring indicator
gustavatmel 1:9c5af431a1f1 856 #define UART_FR_TXFE (0x01ul << 7) // Transmit FIFO empty
gustavatmel 1:9c5af431a1f1 857 #define UART_FR_RXFF (0x01ul << 6) // Receive FIFO full
gustavatmel 1:9c5af431a1f1 858 #define UART_FR_TXFF (0x01ul << 5) // Transmit FIFO full
gustavatmel 1:9c5af431a1f1 859 #define UART_FR_RXFE (0x01ul << 4) // Receive FIFO empty
gustavatmel 1:9c5af431a1f1 860 #define UART_FR_BUSY (0x01ul << 3) // UART busy
gustavatmel 1:9c5af431a1f1 861 #define UART_FR_DCD (0x01ul << 2) // Data carrier detect
gustavatmel 1:9c5af431a1f1 862 #define UART_FR_DSR (0x01ul << 1) // Data set ready
gustavatmel 1:9c5af431a1f1 863 #define UART_FR_CTS (0x01ul << 0) // Clear to send
gustavatmel 1:9c5af431a1f1 864 /********** Bit definition for UART Low-power Counter(UARTILPR) register *******************/
gustavatmel 1:9c5af431a1f1 865 #define UARTILPR_COUNTER (0xFFul << 0) // 8-bit low-power divisor value (0..255)
gustavatmel 1:9c5af431a1f1 866 /********************* Bit definition for Line Control(UARTLCR_H) register *****************/
gustavatmel 1:9c5af431a1f1 867 #define UART_LCR_H_SPS (0x1ul << 7) // Stick parity select
gustavatmel 1:9c5af431a1f1 868 #define UART_LCR_H_WLEN(n) ((n & 0x3ul) << 5) // Word length ( 0=5bits, 1=6bits, 2=7bits, 3=8bits )
gustavatmel 1:9c5af431a1f1 869 #define UART_LCR_H_FEN (0x1ul << 4) // Enable FIFOs
gustavatmel 1:9c5af431a1f1 870 #define UART_LCR_H_STP2 (0x1ul << 3) // Two stop bits select
gustavatmel 1:9c5af431a1f1 871 #define UART_LCR_H_EPS (0x1ul << 2) // Even parity select
gustavatmel 1:9c5af431a1f1 872 #define UART_LCR_H_PEN (0x1ul << 1) // Parity enable
gustavatmel 1:9c5af431a1f1 873 #define UART_LCR_H_BRK (0x1ul << 0) // Send break
gustavatmel 1:9c5af431a1f1 874 /********************* Bit definition for Contro(UARTCR) register *************************/
gustavatmel 1:9c5af431a1f1 875 #define UART_CR_CTSEn (0x1ul << 15) // CTS hardware flow control enable
gustavatmel 1:9c5af431a1f1 876 #define UART_CR_RTSEn (0x1ul << 14) // RTS hardware flow control enable
gustavatmel 1:9c5af431a1f1 877 #define UART_CR_Out2 (0x1ul << 13) // Complement of Out2 modem status output
gustavatmel 1:9c5af431a1f1 878 #define UART_CR_Out1 (0x1ul << 12) // Complement of Out1 modem status output
gustavatmel 1:9c5af431a1f1 879 #define UART_CR_RTS (0x1ul << 11) // Request to send
gustavatmel 1:9c5af431a1f1 880 #define UART_CR_DTR (0x1ul << 10) // Data transmit ready
gustavatmel 1:9c5af431a1f1 881 #define UART_CR_RXE (0x1ul << 9) // Receive enable
gustavatmel 1:9c5af431a1f1 882 #define UART_CR_TXE (0x1ul << 8) // Transmit enable
gustavatmel 1:9c5af431a1f1 883 #define UART_CR_LBE (0x1ul << 7) // Loop-back enable
gustavatmel 1:9c5af431a1f1 884 #define UART_CR_SIRLP (0x1ul << 2) // IrDA SIR low power mode
gustavatmel 1:9c5af431a1f1 885 #define UART_CR_SIREN (0x1ul << 1) // SIR enable
gustavatmel 1:9c5af431a1f1 886 #define UART_CR_UARTEN (0x1ul << 0) // UART enable
gustavatmel 1:9c5af431a1f1 887 /******* Bit definition for Interrupt FIFO Level Select(UARTIFLS) register *****************/
gustavatmel 1:9c5af431a1f1 888 #define UART_IFLS_RXIFLSEL(n) ((n & 0x7ul) << 3) // Receive interrupt FIFO level select(0=1/8 full, 1=1/4 full, 2=1/2 full, 3=3/4 full, 4=7/8 full)
gustavatmel 1:9c5af431a1f1 889 #define UART_IFLS_TXIFLSEL(n) ((n & 0x7ul) << 0) // Transmit interrupt FIFO level select(0=1/8 full, 1=1/4 full, 2=1/2 full, 3=3/4 full, 4=7/8 full)
gustavatmel 1:9c5af431a1f1 890 /******* Bit definition for Interrupt Mask Set/Clear(UARTIMSC) register ********************/
gustavatmel 1:9c5af431a1f1 891 #define UART_IMSC_OEIM (0x1ul << 10) // Overrun error interrupt mask
gustavatmel 1:9c5af431a1f1 892 #define UART_IMSC_BEIM (0x1ul << 9) // Break error interrupt mask
gustavatmel 1:9c5af431a1f1 893 #define UART_IMSC_PEIM (0x1ul << 8) // Parity error interrupt mask
gustavatmel 1:9c5af431a1f1 894 #define UART_IMSC_FEIM (0x1ul << 7) // Framing error interrupt mask
gustavatmel 1:9c5af431a1f1 895 #define UART_IMSC_RTIM (0x1ul << 6) // Receive interrupt mask
gustavatmel 1:9c5af431a1f1 896 #define UART_IMSC_TXIM (0x1ul << 5) // Transmit interrupt mask
gustavatmel 1:9c5af431a1f1 897 #define UART_IMSC_RXIM (0x1ul << 4) // Receive interrupt mask
gustavatmel 1:9c5af431a1f1 898 #define UART_IMSC_DSRMIM (0x1ul << 3) // nUARTDSR modem interrupt mask
gustavatmel 1:9c5af431a1f1 899 #define UART_IMSC_DCDMIM (0x1ul << 2) // nUARTDCD modem interrupt mask
gustavatmel 1:9c5af431a1f1 900 #define UART_IMSC_CTSMIM (0x1ul << 1) // nUARTCTS modem interrupt mask
gustavatmel 1:9c5af431a1f1 901 #define UART_IMSC_RIMIM (0x1ul << 0) // nUARTRI modem interrupt mask
gustavatmel 1:9c5af431a1f1 902 /*************** Bit definition for Raw Interrupt Status(UARTRIS) register *****************/
gustavatmel 1:9c5af431a1f1 903 #define UART_RIS_OEIM (0x1ul << 10) // Overrun error interrupt status
gustavatmel 1:9c5af431a1f1 904 #define UART_RIS_BEIM (0x1ul << 9) // Break error interrupt status
gustavatmel 1:9c5af431a1f1 905 #define UART_RIS_PEIM (0x1ul << 8) // Parity error interrupt status
gustavatmel 1:9c5af431a1f1 906 #define UART_RIS_FEIM (0x1ul << 7) // Framing error interrupt status
gustavatmel 1:9c5af431a1f1 907 #define UART_RIS_RTIM (0x1ul << 6) // Receive interrupt status
gustavatmel 1:9c5af431a1f1 908 #define UART_RIS_TXIM (0x1ul << 5) // Transmit interrupt status
gustavatmel 1:9c5af431a1f1 909 #define UART_RIS_RXIM (0x1ul << 4) // Receive interrupt status
gustavatmel 1:9c5af431a1f1 910 #define UART_RIS_DSRMIM (0x1ul << 3) // nUARTDSR modem interrupt status
gustavatmel 1:9c5af431a1f1 911 #define UART_RIS_DCDMIM (0x1ul << 2) // nUARTDCD modem interrupt status
gustavatmel 1:9c5af431a1f1 912 #define UART_RIS_CTSMIM (0x1ul << 1) // nUARTCTS modem interrupt status
gustavatmel 1:9c5af431a1f1 913 #define UART_RIS_RIMIM (0x1ul << 0) // nUARTRI modem interrupt status
gustavatmel 1:9c5af431a1f1 914 /************** Bit definition for Masked Interrupt Status(UARTMIS) register ****************/
gustavatmel 1:9c5af431a1f1 915 #define UART_MIS_OEIM (0x1ul << 10) // Overrun error masked interrupt status
gustavatmel 1:9c5af431a1f1 916 #define UART_MIS_BEIM (0x1ul << 9) // Break error masked interrupt status
gustavatmel 1:9c5af431a1f1 917 #define UART_MIS_PEIM (0x1ul << 8) // Parity error masked interrupt status
gustavatmel 1:9c5af431a1f1 918 #define UART_MIS_FEIM (0x1ul << 7) // Framing error masked interrupt status
gustavatmel 1:9c5af431a1f1 919 #define UART_MIS_RTIM (0x1ul << 6) // Receive masked interrupt status
gustavatmel 1:9c5af431a1f1 920 #define UART_MIS_TXIM (0x1ul << 5) // Transmit masked interrupt status
gustavatmel 1:9c5af431a1f1 921 #define UART_MIS_RXIM (0x1ul << 4) // Receive masked interrupt status
gustavatmel 1:9c5af431a1f1 922 #define UART_MIS_DSRMIM (0x1ul << 3) // nUARTDSR modem masked interrupt status
gustavatmel 1:9c5af431a1f1 923 #define UART_MIS_DCDMIM (0x1ul << 2) // nUARTDCD modem masked interrupt status
gustavatmel 1:9c5af431a1f1 924 #define UART_MIS_CTSMIM (0x1ul << 1) // nUARTCTS modem masked interrupt status
gustavatmel 1:9c5af431a1f1 925 #define UART_MIS_RIMIM (0x1ul << 0) // nUARTRI modem masked interrupt status
gustavatmel 1:9c5af431a1f1 926 /*************** Bit definition for Interrupt Clear(UARTICR) register ************************/
gustavatmel 1:9c5af431a1f1 927 #define UART_ICR_OEIM (0x1ul << 10) // Overrun error interrupt clear
gustavatmel 1:9c5af431a1f1 928 #define UART_ICR_BEIM (0x1ul << 9) // Break error interrupt clear
gustavatmel 1:9c5af431a1f1 929 #define UART_ICR_PEIM (0x1ul << 8) // Parity error interrupt clear
gustavatmel 1:9c5af431a1f1 930 #define UART_ICR_FEIM (0x1ul << 7) // Framing error interrupt clear
gustavatmel 1:9c5af431a1f1 931 #define UART_ICR_RTIM (0x1ul << 6) // Receive interrupt clear
gustavatmel 1:9c5af431a1f1 932 #define UART_ICR_TXIM (0x1ul << 5) // Transmit interrupt clear
gustavatmel 1:9c5af431a1f1 933 #define UART_ICR_RXIM (0x1ul << 4) // Receive interrupt clear
gustavatmel 1:9c5af431a1f1 934 #define UART_ICR_DSRMIM (0x1ul << 3) // nUARTDSR modem interrupt clear
gustavatmel 1:9c5af431a1f1 935 #define UART_ICR_DCDMIM (0x1ul << 2) // nUARTDCD modem interrupt clear
gustavatmel 1:9c5af431a1f1 936 #define UART_ICR_CTSMIM (0x1ul << 1) // nUARTCTS modem interrupt clear
gustavatmel 1:9c5af431a1f1 937 #define UART_ICR_RIMIM (0x1ul << 0) // nUARTRI modem interrupt clear
gustavatmel 1:9c5af431a1f1 938 /***************** Bit definition for DMA Control(UARTDMACR) register ************************/
gustavatmel 1:9c5af431a1f1 939 #define UART_DMACR_DMAONERR (0x1ul << 2) // DMA on error
gustavatmel 1:9c5af431a1f1 940 #define UART_DMACR_TXDMAE (0x1ul << 1) // Transmit DMA enable
gustavatmel 1:9c5af431a1f1 941 #define UART_DMACR_RXDMAE (0x1ul << 0) // Receive DMA enable
gustavatmel 1:9c5af431a1f1 942
gustavatmel 1:9c5af431a1f1 943 /******************************************************************************/
gustavatmel 1:9c5af431a1f1 944 /* */
gustavatmel 1:9c5af431a1f1 945 /* Simple UART */
gustavatmel 1:9c5af431a1f1 946 /* */
gustavatmel 1:9c5af431a1f1 947 /******************************************************************************/
gustavatmel 1:9c5af431a1f1 948 /***************** Bit definition for S_UART Data () register ************************/
gustavatmel 1:9c5af431a1f1 949 #define S_UART_DATA (0xFFul << 0)
gustavatmel 1:9c5af431a1f1 950 /***************** Bit definition for S_UART State() register ************************/
gustavatmel 1:9c5af431a1f1 951 #define S_UART_STATE_TX_BUF_OVERRUN (0x01ul << 2) // TX buffer overrun, wirte 1 to clear.
gustavatmel 1:9c5af431a1f1 952 #define S_UART_STATE_RX_BUF_FULL (0x01ul << 1) // RX buffer full, read only.
gustavatmel 1:9c5af431a1f1 953 #define S_UART_STATE_TX_BUF_FULL (0x01ul << 0) // TX buffer full, read only.
gustavatmel 1:9c5af431a1f1 954 /***************** Bit definition for S_UART Control() register ************************/
gustavatmel 1:9c5af431a1f1 955 #define S_UART_CTRL_HIGH_SPEED_TEST (0x01ul << 6) // High-speed test mode for TX only.
gustavatmel 1:9c5af431a1f1 956 #define S_UART_CTRL_RX_OVERRUN_EN (0x01ul << 5) // RX overrun interrupt enable.
gustavatmel 1:9c5af431a1f1 957 #define S_UART_CTRL_TX_OVERRUN_EN (0x01ul << 4) // TX overrun interrupt enable.
gustavatmel 1:9c5af431a1f1 958 #define S_UART_CTRL_RX_INT_EN (0x01ul << 3) // RX interrupt enable.
gustavatmel 1:9c5af431a1f1 959 #define S_UART_CTRL_TX_INT_EN (0x01ul << 2) // TX interrupt enable.
gustavatmel 1:9c5af431a1f1 960 #define S_UART_CTRL_RX_EN (0x01ul << 1) // RX enable.
gustavatmel 1:9c5af431a1f1 961 #define S_UART_CTRL_TX_EN (0x01ul << 0) // TX enable.
gustavatmel 1:9c5af431a1f1 962 /***************** Bit definition for S_UART Interrupt() register ************************/
gustavatmel 1:9c5af431a1f1 963 #define S_UART_INT_RX_OVERRUN (0x01ul << 3) // RX overrun interrupt. Wirte 1 to clear
gustavatmel 1:9c5af431a1f1 964 #define S_UART_INT_TX_OVERRUN (0x01ul << 2) // TX overrun interrupt. Write 1 to clear
gustavatmel 1:9c5af431a1f1 965 #define S_UART_INT_RX (0x01ul << 1) // RX interrupt. Write 1 to clear
gustavatmel 1:9c5af431a1f1 966 #define S_UART_INT_TX (0x01ul << 0) // TX interrupt. Write 1 to clear
gustavatmel 1:9c5af431a1f1 967
gustavatmel 1:9c5af431a1f1 968 /******************************************************************************/
gustavatmel 1:9c5af431a1f1 969 /* */
gustavatmel 1:9c5af431a1f1 970 /* Analog Digital Register */
gustavatmel 1:9c5af431a1f1 971 /* */
gustavatmel 1:9c5af431a1f1 972 /******************************************************************************/
gustavatmel 1:9c5af431a1f1 973
gustavatmel 1:9c5af431a1f1 974 /*********************** Bit definition for ADC_CTR ***********************/
gustavatmel 1:9c5af431a1f1 975 //#define ADC_CTR_SAMSEL_ABNORMAL (0x0ul) // Abnormal Operation
gustavatmel 1:9c5af431a1f1 976 //#define ADC_CTR_SAMSEL_NORMAL (0x1ul) // Normal Operation
gustavatmel 1:9c5af431a1f1 977 #define ADC_CTR_PWD_NRMOP (0x1ul) // Active Operation
gustavatmel 1:9c5af431a1f1 978 #define ADC_CTR_PWD_PD (0x3ul) // Power down
gustavatmel 1:9c5af431a1f1 979 /*********************** Bit definition for ADC_CHSEL ***********************/
gustavatmel 1:9c5af431a1f1 980 #define ADC_CHSEL_CH0 (0x0ul) // Channel 0
gustavatmel 1:9c5af431a1f1 981 #define ADC_CHSEL_CH1 (0x1ul) // Channel 1
gustavatmel 1:9c5af431a1f1 982 #define ADC_CHSEL_CH2 (0x2ul) // Channel 2
gustavatmel 1:9c5af431a1f1 983 #define ADC_CHSEL_CH3 (0x3ul) // Channel 3
gustavatmel 1:9c5af431a1f1 984 #define ADC_CHSEL_CH4 (0x4ul) // Channel 4
gustavatmel 1:9c5af431a1f1 985 #define ADC_CHSEL_CH5 (0x5ul) // Channel 5
gustavatmel 1:9c5af431a1f1 986 #define ADC_CHSEL_CH6 (0x6ul) // Channel 6
gustavatmel 1:9c5af431a1f1 987 #define ADC_CHSEL_CH7 (0x7ul) // Channel 7
gustavatmel 1:9c5af431a1f1 988 #define ADC_CHSEL_CH15 (0xful) // LDO output(1.5V)
gustavatmel 1:9c5af431a1f1 989 /*********************** Bit definition for ADC_START ***********************/
gustavatmel 1:9c5af431a1f1 990 #define ADC_START_START (0x1ul) // ADC conversion start
gustavatmel 1:9c5af431a1f1 991 /*********************** Bit definition for ADC_DATA ***********************/
gustavatmel 1:9c5af431a1f1 992 //ToDo (Readonly)
gustavatmel 1:9c5af431a1f1 993
gustavatmel 1:9c5af431a1f1 994 /*********************** Bit definition for ADC_INT ***********************/
gustavatmel 1:9c5af431a1f1 995 #define ADC_INT_MASK_DIS (0x0ul << 1) // Interrupt disable
gustavatmel 1:9c5af431a1f1 996 #define ADC_INT_MASK_ENA (0x1ul << 1) // Interrupt enable
gustavatmel 1:9c5af431a1f1 997 //ToDo (Readonly)
gustavatmel 1:9c5af431a1f1 998
gustavatmel 1:9c5af431a1f1 999 /*********************** Bit definition for ADC_INTCLR ***********************/
gustavatmel 1:9c5af431a1f1 1000 #define ADC_INTCLEAR (0x1ul) // ADC Interrupt clear
gustavatmel 1:9c5af431a1f1 1001
gustavatmel 1:9c5af431a1f1 1002 #define W7500x_ADC_BASE (W7500x_APB2_BASE + 0x00000000UL)
gustavatmel 1:9c5af431a1f1 1003 #define ADC ((ADC_TypeDef *) W7500x_ADC_BASE)
gustavatmel 1:9c5af431a1f1 1004
gustavatmel 1:9c5af431a1f1 1005 /******************************************************************************/
gustavatmel 1:9c5af431a1f1 1006 /* */
gustavatmel 1:9c5af431a1f1 1007 /* Dual Timer */
gustavatmel 1:9c5af431a1f1 1008 /* */
gustavatmel 1:9c5af431a1f1 1009 /******************************************************************************/
gustavatmel 1:9c5af431a1f1 1010
gustavatmel 1:9c5af431a1f1 1011 /*********************** Bit definition for dualtimer ***********************/
gustavatmel 1:9c5af431a1f1 1012 #define DUALTIMER_TimerControl_TimerDIsable 0x0ul
gustavatmel 1:9c5af431a1f1 1013 #define DUALTIMER_TimerControl_TimerEnable 0x1ul
gustavatmel 1:9c5af431a1f1 1014 #define DUALTIMER_TimerControl_TimerEnable_Pos 7
gustavatmel 1:9c5af431a1f1 1015
gustavatmel 1:9c5af431a1f1 1016 #define DUALTIMER_TimerControl_FreeRunning 0x0ul
gustavatmel 1:9c5af431a1f1 1017 #define DUALTIMER_TimerControl_Periodic 0x1ul
gustavatmel 1:9c5af431a1f1 1018 #define DUALTIMER_TimerControl_TimerMode_Pos 6
gustavatmel 1:9c5af431a1f1 1019
gustavatmel 1:9c5af431a1f1 1020 #define DUALTIMER_TimerControl_IntDisable 0x0ul
gustavatmel 1:9c5af431a1f1 1021 #define DUALTIMER_TimerControl_IntEnable 0x1ul
gustavatmel 1:9c5af431a1f1 1022 #define DUALTIMER_TimerControl_IntEnable_Pos 5
gustavatmel 1:9c5af431a1f1 1023
gustavatmel 1:9c5af431a1f1 1024 #define DUALTIMER_TimerControl_Pre_1 0x0ul
gustavatmel 1:9c5af431a1f1 1025 #define DUALTIMER_TimerControl_Pre_16 0x1ul
gustavatmel 1:9c5af431a1f1 1026 #define DUALTIMER_TimerControl_Pre_256 0x2ul
gustavatmel 1:9c5af431a1f1 1027 #define DUALTIMER_TimerControl_Pre_Pos 2
gustavatmel 1:9c5af431a1f1 1028
gustavatmel 1:9c5af431a1f1 1029 #define DUALTIMER_TimerControl_Size_16 0x0ul
gustavatmel 1:9c5af431a1f1 1030 #define DUALTIMER_TimerControl_Size_32 0x1ul
gustavatmel 1:9c5af431a1f1 1031 #define DUALTIMER_TimerControl_Size_Pos 1
gustavatmel 1:9c5af431a1f1 1032
gustavatmel 1:9c5af431a1f1 1033 #define DUALTIMER_TimerControl_Wrapping 0x0ul
gustavatmel 1:9c5af431a1f1 1034 #define DUALTIMER_TimerControl_OneShot 0x1ul
gustavatmel 1:9c5af431a1f1 1035 #define DUALTIMER_TimerControl_OneShot_Pos 0
gustavatmel 1:9c5af431a1f1 1036
gustavatmel 1:9c5af431a1f1 1037 /******************************************************************************/
gustavatmel 1:9c5af431a1f1 1038 /* */
gustavatmel 1:9c5af431a1f1 1039 /* External Interrupt */
gustavatmel 1:9c5af431a1f1 1040 /* */
gustavatmel 1:9c5af431a1f1 1041 /******************************************************************************/
gustavatmel 1:9c5af431a1f1 1042
gustavatmel 1:9c5af431a1f1 1043 /**************** Bit definition for Px_IER **************************/
gustavatmel 1:9c5af431a1f1 1044 #define EXTI_Px_INTPOR_RISING_EDGE (0x00ul << 0)
gustavatmel 1:9c5af431a1f1 1045 #define EXTI_Px_INTPOR_FALLING_EDGE (0x01ul << 0)
gustavatmel 1:9c5af431a1f1 1046 #define EXTI_Px_INTEN_DISABLE (0x00ul << 1)
gustavatmel 1:9c5af431a1f1 1047 #define EXTI_Px_INTEN_ENABLE (0x01ul << 1)
gustavatmel 1:9c5af431a1f1 1048
gustavatmel 1:9c5af431a1f1 1049 /******************************************************************************/
gustavatmel 1:9c5af431a1f1 1050 /* */
gustavatmel 1:9c5af431a1f1 1051 /* GPIO */
gustavatmel 1:9c5af431a1f1 1052 /* */
gustavatmel 1:9c5af431a1f1 1053 /******************************************************************************/
gustavatmel 1:9c5af431a1f1 1054
gustavatmel 1:9c5af431a1f1 1055 /**************** Bit definition for Px_AFSR **************************/
gustavatmel 1:9c5af431a1f1 1056 #define Px_AFSR_AF0 (0x00ul)
gustavatmel 1:9c5af431a1f1 1057 #define Px_AFSR_AF1 (0x01ul)
gustavatmel 1:9c5af431a1f1 1058 #define Px_AFSR_AF2 (0x02ul)
gustavatmel 1:9c5af431a1f1 1059 #define Px_AFSR_AF3 (0x03ul)
gustavatmel 1:9c5af431a1f1 1060 /**************** Bit definition for Px_PCR **************************/
gustavatmel 1:9c5af431a1f1 1061 #define Px_PCR_PUPD_DOWN (0x01ul << 0) // Pull Down
gustavatmel 1:9c5af431a1f1 1062 #define Px_PCR_PUPD_UP (0x01ul << 1) // Pull Up
gustavatmel 1:9c5af431a1f1 1063 #define Px_PCR_DS_HIGH (0x01ul << 2) // High Driving
gustavatmel 1:9c5af431a1f1 1064 #define Px_PCR_OD (0x01ul << 3) // Open Drain
gustavatmel 1:9c5af431a1f1 1065 #define Px_PCR_IE (0x01ul << 5) // Input Buffer Enable
gustavatmel 1:9c5af431a1f1 1066 #define Px_PCR_CS_SUMMIT (0x01ul << 6) // Use Summit Trigger Input Buffer
gustavatmel 1:9c5af431a1f1 1067
gustavatmel 1:9c5af431a1f1 1068 /******************************************************************************/
gustavatmel 1:9c5af431a1f1 1069 /* */
gustavatmel 1:9c5af431a1f1 1070 /* I2C */
gustavatmel 1:9c5af431a1f1 1071 /* */
gustavatmel 1:9c5af431a1f1 1072 /******************************************************************************/
gustavatmel 1:9c5af431a1f1 1073
gustavatmel 1:9c5af431a1f1 1074 /**************** Bit definition for I2C_CTR **************************/
gustavatmel 1:9c5af431a1f1 1075 #define I2C_CTR_COREEN (0x01ul << 7 ) // 0x80
gustavatmel 1:9c5af431a1f1 1076 #define I2C_CTR_INTEREN (0x01ul << 6 ) // 0x40
gustavatmel 1:9c5af431a1f1 1077 #define I2C_CTR_MODE (0x01ul << 5 ) // 0x20
gustavatmel 1:9c5af431a1f1 1078 #define I2C_CTR_ADDR10 (0x01ul << 4 ) // 0x10
gustavatmel 1:9c5af431a1f1 1079 #define I2C_CTR_CTRRWN (0x01ul << 3 ) // 0x08
gustavatmel 1:9c5af431a1f1 1080 #define I2C_CTR_CTEN (0x01ul << 2 ) // 0x04
gustavatmel 1:9c5af431a1f1 1081
gustavatmel 1:9c5af431a1f1 1082 /**************** Bit definition for I2C_CMDR **************************/
gustavatmel 1:9c5af431a1f1 1083 #define I2C_CMDR_STA (0x01ul << 7 ) // 0x80
gustavatmel 1:9c5af431a1f1 1084 #define I2C_CMDR_STO (0x01ul << 6 ) // 0x40
gustavatmel 1:9c5af431a1f1 1085 #define I2C_CMDR_ACK (0x01ul << 5 ) // 0x20
gustavatmel 1:9c5af431a1f1 1086 #define I2C_CMDR_RESTA (0x01ul << 4 ) // 0x10
gustavatmel 1:9c5af431a1f1 1087
gustavatmel 1:9c5af431a1f1 1088 /**************** Bit definition for I2C_ISCR **************************/
gustavatmel 1:9c5af431a1f1 1089 #define I2C_ISCR_RST (0x01ul << 1) // 0x01
gustavatmel 1:9c5af431a1f1 1090
gustavatmel 1:9c5af431a1f1 1091 /**************** Bit definition for I2C_SR **************************/
gustavatmel 1:9c5af431a1f1 1092 #define I2C_SR_TX (0x01ul << 9 ) // 0x200
gustavatmel 1:9c5af431a1f1 1093 #define I2C_SR_RX (0x01ul << 8 ) // 0x100
gustavatmel 1:9c5af431a1f1 1094 #define I2C_SR_ACKT (0x01ul << 7 ) // 0x080
gustavatmel 1:9c5af431a1f1 1095 #define I2C_SR_BT (0x01ul << 6 ) // 0x040
gustavatmel 1:9c5af431a1f1 1096 #define I2C_SR_SA (0x01ul << 5 ) // 0x020
gustavatmel 1:9c5af431a1f1 1097 #define I2C_SR_SB (0x01ul << 4 ) // 0x010
gustavatmel 1:9c5af431a1f1 1098 #define I2C_SR_AL (0x01ul << 3 ) // 0x008
gustavatmel 1:9c5af431a1f1 1099 #define I2C_SR_TO (0x01ul << 2 ) // 0x004
gustavatmel 1:9c5af431a1f1 1100 #define I2C_SR_SRW (0x01ul << 1 ) // 0x002
gustavatmel 1:9c5af431a1f1 1101 #define I2C_SR_ACKR (0x01ul << 0 ) // 0x001
gustavatmel 1:9c5af431a1f1 1102
gustavatmel 1:9c5af431a1f1 1103 /**************** Bit definition for I2C_ISR **************************/
gustavatmel 1:9c5af431a1f1 1104 #define I2C_ISR_STAE (0x01ul << 4 ) // 0x010
gustavatmel 1:9c5af431a1f1 1105 #define I2C_ISR_STOE (0x01ul << 3 ) // 0x008
gustavatmel 1:9c5af431a1f1 1106 #define I2C_ISR_TOE (0x01ul << 2 ) // 0x004
gustavatmel 1:9c5af431a1f1 1107 #define I2C_ISR_ACK_RXE (0x01ul << 1 ) // 0x002
gustavatmel 1:9c5af431a1f1 1108 #define I2C_ISR_ACK_TXE (0x01ul << 0 ) // 0x001
gustavatmel 1:9c5af431a1f1 1109
gustavatmel 1:9c5af431a1f1 1110 /**************** Bit definition for I2C_ISMR **************************/
gustavatmel 1:9c5af431a1f1 1111 #define I2C_ISR_STAEM (0x01ul << 4 ) // 0x010
gustavatmel 1:9c5af431a1f1 1112 #define I2C_ISR_STOEM (0x01ul << 3 ) // 0x008
gustavatmel 1:9c5af431a1f1 1113 #define I2C_ISR_TOEM (0x01ul << 2 ) // 0x004
gustavatmel 1:9c5af431a1f1 1114 #define I2C_ISR_ACK_RXEM (0x01ul << 1 ) // 0x002
gustavatmel 1:9c5af431a1f1 1115 #define I2C_ISR_ACK_TXEM (0x01ul << 0 ) // 0x001
gustavatmel 1:9c5af431a1f1 1116
gustavatmel 1:9c5af431a1f1 1117 /******************************************************************************/
gustavatmel 1:9c5af431a1f1 1118 /* */
gustavatmel 1:9c5af431a1f1 1119 /* PWM */
gustavatmel 1:9c5af431a1f1 1120 /* */
gustavatmel 1:9c5af431a1f1 1121 /******************************************************************************/
gustavatmel 1:9c5af431a1f1 1122
gustavatmel 1:9c5af431a1f1 1123 /******************************************************************************/
gustavatmel 1:9c5af431a1f1 1124 /* */
gustavatmel 1:9c5af431a1f1 1125 /* Random number generator Register */
gustavatmel 1:9c5af431a1f1 1126 /* */
gustavatmel 1:9c5af431a1f1 1127 /******************************************************************************/
gustavatmel 1:9c5af431a1f1 1128
gustavatmel 1:9c5af431a1f1 1129 /*********************** Bit definition for RNG_RUN ***********************/
gustavatmel 1:9c5af431a1f1 1130 #define RNG_RUN_STOP (0x0ul) // STOP RNG shift register
gustavatmel 1:9c5af431a1f1 1131 #define RNG_RUN_RUN (0x1ul) // RUN RNG shift register
gustavatmel 1:9c5af431a1f1 1132 /*********************** Bit definition for RNG_SEED ***********************/
gustavatmel 1:9c5af431a1f1 1133 //ToDo
gustavatmel 1:9c5af431a1f1 1134
gustavatmel 1:9c5af431a1f1 1135 /*********************** Bit definition for RNG_CLKSEL ***********************/
gustavatmel 1:9c5af431a1f1 1136 #define RNG_CLKSEL_RNGCLK (0x0ul) // RNGCLK is source clock for rng shift register
gustavatmel 1:9c5af431a1f1 1137 #define RNG_CLKSEL_APBCLK (0x1ul) // APBCLK is source clock for rng shift register
gustavatmel 1:9c5af431a1f1 1138 /*********************** Bit definition for RNG_ENABLE ***********************/
gustavatmel 1:9c5af431a1f1 1139 #define RNG_MANUAL_DISABLE (0x0ul) // RNG disble
gustavatmel 1:9c5af431a1f1 1140 #define RNG_MANUAL_ENABLE (0x1ul) // RNG enable
gustavatmel 1:9c5af431a1f1 1141 /*********************** Bit definition for RNG_RN ***********************/
gustavatmel 1:9c5af431a1f1 1142 //ToDo
gustavatmel 1:9c5af431a1f1 1143
gustavatmel 1:9c5af431a1f1 1144 /*********************** Bit definition for RNG_POLY ***********************/
gustavatmel 1:9c5af431a1f1 1145 //ToDo
gustavatmel 1:9c5af431a1f1 1146
gustavatmel 1:9c5af431a1f1 1147
gustavatmel 1:9c5af431a1f1 1148
gustavatmel 1:9c5af431a1f1 1149 typedef enum
gustavatmel 1:9c5af431a1f1 1150 {
gustavatmel 1:9c5af431a1f1 1151 PAD_PA = 0,
gustavatmel 1:9c5af431a1f1 1152 PAD_PB,
gustavatmel 1:9c5af431a1f1 1153 PAD_PC,
gustavatmel 1:9c5af431a1f1 1154 PAD_PD
gustavatmel 1:9c5af431a1f1 1155 }PAD_Type;
gustavatmel 1:9c5af431a1f1 1156
gustavatmel 1:9c5af431a1f1 1157 typedef enum
gustavatmel 1:9c5af431a1f1 1158 {
gustavatmel 1:9c5af431a1f1 1159 PAD_AF0 = Px_AFSR_AF0,
gustavatmel 1:9c5af431a1f1 1160 PAD_AF1 = Px_AFSR_AF1,
gustavatmel 1:9c5af431a1f1 1161 PAD_AF2 = Px_AFSR_AF2,
gustavatmel 1:9c5af431a1f1 1162 PAD_AF3 = Px_AFSR_AF3
gustavatmel 1:9c5af431a1f1 1163 }PAD_AF_TypeDef;
gustavatmel 1:9c5af431a1f1 1164
gustavatmel 1:9c5af431a1f1 1165
gustavatmel 1:9c5af431a1f1 1166 #if !defined (USE_HAL_DRIVER)
gustavatmel 1:9c5af431a1f1 1167 #define USE_HAL_DRIVER
gustavatmel 1:9c5af431a1f1 1168 #endif /* USE_HAL_DRIVER */
gustavatmel 1:9c5af431a1f1 1169
gustavatmel 1:9c5af431a1f1 1170
gustavatmel 1:9c5af431a1f1 1171
gustavatmel 1:9c5af431a1f1 1172 #if defined (USE_HAL_DRIVER)
gustavatmel 1:9c5af431a1f1 1173 // #include "system_W7500x.h"
gustavatmel 1:9c5af431a1f1 1174 // #include "W7500x_conf.h"
gustavatmel 1:9c5af431a1f1 1175 #endif
gustavatmel 1:9c5af431a1f1 1176
gustavatmel 1:9c5af431a1f1 1177 #ifdef USE_FULL_ASSERT
gustavatmel 1:9c5af431a1f1 1178 #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__,__LINE__))
gustavatmel 1:9c5af431a1f1 1179 #else
gustavatmel 1:9c5af431a1f1 1180 #define assert_param(expr) ((void)0)
gustavatmel 1:9c5af431a1f1 1181 #endif /* USE_FULL_ASSERT */
gustavatmel 1:9c5af431a1f1 1182
gustavatmel 1:9c5af431a1f1 1183 #ifdef __cplusplus
gustavatmel 1:9c5af431a1f1 1184 }
gustavatmel 1:9c5af431a1f1 1185 #endif
gustavatmel 1:9c5af431a1f1 1186
gustavatmel 1:9c5af431a1f1 1187 #endif /* W7500x_H */
gustavatmel 1:9c5af431a1f1 1188
gustavatmel 1:9c5af431a1f1 1189
gustavatmel 1:9c5af431a1f1 1190
gustavatmel 1:9c5af431a1f1 1191 /************************ (C) COPYRIGHT Wiznet *****END OF FILE****/