BA / SerialCom

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

Fork of OmniWheels by Gustav Atmel

mbed-os/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_clk.h@2:798925c9e4a8, 2018-05-01 (annotated)

Committer:
gustavatmel
Date:
Tue May 01 15:55:34 2018 +0000
Revision:
2:798925c9e4a8
Parent:
1:9c5af431a1f1 
bluetooth

Who changed what in which revision?

UserRevisionLine numberNew contents of line
gustavatmel 1:9c5af431a1f1 1 /**************************************************************************//**
gustavatmel 1:9c5af431a1f1 2 * @file CLK.h
gustavatmel 1:9c5af431a1f1 3 * @version V1.0
gustavatmel 1:9c5af431a1f1 4 * @brief M480 Series CLK Driver Header File
gustavatmel 1:9c5af431a1f1 5 *
gustavatmel 1:9c5af431a1f1 6 * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
gustavatmel 1:9c5af431a1f1 7 ******************************************************************************/
gustavatmel 1:9c5af431a1f1 8 #ifndef __CLK_H__
gustavatmel 1:9c5af431a1f1 9 #define __CLK_H__
gustavatmel 1:9c5af431a1f1 10
gustavatmel 1:9c5af431a1f1 11 #ifdef __cplusplus
gustavatmel 1:9c5af431a1f1 12 extern "C"
gustavatmel 1:9c5af431a1f1 13 {
gustavatmel 1:9c5af431a1f1 14 #endif
gustavatmel 1:9c5af431a1f1 15
gustavatmel 1:9c5af431a1f1 16
gustavatmel 1:9c5af431a1f1 17 /** @addtogroup M480_Device_Driver M480 Device Driver
gustavatmel 1:9c5af431a1f1 18 @{
gustavatmel 1:9c5af431a1f1 19 */
gustavatmel 1:9c5af431a1f1 20
gustavatmel 1:9c5af431a1f1 21 /** @addtogroup M480_CLK_Driver CLK Driver
gustavatmel 1:9c5af431a1f1 22 @{
gustavatmel 1:9c5af431a1f1 23 */
gustavatmel 1:9c5af431a1f1 24
gustavatmel 1:9c5af431a1f1 25 /** @addtogroup M480_CLK_EXPORTED_CONSTANTS CLK Exported Constants
gustavatmel 1:9c5af431a1f1 26 @{
gustavatmel 1:9c5af431a1f1 27 */
gustavatmel 1:9c5af431a1f1 28
gustavatmel 1:9c5af431a1f1 29
gustavatmel 1:9c5af431a1f1 30 #define FREQ_25MHZ 25000000UL /*!< 25 MHz \hideinitializer */
gustavatmel 1:9c5af431a1f1 31 #define FREQ_50MHZ 50000000UL /*!< 50 MHz \hideinitializer */
gustavatmel 1:9c5af431a1f1 32 #define FREQ_72MHZ 72000000UL /*!< 72 MHz \hideinitializer */
gustavatmel 1:9c5af431a1f1 33 #define FREQ_80MHZ 80000000UL /*!< 80 MHz \hideinitializer */
gustavatmel 1:9c5af431a1f1 34 #define FREQ_100MHZ 100000000UL /*!< 100 MHz \hideinitializer */
gustavatmel 1:9c5af431a1f1 35 #define FREQ_125MHZ 125000000UL /*!< 125 MHz \hideinitializer */
gustavatmel 1:9c5af431a1f1 36 #define FREQ_160MHZ 160000000UL /*!< 160 MHz \hideinitializer */
gustavatmel 1:9c5af431a1f1 37 #define FREQ_192MHZ 192000000UL /*!< 192 MHz \hideinitializer */
gustavatmel 1:9c5af431a1f1 38 #define FREQ_200MHZ 200000000UL /*!< 200 MHz \hideinitializer */
gustavatmel 1:9c5af431a1f1 39 #define FREQ_250MHZ 250000000UL /*!< 250 MHz \hideinitializer */
gustavatmel 1:9c5af431a1f1 40 #define FREQ_500MHZ 500000000UL /*!< 500 MHz \hideinitializer */
gustavatmel 1:9c5af431a1f1 41
gustavatmel 1:9c5af431a1f1 42 /*---------------------------------------------------------------------------------------------------------*/
gustavatmel 1:9c5af431a1f1 43 /* CLKSEL0 constant definitions. (Write-protection) */
gustavatmel 1:9c5af431a1f1 44 /*---------------------------------------------------------------------------------------------------------*/
gustavatmel 1:9c5af431a1f1 45 #define CLK_CLKSEL0_HCLKSEL_HXT (0x0UL << CLK_CLKSEL0_HCLKSEL_Pos) /*!< Select HCLK clock source from high speed crystal \hideinitializer */
gustavatmel 1:9c5af431a1f1 46 #define CLK_CLKSEL0_HCLKSEL_LXT (0x1UL << CLK_CLKSEL0_HCLKSEL_Pos) /*!< Select HCLK clock source from low speed crystal \hideinitializer */
gustavatmel 1:9c5af431a1f1 47 #define CLK_CLKSEL0_HCLKSEL_PLL (0x2UL << CLK_CLKSEL0_HCLKSEL_Pos) /*!< Select HCLK clock source from PLL \hideinitializer */
gustavatmel 1:9c5af431a1f1 48 #define CLK_CLKSEL0_HCLKSEL_LIRC (0x3UL << CLK_CLKSEL0_HCLKSEL_Pos) /*!< Select HCLK clock source from low speed oscillator \hideinitializer */
gustavatmel 1:9c5af431a1f1 49 #define CLK_CLKSEL0_HCLKSEL_HIRC (0x7UL << CLK_CLKSEL0_HCLKSEL_Pos) /*!< Select HCLK clock source from high speed oscillator \hideinitializer */
gustavatmel 1:9c5af431a1f1 50
gustavatmel 1:9c5af431a1f1 51 #define CLK_CLKSEL0_STCLKSEL_HXT (0x0UL << CLK_CLKSEL0_STCLKSEL_Pos) /*!< Select SysTick clock source from high speed crystal \hideinitializer */
gustavatmel 1:9c5af431a1f1 52 #define CLK_CLKSEL0_STCLKSEL_LXT (0x1UL << CLK_CLKSEL0_STCLKSEL_Pos) /*!< Select SysTick clock source from low speed crystal \hideinitializer */
gustavatmel 1:9c5af431a1f1 53 #define CLK_CLKSEL0_STCLKSEL_HXT_DIV2 (0x2UL << CLK_CLKSEL0_STCLKSEL_Pos) /*!< Select SysTick clock source from HXT/2 \hideinitializer */
gustavatmel 1:9c5af431a1f1 54 #define CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 (0x3UL << CLK_CLKSEL0_STCLKSEL_Pos) /*!< Select SysTick clock source from HCLK/2 \hideinitializer */
gustavatmel 1:9c5af431a1f1 55 #define CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 (0x7UL << CLK_CLKSEL0_STCLKSEL_Pos) /*!< Select SysTick clock source from HIRC/2 \hideinitializer */
gustavatmel 1:9c5af431a1f1 56 #define CLK_CLKSEL0_STCLKSEL_HCLK (0x01UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< Select SysTick clock source from HCLK \hideinitializer */
gustavatmel 1:9c5af431a1f1 57
gustavatmel 1:9c5af431a1f1 58 #if(0)
gustavatmel 1:9c5af431a1f1 59 #define CLK_CLKSEL0_PCLK0DIV1 (0x0UL << CLK_CLKSEL0_PCLK0SEL_Pos) /*!< Select PCLK0 clock source from HCLK \hideinitializer */
gustavatmel 1:9c5af431a1f1 60 #define CLK_CLKSEL0_PCLK0DIV2 (0x1UL << CLK_CLKSEL0_PCLK0SEL_Pos) /*!< Select PCLK0 clock source from 1/2 HCLK \hideinitializer */
gustavatmel 1:9c5af431a1f1 61
gustavatmel 1:9c5af431a1f1 62 #define CLK_CLKSEL0_PCLK1DIV1 (0x0UL << CLK_CLKSEL0_PCLK1SEL_Pos) /*!< Select PCLK1 clock source from HCLK \hideinitializer */
gustavatmel 1:9c5af431a1f1 63 #define CLK_CLKSEL0_PCLK1DIV2 (0x1UL << CLK_CLKSEL0_PCLK1SEL_Pos) /*!< Select PCLK1 clock source from 1/2 HCLK \hideinitializer */
gustavatmel 1:9c5af431a1f1 64 #endif
gustavatmel 1:9c5af431a1f1 65
gustavatmel 1:9c5af431a1f1 66 #define CLK_CLKSEL0_SDH0SEL_HXT (0x0UL << CLK_CLKSEL0_SDH0SEL_Pos) /*!< Select SDH0 clock source from high speed crystal \hideinitializer */
gustavatmel 1:9c5af431a1f1 67 #define CLK_CLKSEL0_SDH0SEL_PLL (0x1UL << CLK_CLKSEL0_SDH0SEL_Pos) /*!< Select SDH0 clock source from PLL \hideinitializer */
gustavatmel 1:9c5af431a1f1 68 #define CLK_CLKSEL0_SDH0SEL_HIRC (0x3UL << CLK_CLKSEL0_SDH0SEL_Pos) /*!< Select SDH0 clock source from high speed oscillator \hideinitializer */
gustavatmel 1:9c5af431a1f1 69 #define CLK_CLKSEL0_SDH0SEL_HCLK (0x2UL << CLK_CLKSEL0_SDH0SEL_Pos) /*!< Select SDH0 clock source from HCLK \hideinitializer */
gustavatmel 1:9c5af431a1f1 70
gustavatmel 1:9c5af431a1f1 71 #define CLK_CLKSEL0_SDH1SEL_HXT (0x0UL << CLK_CLKSEL0_SDH1SEL_Pos) /*!< Select SDH1 clock source from high speed crystal \hideinitializer */
gustavatmel 1:9c5af431a1f1 72 #define CLK_CLKSEL0_SDH1SEL_PLL (0x1UL << CLK_CLKSEL0_SDH1SEL_Pos) /*!< Select SDH1 clock source from PLL \hideinitializer */
gustavatmel 1:9c5af431a1f1 73 #define CLK_CLKSEL0_SDH1SEL_HIRC (0x3UL << CLK_CLKSEL0_SDH1SEL_Pos) /*!< Select SDH1 clock source from high speed oscillator \hideinitializer */
gustavatmel 1:9c5af431a1f1 74 #define CLK_CLKSEL0_SDH1SEL_HCLK (0x2UL << CLK_CLKSEL0_SDH1SEL_Pos) /*!< Select SDH1 clock source from HCLK \hideinitializer */
gustavatmel 1:9c5af431a1f1 75
gustavatmel 1:9c5af431a1f1 76
gustavatmel 1:9c5af431a1f1 77 /*---------------------------------------------------------------------------------------------------------*/
gustavatmel 1:9c5af431a1f1 78 /* CLKSEL1 constant definitions. */
gustavatmel 1:9c5af431a1f1 79 /*---------------------------------------------------------------------------------------------------------*/
gustavatmel 1:9c5af431a1f1 80 #define CLK_CLKSEL1_WDTSEL_LXT (0x1UL << CLK_CLKSEL1_WDTSEL_Pos) /*!< Select WDT clock source from low speed crystal \hideinitializer */
gustavatmel 1:9c5af431a1f1 81 #define CLK_CLKSEL1_WDTSEL_LIRC (0x3UL << CLK_CLKSEL1_WDTSEL_Pos) /*!< Select WDT clock source from low speed oscillator \hideinitializer */
gustavatmel 1:9c5af431a1f1 82 #define CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 (0x2UL << CLK_CLKSEL1_WDTSEL_Pos) /*!< Select WDT clock source from HCLK/2048 \hideinitializer */
gustavatmel 1:9c5af431a1f1 83
gustavatmel 1:9c5af431a1f1 84 #define CLK_CLKSEL1_TMR0SEL_HXT (0x0UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from high speed crystal \hideinitializer */
gustavatmel 1:9c5af431a1f1 85 #define CLK_CLKSEL1_TMR0SEL_LXT (0x1UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from low speed crystal \hideinitializer */
gustavatmel 1:9c5af431a1f1 86 #define CLK_CLKSEL1_TMR0SEL_LIRC (0x5UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from low speed oscillator \hideinitializer */
gustavatmel 1:9c5af431a1f1 87 #define CLK_CLKSEL1_TMR0SEL_HIRC (0x7UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from high speed oscillator \hideinitializer */
gustavatmel 1:9c5af431a1f1 88 #define CLK_CLKSEL1_TMR0SEL_PCLK0 (0x2UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from PCLK0 \hideinitializer */
gustavatmel 1:9c5af431a1f1 89 #define CLK_CLKSEL1_TMR0SEL_EXT (0x3UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from external trigger \hideinitializer */
gustavatmel 1:9c5af431a1f1 90
gustavatmel 1:9c5af431a1f1 91 #define CLK_CLKSEL1_TMR1SEL_HXT (0x0UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from high speed crystal \hideinitializer */
gustavatmel 1:9c5af431a1f1 92 #define CLK_CLKSEL1_TMR1SEL_LXT (0x1UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from low speed crystal \hideinitializer */
gustavatmel 1:9c5af431a1f1 93 #define CLK_CLKSEL1_TMR1SEL_LIRC (0x5UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from low speed oscillator \hideinitializer */
gustavatmel 1:9c5af431a1f1 94 #define CLK_CLKSEL1_TMR1SEL_HIRC (0x7UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from high speed oscillator \hideinitializer */
gustavatmel 1:9c5af431a1f1 95 #define CLK_CLKSEL1_TMR1SEL_PCLK0 (0x2UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from PCLK0 \hideinitializer */
gustavatmel 1:9c5af431a1f1 96 #define CLK_CLKSEL1_TMR1SEL_EXT (0x3UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from external trigger \hideinitializer */
gustavatmel 1:9c5af431a1f1 97
gustavatmel 1:9c5af431a1f1 98 #define CLK_CLKSEL1_TMR2SEL_HXT (0x0UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from high speed crystal \hideinitializer */
gustavatmel 1:9c5af431a1f1 99 #define CLK_CLKSEL1_TMR2SEL_LXT (0x1UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from low speed crystal \hideinitializer */
gustavatmel 1:9c5af431a1f1 100 #define CLK_CLKSEL1_TMR2SEL_LIRC (0x5UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from low speed oscillator \hideinitializer */
gustavatmel 1:9c5af431a1f1 101 #define CLK_CLKSEL1_TMR2SEL_HIRC (0x7UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from high speed oscillator \hideinitializer */
gustavatmel 1:9c5af431a1f1 102 #define CLK_CLKSEL1_TMR2SEL_PCLK1 (0x2UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from PCLK1 \hideinitializer */
gustavatmel 1:9c5af431a1f1 103 #define CLK_CLKSEL1_TMR2SEL_EXT (0x3UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from external trigger \hideinitializer */
gustavatmel 1:9c5af431a1f1 104
gustavatmel 1:9c5af431a1f1 105 #define CLK_CLKSEL1_TMR3SEL_HXT (0x0UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from high speed crystal \hideinitializer */
gustavatmel 1:9c5af431a1f1 106 #define CLK_CLKSEL1_TMR3SEL_LXT (0x1UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from low speed crystal \hideinitializer */
gustavatmel 1:9c5af431a1f1 107 #define CLK_CLKSEL1_TMR3SEL_LIRC (0x5UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from low speed oscillator \hideinitializer */
gustavatmel 1:9c5af431a1f1 108 #define CLK_CLKSEL1_TMR3SEL_HIRC (0x7UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from high speed oscillator \hideinitializer */
gustavatmel 1:9c5af431a1f1 109 #define CLK_CLKSEL1_TMR3SEL_PCLK1 (0x2UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from PCLK1 \hideinitializer */
gustavatmel 1:9c5af431a1f1 110 #define CLK_CLKSEL1_TMR3SEL_EXT (0x3UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from external trigger \hideinitializer */
gustavatmel 1:9c5af431a1f1 111
gustavatmel 1:9c5af431a1f1 112 #define CLK_CLKSEL1_UART0SEL_HXT (0x0UL << CLK_CLKSEL1_UART0SEL_Pos) /*!< Select UART0 clock source from high speed crystal \hideinitializer */
gustavatmel 1:9c5af431a1f1 113 #define CLK_CLKSEL1_UART0SEL_LXT (0x2UL << CLK_CLKSEL1_UART0SEL_Pos) /*!< Select UART0 clock source from low speed crystal \hideinitializer */
gustavatmel 1:9c5af431a1f1 114 #define CLK_CLKSEL1_UART0SEL_PLL (0x1UL << CLK_CLKSEL1_UART0SEL_Pos) /*!< Select UART0 clock source from PLL \hideinitializer */
gustavatmel 1:9c5af431a1f1 115 #define CLK_CLKSEL1_UART0SEL_HIRC (0x3UL << CLK_CLKSEL1_UART0SEL_Pos) /*!< Select UART0 clock source from high speed oscillator \hideinitializer */
gustavatmel 1:9c5af431a1f1 116
gustavatmel 1:9c5af431a1f1 117 #define CLK_CLKSEL1_UART1SEL_HXT (0x0UL << CLK_CLKSEL1_UART1SEL_Pos) /*!< Select UART1 clock source from high speed crystal \hideinitializer */
gustavatmel 1:9c5af431a1f1 118 #define CLK_CLKSEL1_UART1SEL_LXT (0x2UL << CLK_CLKSEL1_UART1SEL_Pos) /*!< Select UART1 clock source from low speed crystal \hideinitializer */
gustavatmel 1:9c5af431a1f1 119 #define CLK_CLKSEL1_UART1SEL_PLL (0x1UL << CLK_CLKSEL1_UART1SEL_Pos) /*!< Select UART1 clock source from PLL \hideinitializer */
gustavatmel 1:9c5af431a1f1 120 #define CLK_CLKSEL1_UART1SEL_HIRC (0x3UL << CLK_CLKSEL1_UART1SEL_Pos) /*!< Select UART1 clock source from high speed oscillator \hideinitializer */
gustavatmel 1:9c5af431a1f1 121
gustavatmel 1:9c5af431a1f1 122 #define CLK_CLKSEL1_CLKOSEL_HXT (0x0UL << CLK_CLKSEL1_CLKOSEL_Pos) /*!< Select CLKO clock source from high speed crystal \hideinitializer */
gustavatmel 1:9c5af431a1f1 123 #define CLK_CLKSEL1_CLKOSEL_LXT (0x1UL << CLK_CLKSEL1_CLKOSEL_Pos) /*!< Select CLKO clock source from low speed crystal \hideinitializer */
gustavatmel 1:9c5af431a1f1 124 #define CLK_CLKSEL1_CLKOSEL_HIRC (0x3UL << CLK_CLKSEL1_CLKOSEL_Pos) /*!< Select CLKO clock source from high speed oscillator \hideinitializer */
gustavatmel 1:9c5af431a1f1 125 #define CLK_CLKSEL1_CLKOSEL_HCLK (0x2UL << CLK_CLKSEL1_CLKOSEL_Pos) /*!< Select CLKO clock source from HCLK \hideinitializer */
gustavatmel 1:9c5af431a1f1 126
gustavatmel 1:9c5af431a1f1 127 #define CLK_CLKSEL1_WWDTSEL_LIRC (0x3UL << CLK_CLKSEL1_WWDTSEL_Pos) /*!< Select WWDT clock source from low speed oscillator \hideinitializer */
gustavatmel 1:9c5af431a1f1 128 #define CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048 (0x2UL << CLK_CLKSEL1_WWDTSEL_Pos) /*!< Select WWDT clock source from HCLK/2048 \hideinitializer */
gustavatmel 1:9c5af431a1f1 129
gustavatmel 1:9c5af431a1f1 130
gustavatmel 1:9c5af431a1f1 131 /*---------------------------------------------------------------------------------------------------------*/
gustavatmel 1:9c5af431a1f1 132 /* CLKSEL2 constant definitions. */
gustavatmel 1:9c5af431a1f1 133 /*---------------------------------------------------------------------------------------------------------*/
gustavatmel 1:9c5af431a1f1 134 #define CLK_CLKSEL2_SPI0SEL_HXT (0x0UL << CLK_CLKSEL2_SPI0SEL_Pos) /*!< Select SPI0 clock source from high speed crystal \hideinitializer */
gustavatmel 1:9c5af431a1f1 135 #define CLK_CLKSEL2_SPI0SEL_PLL (0x1UL << CLK_CLKSEL2_SPI0SEL_Pos) /*!< Select SPI0 clock source from PLL \hideinitializer */
gustavatmel 1:9c5af431a1f1 136 #define CLK_CLKSEL2_SPI0SEL_HIRC (0x3UL << CLK_CLKSEL2_SPI0SEL_Pos) /*!< Select SPI0 clock source from high speed oscillator \hideinitializer */
gustavatmel 1:9c5af431a1f1 137 #define CLK_CLKSEL2_SPI0SEL_PCLK0 (0x2UL << CLK_CLKSEL2_SPI0SEL_Pos) /*!< Select SPI0 clock source from PCLK0 \hideinitializer */
gustavatmel 1:9c5af431a1f1 138
gustavatmel 1:9c5af431a1f1 139 #define CLK_CLKSEL2_SPI1SEL_HXT (0x0UL << CLK_CLKSEL2_SPI1SEL_Pos) /*!< Select SPI1 clock source from high speed crystal \hideinitializer */
gustavatmel 1:9c5af431a1f1 140 #define CLK_CLKSEL2_SPI1SEL_PLL (0x1UL << CLK_CLKSEL2_SPI1SEL_Pos) /*!< Select SPI1 clock source from PLL \hideinitializer */
gustavatmel 1:9c5af431a1f1 141 #define CLK_CLKSEL2_SPI1SEL_HIRC (0x3UL << CLK_CLKSEL2_SPI1SEL_Pos) /*!< Select SPI1 clock source from high speed oscillator \hideinitializer */
gustavatmel 1:9c5af431a1f1 142 #define CLK_CLKSEL2_SPI1SEL_PCLK1 (0x2UL << CLK_CLKSEL2_SPI1SEL_Pos) /*!< Select SPI1 clock source from PCLK1 \hideinitializer */
gustavatmel 1:9c5af431a1f1 143
gustavatmel 1:9c5af431a1f1 144 #define CLK_CLKSEL2_SPI2SEL_HXT (0x0UL << CLK_CLKSEL2_SPI2SEL_Pos) /*!< Select SPI2 clock source from high speed crystal \hideinitializer */
gustavatmel 1:9c5af431a1f1 145 #define CLK_CLKSEL2_SPI2SEL_PLL (0x1UL << CLK_CLKSEL2_SPI2SEL_Pos) /*!< Select SPI2 clock source from PLL \hideinitializer */
gustavatmel 1:9c5af431a1f1 146 #define CLK_CLKSEL2_SPI2SEL_HIRC (0x3UL << CLK_CLKSEL2_SPI2SEL_Pos) /*!< Select SPI2 clock source from high speed oscillator \hideinitializer */
gustavatmel 1:9c5af431a1f1 147 #define CLK_CLKSEL2_SPI2SEL_PCLK0 (0x2UL << CLK_CLKSEL2_SPI2SEL_Pos) /*!< Select SPI2 clock source from PCLK0 \hideinitializer */
gustavatmel 1:9c5af431a1f1 148
gustavatmel 1:9c5af431a1f1 149 #define CLK_CLKSEL2_EPWM0SEL_PLL (0x0UL << CLK_CLKSEL2_EPWM0SEL_Pos) /*!< Select EPWM0 clock source from PLL \hideinitializer */
gustavatmel 1:9c5af431a1f1 150 #define CLK_CLKSEL2_EPWM0SEL_PCLK0 (0x1UL << CLK_CLKSEL2_EPWM0SEL_Pos) /*!< Select EPWM0 clock source from PCLK0 \hideinitializer */
gustavatmel 1:9c5af431a1f1 151
gustavatmel 1:9c5af431a1f1 152 #define CLK_CLKSEL2_EPWM1SEL_PLL (0x0UL << CLK_CLKSEL2_EPWM1SEL_Pos) /*!< Select EPWM1 clock source from PLL \hideinitializer */
gustavatmel 1:9c5af431a1f1 153 #define CLK_CLKSEL2_EPWM1SEL_PCLK1 (0x1UL << CLK_CLKSEL2_EPWM1SEL_Pos) /*!< Select EPWM1 clock source from PCLK1 \hideinitializer */
gustavatmel 1:9c5af431a1f1 154
gustavatmel 1:9c5af431a1f1 155 #define CLK_CLKSEL2_BPWM0SEL_PLL (0x0UL << CLK_CLKSEL2_BPWM0SEL_Pos) /*!< Select BPWM0 clock source from PLL \hideinitializer */
gustavatmel 1:9c5af431a1f1 156 #define CLK_CLKSEL2_BPWM0SEL_PCLK0 (0x1UL << CLK_CLKSEL2_BPWM0SEL_Pos) /*!< Select BPWM0 clock source from PCLK0 \hideinitializer */
gustavatmel 1:9c5af431a1f1 157
gustavatmel 1:9c5af431a1f1 158 #define CLK_CLKSEL2_BPWM1SEL_PLL (0x0UL << CLK_CLKSEL2_BPWM1SEL_Pos) /*!< Select BPWM1 clock source from PLL \hideinitializer */
gustavatmel 1:9c5af431a1f1 159 #define CLK_CLKSEL2_BPWM1SEL_PCLK1 (0x1UL << CLK_CLKSEL2_BPWM1SEL_Pos) /*!< Select BPWM1 clock source from PCLK1 \hideinitializer */
gustavatmel 1:9c5af431a1f1 160
gustavatmel 1:9c5af431a1f1 161 #define CLK_CLKSEL2_SPI3SEL_HXT (0x0UL << CLK_CLKSEL2_SPI3SEL_Pos) /*!< Select SPI3 clock source from high speed crystal \hideinitializer */
gustavatmel 1:9c5af431a1f1 162 #define CLK_CLKSEL2_SPI3SEL_PLL (0x1UL << CLK_CLKSEL2_SPI3SEL_Pos) /*!< Select SPI3 clock source from PLL \hideinitializer */
gustavatmel 1:9c5af431a1f1 163 #define CLK_CLKSEL2_SPI3SEL_HIRC (0x3UL << CLK_CLKSEL2_SPI3SEL_Pos) /*!< Select SPI3 clock source from high speed oscillator \hideinitializer */
gustavatmel 1:9c5af431a1f1 164 #define CLK_CLKSEL2_SPI3SEL_PCLK1 (0x2UL << CLK_CLKSEL2_SPI3SEL_Pos) /*!< Select SPI3 clock source from PCLK1 \hideinitializer */
gustavatmel 1:9c5af431a1f1 165
gustavatmel 1:9c5af431a1f1 166 #define CLK_CLKSEL2_SPI4SEL_HXT (0x0UL << CLK_CLKSEL2_SPI4SEL_Pos) /*!< Select SPI4 clock source from high speed crystal \hideinitializer */
gustavatmel 1:9c5af431a1f1 167 #define CLK_CLKSEL2_SPI4SEL_PLL (0x1UL << CLK_CLKSEL2_SPI4SEL_Pos) /*!< Select SPI4 clock source from PLL \hideinitializer */
gustavatmel 1:9c5af431a1f1 168 #define CLK_CLKSEL2_SPI4SEL_HIRC (0x3UL << CLK_CLKSEL2_SPI4SEL_Pos) /*!< Select SPI4 clock source from high speed oscillator \hideinitializer */
gustavatmel 1:9c5af431a1f1 169 #define CLK_CLKSEL2_SPI4SEL_PCLK0 (0x2UL << CLK_CLKSEL2_SPI4SEL_Pos) /*!< Select SPI4 clock source from PCLK0 \hideinitializer */
gustavatmel 1:9c5af431a1f1 170
gustavatmel 1:9c5af431a1f1 171
gustavatmel 1:9c5af431a1f1 172 /*---------------------------------------------------------------------------------------------------------*/
gustavatmel 1:9c5af431a1f1 173 /* CLKSEL3 constant definitions. */
gustavatmel 1:9c5af431a1f1 174 /*---------------------------------------------------------------------------------------------------------*/
gustavatmel 1:9c5af431a1f1 175 #define CLK_CLKSEL3_SC0SEL_HXT (0x0UL << CLK_CLKSEL3_SC0SEL_Pos) /*!< Select SC0 clock source from high speed crystal \hideinitializer */
gustavatmel 1:9c5af431a1f1 176 #define CLK_CLKSEL3_SC0SEL_PLL (0x1UL << CLK_CLKSEL3_SC0SEL_Pos) /*!< Select SC0 clock source from PLL \hideinitializer */
gustavatmel 1:9c5af431a1f1 177 #define CLK_CLKSEL3_SC0SEL_HIRC (0x3UL << CLK_CLKSEL3_SC0SEL_Pos) /*!< Select SC0 clock source from high speed oscillator \hideinitializer */
gustavatmel 1:9c5af431a1f1 178 #define CLK_CLKSEL3_SC0SEL_PCLK0 (0x2UL << CLK_CLKSEL3_SC0SEL_Pos) /*!< Select SC0 clock source from PCLK0 \hideinitializer */
gustavatmel 1:9c5af431a1f1 179
gustavatmel 1:9c5af431a1f1 180 #define CLK_CLKSEL3_SC1SEL_HXT (0x0UL << CLK_CLKSEL3_SC1SEL_Pos) /*!< Select SC1 clock source from high speed crystal \hideinitializer */
gustavatmel 1:9c5af431a1f1 181 #define CLK_CLKSEL3_SC1SEL_PLL (0x1UL << CLK_CLKSEL3_SC1SEL_Pos) /*!< Select SC1 clock source from PLL \hideinitializer */
gustavatmel 1:9c5af431a1f1 182 #define CLK_CLKSEL3_SC1SEL_HIRC (0x3UL << CLK_CLKSEL3_SC1SEL_Pos) /*!< Select SC1 clock source from high speed oscillator \hideinitializer */
gustavatmel 1:9c5af431a1f1 183 #define CLK_CLKSEL3_SC1SEL_PCLK1 (0x2UL << CLK_CLKSEL3_SC1SEL_Pos) /*!< Select SC1 clock source from PCLK1 \hideinitializer */
gustavatmel 1:9c5af431a1f1 184
gustavatmel 1:9c5af431a1f1 185 #define CLK_CLKSEL3_SC2SEL_HXT (0x0UL << CLK_CLKSEL3_SC2SEL_Pos) /*!< Select SC2 clock source from high speed crystal \hideinitializer */
gustavatmel 1:9c5af431a1f1 186 #define CLK_CLKSEL3_SC2SEL_PLL (0x1UL << CLK_CLKSEL3_SC2SEL_Pos) /*!< Select SC2 clock source from PLL \hideinitializer */
gustavatmel 1:9c5af431a1f1 187 #define CLK_CLKSEL3_SC2SEL_HIRC (0x3UL << CLK_CLKSEL3_SC2SEL_Pos) /*!< Select SC2 clock source from high speed oscillator \hideinitializer */
gustavatmel 1:9c5af431a1f1 188 #define CLK_CLKSEL3_SC2SEL_PCLK0 (0x2UL << CLK_CLKSEL3_SC2SEL_Pos) /*!< Select SC2 clock source from PCLK0 \hideinitializer */
gustavatmel 1:9c5af431a1f1 189
gustavatmel 1:9c5af431a1f1 190 #define CLK_CLKSEL3_RTCSEL_LXT (0x0UL << CLK_CLKSEL3_RTCSEL_Pos) /*!< Select RTC clock source from low speed crystal \hideinitializer */
gustavatmel 1:9c5af431a1f1 191 #define CLK_CLKSEL3_RTCSEL_LIRC (0x1UL << CLK_CLKSEL3_RTCSEL_Pos) /*!< Select RTC clock source from low speed oscillator \hideinitializer */
gustavatmel 1:9c5af431a1f1 192
gustavatmel 1:9c5af431a1f1 193 #define CLK_CLKSEL3_I2S0SEL_HXT (0x0UL << CLK_CLKSEL3_I2S0SEL_Pos) /*!< Select I2S0 clock source from high speed crystal \hideinitializer */
gustavatmel 1:9c5af431a1f1 194 #define CLK_CLKSEL3_I2S0SEL_PLL (0x1UL << CLK_CLKSEL3_I2S0SEL_Pos) /*!< Select I2S0 clock source from PLL \hideinitializer */
gustavatmel 1:9c5af431a1f1 195 #define CLK_CLKSEL3_I2S0SEL_HIRC (0x3UL << CLK_CLKSEL3_I2S0SEL_Pos) /*!< Select I2S0 clock source from high speed oscillator \hideinitializer */
gustavatmel 1:9c5af431a1f1 196 #define CLK_CLKSEL3_I2S0SEL_PCLK0 (0x2UL << CLK_CLKSEL3_I2S0SEL_Pos) /*!< Select I2S0 clock source from PCLK0 \hideinitializer */
gustavatmel 1:9c5af431a1f1 197
gustavatmel 1:9c5af431a1f1 198 #define CLK_CLKSEL3_UART2SEL_HXT (0x0UL << CLK_CLKSEL3_UART2SEL_Pos) /*!< Select UART2 clock source from high speed crystal \hideinitializer */
gustavatmel 1:9c5af431a1f1 199 #define CLK_CLKSEL3_UART2SEL_LXT (0x2UL << CLK_CLKSEL3_UART2SEL_Pos) /*!< Select UART2 clock source from low speed crystal \hideinitializer */
gustavatmel 1:9c5af431a1f1 200 #define CLK_CLKSEL3_UART2SEL_PLL (0x1UL << CLK_CLKSEL3_UART2SEL_Pos) /*!< Select UART2 clock source from PLL \hideinitializer */
gustavatmel 1:9c5af431a1f1 201 #define CLK_CLKSEL3_UART2SEL_HIRC (0x3UL << CLK_CLKSEL3_UART2SEL_Pos) /*!< Select UART2 clock source from high speed oscillator \hideinitializer */
gustavatmel 1:9c5af431a1f1 202
gustavatmel 1:9c5af431a1f1 203 #define CLK_CLKSEL3_UART3SEL_HXT (0x0UL << CLK_CLKSEL3_UART3SEL_Pos) /*!< Select UART3 clock source from high speed crystal \hideinitializer */
gustavatmel 1:9c5af431a1f1 204 #define CLK_CLKSEL3_UART3SEL_LXT (0x2UL << CLK_CLKSEL3_UART3SEL_Pos) /*!< Select UART3 clock source from low speed crystal \hideinitializer */
gustavatmel 1:9c5af431a1f1 205 #define CLK_CLKSEL3_UART3SEL_PLL (0x1UL << CLK_CLKSEL3_UART3SEL_Pos) /*!< Select UART3 clock source from PLL \hideinitializer */
gustavatmel 1:9c5af431a1f1 206 #define CLK_CLKSEL3_UART3SEL_HIRC (0x3UL << CLK_CLKSEL3_UART3SEL_Pos) /*!< Select UART3 clock source from high speed oscillator \hideinitializer */
gustavatmel 1:9c5af431a1f1 207
gustavatmel 1:9c5af431a1f1 208 #define CLK_CLKSEL3_UART4SEL_HXT (0x0UL << CLK_CLKSEL3_UART4SEL_Pos) /*!< Select UART4 clock source from high speed crystal \hideinitializer */
gustavatmel 1:9c5af431a1f1 209 #define CLK_CLKSEL3_UART4SEL_LXT (0x2UL << CLK_CLKSEL3_UART4SEL_Pos) /*!< Select UART4 clock source from low speed crystal \hideinitializer */
gustavatmel 1:9c5af431a1f1 210 #define CLK_CLKSEL3_UART4SEL_PLL (0x1UL << CLK_CLKSEL3_UART4SEL_Pos) /*!< Select UART4 clock source from PLL \hideinitializer */
gustavatmel 1:9c5af431a1f1 211 #define CLK_CLKSEL3_UART4SEL_HIRC (0x3UL << CLK_CLKSEL3_UART4SEL_Pos) /*!< Select UART4 clock source from high speed oscillator \hideinitializer */
gustavatmel 1:9c5af431a1f1 212
gustavatmel 1:9c5af431a1f1 213 #define CLK_CLKSEL3_UART5SEL_HXT (0x0UL << CLK_CLKSEL3_UART5SEL_Pos) /*!< Select UART5 clock source from high speed crystal \hideinitializer */
gustavatmel 1:9c5af431a1f1 214 #define CLK_CLKSEL3_UART5SEL_LXT (0x2UL << CLK_CLKSEL3_UART5SEL_Pos) /*!< Select UART5 clock source from low speed crystal \hideinitializer */
gustavatmel 1:9c5af431a1f1 215 #define CLK_CLKSEL3_UART5SEL_PLL (0x1UL << CLK_CLKSEL3_UART5SEL_Pos) /*!< Select UART5 clock source from PLL \hideinitializer */
gustavatmel 1:9c5af431a1f1 216 #define CLK_CLKSEL3_UART5SEL_HIRC (0x3UL << CLK_CLKSEL3_UART5SEL_Pos) /*!< Select UART5 clock source from high speed oscillator \hideinitializer */
gustavatmel 1:9c5af431a1f1 217
gustavatmel 1:9c5af431a1f1 218
gustavatmel 1:9c5af431a1f1 219 /*---------------------------------------------------------------------------------------------------------*/
gustavatmel 1:9c5af431a1f1 220 /* CLKDIV0 constant definitions. */
gustavatmel 1:9c5af431a1f1 221 /*---------------------------------------------------------------------------------------------------------*/
gustavatmel 1:9c5af431a1f1 222 #define CLK_CLKDIV0_HCLK(x) (((x) - 1UL) << CLK_CLKDIV0_HCLKDIV_Pos) /*!< CLKDIV0 Setting for HCLK clock divider. It could be 1~16 \hideinitializer */
gustavatmel 1:9c5af431a1f1 223 #define CLK_CLKDIV0_USB(x) (((x) - 1UL) << CLK_CLKDIV0_USBDIV_Pos) /*!< CLKDIV0 Setting for USB clock divider. It could be 1~16 \hideinitializer */
gustavatmel 1:9c5af431a1f1 224 #define CLK_CLKDIV0_SDH0(x) (((x) - 1UL) << CLK_CLKDIV0_SDH0DIV_Pos) /*!< CLKDIV0 Setting for SDH0 clock divider. It could be 1~256 \hideinitializer */
gustavatmel 1:9c5af431a1f1 225 #define CLK_CLKDIV0_UART0(x) (((x) - 1UL) << CLK_CLKDIV0_UART0DIV_Pos) /*!< CLKDIV0 Setting for UART0 clock divider. It could be 1~16 \hideinitializer */
gustavatmel 1:9c5af431a1f1 226 #define CLK_CLKDIV0_UART1(x) (((x) - 1UL) << CLK_CLKDIV0_UART1DIV_Pos) /*!< CLKDIV0 Setting for UART1 clock divider. It could be 1~16 \hideinitializer */
gustavatmel 1:9c5af431a1f1 227 #define CLK_CLKDIV0_EADC(x) (((x) - 1UL) << CLK_CLKDIV0_EADCDIV_Pos) /*!< CLKDIV0 Setting for EADC clock divider. It could be 1~256 \hideinitializer */
gustavatmel 1:9c5af431a1f1 228
gustavatmel 1:9c5af431a1f1 229 /*---------------------------------------------------------------------------------------------------------*/
gustavatmel 1:9c5af431a1f1 230 /* CLKDIV1 constant definitions. */
gustavatmel 1:9c5af431a1f1 231 /*---------------------------------------------------------------------------------------------------------*/
gustavatmel 1:9c5af431a1f1 232 #define CLK_CLKDIV1_SC0(x) (((x) - 1UL) << CLK_CLKDIV1_SC0DIV_Pos) /*!< CLKDIV1 Setting for SC0 clock divider. It could be 1~256 \hideinitializer */
gustavatmel 1:9c5af431a1f1 233 #define CLK_CLKDIV1_SC1(x) (((x) - 1UL) << CLK_CLKDIV1_SC1DIV_Pos) /*!< CLKDIV1 Setting for SC1 clock divider. It could be 1~256 \hideinitializer */
gustavatmel 1:9c5af431a1f1 234 #define CLK_CLKDIV1_SC2(x) (((x) - 1UL) << CLK_CLKDIV1_SC2DIV_Pos) /*!< CLKDIV1 Setting for SC2 clock divider. It could be 1~256 \hideinitializer */
gustavatmel 1:9c5af431a1f1 235
gustavatmel 1:9c5af431a1f1 236 /*---------------------------------------------------------------------------------------------------------*/
gustavatmel 1:9c5af431a1f1 237 /* CLKDIV3 constant definitions. */
gustavatmel 1:9c5af431a1f1 238 /*---------------------------------------------------------------------------------------------------------*/
gustavatmel 1:9c5af431a1f1 239 #define CLK_CLKDIV3_EMAC(x) (((x) - 1UL) << CLK_CLKDIV3_EMACDIV_Pos) /*!< CLKDIV3 Setting for EMAC clock divider. It could be 1~256 \hideinitializer */
gustavatmel 1:9c5af431a1f1 240 #define CLK_CLKDIV3_SDH1(x) (((x) - 1UL) << CLK_CLKDIV3_SDH1DIV_Pos) /*!< CLKDIV3 Setting for SDH1 clock divider. It could be 1~256 \hideinitializer */
gustavatmel 1:9c5af431a1f1 241
gustavatmel 1:9c5af431a1f1 242 /*---------------------------------------------------------------------------------------------------------*/
gustavatmel 1:9c5af431a1f1 243 /* CLKDIV4 constant definitions. */
gustavatmel 1:9c5af431a1f1 244 /*---------------------------------------------------------------------------------------------------------*/
gustavatmel 1:9c5af431a1f1 245 #define CLK_CLKDIV4_UART2(x) (((x) - 1UL) << CLK_CLKDIV4_UART2DIV_Pos) /*!< CLKDIV4 Setting for UART2 clock divider. It could be 1~16 \hideinitializer */
gustavatmel 1:9c5af431a1f1 246 #define CLK_CLKDIV4_UART3(x) (((x) - 1UL) << CLK_CLKDIV4_UART3DIV_Pos) /*!< CLKDIV4 Setting for UART3 clock divider. It could be 1~16 \hideinitializer */
gustavatmel 1:9c5af431a1f1 247 #define CLK_CLKDIV4_UART4(x) (((x) - 1UL) << CLK_CLKDIV4_UART4DIV_Pos) /*!< CLKDIV4 Setting for UART4 clock divider. It could be 1~16 \hideinitializer */
gustavatmel 1:9c5af431a1f1 248 #define CLK_CLKDIV4_UART5(x) (((x) - 1UL) << CLK_CLKDIV4_UART5DIV_Pos) /*!< CLKDIV4 Setting for UART5 clock divider. It could be 1~16 \hideinitializer */
gustavatmel 1:9c5af431a1f1 249
gustavatmel 1:9c5af431a1f1 250 /*---------------------------------------------------------------------------------------------------------*/
gustavatmel 1:9c5af431a1f1 251 /* PCLKDIV constant definitions. */
gustavatmel 1:9c5af431a1f1 252 /*---------------------------------------------------------------------------------------------------------*/
gustavatmel 1:9c5af431a1f1 253 #if(1)
gustavatmel 1:9c5af431a1f1 254 #define CLK_PCLKDIV_PCLK0DIV1 (0x0UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = HCLK \hideinitializer */
gustavatmel 1:9c5af431a1f1 255 #define CLK_PCLKDIV_PCLK0DIV2 (0x1UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/2 HCLK \hideinitializer */
gustavatmel 1:9c5af431a1f1 256 #define CLK_PCLKDIV_PCLK0DIV4 (0x2UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/4 HCLK \hideinitializer */
gustavatmel 1:9c5af431a1f1 257 #define CLK_PCLKDIV_PCLK0DIV8 (0x3UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/8 HCLK \hideinitializer */
gustavatmel 1:9c5af431a1f1 258 #define CLK_PCLKDIV_PCLK0DIV16 (0x4UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/16 HCLK \hideinitializer */
gustavatmel 1:9c5af431a1f1 259 #define CLK_PCLKDIV_PCLK1DIV1 (0x0UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = HCLK \hideinitializer */
gustavatmel 1:9c5af431a1f1 260 #define CLK_PCLKDIV_PCLK1DIV2 (0x1UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/2 HCLK \hideinitializer */
gustavatmel 1:9c5af431a1f1 261 #define CLK_PCLKDIV_PCLK1DIV4 (0x2UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/4 HCLK \hideinitializer */
gustavatmel 1:9c5af431a1f1 262 #define CLK_PCLKDIV_PCLK1DIV8 (0x3UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/8 HCLK \hideinitializer */
gustavatmel 1:9c5af431a1f1 263 #define CLK_PCLKDIV_PCLK1DIV16 (0x4UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/16 HCLK \hideinitializer */
gustavatmel 1:9c5af431a1f1 264 #endif
gustavatmel 1:9c5af431a1f1 265 /*---------------------------------------------------------------------------------------------------------*/
gustavatmel 1:9c5af431a1f1 266 /* PLLCTL constant definitions. PLL = FIN * 2 * NF / NR / NO */
gustavatmel 1:9c5af431a1f1 267 /*---------------------------------------------------------------------------------------------------------*/
gustavatmel 1:9c5af431a1f1 268 #define CLK_PLLCTL_PLLSRC_HXT 0x00000000UL /*!< For PLL clock source is HXT. 4MHz < FIN/NR < 8MHz \hideinitializer */
gustavatmel 1:9c5af431a1f1 269 #define CLK_PLLCTL_PLLSRC_HIRC 0x00080000UL /*!< For PLL clock source is HIRC. 4MHz < FIN/NR < 8MHz \hideinitializer */
gustavatmel 1:9c5af431a1f1 270
gustavatmel 1:9c5af431a1f1 271 #define CLK_PLLCTL_NF(x) (((x)-2UL)) /*!< x must be constant and 2 <= x <= 513. 200MHz < FIN*2*NF/NR < 500MHz. \hideinitializer */
gustavatmel 1:9c5af431a1f1 272 #define CLK_PLLCTL_NR(x) (((x)-1UL)<<9) /*!< x must be constant and 1 <= x <= 32. 4MHz < FIN/NR < 8MHz \hideinitializer */
gustavatmel 1:9c5af431a1f1 273
gustavatmel 1:9c5af431a1f1 274 #define CLK_PLLCTL_NO_1 0x0000UL /*!< For output divider is 1 \hideinitializer */
gustavatmel 1:9c5af431a1f1 275 #define CLK_PLLCTL_NO_2 0x4000UL /*!< For output divider is 2 \hideinitializer */
gustavatmel 1:9c5af431a1f1 276 #define CLK_PLLCTL_NO_4 0xC000UL /*!< For output divider is 4 \hideinitializer */
gustavatmel 1:9c5af431a1f1 277
gustavatmel 1:9c5af431a1f1 278 #define CLK_PLLCTL_72MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 36UL) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 72MHz PLL output with HXT(12MHz X'tal) \hideinitializer */
gustavatmel 1:9c5af431a1f1 279 #define CLK_PLLCTL_80MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 40UL) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 80MHz PLL output with HXT(12MHz X'tal) \hideinitializer */
gustavatmel 1:9c5af431a1f1 280 #define CLK_PLLCTL_144MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF( 24UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 144MHz PLL output with HXT(12MHz X'tal) \hideinitializer */
gustavatmel 1:9c5af431a1f1 281 #define CLK_PLLCTL_160MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 40UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 160MHz PLL output with HXT(12MHz X'tal) \hideinitializer */
gustavatmel 1:9c5af431a1f1 282 #define CLK_PLLCTL_192MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF( 32UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 192MHz PLL output with HXT(12MHz X'tal) \hideinitializer */
gustavatmel 1:9c5af431a1f1 283
gustavatmel 1:9c5af431a1f1 284 #define CLK_PLLCTL_72MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 36UL) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 72MHz PLL output with HIRC(12MHz IRC) \hideinitializer */
gustavatmel 1:9c5af431a1f1 285 #define CLK_PLLCTL_80MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 40UL) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 80MHz PLL output with HIRC(12MHz IRC) \hideinitializer */
gustavatmel 1:9c5af431a1f1 286 #define CLK_PLLCTL_144MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF( 24UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 144MHz PLL output with HIRC(12MHz IRC) \hideinitializer */
gustavatmel 1:9c5af431a1f1 287 #define CLK_PLLCTL_160MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 40UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 160MHz PLL output with HIRC(12MHz IRC) \hideinitializer */
gustavatmel 1:9c5af431a1f1 288 #define CLK_PLLCTL_192MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF( 32UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 192MHz PLL output with HIRC(12MHz IRC) \hideinitializer */
gustavatmel 1:9c5af431a1f1 289
gustavatmel 1:9c5af431a1f1 290 /*---------------------------------------------------------------------------------------------------------*/
gustavatmel 1:9c5af431a1f1 291 /* MODULE constant definitions. */
gustavatmel 1:9c5af431a1f1 292 /*---------------------------------------------------------------------------------------------------------*/
gustavatmel 1:9c5af431a1f1 293
gustavatmel 1:9c5af431a1f1 294 /* APBCLK(31:30)|CLKSEL(29:28)|CLKSEL_Msk(27:25) |CLKSEL_Pos(24:20)|CLKDIV(19:18)|CLKDIV_Msk(17:10)|CLKDIV_Pos(9:5)|IP_EN_Pos(4:0) */
gustavatmel 1:9c5af431a1f1 295
gustavatmel 1:9c5af431a1f1 296 #define MODULE_APBCLK(x) (((x) >>30) & 0x3UL) /*!< Calculate AHBCLK/APBCLK offset on MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1 \hideinitializer */
gustavatmel 1:9c5af431a1f1 297 #define MODULE_CLKSEL(x) (((x) >>28) & 0x3UL) /*!< Calculate CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3 \hideinitializer */
gustavatmel 1:9c5af431a1f1 298 #define MODULE_CLKSEL_Msk(x) (((x) >>25) & 0x7UL) /*!< Calculate CLKSEL mask offset on MODULE index \hideinitializer */
gustavatmel 1:9c5af431a1f1 299 #define MODULE_CLKSEL_Pos(x) (((x) >>20) & 0x1fUL) /*!< Calculate CLKSEL position offset on MODULE index \hideinitializer */
gustavatmel 1:9c5af431a1f1 300 #define MODULE_CLKDIV(x) (((x) >>18) & 0x3UL) /*!< Calculate APBCLK CLKDIV on MODULE index, 0x0:CLKDIV0, 0x1:CLKDIV1, 0x2:CLKDIV3, 0x3:CLKDIV4 \hideinitializer */
gustavatmel 1:9c5af431a1f1 301 #define MODULE_CLKDIV_Msk(x) (((x) >>10) & 0xffUL) /*!< Calculate CLKDIV mask offset on MODULE index \hideinitializer */
gustavatmel 1:9c5af431a1f1 302 #define MODULE_CLKDIV_Pos(x) (((x) >>5 ) & 0x1fUL) /*!< Calculate CLKDIV position offset on MODULE index \hideinitializer */
gustavatmel 1:9c5af431a1f1 303 #define MODULE_IP_EN_Pos(x) (((x) >>0 ) & 0x1fUL) /*!< Calculate APBCLK offset on MODULE index \hideinitializer */
gustavatmel 1:9c5af431a1f1 304 #define MODULE_NoMsk 0x0UL /*!< Not mask on MODULE index \hideinitializer */
gustavatmel 1:9c5af431a1f1 305 #define NA MODULE_NoMsk /*!< Not Available \hideinitializer */
gustavatmel 1:9c5af431a1f1 306
gustavatmel 1:9c5af431a1f1 307 #define MODULE_APBCLK_ENC(x) (((x) & 0x03UL) << 30) /*!< MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1 \hideinitializer */
gustavatmel 1:9c5af431a1f1 308 #define MODULE_CLKSEL_ENC(x) (((x) & 0x03UL) << 28) /*!< CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3 \hideinitializer */
gustavatmel 1:9c5af431a1f1 309 #define MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x07UL) << 25) /*!< CLKSEL mask offset on MODULE index \hideinitializer */
gustavatmel 1:9c5af431a1f1 310 #define MODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1fUL) << 20) /*!< CLKSEL position offset on MODULE index \hideinitializer */
gustavatmel 1:9c5af431a1f1 311 #define MODULE_CLKDIV_ENC(x) (((x) & 0x03UL) << 18) /*!< APBCLK CLKDIV on MODULE index, 0x0:CLKDIV0, 0x1:CLKDIV1, 0x2:CLKDIV3, 0x3:CLKDIV4 \hideinitializer */
gustavatmel 1:9c5af431a1f1 312 #define MODULE_CLKDIV_Msk_ENC(x) (((x) & 0xffUL) << 10) /*!< CLKDIV mask offset on MODULE index \hideinitializer */
gustavatmel 1:9c5af431a1f1 313 #define MODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1fUL) << 5) /*!< CLKDIV position offset on MODULE index \hideinitializer */
gustavatmel 1:9c5af431a1f1 314 #define MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1fUL) << 0) /*!< AHBCLK/APBCLK offset on MODULE index \hideinitializer */
gustavatmel 1:9c5af431a1f1 315
gustavatmel 1:9c5af431a1f1 316 #define PDMA_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(1UL<<0)) /*!< PDMA Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 317 #define ISP_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(2UL<<0)) /*!< ISP Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 318 #define EBI_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(3UL<<0)) /*!< EBI Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 319 #define USBH_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(16UL<<0)) /*!< USBH Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 320 #define EMAC_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(2UL<<18) |(0xFFUL<<10) |(16UL<<5) |(5UL<<0)) /*!< EMAC Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 321 #define SDH0_MODULE ((0UL<<30)|(0UL<<28) |(0x3UL<<25) |(20UL<<20) |(0UL<<18) |(0xFFUL<<10) |(24UL<<5) |(6UL<<0)) /*!< SDH0 Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 322 #define CRC_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(7UL<<0)) /*!< CRC Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 323 #define HSUSBD_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(10UL<<0)) /*!< HSUSBD Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 324 #define CRPT_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(12UL<<0)) /*!< CRPT Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 325 #define SPIM_MODULE ((0UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(14UL<<0)) /*!< SPIM Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 326 #define SDH1_MODULE ((0UL<<30)|(0UL<<28) |(0x3UL<<25) |(22UL<<20) |(2UL<<18) |(0xFFUL<<10) |(24UL<<5) |(17UL<<0)) /*!< SDH1 Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 327 #define WDT_MODULE ((1UL<<30)|(1UL<<28) |(0x3UL<<25) |(0UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(0UL<<0)) /*!< WDT Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 328 #define RTC_MODULE ((1UL<<30)|(3UL<<28) |(0x1UL<<25) |(8UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(1UL<<0)) /*!< RTC Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 329 #define TMR0_MODULE ((1UL<<30)|(1UL<<28) |(0x7UL<<25) |(8UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(2UL<<0)) /*!< TMR0 Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 330 #define TMR1_MODULE ((1UL<<30)|(1UL<<28) |(0x7UL<<25) |(12UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(3UL<<0)) /*!< TMR1 Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 331 #define TMR2_MODULE ((1UL<<30)|(1UL<<28) |(0x7UL<<25) |(16UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(4UL<<0)) /*!< TMR2 Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 332 #define TMR3_MODULE ((1UL<<30)|(1UL<<28) |(0x7UL<<25) |(20UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(5UL<<0)) /*!< TMR3 Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 333 #define CLKO_MODULE ((1UL<<30)|(1UL<<28) |(0x3UL<<25) |(28UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(6UL<<0)) /*!< CLKO Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 334 #define WWDT_MODULE ((1UL<<30)|(1UL<<28) |(0x3UL<<25) |(30UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(0UL<<0)) /*!< WWDT Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 335 #define ACMP01_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(7UL<<0)) /*!< ACMP01 Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 336 #define I2C0_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(8UL<<0)) /*!< I2C0 Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 337 #define I2C1_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(9UL<<0)) /*!< I2C1 Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 338 #define I2C2_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(10UL<<0)) /*!< I2C2 Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 339 #define SPI0_MODULE ((1UL<<30)|(2UL<<28) |(0x3UL<<25) |(2UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(12UL<<0)) /*!< SPI0 Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 340 #define SPI1_MODULE ((1UL<<30)|(2UL<<28) |(0x3UL<<25) |(4UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(13UL<<0)) /*!< SPI1 Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 341 #define SPI2_MODULE ((1UL<<30)|(2UL<<28) |(0x3UL<<25) |(6UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(14UL<<0)) /*!< SPI2 Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 342 #define SPI3_MODULE ((1UL<<30)|(2UL<<28) |(0x3UL<<25) |(10UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(15UL<<0)) /*!< SPI3 Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 343 #define UART0_MODULE ((1UL<<30)|(1UL<<28) |(0x3UL<<25) |(24UL<<20) |(0UL<<18) |(0xFUL<<10) |(8UL<<5) |(16UL<<0)) /*!< UART0 Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 344 #define UART1_MODULE ((1UL<<30)|(1UL<<28) |(0x3UL<<25) |(26UL<<20) |(0UL<<18) |(0xFUL<<10) |(12UL<<5) |(17UL<<0)) /*!< UART1 Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 345 #define UART2_MODULE ((1UL<<30)|(3UL<<28) |(0x3UL<<25) |(24UL<<20) |(3UL<<18) |(0xFUL<<10) |(0UL<<5) |(18UL<<0)) /*!< UART2 Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 346 #define UART3_MODULE ((1UL<<30)|(3UL<<28) |(0x3UL<<25) |(26UL<<20) |(3UL<<18) |(0xFUL<<10) |(4UL<<5) |(19UL<<0)) /*!< UART3 Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 347 #define UART4_MODULE ((1UL<<30)|(3UL<<28) |(0x3UL<<25) |(28UL<<20) |(3UL<<18) |(0xFUL<<10) |(8UL<<5) |(20UL<<0)) /*!< UART4 Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 348 #define UART5_MODULE ((1UL<<30)|(3UL<<28) |(0x3UL<<25) |(30UL<<20) |(3UL<<18) |(0xFUL<<10) |(12UL<<5) |(21UL<<0)) /*!< UART5 Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 349 #define CAN0_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(24UL<<0)) /*!< CAN0 Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 350 #define CAN1_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(25UL<<0)) /*!< CAN1 Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 351 #define OTG_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(26UL<<0)) /*!< OTG Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 352 #define USBD_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(27UL<<0)) /*!< USBD Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 353 #define EADC_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(0UL<<18) |(0xFFUL<<10) |(16UL<<5) |(28UL<<0)) /*!< EADC Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 354 #define I2S0_MODULE ((1UL<<30)|(3UL<<28) |(0x3UL<<25) |(16UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(29UL<<0)) /*!< I2S0 Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 355 #define HSOTG_MODULE ((1UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(30UL<<0)) /*!< HSOTG Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 356 #define SC0_MODULE ((2UL<<30)|(3UL<<28) |(0x3UL<<25) |(0UL<<20) |(1UL<<18) |(0xFFUL<<10) |(0UL<<5) |(0UL<<0)) /*!< SC0 Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 357 #define SC1_MODULE ((2UL<<30)|(3UL<<28) |(0x3UL<<25) |(2UL<<20) |(1UL<<18) |(0xFFUL<<10) |(8UL<<5) |(1UL<<0)) /*!< SC1 Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 358 #define SC2_MODULE ((2UL<<30)|(3UL<<28) |(0x3UL<<25) |(4UL<<20) |(1UL<<18) |(0xFFUL<<10) |(16UL<<5) |(2UL<<0)) /*!< SC2 Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 359 #define SPI4_MODULE ((2UL<<30)|(2UL<<28) |(0x3UL<<25) |(12UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(6UL<<0)) /*!< SPI4 Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 360 #define USCI0_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(8UL<<0)) /*!< USCI0 Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 361 #define USCI1_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(9UL<<0)) /*!< USCI1 Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 362 #define DAC_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(12UL<<0)) /*!< DAC Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 363 #define EPWM0_MODULE ((2UL<<30)|(2UL<<28) |(0x1UL<<25) |(0UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(16UL<<0)) /*!< EPWM0 Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 364 #define EPWM1_MODULE ((2UL<<30)|(2UL<<28) |(0x1UL<<25) |(1UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(17UL<<0)) /*!< EPWM1 Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 365 #define BPWM0_MODULE ((2UL<<30)|(2UL<<28) |(0x1UL<<25) |(8UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(18UL<<0)) /*!< BPWM0 Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 366 #define BPWM1_MODULE ((2UL<<30)|(2UL<<28) |(0x1UL<<25) |(9UL<<20) |(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(19UL<<0)) /*!< BPWM1 Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 367 #define QEI0_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(22UL<<0)) /*!< QEI0 Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 368 #define QEI1_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(23UL<<0)) /*!< QEI1 Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 369 #define ECAP0_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(26UL<<0)) /*!< ECAP0 Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 370 #define ECAP1_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(27UL<<0)) /*!< ECAP1 Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 371 #define OPA_MODULE ((2UL<<30)|(MODULE_NoMsk<<28)|(MODULE_NoMsk<<25)|(MODULE_NoMsk<<20)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(30UL<<0)) /*!< OPA Module \hideinitializer */
gustavatmel 1:9c5af431a1f1 372
gustavatmel 1:9c5af431a1f1 373 /*---------------------------------------------------------------------------------------------------------*/
gustavatmel 1:9c5af431a1f1 374 /* PDMSEL constant definitions. */
gustavatmel 1:9c5af431a1f1 375 /*---------------------------------------------------------------------------------------------------------*/
gustavatmel 1:9c5af431a1f1 376 #define CLK_PMUCTL_PDMSEL_PD (0x0UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mdoe is Power-down mode \hideinitializer */
gustavatmel 1:9c5af431a1f1 377 #define CLK_PMUCTL_PDMSEL_LLPD (0x1UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mdoe is Low leakage Power-down mode \hideinitializer */
gustavatmel 1:9c5af431a1f1 378 #define CLK_PMUCTL_PDMSEL_FWPD (0x2UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mdoe is Fast wake-up Power-down mode \hideinitializer */
gustavatmel 1:9c5af431a1f1 379 #define CLK_PMUCTL_PDMSEL_SPD0 (0x4UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mdoe is Standby Power-down mode 0 \hideinitializer */
gustavatmel 1:9c5af431a1f1 380 #define CLK_PMUCTL_PDMSEL_SPD1 (0x5UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mdoe is Standby Power-down mode 1 \hideinitializer */
gustavatmel 1:9c5af431a1f1 381 #define CLK_PMUCTL_PDMSEL_DPD (0x6UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mdoe is Deep Power-down mode \hideinitializer */
gustavatmel 1:9c5af431a1f1 382
gustavatmel 1:9c5af431a1f1 383 /*---------------------------------------------------------------------------------------------------------*/
gustavatmel 1:9c5af431a1f1 384 /* WKTMRIS constant definitions. */
gustavatmel 1:9c5af431a1f1 385 /*---------------------------------------------------------------------------------------------------------*/
gustavatmel 1:9c5af431a1f1 386 #define CLK_PMUCTL_WKTMRIS_128 (0x0UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 128 OSC10K clocks (12.8 ms) \hideinitializer */
gustavatmel 1:9c5af431a1f1 387 #define CLK_PMUCTL_WKTMRIS_256 (0x1UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 256 OSC10K clocks (25.6 ms) \hideinitializer */
gustavatmel 1:9c5af431a1f1 388 #define CLK_PMUCTL_WKTMRIS_512 (0x2UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 512 OSC10K clocks (51.2 ms) \hideinitializer */
gustavatmel 1:9c5af431a1f1 389 #define CLK_PMUCTL_WKTMRIS_1024 (0x3UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 1024 OSC10K clocks (102.4ms) \hideinitializer */
gustavatmel 1:9c5af431a1f1 390 #define CLK_PMUCTL_WKTMRIS_4096 (0x4UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 4096 OSC10K clocks (409.6ms) \hideinitializer */
gustavatmel 1:9c5af431a1f1 391 #define CLK_PMUCTL_WKTMRIS_8192 (0x5UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 8192 OSC10K clocks (819.2ms) \hideinitializer */
gustavatmel 1:9c5af431a1f1 392 #define CLK_PMUCTL_WKTMRIS_16384 (0x6UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 16384 OSC10K clocks (1638.4ms) \hideinitializer */
gustavatmel 1:9c5af431a1f1 393 #define CLK_PMUCTL_WKTMRIS_65536 (0x7UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 65536 OSC10K clocks (6553.6ms) \hideinitializer */
gustavatmel 1:9c5af431a1f1 394
gustavatmel 1:9c5af431a1f1 395
gustavatmel 1:9c5af431a1f1 396 /*---------------------------------------------------------------------------------------------------------*/
gustavatmel 1:9c5af431a1f1 397 /* SWKDBCLKSEL constant definitions. */
gustavatmel 1:9c5af431a1f1 398 /*---------------------------------------------------------------------------------------------------------*/
gustavatmel 1:9c5af431a1f1 399 #define CLK_SWKDBCTL_SWKDBCLKSEL_1 (0x0UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 1 clocks \hideinitializer */
gustavatmel 1:9c5af431a1f1 400 #define CLK_SWKDBCTL_SWKDBCLKSEL_2 (0x1UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 2 clocks \hideinitializer */
gustavatmel 1:9c5af431a1f1 401 #define CLK_SWKDBCTL_SWKDBCLKSEL_4 (0x2UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 4 clocks \hideinitializer */
gustavatmel 1:9c5af431a1f1 402 #define CLK_SWKDBCTL_SWKDBCLKSEL_8 (0x3UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 8 clocks \hideinitializer */
gustavatmel 1:9c5af431a1f1 403 #define CLK_SWKDBCTL_SWKDBCLKSEL_16 (0x4UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 16 clocks \hideinitializer */
gustavatmel 1:9c5af431a1f1 404 #define CLK_SWKDBCTL_SWKDBCLKSEL_32 (0x5UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 32 clocks \hideinitializer */
gustavatmel 1:9c5af431a1f1 405 #define CLK_SWKDBCTL_SWKDBCLKSEL_64 (0x6UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 64 clocks \hideinitializer */
gustavatmel 1:9c5af431a1f1 406 #define CLK_SWKDBCTL_SWKDBCLKSEL_128 (0x7UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 128 clocks \hideinitializer */
gustavatmel 1:9c5af431a1f1 407 #define CLK_SWKDBCTL_SWKDBCLKSEL_256 (0x8UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 256 clocks \hideinitializer */
gustavatmel 1:9c5af431a1f1 408 #define CLK_SWKDBCTL_SWKDBCLKSEL_2x256 (0x9UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 2x256 clocks \hideinitializer */
gustavatmel 1:9c5af431a1f1 409 #define CLK_SWKDBCTL_SWKDBCLKSEL_4x256 (0xaUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 4x256 clocks \hideinitializer */
gustavatmel 1:9c5af431a1f1 410 #define CLK_SWKDBCTL_SWKDBCLKSEL_8x256 (0xbUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 8x256 clocks \hideinitializer */
gustavatmel 1:9c5af431a1f1 411 #define CLK_SWKDBCTL_SWKDBCLKSEL_16x256 (0xcUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 16x256 clocks \hideinitializer */
gustavatmel 1:9c5af431a1f1 412 #define CLK_SWKDBCTL_SWKDBCLKSEL_32x256 (0xdUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 32x256 clocks \hideinitializer */
gustavatmel 1:9c5af431a1f1 413 #define CLK_SWKDBCTL_SWKDBCLKSEL_64x256 (0xeUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 64x256 clocks \hideinitializer */
gustavatmel 1:9c5af431a1f1 414 #define CLK_SWKDBCTL_SWKDBCLKSEL_128x256 (0xfUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 128x256 clocks \hideinitializer */
gustavatmel 1:9c5af431a1f1 415
gustavatmel 1:9c5af431a1f1 416 /*---------------------------------------------------------------------------------------------------------*/
gustavatmel 1:9c5af431a1f1 417 /* DPD Pin Rising/Falling Edge Wake-up Enable constant definitions. */
gustavatmel 1:9c5af431a1f1 418 /*---------------------------------------------------------------------------------------------------------*/
gustavatmel 1:9c5af431a1f1 419 #define CLK_DPDWKPIN_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Disable Wake-up pin at Deep Power-down mode \hideinitializer */
gustavatmel 1:9c5af431a1f1 420 #define CLK_DPDWKPIN_RISING (0x1UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin rising edge at Deep Power-down mode \hideinitializer */
gustavatmel 1:9c5af431a1f1 421 #define CLK_DPDWKPIN_FALLING (0x2UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin falling edge at Deep Power-down mode \hideinitializer */
gustavatmel 1:9c5af431a1f1 422 #define CLK_DPDWKPIN_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin both edge at Deep Power-down mode \hideinitializer */
gustavatmel 1:9c5af431a1f1 423
gustavatmel 1:9c5af431a1f1 424 /*---------------------------------------------------------------------------------------------------------*/
gustavatmel 1:9c5af431a1f1 425 /* SPD Pin Rising/Falling Edge Wake-up Enable constant definitions. */
gustavatmel 1:9c5af431a1f1 426 /*---------------------------------------------------------------------------------------------------------*/
gustavatmel 1:9c5af431a1f1 427 #define CLK_SPDWKPIN_ENABLE (0x1UL << 0) /*!< Enable Standby Power-down Pin Wake-up \hideinitializer */
gustavatmel 1:9c5af431a1f1 428 #define CLK_SPDWKPIN_RISING (0x1UL << 1) /*!< Standby Power-down Wake-up on Standby Power-down Pin rising edge \hideinitializer */
gustavatmel 1:9c5af431a1f1 429 #define CLK_SPDWKPIN_FALLING (0x1UL << 2) /*!< Standby Power-down Wake-up on Standby Power-down Pin falling edge \hideinitializer */
gustavatmel 1:9c5af431a1f1 430 #define CLK_SPDWKPIN_DEBOUNCEEN (0x1UL << 8) /*!< Enable Standby power-down pin De-bounce function \hideinitializer */
gustavatmel 1:9c5af431a1f1 431 #define CLK_SPDWKPIN_DEBOUNCEDIS (0x0UL << 8) /*!< Disable Standby power-down pin De-bounce function \hideinitializer */
gustavatmel 1:9c5af431a1f1 432
gustavatmel 1:9c5af431a1f1 433 #define CLK_DISABLE_WKTMR(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKTMREN_Msk) /*!< Disable Wake-up timer at Standby or Deep Power-down mode \hideinitializer */
gustavatmel 1:9c5af431a1f1 434 #define CLK_ENABLE_WKTMR(void) (CLK->PMUCTL |= CLK_PMUCTL_WKTMREN_Msk) /*!< Enable Wake-up timer at Standby or Deep Power-down mode \hideinitializer */
gustavatmel 1:9c5af431a1f1 435 #define CLK_DISABLE_DPDWKPIN(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN_Msk) /*!< Disable Wake-up pin at Deep Power-down mode \hideinitializer */
gustavatmel 1:9c5af431a1f1 436 #define CLK_DISABLE_SPDACMP(void) (CLK->PMUCTL &= ~CLK_PMUCTL_ACMPSPWK_Msk) /*!< Disable ACMP wake-up at Standby Power-down mode \hideinitializer */
gustavatmel 1:9c5af431a1f1 437 #define CLK_ENABLE_SPDACMP(void) (CLK->PMUCTL |= CLK_PMUCTL_ACMPSPWK_Msk) /*!< Enable ACMP wake-up at Standby Power-down mode \hideinitializer */
gustavatmel 1:9c5af431a1f1 438 #define CLK_DISABLE_RTCWK(void) (CLK->PMUCTL &= ~CLK_PMUCTL_RTCWKEN_Msk) /*!< Disable RTC Wake-up at Standby or Deep Power-down mode \hideinitializer */
gustavatmel 1:9c5af431a1f1 439 #define CLK_ENABLE_RTCWK(void) (CLK->PMUCTL |= CLK_PMUCTL_RTCWKEN_Msk) /*!< Enable RTC Wake-up at Standby or Deep Power-down mode \hideinitializer */
gustavatmel 1:9c5af431a1f1 440
gustavatmel 1:9c5af431a1f1 441 /*@}*/ /* end of group M480_CLK_EXPORTED_CONSTANTS */
gustavatmel 1:9c5af431a1f1 442
gustavatmel 1:9c5af431a1f1 443 /** @addtogroup M480_CLK_EXPORTED_FUNCTIONS CLK Exported Functions
gustavatmel 1:9c5af431a1f1 444 @{
gustavatmel 1:9c5af431a1f1 445 */
gustavatmel 1:9c5af431a1f1 446
gustavatmel 1:9c5af431a1f1 447 /**
gustavatmel 1:9c5af431a1f1 448 * @brief Set Wake-up Timer Time-out Interval
gustavatmel 1:9c5af431a1f1 449 *
gustavatmel 1:9c5af431a1f1 450 * @param[in] u32Interval The de-bounce sampling cycle selection. It could be
gustavatmel 1:9c5af431a1f1 451 * - \ref CLK_PMUCTL_WKTMRIS_128
gustavatmel 1:9c5af431a1f1 452 * - \ref CLK_PMUCTL_WKTMRIS_256
gustavatmel 1:9c5af431a1f1 453 * - \ref CLK_PMUCTL_WKTMRIS_512
gustavatmel 1:9c5af431a1f1 454 * - \ref CLK_PMUCTL_WKTMRIS_1024
gustavatmel 1:9c5af431a1f1 455 * - \ref CLK_PMUCTL_WKTMRIS_4096
gustavatmel 1:9c5af431a1f1 456 * - \ref CLK_PMUCTL_WKTMRIS_8192
gustavatmel 1:9c5af431a1f1 457 * - \ref CLK_PMUCTL_WKTMRIS_16384
gustavatmel 1:9c5af431a1f1 458 * - \ref CLK_PMUCTL_WKTMRIS_65536
gustavatmel 1:9c5af431a1f1 459 *
gustavatmel 1:9c5af431a1f1 460 * @return None
gustavatmel 1:9c5af431a1f1 461 *
gustavatmel 1:9c5af431a1f1 462 * @details This function set Wake-up Timer Time-out Interval.
gustavatmel 1:9c5af431a1f1 463 *
gustavatmel 1:9c5af431a1f1 464 * \hideinitializer
gustavatmel 1:9c5af431a1f1 465 */
gustavatmel 1:9c5af431a1f1 466 #define CLK_SET_WKTMR_INTERVAL(u32Interval) (CLK->PMUCTL |= (u32Interval))
gustavatmel 1:9c5af431a1f1 467
gustavatmel 1:9c5af431a1f1 468 /**
gustavatmel 1:9c5af431a1f1 469 * @brief Set De-bounce Sampling Cycle Time
gustavatmel 1:9c5af431a1f1 470 *
gustavatmel 1:9c5af431a1f1 471 * @param[in] u32CycleSel The de-bounce sampling cycle selection. It could be
gustavatmel 1:9c5af431a1f1 472 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_1
gustavatmel 1:9c5af431a1f1 473 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_2
gustavatmel 1:9c5af431a1f1 474 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_4
gustavatmel 1:9c5af431a1f1 475 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_8
gustavatmel 1:9c5af431a1f1 476 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_16
gustavatmel 1:9c5af431a1f1 477 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_32
gustavatmel 1:9c5af431a1f1 478 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_64
gustavatmel 1:9c5af431a1f1 479 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_128
gustavatmel 1:9c5af431a1f1 480 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_256
gustavatmel 1:9c5af431a1f1 481 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_2x256
gustavatmel 1:9c5af431a1f1 482 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_4x256
gustavatmel 1:9c5af431a1f1 483 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_8x256
gustavatmel 1:9c5af431a1f1 484 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_16x256
gustavatmel 1:9c5af431a1f1 485 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_32x256
gustavatmel 1:9c5af431a1f1 486 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_64x256
gustavatmel 1:9c5af431a1f1 487 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_128x256
gustavatmel 1:9c5af431a1f1 488 *
gustavatmel 1:9c5af431a1f1 489 * @return None
gustavatmel 1:9c5af431a1f1 490 *
gustavatmel 1:9c5af431a1f1 491 * @details This function set Set De-bounce Sampling Cycle Time.
gustavatmel 1:9c5af431a1f1 492 *
gustavatmel 1:9c5af431a1f1 493 * \hideinitializer
gustavatmel 1:9c5af431a1f1 494 */
gustavatmel 1:9c5af431a1f1 495 #define CLK_SET_SPDDEBOUNCETIME(u32CycleSel) (CLK->SWKDBCTL = (u32CycleSel))
gustavatmel 1:9c5af431a1f1 496
gustavatmel 1:9c5af431a1f1 497
gustavatmel 1:9c5af431a1f1 498
gustavatmel 1:9c5af431a1f1 499
gustavatmel 1:9c5af431a1f1 500
gustavatmel 1:9c5af431a1f1 501 /* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
gustavatmel 1:9c5af431a1f1 502 static __INLINE uint32_t CLK_GetPLLClockFreq(void);
gustavatmel 1:9c5af431a1f1 503 static __INLINE void CLK_SysTickDelay(uint32_t us);
gustavatmel 1:9c5af431a1f1 504
gustavatmel 1:9c5af431a1f1 505 /**
gustavatmel 1:9c5af431a1f1 506 * @brief Get PLL clock frequency
gustavatmel 1:9c5af431a1f1 507 * @param None
gustavatmel 1:9c5af431a1f1 508 * @return PLL frequency
gustavatmel 1:9c5af431a1f1 509 * @details This function get PLL frequency. The frequency unit is Hz.
gustavatmel 1:9c5af431a1f1 510 */
gustavatmel 1:9c5af431a1f1 511 __STATIC_INLINE uint32_t CLK_GetPLLClockFreq(void)
gustavatmel 1:9c5af431a1f1 512 {
gustavatmel 1:9c5af431a1f1 513 uint32_t u32PllFreq = 0UL, u32PllReg;
gustavatmel 1:9c5af431a1f1 514 uint32_t u32FIN, u32NF, u32NR, u32NO;
gustavatmel 1:9c5af431a1f1 515 uint8_t au8NoTbl[4] = {1U, 2U, 2U, 4U};
gustavatmel 1:9c5af431a1f1 516
gustavatmel 1:9c5af431a1f1 517 u32PllReg = CLK->PLLCTL;
gustavatmel 1:9c5af431a1f1 518
gustavatmel 1:9c5af431a1f1 519 if(u32PllReg & (CLK_PLLCTL_PD_Msk | CLK_PLLCTL_OE_Msk)) {
gustavatmel 1:9c5af431a1f1 520 u32PllFreq = 0UL; /* PLL is in power down mode or fix low */
gustavatmel 1:9c5af431a1f1 521 } else if((u32PllReg & CLK_PLLCTL_BP_Msk) == CLK_PLLCTL_BP_Msk) {
gustavatmel 1:9c5af431a1f1 522 if((u32PllReg & CLK_PLLCTL_PLLSRC_HIRC) == CLK_PLLCTL_PLLSRC_HIRC) {
gustavatmel 1:9c5af431a1f1 523 u32FIN = __HIRC; /* PLL source clock from HIRC */
gustavatmel 1:9c5af431a1f1 524 } else {
gustavatmel 1:9c5af431a1f1 525 u32FIN = __HXT; /* PLL source clock from HXT */
gustavatmel 1:9c5af431a1f1 526 }
gustavatmel 1:9c5af431a1f1 527
gustavatmel 1:9c5af431a1f1 528 u32PllFreq = u32FIN;
gustavatmel 1:9c5af431a1f1 529 } else {
gustavatmel 1:9c5af431a1f1 530 if((u32PllReg & CLK_PLLCTL_PLLSRC_HIRC) == CLK_PLLCTL_PLLSRC_HIRC) {
gustavatmel 1:9c5af431a1f1 531 u32FIN = __HIRC; /* PLL source clock from HIRC */
gustavatmel 1:9c5af431a1f1 532 } else {
gustavatmel 1:9c5af431a1f1 533 u32FIN = __HXT; /* PLL source clock from HXT */
gustavatmel 1:9c5af431a1f1 534 }
gustavatmel 1:9c5af431a1f1 535 /* PLL is output enabled in normal work mode */
gustavatmel 1:9c5af431a1f1 536 u32NO = au8NoTbl[((u32PllReg & CLK_PLLCTL_OUTDIV_Msk) >> CLK_PLLCTL_OUTDIV_Pos)];
gustavatmel 1:9c5af431a1f1 537 u32NF = ((u32PllReg & CLK_PLLCTL_FBDIV_Msk) >> CLK_PLLCTL_FBDIV_Pos) + 2UL;
gustavatmel 1:9c5af431a1f1 538 u32NR = ((u32PllReg & CLK_PLLCTL_INDIV_Msk) >> CLK_PLLCTL_INDIV_Pos) + 1UL;
gustavatmel 1:9c5af431a1f1 539
gustavatmel 1:9c5af431a1f1 540 /* u32FIN is shifted 2 bits to avoid overflow */
gustavatmel 1:9c5af431a1f1 541 u32PllFreq = (((u32FIN >> 2) * u32NF) / (u32NR * u32NO) << 2) * 2UL;
gustavatmel 1:9c5af431a1f1 542 }
gustavatmel 1:9c5af431a1f1 543
gustavatmel 1:9c5af431a1f1 544 return u32PllFreq;
gustavatmel 1:9c5af431a1f1 545 }
gustavatmel 1:9c5af431a1f1 546
gustavatmel 1:9c5af431a1f1 547 /**
gustavatmel 1:9c5af431a1f1 548 * @brief This function execute delay function.
gustavatmel 1:9c5af431a1f1 549 * @param us Delay time. The Max value is 2^24 / CPU Clock(MHz). Ex:
gustavatmel 1:9c5af431a1f1 550 * 72MHz => 233016us, 50MHz => 335544us,
gustavatmel 1:9c5af431a1f1 551 * 48MHz => 349525us, 28MHz => 699050us ...
gustavatmel 1:9c5af431a1f1 552 * @return None
gustavatmel 1:9c5af431a1f1 553 * @details Use the SysTick to generate the delay time and the unit is in us.
gustavatmel 1:9c5af431a1f1 554 * The SysTick clock source is from HCLK, i.e the same as system core clock.
gustavatmel 1:9c5af431a1f1 555 */
gustavatmel 1:9c5af431a1f1 556 __STATIC_INLINE void CLK_SysTickDelay(uint32_t us)
gustavatmel 1:9c5af431a1f1 557 {
gustavatmel 1:9c5af431a1f1 558 SysTick->LOAD = us * CyclesPerUs;
gustavatmel 1:9c5af431a1f1 559 SysTick->VAL = 0x0UL;
gustavatmel 1:9c5af431a1f1 560 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
gustavatmel 1:9c5af431a1f1 561
gustavatmel 1:9c5af431a1f1 562 /* Waiting for down-count to zero */
gustavatmel 1:9c5af431a1f1 563 while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL) {
gustavatmel 1:9c5af431a1f1 564 }
gustavatmel 1:9c5af431a1f1 565
gustavatmel 1:9c5af431a1f1 566 /* Disable SysTick counter */
gustavatmel 1:9c5af431a1f1 567 SysTick->CTRL = 0UL;
gustavatmel 1:9c5af431a1f1 568 }
gustavatmel 1:9c5af431a1f1 569
gustavatmel 1:9c5af431a1f1 570
gustavatmel 1:9c5af431a1f1 571 void CLK_DisableCKO(void);
gustavatmel 1:9c5af431a1f1 572 void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En);
gustavatmel 1:9c5af431a1f1 573 void CLK_PowerDown(void);
gustavatmel 1:9c5af431a1f1 574 void CLK_Idle(void);
gustavatmel 1:9c5af431a1f1 575 uint32_t CLK_GetHXTFreq(void);
gustavatmel 1:9c5af431a1f1 576 uint32_t CLK_GetLXTFreq(void);
gustavatmel 1:9c5af431a1f1 577 uint32_t CLK_GetHCLKFreq(void);
gustavatmel 1:9c5af431a1f1 578 uint32_t CLK_GetPCLK0Freq(void);
gustavatmel 1:9c5af431a1f1 579 uint32_t CLK_GetPCLK1Freq(void);
gustavatmel 1:9c5af431a1f1 580 uint32_t CLK_GetCPUFreq(void);
gustavatmel 1:9c5af431a1f1 581 uint32_t CLK_SetCoreClock(uint32_t u32Hclk);
gustavatmel 1:9c5af431a1f1 582 void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv);
gustavatmel 1:9c5af431a1f1 583 void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv);
gustavatmel 1:9c5af431a1f1 584 void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc);
gustavatmel 1:9c5af431a1f1 585 void CLK_EnableXtalRC(uint32_t u32ClkMask);
gustavatmel 1:9c5af431a1f1 586 void CLK_DisableXtalRC(uint32_t u32ClkMask);
gustavatmel 1:9c5af431a1f1 587 void CLK_EnableModuleClock(uint32_t u32ModuleIdx);
gustavatmel 1:9c5af431a1f1 588 void CLK_DisableModuleClock(uint32_t u32ModuleIdx);
gustavatmel 1:9c5af431a1f1 589 uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq);
gustavatmel 1:9c5af431a1f1 590 void CLK_DisablePLL(void);
gustavatmel 1:9c5af431a1f1 591 uint32_t CLK_WaitClockReady(uint32_t u32ClkMask);
gustavatmel 1:9c5af431a1f1 592 void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count);
gustavatmel 1:9c5af431a1f1 593 void CLK_DisableSysTick(void);
gustavatmel 1:9c5af431a1f1 594 void CLK_SetPowerDownMode(uint32_t u32PDMode);
gustavatmel 1:9c5af431a1f1 595 void CLK_EnableDPDWKPin(uint32_t u32TriggerType);
gustavatmel 1:9c5af431a1f1 596 uint32_t CLK_GetPMUWKSrc(void);
gustavatmel 1:9c5af431a1f1 597 void CLK_EnableSPDWKPin(uint32_t u32Port, uint32_t u32Pin, uint32_t u32TriggerType, uint32_t u32DebounceEn);
gustavatmel 1:9c5af431a1f1 598 void CLK_SetUSBModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv);
gustavatmel 1:9c5af431a1f1 599
gustavatmel 1:9c5af431a1f1 600 /*@}*/ /* end of group M480_CLK_EXPORTED_FUNCTIONS */
gustavatmel 1:9c5af431a1f1 601
gustavatmel 1:9c5af431a1f1 602 /*@}*/ /* end of group M480_CLK_Driver */
gustavatmel 1:9c5af431a1f1 603
gustavatmel 1:9c5af431a1f1 604 /*@}*/ /* end of group M480_Device_Driver */
gustavatmel 1:9c5af431a1f1 605
gustavatmel 1:9c5af431a1f1 606 #ifdef __cplusplus
gustavatmel 1:9c5af431a1f1 607 }
gustavatmel 1:9c5af431a1f1 608 #endif
gustavatmel 1:9c5af431a1f1 609
gustavatmel 1:9c5af431a1f1 610 #endif /* __CLK_H__ */
gustavatmel 1:9c5af431a1f1 611
gustavatmel 1:9c5af431a1f1 612 /*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/