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mbed-os/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_bus.h@0:02dd72d1d465, 2018-04-24 (annotated)

Committer:
borlanic
Date:
Tue Apr 24 11:45:18 2018 +0000
Revision:
0:02dd72d1d465
BaBoRo_test2 - backup 1

Who changed what in which revision?

UserRevisionLine numberNew contents of line
borlanic 0:02dd72d1d465 1 /**
borlanic 0:02dd72d1d465 2 ******************************************************************************
borlanic 0:02dd72d1d465 3 * @file stm32l1xx_ll_bus.h
borlanic 0:02dd72d1d465 4 * @author MCD Application Team
borlanic 0:02dd72d1d465 5 * @brief Header file of BUS LL module.
borlanic 0:02dd72d1d465 6
borlanic 0:02dd72d1d465 7 @verbatim
borlanic 0:02dd72d1d465 8 ##### RCC Limitations #####
borlanic 0:02dd72d1d465 9 ==============================================================================
borlanic 0:02dd72d1d465 10 [..]
borlanic 0:02dd72d1d465 11 A delay between an RCC peripheral clock enable and the effective peripheral
borlanic 0:02dd72d1d465 12 enabling should be taken into account in order to manage the peripheral read/write
borlanic 0:02dd72d1d465 13 from/to registers.
borlanic 0:02dd72d1d465 14 (+) This delay depends on the peripheral mapping.
borlanic 0:02dd72d1d465 15 (++) AHB & APB peripherals, 1 dummy read is necessary
borlanic 0:02dd72d1d465 16
borlanic 0:02dd72d1d465 17 [..]
borlanic 0:02dd72d1d465 18 Workarounds:
borlanic 0:02dd72d1d465 19 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
borlanic 0:02dd72d1d465 20 inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
borlanic 0:02dd72d1d465 21
borlanic 0:02dd72d1d465 22 @endverbatim
borlanic 0:02dd72d1d465 23 ******************************************************************************
borlanic 0:02dd72d1d465 24 * @attention
borlanic 0:02dd72d1d465 25 *
borlanic 0:02dd72d1d465 26 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
borlanic 0:02dd72d1d465 27 *
borlanic 0:02dd72d1d465 28 * Redistribution and use in source and binary forms, with or without modification,
borlanic 0:02dd72d1d465 29 * are permitted provided that the following conditions are met:
borlanic 0:02dd72d1d465 30 * 1. Redistributions of source code must retain the above copyright notice,
borlanic 0:02dd72d1d465 31 * this list of conditions and the following disclaimer.
borlanic 0:02dd72d1d465 32 * 2. Redistributions in binary form must reproduce the above copyright notice,
borlanic 0:02dd72d1d465 33 * this list of conditions and the following disclaimer in the documentation
borlanic 0:02dd72d1d465 34 * and/or other materials provided with the distribution.
borlanic 0:02dd72d1d465 35 * 3. Neither the name of STMicroelectronics nor the names of its contributors
borlanic 0:02dd72d1d465 36 * may be used to endorse or promote products derived from this software
borlanic 0:02dd72d1d465 37 * without specific prior written permission.
borlanic 0:02dd72d1d465 38 *
borlanic 0:02dd72d1d465 39 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
borlanic 0:02dd72d1d465 40 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
borlanic 0:02dd72d1d465 41 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
borlanic 0:02dd72d1d465 42 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
borlanic 0:02dd72d1d465 43 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
borlanic 0:02dd72d1d465 44 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
borlanic 0:02dd72d1d465 45 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
borlanic 0:02dd72d1d465 46 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
borlanic 0:02dd72d1d465 47 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
borlanic 0:02dd72d1d465 48 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
borlanic 0:02dd72d1d465 49 *
borlanic 0:02dd72d1d465 50 ******************************************************************************
borlanic 0:02dd72d1d465 51 */
borlanic 0:02dd72d1d465 52
borlanic 0:02dd72d1d465 53 /* Define to prevent recursive inclusion -------------------------------------*/
borlanic 0:02dd72d1d465 54 #ifndef __STM32L1xx_LL_BUS_H
borlanic 0:02dd72d1d465 55 #define __STM32L1xx_LL_BUS_H
borlanic 0:02dd72d1d465 56
borlanic 0:02dd72d1d465 57 #ifdef __cplusplus
borlanic 0:02dd72d1d465 58 extern "C" {
borlanic 0:02dd72d1d465 59 #endif
borlanic 0:02dd72d1d465 60
borlanic 0:02dd72d1d465 61 /* Includes ------------------------------------------------------------------*/
borlanic 0:02dd72d1d465 62 #include "stm32l1xx.h"
borlanic 0:02dd72d1d465 63
borlanic 0:02dd72d1d465 64 /** @addtogroup STM32L1xx_LL_Driver
borlanic 0:02dd72d1d465 65 * @{
borlanic 0:02dd72d1d465 66 */
borlanic 0:02dd72d1d465 67
borlanic 0:02dd72d1d465 68 #if defined(RCC)
borlanic 0:02dd72d1d465 69
borlanic 0:02dd72d1d465 70 /** @defgroup BUS_LL BUS
borlanic 0:02dd72d1d465 71 * @{
borlanic 0:02dd72d1d465 72 */
borlanic 0:02dd72d1d465 73
borlanic 0:02dd72d1d465 74 /* Private types -------------------------------------------------------------*/
borlanic 0:02dd72d1d465 75 /* Private variables ---------------------------------------------------------*/
borlanic 0:02dd72d1d465 76
borlanic 0:02dd72d1d465 77 /* Private constants ---------------------------------------------------------*/
borlanic 0:02dd72d1d465 78
borlanic 0:02dd72d1d465 79 /* Private macros ------------------------------------------------------------*/
borlanic 0:02dd72d1d465 80
borlanic 0:02dd72d1d465 81 /* Exported types ------------------------------------------------------------*/
borlanic 0:02dd72d1d465 82 /* Exported constants --------------------------------------------------------*/
borlanic 0:02dd72d1d465 83 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
borlanic 0:02dd72d1d465 84 * @{
borlanic 0:02dd72d1d465 85 */
borlanic 0:02dd72d1d465 86
borlanic 0:02dd72d1d465 87 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
borlanic 0:02dd72d1d465 88 * @{
borlanic 0:02dd72d1d465 89 */
borlanic 0:02dd72d1d465 90 #define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
borlanic 0:02dd72d1d465 91 #define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHBENR_GPIOAEN
borlanic 0:02dd72d1d465 92 #define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHBENR_GPIOBEN
borlanic 0:02dd72d1d465 93 #define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHBENR_GPIOCEN
borlanic 0:02dd72d1d465 94 #define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHBENR_GPIODEN
borlanic 0:02dd72d1d465 95 #if defined(GPIOE)
borlanic 0:02dd72d1d465 96 #define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHBENR_GPIOEEN
borlanic 0:02dd72d1d465 97 #endif/*GPIOE*/
borlanic 0:02dd72d1d465 98 #define LL_AHB1_GRP1_PERIPH_GPIOH RCC_AHBENR_GPIOHEN
borlanic 0:02dd72d1d465 99 #if defined(GPIOF)
borlanic 0:02dd72d1d465 100 #define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHBENR_GPIOFEN
borlanic 0:02dd72d1d465 101 #endif/*GPIOF*/
borlanic 0:02dd72d1d465 102 #if defined(GPIOG)
borlanic 0:02dd72d1d465 103 #define LL_AHB1_GRP1_PERIPH_GPIOG RCC_AHBENR_GPIOGEN
borlanic 0:02dd72d1d465 104 #endif/*GPIOG*/
borlanic 0:02dd72d1d465 105 #define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBLPENR_SRAMLPEN
borlanic 0:02dd72d1d465 106 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN
borlanic 0:02dd72d1d465 107 #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN
borlanic 0:02dd72d1d465 108 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN
borlanic 0:02dd72d1d465 109 #if defined(DMA2)
borlanic 0:02dd72d1d465 110 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN
borlanic 0:02dd72d1d465 111 #endif/*DMA2*/
borlanic 0:02dd72d1d465 112 #if defined(AES)
borlanic 0:02dd72d1d465 113 #define LL_AHB1_GRP1_PERIPH_CRYP RCC_AHBENR_AESEN
borlanic 0:02dd72d1d465 114 #endif/*AES*/
borlanic 0:02dd72d1d465 115 #if defined(FSMC_Bank1)
borlanic 0:02dd72d1d465 116 #define LL_AHB1_GRP1_PERIPH_FSMC RCC_AHBENR_FSMCEN
borlanic 0:02dd72d1d465 117 #endif/*FSMC_Bank1*/
borlanic 0:02dd72d1d465 118 /**
borlanic 0:02dd72d1d465 119 * @}
borlanic 0:02dd72d1d465 120 */
borlanic 0:02dd72d1d465 121
borlanic 0:02dd72d1d465 122 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
borlanic 0:02dd72d1d465 123 * @{
borlanic 0:02dd72d1d465 124 */
borlanic 0:02dd72d1d465 125 #define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
borlanic 0:02dd72d1d465 126 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN
borlanic 0:02dd72d1d465 127 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN
borlanic 0:02dd72d1d465 128 #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN
borlanic 0:02dd72d1d465 129 #if defined(TIM5)
borlanic 0:02dd72d1d465 130 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN
borlanic 0:02dd72d1d465 131 #endif /*TIM5*/
borlanic 0:02dd72d1d465 132 #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN
borlanic 0:02dd72d1d465 133 #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN
borlanic 0:02dd72d1d465 134 #if defined(LCD)
borlanic 0:02dd72d1d465 135 #define LL_APB1_GRP1_PERIPH_LCD RCC_APB1ENR_LCDEN
borlanic 0:02dd72d1d465 136 #endif /*LCD*/
borlanic 0:02dd72d1d465 137 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN
borlanic 0:02dd72d1d465 138 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN
borlanic 0:02dd72d1d465 139 #if defined(SPI3)
borlanic 0:02dd72d1d465 140 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN
borlanic 0:02dd72d1d465 141 #endif /*SPI3*/
borlanic 0:02dd72d1d465 142 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
borlanic 0:02dd72d1d465 143 #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN
borlanic 0:02dd72d1d465 144 #if defined(UART4)
borlanic 0:02dd72d1d465 145 #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN
borlanic 0:02dd72d1d465 146 #endif /*UART4*/
borlanic 0:02dd72d1d465 147 #if defined(UART5)
borlanic 0:02dd72d1d465 148 #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN
borlanic 0:02dd72d1d465 149 #endif /*UART5*/
borlanic 0:02dd72d1d465 150 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN
borlanic 0:02dd72d1d465 151 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
borlanic 0:02dd72d1d465 152 #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN
borlanic 0:02dd72d1d465 153 #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
borlanic 0:02dd72d1d465 154 #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN
borlanic 0:02dd72d1d465 155 #define LL_APB1_GRP1_PERIPH_COMP RCC_APB1ENR_COMPEN
borlanic 0:02dd72d1d465 156 #if defined(OPAMP)
borlanic 0:02dd72d1d465 157 /* Note: Peripherals COMP and OPAMP share the same clock domain */
borlanic 0:02dd72d1d465 158 #define LL_APB1_GRP1_PERIPH_OPAMP LL_APB1_GRP1_PERIPH_COMP
borlanic 0:02dd72d1d465 159 #endif
borlanic 0:02dd72d1d465 160 /**
borlanic 0:02dd72d1d465 161 * @}
borlanic 0:02dd72d1d465 162 */
borlanic 0:02dd72d1d465 163
borlanic 0:02dd72d1d465 164 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
borlanic 0:02dd72d1d465 165 * @{
borlanic 0:02dd72d1d465 166 */
borlanic 0:02dd72d1d465 167 #define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
borlanic 0:02dd72d1d465 168 #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
borlanic 0:02dd72d1d465 169 #define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN
borlanic 0:02dd72d1d465 170 #define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN
borlanic 0:02dd72d1d465 171 #define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN
borlanic 0:02dd72d1d465 172 #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
borlanic 0:02dd72d1d465 173 #if defined(SDIO)
borlanic 0:02dd72d1d465 174 #define LL_APB2_GRP1_PERIPH_SDIO RCC_APB2ENR_SDIOEN
borlanic 0:02dd72d1d465 175 #endif /*SDIO*/
borlanic 0:02dd72d1d465 176 #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
borlanic 0:02dd72d1d465 177 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
borlanic 0:02dd72d1d465 178 /**
borlanic 0:02dd72d1d465 179 * @}
borlanic 0:02dd72d1d465 180 */
borlanic 0:02dd72d1d465 181
borlanic 0:02dd72d1d465 182 /**
borlanic 0:02dd72d1d465 183 * @}
borlanic 0:02dd72d1d465 184 */
borlanic 0:02dd72d1d465 185
borlanic 0:02dd72d1d465 186 /* Exported macro ------------------------------------------------------------*/
borlanic 0:02dd72d1d465 187
borlanic 0:02dd72d1d465 188 /* Exported functions --------------------------------------------------------*/
borlanic 0:02dd72d1d465 189 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
borlanic 0:02dd72d1d465 190 * @{
borlanic 0:02dd72d1d465 191 */
borlanic 0:02dd72d1d465 192
borlanic 0:02dd72d1d465 193 /** @defgroup BUS_LL_EF_AHB1 AHB1
borlanic 0:02dd72d1d465 194 * @{
borlanic 0:02dd72d1d465 195 */
borlanic 0:02dd72d1d465 196
borlanic 0:02dd72d1d465 197 /**
borlanic 0:02dd72d1d465 198 * @brief Enable AHB1 peripherals clock.
borlanic 0:02dd72d1d465 199 * @rmtoll AHBENR GPIOAEN LL_AHB1_GRP1_EnableClock\n
borlanic 0:02dd72d1d465 200 * AHBENR GPIOBEN LL_AHB1_GRP1_EnableClock\n
borlanic 0:02dd72d1d465 201 * AHBENR GPIOCEN LL_AHB1_GRP1_EnableClock\n
borlanic 0:02dd72d1d465 202 * AHBENR GPIODEN LL_AHB1_GRP1_EnableClock\n
borlanic 0:02dd72d1d465 203 * AHBENR GPIOEEN LL_AHB1_GRP1_EnableClock\n
borlanic 0:02dd72d1d465 204 * AHBENR GPIOHEN LL_AHB1_GRP1_EnableClock\n
borlanic 0:02dd72d1d465 205 * AHBENR GPIOFEN LL_AHB1_GRP1_EnableClock\n
borlanic 0:02dd72d1d465 206 * AHBENR GPIOGEN LL_AHB1_GRP1_EnableClock\n
borlanic 0:02dd72d1d465 207 * AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n
borlanic 0:02dd72d1d465 208 * AHBENR FLITFEN LL_AHB1_GRP1_EnableClock\n
borlanic 0:02dd72d1d465 209 * AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n
borlanic 0:02dd72d1d465 210 * AHBENR DMA2EN LL_AHB1_GRP1_EnableClock\n
borlanic 0:02dd72d1d465 211 * AHBENR AESEN LL_AHB1_GRP1_EnableClock\n
borlanic 0:02dd72d1d465 212 * AHBENR FSMCEN LL_AHB1_GRP1_EnableClock
borlanic 0:02dd72d1d465 213 * @param Periphs This parameter can be a combination of the following values:
borlanic 0:02dd72d1d465 214 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
borlanic 0:02dd72d1d465 215 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
borlanic 0:02dd72d1d465 216 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
borlanic 0:02dd72d1d465 217 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
borlanic 0:02dd72d1d465 218 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
borlanic 0:02dd72d1d465 219 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
borlanic 0:02dd72d1d465 220 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
borlanic 0:02dd72d1d465 221 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
borlanic 0:02dd72d1d465 222 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
borlanic 0:02dd72d1d465 223 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
borlanic 0:02dd72d1d465 224 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
borlanic 0:02dd72d1d465 225 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
borlanic 0:02dd72d1d465 226 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
borlanic 0:02dd72d1d465 227 * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
borlanic 0:02dd72d1d465 228 *
borlanic 0:02dd72d1d465 229 * (*) value not defined in all devices.
borlanic 0:02dd72d1d465 230 * @retval None
borlanic 0:02dd72d1d465 231 */
borlanic 0:02dd72d1d465 232 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
borlanic 0:02dd72d1d465 233 {
borlanic 0:02dd72d1d465 234 __IO uint32_t tmpreg;
borlanic 0:02dd72d1d465 235 SET_BIT(RCC->AHBENR, Periphs);
borlanic 0:02dd72d1d465 236 /* Delay after an RCC peripheral clock enabling */
borlanic 0:02dd72d1d465 237 tmpreg = READ_BIT(RCC->AHBENR, Periphs);
borlanic 0:02dd72d1d465 238 (void)tmpreg;
borlanic 0:02dd72d1d465 239 }
borlanic 0:02dd72d1d465 240
borlanic 0:02dd72d1d465 241 /**
borlanic 0:02dd72d1d465 242 * @brief Check if AHB1 peripheral clock is enabled or not
borlanic 0:02dd72d1d465 243 * @rmtoll AHBENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n
borlanic 0:02dd72d1d465 244 * AHBENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n
borlanic 0:02dd72d1d465 245 * AHBENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n
borlanic 0:02dd72d1d465 246 * AHBENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n
borlanic 0:02dd72d1d465 247 * AHBENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n
borlanic 0:02dd72d1d465 248 * AHBENR GPIOHEN LL_AHB1_GRP1_IsEnabledClock\n
borlanic 0:02dd72d1d465 249 * AHBENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n
borlanic 0:02dd72d1d465 250 * AHBENR GPIOGEN LL_AHB1_GRP1_IsEnabledClock\n
borlanic 0:02dd72d1d465 251 * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
borlanic 0:02dd72d1d465 252 * AHBENR FLITFEN LL_AHB1_GRP1_IsEnabledClock\n
borlanic 0:02dd72d1d465 253 * AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
borlanic 0:02dd72d1d465 254 * AHBENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
borlanic 0:02dd72d1d465 255 * AHBENR AESEN LL_AHB1_GRP1_IsEnabledClock\n
borlanic 0:02dd72d1d465 256 * AHBENR FSMCEN LL_AHB1_GRP1_IsEnabledClock
borlanic 0:02dd72d1d465 257 * @param Periphs This parameter can be a combination of the following values:
borlanic 0:02dd72d1d465 258 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
borlanic 0:02dd72d1d465 259 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
borlanic 0:02dd72d1d465 260 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
borlanic 0:02dd72d1d465 261 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
borlanic 0:02dd72d1d465 262 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
borlanic 0:02dd72d1d465 263 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
borlanic 0:02dd72d1d465 264 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
borlanic 0:02dd72d1d465 265 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
borlanic 0:02dd72d1d465 266 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
borlanic 0:02dd72d1d465 267 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
borlanic 0:02dd72d1d465 268 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
borlanic 0:02dd72d1d465 269 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
borlanic 0:02dd72d1d465 270 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
borlanic 0:02dd72d1d465 271 * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
borlanic 0:02dd72d1d465 272 *
borlanic 0:02dd72d1d465 273 * (*) value not defined in all devices.
borlanic 0:02dd72d1d465 274 * @retval State of Periphs (1 or 0).
borlanic 0:02dd72d1d465 275 */
borlanic 0:02dd72d1d465 276 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
borlanic 0:02dd72d1d465 277 {
borlanic 0:02dd72d1d465 278 return (READ_BIT(RCC->AHBENR, Periphs) == Periphs);
borlanic 0:02dd72d1d465 279 }
borlanic 0:02dd72d1d465 280
borlanic 0:02dd72d1d465 281 /**
borlanic 0:02dd72d1d465 282 * @brief Disable AHB1 peripherals clock.
borlanic 0:02dd72d1d465 283 * @rmtoll AHBENR GPIOAEN LL_AHB1_GRP1_DisableClock\n
borlanic 0:02dd72d1d465 284 * AHBENR GPIOBEN LL_AHB1_GRP1_DisableClock\n
borlanic 0:02dd72d1d465 285 * AHBENR GPIOCEN LL_AHB1_GRP1_DisableClock\n
borlanic 0:02dd72d1d465 286 * AHBENR GPIODEN LL_AHB1_GRP1_DisableClock\n
borlanic 0:02dd72d1d465 287 * AHBENR GPIOEEN LL_AHB1_GRP1_DisableClock\n
borlanic 0:02dd72d1d465 288 * AHBENR GPIOHEN LL_AHB1_GRP1_DisableClock\n
borlanic 0:02dd72d1d465 289 * AHBENR GPIOFEN LL_AHB1_GRP1_DisableClock\n
borlanic 0:02dd72d1d465 290 * AHBENR GPIOGEN LL_AHB1_GRP1_DisableClock\n
borlanic 0:02dd72d1d465 291 * AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n
borlanic 0:02dd72d1d465 292 * AHBENR FLITFEN LL_AHB1_GRP1_DisableClock\n
borlanic 0:02dd72d1d465 293 * AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n
borlanic 0:02dd72d1d465 294 * AHBENR DMA2EN LL_AHB1_GRP1_DisableClock\n
borlanic 0:02dd72d1d465 295 * AHBENR AESEN LL_AHB1_GRP1_DisableClock\n
borlanic 0:02dd72d1d465 296 * AHBENR FSMCEN LL_AHB1_GRP1_DisableClock
borlanic 0:02dd72d1d465 297 * @param Periphs This parameter can be a combination of the following values:
borlanic 0:02dd72d1d465 298 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
borlanic 0:02dd72d1d465 299 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
borlanic 0:02dd72d1d465 300 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
borlanic 0:02dd72d1d465 301 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
borlanic 0:02dd72d1d465 302 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
borlanic 0:02dd72d1d465 303 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
borlanic 0:02dd72d1d465 304 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
borlanic 0:02dd72d1d465 305 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
borlanic 0:02dd72d1d465 306 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
borlanic 0:02dd72d1d465 307 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
borlanic 0:02dd72d1d465 308 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
borlanic 0:02dd72d1d465 309 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
borlanic 0:02dd72d1d465 310 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
borlanic 0:02dd72d1d465 311 * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
borlanic 0:02dd72d1d465 312 *
borlanic 0:02dd72d1d465 313 * (*) value not defined in all devices.
borlanic 0:02dd72d1d465 314 * @retval None
borlanic 0:02dd72d1d465 315 */
borlanic 0:02dd72d1d465 316 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
borlanic 0:02dd72d1d465 317 {
borlanic 0:02dd72d1d465 318 CLEAR_BIT(RCC->AHBENR, Periphs);
borlanic 0:02dd72d1d465 319 }
borlanic 0:02dd72d1d465 320
borlanic 0:02dd72d1d465 321 /**
borlanic 0:02dd72d1d465 322 * @brief Force AHB1 peripherals reset.
borlanic 0:02dd72d1d465 323 * @rmtoll AHBRSTR GPIOARST LL_AHB1_GRP1_ForceReset\n
borlanic 0:02dd72d1d465 324 * AHBRSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n
borlanic 0:02dd72d1d465 325 * AHBRSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n
borlanic 0:02dd72d1d465 326 * AHBRSTR GPIODRST LL_AHB1_GRP1_ForceReset\n
borlanic 0:02dd72d1d465 327 * AHBRSTR GPIOERST LL_AHB1_GRP1_ForceReset\n
borlanic 0:02dd72d1d465 328 * AHBRSTR GPIOHRST LL_AHB1_GRP1_ForceReset\n
borlanic 0:02dd72d1d465 329 * AHBRSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n
borlanic 0:02dd72d1d465 330 * AHBRSTR GPIOGRST LL_AHB1_GRP1_ForceReset\n
borlanic 0:02dd72d1d465 331 * AHBRSTR CRCRST LL_AHB1_GRP1_ForceReset\n
borlanic 0:02dd72d1d465 332 * AHBRSTR FLITFRST LL_AHB1_GRP1_ForceReset\n
borlanic 0:02dd72d1d465 333 * AHBRSTR DMA1RST LL_AHB1_GRP1_ForceReset\n
borlanic 0:02dd72d1d465 334 * AHBRSTR DMA2RST LL_AHB1_GRP1_ForceReset\n
borlanic 0:02dd72d1d465 335 * AHBRSTR AESRST LL_AHB1_GRP1_ForceReset\n
borlanic 0:02dd72d1d465 336 * AHBRSTR FSMCRST LL_AHB1_GRP1_ForceReset
borlanic 0:02dd72d1d465 337 * @param Periphs This parameter can be a combination of the following values:
borlanic 0:02dd72d1d465 338 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
borlanic 0:02dd72d1d465 339 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
borlanic 0:02dd72d1d465 340 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
borlanic 0:02dd72d1d465 341 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
borlanic 0:02dd72d1d465 342 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
borlanic 0:02dd72d1d465 343 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
borlanic 0:02dd72d1d465 344 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
borlanic 0:02dd72d1d465 345 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
borlanic 0:02dd72d1d465 346 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
borlanic 0:02dd72d1d465 347 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
borlanic 0:02dd72d1d465 348 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
borlanic 0:02dd72d1d465 349 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
borlanic 0:02dd72d1d465 350 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
borlanic 0:02dd72d1d465 351 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
borlanic 0:02dd72d1d465 352 * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
borlanic 0:02dd72d1d465 353 *
borlanic 0:02dd72d1d465 354 * (*) value not defined in all devices.
borlanic 0:02dd72d1d465 355 * @retval None
borlanic 0:02dd72d1d465 356 */
borlanic 0:02dd72d1d465 357 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
borlanic 0:02dd72d1d465 358 {
borlanic 0:02dd72d1d465 359 SET_BIT(RCC->AHBRSTR, Periphs);
borlanic 0:02dd72d1d465 360 }
borlanic 0:02dd72d1d465 361
borlanic 0:02dd72d1d465 362 /**
borlanic 0:02dd72d1d465 363 * @brief Release AHB1 peripherals reset.
borlanic 0:02dd72d1d465 364 * @rmtoll AHBRSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n
borlanic 0:02dd72d1d465 365 * AHBRSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n
borlanic 0:02dd72d1d465 366 * AHBRSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n
borlanic 0:02dd72d1d465 367 * AHBRSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n
borlanic 0:02dd72d1d465 368 * AHBRSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n
borlanic 0:02dd72d1d465 369 * AHBRSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset\n
borlanic 0:02dd72d1d465 370 * AHBRSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n
borlanic 0:02dd72d1d465 371 * AHBRSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset\n
borlanic 0:02dd72d1d465 372 * AHBRSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n
borlanic 0:02dd72d1d465 373 * AHBRSTR FLITFRST LL_AHB1_GRP1_ReleaseReset\n
borlanic 0:02dd72d1d465 374 * AHBRSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n
borlanic 0:02dd72d1d465 375 * AHBRSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n
borlanic 0:02dd72d1d465 376 * AHBRSTR AESRST LL_AHB1_GRP1_ReleaseReset\n
borlanic 0:02dd72d1d465 377 * AHBRSTR FSMCRST LL_AHB1_GRP1_ReleaseReset
borlanic 0:02dd72d1d465 378 * @param Periphs This parameter can be a combination of the following values:
borlanic 0:02dd72d1d465 379 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
borlanic 0:02dd72d1d465 380 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
borlanic 0:02dd72d1d465 381 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
borlanic 0:02dd72d1d465 382 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
borlanic 0:02dd72d1d465 383 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
borlanic 0:02dd72d1d465 384 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
borlanic 0:02dd72d1d465 385 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
borlanic 0:02dd72d1d465 386 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
borlanic 0:02dd72d1d465 387 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
borlanic 0:02dd72d1d465 388 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
borlanic 0:02dd72d1d465 389 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
borlanic 0:02dd72d1d465 390 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
borlanic 0:02dd72d1d465 391 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
borlanic 0:02dd72d1d465 392 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
borlanic 0:02dd72d1d465 393 * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
borlanic 0:02dd72d1d465 394 *
borlanic 0:02dd72d1d465 395 * (*) value not defined in all devices.
borlanic 0:02dd72d1d465 396 * @retval None
borlanic 0:02dd72d1d465 397 */
borlanic 0:02dd72d1d465 398 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
borlanic 0:02dd72d1d465 399 {
borlanic 0:02dd72d1d465 400 CLEAR_BIT(RCC->AHBRSTR, Periphs);
borlanic 0:02dd72d1d465 401 }
borlanic 0:02dd72d1d465 402
borlanic 0:02dd72d1d465 403 /**
borlanic 0:02dd72d1d465 404 * @brief Enable AHB1 peripherals clock during Low Power (Sleep) mode.
borlanic 0:02dd72d1d465 405 * @rmtoll AHBLPENR GPIOALPEN LL_AHB1_GRP1_EnableClockSleep\n
borlanic 0:02dd72d1d465 406 * AHBLPENR GPIOBLPEN LL_AHB1_GRP1_EnableClockSleep\n
borlanic 0:02dd72d1d465 407 * AHBLPENR GPIOCLPEN LL_AHB1_GRP1_EnableClockSleep\n
borlanic 0:02dd72d1d465 408 * AHBLPENR GPIODLPEN LL_AHB1_GRP1_EnableClockSleep\n
borlanic 0:02dd72d1d465 409 * AHBLPENR GPIOELPEN LL_AHB1_GRP1_EnableClockSleep\n
borlanic 0:02dd72d1d465 410 * AHBLPENR GPIOHLPEN LL_AHB1_GRP1_EnableClockSleep\n
borlanic 0:02dd72d1d465 411 * AHBLPENR GPIOFLPEN LL_AHB1_GRP1_EnableClockSleep\n
borlanic 0:02dd72d1d465 412 * AHBLPENR GPIOGLPEN LL_AHB1_GRP1_EnableClockSleep\n
borlanic 0:02dd72d1d465 413 * AHBLPENR CRCLPEN LL_AHB1_GRP1_EnableClockSleep\n
borlanic 0:02dd72d1d465 414 * AHBLPENR FLITFLPEN LL_AHB1_GRP1_EnableClockSleep\n
borlanic 0:02dd72d1d465 415 * AHBLPENR SRAMLPEN LL_AHB1_GRP1_EnableClockSleep\n
borlanic 0:02dd72d1d465 416 * AHBLPENR DMA1LPEN LL_AHB1_GRP1_EnableClockSleep\n
borlanic 0:02dd72d1d465 417 * AHBLPENR DMA2LPEN LL_AHB1_GRP1_EnableClockSleep\n
borlanic 0:02dd72d1d465 418 * AHBLPENR AESLPEN LL_AHB1_GRP1_EnableClockSleep\n
borlanic 0:02dd72d1d465 419 * AHBLPENR FSMCLPEN LL_AHB1_GRP1_EnableClockSleep
borlanic 0:02dd72d1d465 420 * @param Periphs This parameter can be a combination of the following values:
borlanic 0:02dd72d1d465 421 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
borlanic 0:02dd72d1d465 422 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
borlanic 0:02dd72d1d465 423 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
borlanic 0:02dd72d1d465 424 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
borlanic 0:02dd72d1d465 425 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
borlanic 0:02dd72d1d465 426 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
borlanic 0:02dd72d1d465 427 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
borlanic 0:02dd72d1d465 428 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
borlanic 0:02dd72d1d465 429 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
borlanic 0:02dd72d1d465 430 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
borlanic 0:02dd72d1d465 431 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
borlanic 0:02dd72d1d465 432 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
borlanic 0:02dd72d1d465 433 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
borlanic 0:02dd72d1d465 434 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
borlanic 0:02dd72d1d465 435 * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
borlanic 0:02dd72d1d465 436 *
borlanic 0:02dd72d1d465 437 * (*) value not defined in all devices.
borlanic 0:02dd72d1d465 438 * @retval None
borlanic 0:02dd72d1d465 439 */
borlanic 0:02dd72d1d465 440 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)
borlanic 0:02dd72d1d465 441 {
borlanic 0:02dd72d1d465 442 __IO uint32_t tmpreg;
borlanic 0:02dd72d1d465 443 SET_BIT(RCC->AHBLPENR, Periphs);
borlanic 0:02dd72d1d465 444 /* Delay after an RCC peripheral clock enabling */
borlanic 0:02dd72d1d465 445 tmpreg = READ_BIT(RCC->AHBLPENR, Periphs);
borlanic 0:02dd72d1d465 446 (void)tmpreg;
borlanic 0:02dd72d1d465 447 }
borlanic 0:02dd72d1d465 448
borlanic 0:02dd72d1d465 449 /**
borlanic 0:02dd72d1d465 450 * @brief Disable AHB1 peripherals clock during Low Power (Sleep) mode.
borlanic 0:02dd72d1d465 451 * @rmtoll AHBLPENR GPIOALPEN LL_AHB1_GRP1_DisableClockSleep\n
borlanic 0:02dd72d1d465 452 * AHBLPENR GPIOBLPEN LL_AHB1_GRP1_DisableClockSleep\n
borlanic 0:02dd72d1d465 453 * AHBLPENR GPIOCLPEN LL_AHB1_GRP1_DisableClockSleep\n
borlanic 0:02dd72d1d465 454 * AHBLPENR GPIODLPEN LL_AHB1_GRP1_DisableClockSleep\n
borlanic 0:02dd72d1d465 455 * AHBLPENR GPIOELPEN LL_AHB1_GRP1_DisableClockSleep\n
borlanic 0:02dd72d1d465 456 * AHBLPENR GPIOHLPEN LL_AHB1_GRP1_DisableClockSleep\n
borlanic 0:02dd72d1d465 457 * AHBLPENR GPIOFLPEN LL_AHB1_GRP1_DisableClockSleep\n
borlanic 0:02dd72d1d465 458 * AHBLPENR GPIOGLPEN LL_AHB1_GRP1_DisableClockSleep\n
borlanic 0:02dd72d1d465 459 * AHBLPENR CRCLPEN LL_AHB1_GRP1_DisableClockSleep\n
borlanic 0:02dd72d1d465 460 * AHBLPENR FLITFLPEN LL_AHB1_GRP1_DisableClockSleep\n
borlanic 0:02dd72d1d465 461 * AHBLPENR SRAMLPEN LL_AHB1_GRP1_DisableClockSleep\n
borlanic 0:02dd72d1d465 462 * AHBLPENR DMA1LPEN LL_AHB1_GRP1_DisableClockSleep\n
borlanic 0:02dd72d1d465 463 * AHBLPENR DMA2LPEN LL_AHB1_GRP1_DisableClockSleep\n
borlanic 0:02dd72d1d465 464 * AHBLPENR AESLPEN LL_AHB1_GRP1_DisableClockSleep\n
borlanic 0:02dd72d1d465 465 * AHBLPENR FSMCLPEN LL_AHB1_GRP1_DisableClockSleep
borlanic 0:02dd72d1d465 466 * @param Periphs This parameter can be a combination of the following values:
borlanic 0:02dd72d1d465 467 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
borlanic 0:02dd72d1d465 468 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
borlanic 0:02dd72d1d465 469 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
borlanic 0:02dd72d1d465 470 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
borlanic 0:02dd72d1d465 471 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
borlanic 0:02dd72d1d465 472 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
borlanic 0:02dd72d1d465 473 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
borlanic 0:02dd72d1d465 474 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
borlanic 0:02dd72d1d465 475 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
borlanic 0:02dd72d1d465 476 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
borlanic 0:02dd72d1d465 477 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
borlanic 0:02dd72d1d465 478 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
borlanic 0:02dd72d1d465 479 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
borlanic 0:02dd72d1d465 480 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
borlanic 0:02dd72d1d465 481 * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
borlanic 0:02dd72d1d465 482 *
borlanic 0:02dd72d1d465 483 * (*) value not defined in all devices.
borlanic 0:02dd72d1d465 484 * @retval None
borlanic 0:02dd72d1d465 485 */
borlanic 0:02dd72d1d465 486 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)
borlanic 0:02dd72d1d465 487 {
borlanic 0:02dd72d1d465 488 CLEAR_BIT(RCC->AHBLPENR, Periphs);
borlanic 0:02dd72d1d465 489 }
borlanic 0:02dd72d1d465 490
borlanic 0:02dd72d1d465 491 /**
borlanic 0:02dd72d1d465 492 * @}
borlanic 0:02dd72d1d465 493 */
borlanic 0:02dd72d1d465 494
borlanic 0:02dd72d1d465 495 /** @defgroup BUS_LL_EF_APB1 APB1
borlanic 0:02dd72d1d465 496 * @{
borlanic 0:02dd72d1d465 497 */
borlanic 0:02dd72d1d465 498
borlanic 0:02dd72d1d465 499 /**
borlanic 0:02dd72d1d465 500 * @brief Enable APB1 peripherals clock.
borlanic 0:02dd72d1d465 501 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n
borlanic 0:02dd72d1d465 502 * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n
borlanic 0:02dd72d1d465 503 * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n
borlanic 0:02dd72d1d465 504 * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n
borlanic 0:02dd72d1d465 505 * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n
borlanic 0:02dd72d1d465 506 * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n
borlanic 0:02dd72d1d465 507 * APB1ENR LCDEN LL_APB1_GRP1_EnableClock\n
borlanic 0:02dd72d1d465 508 * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n
borlanic 0:02dd72d1d465 509 * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n
borlanic 0:02dd72d1d465 510 * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n
borlanic 0:02dd72d1d465 511 * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n
borlanic 0:02dd72d1d465 512 * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n
borlanic 0:02dd72d1d465 513 * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n
borlanic 0:02dd72d1d465 514 * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n
borlanic 0:02dd72d1d465 515 * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n
borlanic 0:02dd72d1d465 516 * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n
borlanic 0:02dd72d1d465 517 * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n
borlanic 0:02dd72d1d465 518 * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n
borlanic 0:02dd72d1d465 519 * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n
borlanic 0:02dd72d1d465 520 * APB1ENR COMPEN LL_APB1_GRP1_EnableClock
borlanic 0:02dd72d1d465 521 * @param Periphs This parameter can be a combination of the following values:
borlanic 0:02dd72d1d465 522 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
borlanic 0:02dd72d1d465 523 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
borlanic 0:02dd72d1d465 524 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
borlanic 0:02dd72d1d465 525 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
borlanic 0:02dd72d1d465 526 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
borlanic 0:02dd72d1d465 527 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
borlanic 0:02dd72d1d465 528 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
borlanic 0:02dd72d1d465 529 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
borlanic 0:02dd72d1d465 530 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
borlanic 0:02dd72d1d465 531 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
borlanic 0:02dd72d1d465 532 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
borlanic 0:02dd72d1d465 533 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
borlanic 0:02dd72d1d465 534 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
borlanic 0:02dd72d1d465 535 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
borlanic 0:02dd72d1d465 536 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
borlanic 0:02dd72d1d465 537 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
borlanic 0:02dd72d1d465 538 * @arg @ref LL_APB1_GRP1_PERIPH_USB
borlanic 0:02dd72d1d465 539 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
borlanic 0:02dd72d1d465 540 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
borlanic 0:02dd72d1d465 541 * @arg @ref LL_APB1_GRP1_PERIPH_COMP
borlanic 0:02dd72d1d465 542 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
borlanic 0:02dd72d1d465 543 *
borlanic 0:02dd72d1d465 544 * (*) value not defined in all devices.
borlanic 0:02dd72d1d465 545 * @retval None
borlanic 0:02dd72d1d465 546 */
borlanic 0:02dd72d1d465 547 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
borlanic 0:02dd72d1d465 548 {
borlanic 0:02dd72d1d465 549 __IO uint32_t tmpreg;
borlanic 0:02dd72d1d465 550 SET_BIT(RCC->APB1ENR, Periphs);
borlanic 0:02dd72d1d465 551 /* Delay after an RCC peripheral clock enabling */
borlanic 0:02dd72d1d465 552 tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
borlanic 0:02dd72d1d465 553 (void)tmpreg;
borlanic 0:02dd72d1d465 554 }
borlanic 0:02dd72d1d465 555
borlanic 0:02dd72d1d465 556 /**
borlanic 0:02dd72d1d465 557 * @brief Check if APB1 peripheral clock is enabled or not
borlanic 0:02dd72d1d465 558 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n
borlanic 0:02dd72d1d465 559 * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n
borlanic 0:02dd72d1d465 560 * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n
borlanic 0:02dd72d1d465 561 * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n
borlanic 0:02dd72d1d465 562 * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n
borlanic 0:02dd72d1d465 563 * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n
borlanic 0:02dd72d1d465 564 * APB1ENR LCDEN LL_APB1_GRP1_IsEnabledClock\n
borlanic 0:02dd72d1d465 565 * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n
borlanic 0:02dd72d1d465 566 * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n
borlanic 0:02dd72d1d465 567 * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n
borlanic 0:02dd72d1d465 568 * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n
borlanic 0:02dd72d1d465 569 * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n
borlanic 0:02dd72d1d465 570 * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n
borlanic 0:02dd72d1d465 571 * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n
borlanic 0:02dd72d1d465 572 * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n
borlanic 0:02dd72d1d465 573 * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n
borlanic 0:02dd72d1d465 574 * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n
borlanic 0:02dd72d1d465 575 * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n
borlanic 0:02dd72d1d465 576 * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n
borlanic 0:02dd72d1d465 577 * APB1ENR COMPEN LL_APB1_GRP1_IsEnabledClock
borlanic 0:02dd72d1d465 578 * @param Periphs This parameter can be a combination of the following values:
borlanic 0:02dd72d1d465 579 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
borlanic 0:02dd72d1d465 580 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
borlanic 0:02dd72d1d465 581 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
borlanic 0:02dd72d1d465 582 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
borlanic 0:02dd72d1d465 583 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
borlanic 0:02dd72d1d465 584 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
borlanic 0:02dd72d1d465 585 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
borlanic 0:02dd72d1d465 586 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
borlanic 0:02dd72d1d465 587 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
borlanic 0:02dd72d1d465 588 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
borlanic 0:02dd72d1d465 589 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
borlanic 0:02dd72d1d465 590 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
borlanic 0:02dd72d1d465 591 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
borlanic 0:02dd72d1d465 592 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
borlanic 0:02dd72d1d465 593 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
borlanic 0:02dd72d1d465 594 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
borlanic 0:02dd72d1d465 595 * @arg @ref LL_APB1_GRP1_PERIPH_USB
borlanic 0:02dd72d1d465 596 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
borlanic 0:02dd72d1d465 597 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
borlanic 0:02dd72d1d465 598 * @arg @ref LL_APB1_GRP1_PERIPH_COMP
borlanic 0:02dd72d1d465 599 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
borlanic 0:02dd72d1d465 600 *
borlanic 0:02dd72d1d465 601 * (*) value not defined in all devices.
borlanic 0:02dd72d1d465 602 * @retval State of Periphs (1 or 0).
borlanic 0:02dd72d1d465 603 */
borlanic 0:02dd72d1d465 604 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
borlanic 0:02dd72d1d465 605 {
borlanic 0:02dd72d1d465 606 return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs);
borlanic 0:02dd72d1d465 607 }
borlanic 0:02dd72d1d465 608
borlanic 0:02dd72d1d465 609 /**
borlanic 0:02dd72d1d465 610 * @brief Disable APB1 peripherals clock.
borlanic 0:02dd72d1d465 611 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n
borlanic 0:02dd72d1d465 612 * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n
borlanic 0:02dd72d1d465 613 * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n
borlanic 0:02dd72d1d465 614 * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n
borlanic 0:02dd72d1d465 615 * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n
borlanic 0:02dd72d1d465 616 * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n
borlanic 0:02dd72d1d465 617 * APB1ENR LCDEN LL_APB1_GRP1_DisableClock\n
borlanic 0:02dd72d1d465 618 * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n
borlanic 0:02dd72d1d465 619 * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n
borlanic 0:02dd72d1d465 620 * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n
borlanic 0:02dd72d1d465 621 * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n
borlanic 0:02dd72d1d465 622 * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n
borlanic 0:02dd72d1d465 623 * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n
borlanic 0:02dd72d1d465 624 * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n
borlanic 0:02dd72d1d465 625 * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n
borlanic 0:02dd72d1d465 626 * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n
borlanic 0:02dd72d1d465 627 * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n
borlanic 0:02dd72d1d465 628 * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n
borlanic 0:02dd72d1d465 629 * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n
borlanic 0:02dd72d1d465 630 * APB1ENR COMPEN LL_APB1_GRP1_DisableClock
borlanic 0:02dd72d1d465 631 * @param Periphs This parameter can be a combination of the following values:
borlanic 0:02dd72d1d465 632 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
borlanic 0:02dd72d1d465 633 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
borlanic 0:02dd72d1d465 634 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
borlanic 0:02dd72d1d465 635 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
borlanic 0:02dd72d1d465 636 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
borlanic 0:02dd72d1d465 637 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
borlanic 0:02dd72d1d465 638 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
borlanic 0:02dd72d1d465 639 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
borlanic 0:02dd72d1d465 640 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
borlanic 0:02dd72d1d465 641 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
borlanic 0:02dd72d1d465 642 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
borlanic 0:02dd72d1d465 643 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
borlanic 0:02dd72d1d465 644 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
borlanic 0:02dd72d1d465 645 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
borlanic 0:02dd72d1d465 646 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
borlanic 0:02dd72d1d465 647 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
borlanic 0:02dd72d1d465 648 * @arg @ref LL_APB1_GRP1_PERIPH_USB
borlanic 0:02dd72d1d465 649 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
borlanic 0:02dd72d1d465 650 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
borlanic 0:02dd72d1d465 651 * @arg @ref LL_APB1_GRP1_PERIPH_COMP
borlanic 0:02dd72d1d465 652 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
borlanic 0:02dd72d1d465 653 *
borlanic 0:02dd72d1d465 654 * (*) value not defined in all devices.
borlanic 0:02dd72d1d465 655 * @retval None
borlanic 0:02dd72d1d465 656 */
borlanic 0:02dd72d1d465 657 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
borlanic 0:02dd72d1d465 658 {
borlanic 0:02dd72d1d465 659 CLEAR_BIT(RCC->APB1ENR, Periphs);
borlanic 0:02dd72d1d465 660 }
borlanic 0:02dd72d1d465 661
borlanic 0:02dd72d1d465 662 /**
borlanic 0:02dd72d1d465 663 * @brief Force APB1 peripherals reset.
borlanic 0:02dd72d1d465 664 * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n
borlanic 0:02dd72d1d465 665 * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n
borlanic 0:02dd72d1d465 666 * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n
borlanic 0:02dd72d1d465 667 * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n
borlanic 0:02dd72d1d465 668 * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n
borlanic 0:02dd72d1d465 669 * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n
borlanic 0:02dd72d1d465 670 * APB1RSTR LCDRST LL_APB1_GRP1_ForceReset\n
borlanic 0:02dd72d1d465 671 * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n
borlanic 0:02dd72d1d465 672 * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n
borlanic 0:02dd72d1d465 673 * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n
borlanic 0:02dd72d1d465 674 * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n
borlanic 0:02dd72d1d465 675 * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n
borlanic 0:02dd72d1d465 676 * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n
borlanic 0:02dd72d1d465 677 * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n
borlanic 0:02dd72d1d465 678 * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n
borlanic 0:02dd72d1d465 679 * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n
borlanic 0:02dd72d1d465 680 * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n
borlanic 0:02dd72d1d465 681 * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n
borlanic 0:02dd72d1d465 682 * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n
borlanic 0:02dd72d1d465 683 * APB1RSTR COMPRST LL_APB1_GRP1_ForceReset
borlanic 0:02dd72d1d465 684 * @param Periphs This parameter can be a combination of the following values:
borlanic 0:02dd72d1d465 685 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
borlanic 0:02dd72d1d465 686 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
borlanic 0:02dd72d1d465 687 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
borlanic 0:02dd72d1d465 688 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
borlanic 0:02dd72d1d465 689 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
borlanic 0:02dd72d1d465 690 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
borlanic 0:02dd72d1d465 691 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
borlanic 0:02dd72d1d465 692 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
borlanic 0:02dd72d1d465 693 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
borlanic 0:02dd72d1d465 694 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
borlanic 0:02dd72d1d465 695 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
borlanic 0:02dd72d1d465 696 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
borlanic 0:02dd72d1d465 697 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
borlanic 0:02dd72d1d465 698 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
borlanic 0:02dd72d1d465 699 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
borlanic 0:02dd72d1d465 700 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
borlanic 0:02dd72d1d465 701 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
borlanic 0:02dd72d1d465 702 * @arg @ref LL_APB1_GRP1_PERIPH_USB
borlanic 0:02dd72d1d465 703 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
borlanic 0:02dd72d1d465 704 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
borlanic 0:02dd72d1d465 705 * @arg @ref LL_APB1_GRP1_PERIPH_COMP
borlanic 0:02dd72d1d465 706 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
borlanic 0:02dd72d1d465 707 *
borlanic 0:02dd72d1d465 708 * (*) value not defined in all devices.
borlanic 0:02dd72d1d465 709 * @retval None
borlanic 0:02dd72d1d465 710 */
borlanic 0:02dd72d1d465 711 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
borlanic 0:02dd72d1d465 712 {
borlanic 0:02dd72d1d465 713 SET_BIT(RCC->APB1RSTR, Periphs);
borlanic 0:02dd72d1d465 714 }
borlanic 0:02dd72d1d465 715
borlanic 0:02dd72d1d465 716 /**
borlanic 0:02dd72d1d465 717 * @brief Release APB1 peripherals reset.
borlanic 0:02dd72d1d465 718 * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n
borlanic 0:02dd72d1d465 719 * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n
borlanic 0:02dd72d1d465 720 * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n
borlanic 0:02dd72d1d465 721 * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n
borlanic 0:02dd72d1d465 722 * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n
borlanic 0:02dd72d1d465 723 * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n
borlanic 0:02dd72d1d465 724 * APB1RSTR LCDRST LL_APB1_GRP1_ReleaseReset\n
borlanic 0:02dd72d1d465 725 * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n
borlanic 0:02dd72d1d465 726 * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n
borlanic 0:02dd72d1d465 727 * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n
borlanic 0:02dd72d1d465 728 * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n
borlanic 0:02dd72d1d465 729 * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n
borlanic 0:02dd72d1d465 730 * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n
borlanic 0:02dd72d1d465 731 * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n
borlanic 0:02dd72d1d465 732 * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n
borlanic 0:02dd72d1d465 733 * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n
borlanic 0:02dd72d1d465 734 * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n
borlanic 0:02dd72d1d465 735 * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n
borlanic 0:02dd72d1d465 736 * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n
borlanic 0:02dd72d1d465 737 * APB1RSTR COMPRST LL_APB1_GRP1_ReleaseReset
borlanic 0:02dd72d1d465 738 * @param Periphs This parameter can be a combination of the following values:
borlanic 0:02dd72d1d465 739 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
borlanic 0:02dd72d1d465 740 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
borlanic 0:02dd72d1d465 741 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
borlanic 0:02dd72d1d465 742 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
borlanic 0:02dd72d1d465 743 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
borlanic 0:02dd72d1d465 744 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
borlanic 0:02dd72d1d465 745 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
borlanic 0:02dd72d1d465 746 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
borlanic 0:02dd72d1d465 747 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
borlanic 0:02dd72d1d465 748 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
borlanic 0:02dd72d1d465 749 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
borlanic 0:02dd72d1d465 750 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
borlanic 0:02dd72d1d465 751 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
borlanic 0:02dd72d1d465 752 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
borlanic 0:02dd72d1d465 753 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
borlanic 0:02dd72d1d465 754 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
borlanic 0:02dd72d1d465 755 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
borlanic 0:02dd72d1d465 756 * @arg @ref LL_APB1_GRP1_PERIPH_USB
borlanic 0:02dd72d1d465 757 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
borlanic 0:02dd72d1d465 758 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
borlanic 0:02dd72d1d465 759 * @arg @ref LL_APB1_GRP1_PERIPH_COMP
borlanic 0:02dd72d1d465 760 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
borlanic 0:02dd72d1d465 761 *
borlanic 0:02dd72d1d465 762 * (*) value not defined in all devices.
borlanic 0:02dd72d1d465 763 * @retval None
borlanic 0:02dd72d1d465 764 */
borlanic 0:02dd72d1d465 765 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
borlanic 0:02dd72d1d465 766 {
borlanic 0:02dd72d1d465 767 CLEAR_BIT(RCC->APB1RSTR, Periphs);
borlanic 0:02dd72d1d465 768 }
borlanic 0:02dd72d1d465 769
borlanic 0:02dd72d1d465 770 /**
borlanic 0:02dd72d1d465 771 * @brief Enable APB1 peripherals clock during Low Power (Sleep) mode.
borlanic 0:02dd72d1d465 772 * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_EnableClockSleep\n
borlanic 0:02dd72d1d465 773 * APB1LPENR TIM3LPEN LL_APB1_GRP1_EnableClockSleep\n
borlanic 0:02dd72d1d465 774 * APB1LPENR TIM4LPEN LL_APB1_GRP1_EnableClockSleep\n
borlanic 0:02dd72d1d465 775 * APB1LPENR TIM5LPEN LL_APB1_GRP1_EnableClockSleep\n
borlanic 0:02dd72d1d465 776 * APB1LPENR TIM6LPEN LL_APB1_GRP1_EnableClockSleep\n
borlanic 0:02dd72d1d465 777 * APB1LPENR TIM7LPEN LL_APB1_GRP1_EnableClockSleep\n
borlanic 0:02dd72d1d465 778 * APB1LPENR LCDLPEN LL_APB1_GRP1_EnableClockSleep\n
borlanic 0:02dd72d1d465 779 * APB1LPENR WWDGLPEN LL_APB1_GRP1_EnableClockSleep\n
borlanic 0:02dd72d1d465 780 * APB1LPENR SPI2LPEN LL_APB1_GRP1_EnableClockSleep\n
borlanic 0:02dd72d1d465 781 * APB1LPENR SPI3LPEN LL_APB1_GRP1_EnableClockSleep\n
borlanic 0:02dd72d1d465 782 * APB1LPENR USART2LPEN LL_APB1_GRP1_EnableClockSleep\n
borlanic 0:02dd72d1d465 783 * APB1LPENR USART3LPEN LL_APB1_GRP1_EnableClockSleep\n
borlanic 0:02dd72d1d465 784 * APB1LPENR UART4LPEN LL_APB1_GRP1_EnableClockSleep\n
borlanic 0:02dd72d1d465 785 * APB1LPENR UART5LPEN LL_APB1_GRP1_EnableClockSleep\n
borlanic 0:02dd72d1d465 786 * APB1LPENR I2C1LPEN LL_APB1_GRP1_EnableClockSleep\n
borlanic 0:02dd72d1d465 787 * APB1LPENR I2C2LPEN LL_APB1_GRP1_EnableClockSleep\n
borlanic 0:02dd72d1d465 788 * APB1LPENR USBLPEN LL_APB1_GRP1_EnableClockSleep\n
borlanic 0:02dd72d1d465 789 * APB1LPENR PWRLPEN LL_APB1_GRP1_EnableClockSleep\n
borlanic 0:02dd72d1d465 790 * APB1LPENR DACLPEN LL_APB1_GRP1_EnableClockSleep\n
borlanic 0:02dd72d1d465 791 * APB1LPENR COMPLPEN LL_APB1_GRP1_EnableClockSleep
borlanic 0:02dd72d1d465 792 * @param Periphs This parameter can be a combination of the following values:
borlanic 0:02dd72d1d465 793 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
borlanic 0:02dd72d1d465 794 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
borlanic 0:02dd72d1d465 795 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
borlanic 0:02dd72d1d465 796 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
borlanic 0:02dd72d1d465 797 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
borlanic 0:02dd72d1d465 798 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
borlanic 0:02dd72d1d465 799 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
borlanic 0:02dd72d1d465 800 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
borlanic 0:02dd72d1d465 801 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
borlanic 0:02dd72d1d465 802 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
borlanic 0:02dd72d1d465 803 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
borlanic 0:02dd72d1d465 804 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
borlanic 0:02dd72d1d465 805 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
borlanic 0:02dd72d1d465 806 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
borlanic 0:02dd72d1d465 807 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
borlanic 0:02dd72d1d465 808 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
borlanic 0:02dd72d1d465 809 * @arg @ref LL_APB1_GRP1_PERIPH_USB
borlanic 0:02dd72d1d465 810 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
borlanic 0:02dd72d1d465 811 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
borlanic 0:02dd72d1d465 812 * @arg @ref LL_APB1_GRP1_PERIPH_COMP
borlanic 0:02dd72d1d465 813 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
borlanic 0:02dd72d1d465 814 *
borlanic 0:02dd72d1d465 815 * (*) value not defined in all devices.
borlanic 0:02dd72d1d465 816 * @retval None
borlanic 0:02dd72d1d465 817 */
borlanic 0:02dd72d1d465 818 __STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs)
borlanic 0:02dd72d1d465 819 {
borlanic 0:02dd72d1d465 820 __IO uint32_t tmpreg;
borlanic 0:02dd72d1d465 821 SET_BIT(RCC->APB1LPENR, Periphs);
borlanic 0:02dd72d1d465 822 /* Delay after an RCC peripheral clock enabling */
borlanic 0:02dd72d1d465 823 tmpreg = READ_BIT(RCC->APB1LPENR, Periphs);
borlanic 0:02dd72d1d465 824 (void)tmpreg;
borlanic 0:02dd72d1d465 825 }
borlanic 0:02dd72d1d465 826
borlanic 0:02dd72d1d465 827 /**
borlanic 0:02dd72d1d465 828 * @brief Disable APB1 peripherals clock during Low Power (Sleep) mode.
borlanic 0:02dd72d1d465 829 * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_DisableClockSleep\n
borlanic 0:02dd72d1d465 830 * APB1LPENR TIM3LPEN LL_APB1_GRP1_DisableClockSleep\n
borlanic 0:02dd72d1d465 831 * APB1LPENR TIM4LPEN LL_APB1_GRP1_DisableClockSleep\n
borlanic 0:02dd72d1d465 832 * APB1LPENR TIM5LPEN LL_APB1_GRP1_DisableClockSleep\n
borlanic 0:02dd72d1d465 833 * APB1LPENR TIM6LPEN LL_APB1_GRP1_DisableClockSleep\n
borlanic 0:02dd72d1d465 834 * APB1LPENR TIM7LPEN LL_APB1_GRP1_DisableClockSleep\n
borlanic 0:02dd72d1d465 835 * APB1LPENR LCDLPEN LL_APB1_GRP1_DisableClockSleep\n
borlanic 0:02dd72d1d465 836 * APB1LPENR WWDGLPEN LL_APB1_GRP1_DisableClockSleep\n
borlanic 0:02dd72d1d465 837 * APB1LPENR SPI2LPEN LL_APB1_GRP1_DisableClockSleep\n
borlanic 0:02dd72d1d465 838 * APB1LPENR SPI3LPEN LL_APB1_GRP1_DisableClockSleep\n
borlanic 0:02dd72d1d465 839 * APB1LPENR USART2LPEN LL_APB1_GRP1_DisableClockSleep\n
borlanic 0:02dd72d1d465 840 * APB1LPENR USART3LPEN LL_APB1_GRP1_DisableClockSleep\n
borlanic 0:02dd72d1d465 841 * APB1LPENR UART4LPEN LL_APB1_GRP1_DisableClockSleep\n
borlanic 0:02dd72d1d465 842 * APB1LPENR UART5LPEN LL_APB1_GRP1_DisableClockSleep\n
borlanic 0:02dd72d1d465 843 * APB1LPENR I2C1LPEN LL_APB1_GRP1_DisableClockSleep\n
borlanic 0:02dd72d1d465 844 * APB1LPENR I2C2LPEN LL_APB1_GRP1_DisableClockSleep\n
borlanic 0:02dd72d1d465 845 * APB1LPENR USBLPEN LL_APB1_GRP1_DisableClockSleep\n
borlanic 0:02dd72d1d465 846 * APB1LPENR PWRLPEN LL_APB1_GRP1_DisableClockSleep\n
borlanic 0:02dd72d1d465 847 * APB1LPENR DACLPEN LL_APB1_GRP1_DisableClockSleep\n
borlanic 0:02dd72d1d465 848 * APB1LPENR COMPLPEN LL_APB1_GRP1_DisableClockSleep
borlanic 0:02dd72d1d465 849 * @param Periphs This parameter can be a combination of the following values:
borlanic 0:02dd72d1d465 850 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
borlanic 0:02dd72d1d465 851 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
borlanic 0:02dd72d1d465 852 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
borlanic 0:02dd72d1d465 853 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
borlanic 0:02dd72d1d465 854 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
borlanic 0:02dd72d1d465 855 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
borlanic 0:02dd72d1d465 856 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
borlanic 0:02dd72d1d465 857 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
borlanic 0:02dd72d1d465 858 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
borlanic 0:02dd72d1d465 859 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
borlanic 0:02dd72d1d465 860 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
borlanic 0:02dd72d1d465 861 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
borlanic 0:02dd72d1d465 862 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
borlanic 0:02dd72d1d465 863 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
borlanic 0:02dd72d1d465 864 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
borlanic 0:02dd72d1d465 865 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
borlanic 0:02dd72d1d465 866 * @arg @ref LL_APB1_GRP1_PERIPH_USB
borlanic 0:02dd72d1d465 867 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
borlanic 0:02dd72d1d465 868 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
borlanic 0:02dd72d1d465 869 * @arg @ref LL_APB1_GRP1_PERIPH_COMP
borlanic 0:02dd72d1d465 870 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
borlanic 0:02dd72d1d465 871 *
borlanic 0:02dd72d1d465 872 * (*) value not defined in all devices.
borlanic 0:02dd72d1d465 873 * @retval None
borlanic 0:02dd72d1d465 874 */
borlanic 0:02dd72d1d465 875 __STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs)
borlanic 0:02dd72d1d465 876 {
borlanic 0:02dd72d1d465 877 CLEAR_BIT(RCC->APB1LPENR, Periphs);
borlanic 0:02dd72d1d465 878 }
borlanic 0:02dd72d1d465 879
borlanic 0:02dd72d1d465 880 /**
borlanic 0:02dd72d1d465 881 * @}
borlanic 0:02dd72d1d465 882 */
borlanic 0:02dd72d1d465 883
borlanic 0:02dd72d1d465 884 /** @defgroup BUS_LL_EF_APB2 APB2
borlanic 0:02dd72d1d465 885 * @{
borlanic 0:02dd72d1d465 886 */
borlanic 0:02dd72d1d465 887
borlanic 0:02dd72d1d465 888 /**
borlanic 0:02dd72d1d465 889 * @brief Enable APB2 peripherals clock.
borlanic 0:02dd72d1d465 890 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n
borlanic 0:02dd72d1d465 891 * APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n
borlanic 0:02dd72d1d465 892 * APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n
borlanic 0:02dd72d1d465 893 * APB2ENR TIM11EN LL_APB2_GRP1_EnableClock\n
borlanic 0:02dd72d1d465 894 * APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n
borlanic 0:02dd72d1d465 895 * APB2ENR SDIOEN LL_APB2_GRP1_EnableClock\n
borlanic 0:02dd72d1d465 896 * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
borlanic 0:02dd72d1d465 897 * APB2ENR USART1EN LL_APB2_GRP1_EnableClock
borlanic 0:02dd72d1d465 898 * @param Periphs This parameter can be a combination of the following values:
borlanic 0:02dd72d1d465 899 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
borlanic 0:02dd72d1d465 900 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
borlanic 0:02dd72d1d465 901 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
borlanic 0:02dd72d1d465 902 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
borlanic 0:02dd72d1d465 903 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
borlanic 0:02dd72d1d465 904 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
borlanic 0:02dd72d1d465 905 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
borlanic 0:02dd72d1d465 906 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
borlanic 0:02dd72d1d465 907 *
borlanic 0:02dd72d1d465 908 * (*) value not defined in all devices.
borlanic 0:02dd72d1d465 909 * @retval None
borlanic 0:02dd72d1d465 910 */
borlanic 0:02dd72d1d465 911 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
borlanic 0:02dd72d1d465 912 {
borlanic 0:02dd72d1d465 913 __IO uint32_t tmpreg;
borlanic 0:02dd72d1d465 914 SET_BIT(RCC->APB2ENR, Periphs);
borlanic 0:02dd72d1d465 915 /* Delay after an RCC peripheral clock enabling */
borlanic 0:02dd72d1d465 916 tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
borlanic 0:02dd72d1d465 917 (void)tmpreg;
borlanic 0:02dd72d1d465 918 }
borlanic 0:02dd72d1d465 919
borlanic 0:02dd72d1d465 920 /**
borlanic 0:02dd72d1d465 921 * @brief Check if APB2 peripheral clock is enabled or not
borlanic 0:02dd72d1d465 922 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n
borlanic 0:02dd72d1d465 923 * APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock\n
borlanic 0:02dd72d1d465 924 * APB2ENR TIM10EN LL_APB2_GRP1_IsEnabledClock\n
borlanic 0:02dd72d1d465 925 * APB2ENR TIM11EN LL_APB2_GRP1_IsEnabledClock\n
borlanic 0:02dd72d1d465 926 * APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n
borlanic 0:02dd72d1d465 927 * APB2ENR SDIOEN LL_APB2_GRP1_IsEnabledClock\n
borlanic 0:02dd72d1d465 928 * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
borlanic 0:02dd72d1d465 929 * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock
borlanic 0:02dd72d1d465 930 * @param Periphs This parameter can be a combination of the following values:
borlanic 0:02dd72d1d465 931 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
borlanic 0:02dd72d1d465 932 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
borlanic 0:02dd72d1d465 933 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
borlanic 0:02dd72d1d465 934 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
borlanic 0:02dd72d1d465 935 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
borlanic 0:02dd72d1d465 936 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
borlanic 0:02dd72d1d465 937 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
borlanic 0:02dd72d1d465 938 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
borlanic 0:02dd72d1d465 939 *
borlanic 0:02dd72d1d465 940 * (*) value not defined in all devices.
borlanic 0:02dd72d1d465 941 * @retval State of Periphs (1 or 0).
borlanic 0:02dd72d1d465 942 */
borlanic 0:02dd72d1d465 943 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
borlanic 0:02dd72d1d465 944 {
borlanic 0:02dd72d1d465 945 return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
borlanic 0:02dd72d1d465 946 }
borlanic 0:02dd72d1d465 947
borlanic 0:02dd72d1d465 948 /**
borlanic 0:02dd72d1d465 949 * @brief Disable APB2 peripherals clock.
borlanic 0:02dd72d1d465 950 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n
borlanic 0:02dd72d1d465 951 * APB2ENR TIM9EN LL_APB2_GRP1_DisableClock\n
borlanic 0:02dd72d1d465 952 * APB2ENR TIM10EN LL_APB2_GRP1_DisableClock\n
borlanic 0:02dd72d1d465 953 * APB2ENR TIM11EN LL_APB2_GRP1_DisableClock\n
borlanic 0:02dd72d1d465 954 * APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n
borlanic 0:02dd72d1d465 955 * APB2ENR SDIOEN LL_APB2_GRP1_DisableClock\n
borlanic 0:02dd72d1d465 956 * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
borlanic 0:02dd72d1d465 957 * APB2ENR USART1EN LL_APB2_GRP1_DisableClock
borlanic 0:02dd72d1d465 958 * @param Periphs This parameter can be a combination of the following values:
borlanic 0:02dd72d1d465 959 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
borlanic 0:02dd72d1d465 960 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
borlanic 0:02dd72d1d465 961 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
borlanic 0:02dd72d1d465 962 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
borlanic 0:02dd72d1d465 963 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
borlanic 0:02dd72d1d465 964 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
borlanic 0:02dd72d1d465 965 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
borlanic 0:02dd72d1d465 966 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
borlanic 0:02dd72d1d465 967 *
borlanic 0:02dd72d1d465 968 * (*) value not defined in all devices.
borlanic 0:02dd72d1d465 969 * @retval None
borlanic 0:02dd72d1d465 970 */
borlanic 0:02dd72d1d465 971 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
borlanic 0:02dd72d1d465 972 {
borlanic 0:02dd72d1d465 973 CLEAR_BIT(RCC->APB2ENR, Periphs);
borlanic 0:02dd72d1d465 974 }
borlanic 0:02dd72d1d465 975
borlanic 0:02dd72d1d465 976 /**
borlanic 0:02dd72d1d465 977 * @brief Force APB2 peripherals reset.
borlanic 0:02dd72d1d465 978 * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n
borlanic 0:02dd72d1d465 979 * APB2RSTR TIM9RST LL_APB2_GRP1_ForceReset\n
borlanic 0:02dd72d1d465 980 * APB2RSTR TIM10RST LL_APB2_GRP1_ForceReset\n
borlanic 0:02dd72d1d465 981 * APB2RSTR TIM11RST LL_APB2_GRP1_ForceReset\n
borlanic 0:02dd72d1d465 982 * APB2RSTR ADC1RST LL_APB2_GRP1_ForceReset\n
borlanic 0:02dd72d1d465 983 * APB2RSTR SDIORST LL_APB2_GRP1_ForceReset\n
borlanic 0:02dd72d1d465 984 * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
borlanic 0:02dd72d1d465 985 * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset
borlanic 0:02dd72d1d465 986 * @param Periphs This parameter can be a combination of the following values:
borlanic 0:02dd72d1d465 987 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
borlanic 0:02dd72d1d465 988 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
borlanic 0:02dd72d1d465 989 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
borlanic 0:02dd72d1d465 990 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
borlanic 0:02dd72d1d465 991 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
borlanic 0:02dd72d1d465 992 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
borlanic 0:02dd72d1d465 993 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
borlanic 0:02dd72d1d465 994 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
borlanic 0:02dd72d1d465 995 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
borlanic 0:02dd72d1d465 996 *
borlanic 0:02dd72d1d465 997 * (*) value not defined in all devices.
borlanic 0:02dd72d1d465 998 * @retval None
borlanic 0:02dd72d1d465 999 */
borlanic 0:02dd72d1d465 1000 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
borlanic 0:02dd72d1d465 1001 {
borlanic 0:02dd72d1d465 1002 SET_BIT(RCC->APB2RSTR, Periphs);
borlanic 0:02dd72d1d465 1003 }
borlanic 0:02dd72d1d465 1004
borlanic 0:02dd72d1d465 1005 /**
borlanic 0:02dd72d1d465 1006 * @brief Release APB2 peripherals reset.
borlanic 0:02dd72d1d465 1007 * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n
borlanic 0:02dd72d1d465 1008 * APB2RSTR TIM9RST LL_APB2_GRP1_ReleaseReset\n
borlanic 0:02dd72d1d465 1009 * APB2RSTR TIM10RST LL_APB2_GRP1_ReleaseReset\n
borlanic 0:02dd72d1d465 1010 * APB2RSTR TIM11RST LL_APB2_GRP1_ReleaseReset\n
borlanic 0:02dd72d1d465 1011 * APB2RSTR ADC1RST LL_APB2_GRP1_ReleaseReset\n
borlanic 0:02dd72d1d465 1012 * APB2RSTR SDIORST LL_APB2_GRP1_ReleaseReset\n
borlanic 0:02dd72d1d465 1013 * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
borlanic 0:02dd72d1d465 1014 * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset
borlanic 0:02dd72d1d465 1015 * @param Periphs This parameter can be a combination of the following values:
borlanic 0:02dd72d1d465 1016 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
borlanic 0:02dd72d1d465 1017 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
borlanic 0:02dd72d1d465 1018 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
borlanic 0:02dd72d1d465 1019 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
borlanic 0:02dd72d1d465 1020 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
borlanic 0:02dd72d1d465 1021 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
borlanic 0:02dd72d1d465 1022 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
borlanic 0:02dd72d1d465 1023 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
borlanic 0:02dd72d1d465 1024 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
borlanic 0:02dd72d1d465 1025 *
borlanic 0:02dd72d1d465 1026 * (*) value not defined in all devices.
borlanic 0:02dd72d1d465 1027 * @retval None
borlanic 0:02dd72d1d465 1028 */
borlanic 0:02dd72d1d465 1029 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
borlanic 0:02dd72d1d465 1030 {
borlanic 0:02dd72d1d465 1031 CLEAR_BIT(RCC->APB2RSTR, Periphs);
borlanic 0:02dd72d1d465 1032 }
borlanic 0:02dd72d1d465 1033
borlanic 0:02dd72d1d465 1034 /**
borlanic 0:02dd72d1d465 1035 * @brief Enable APB2 peripherals clock during Low Power (Sleep) mode.
borlanic 0:02dd72d1d465 1036 * @rmtoll APB2LPENR SYSCFGLPEN LL_APB2_GRP1_EnableClockSleep\n
borlanic 0:02dd72d1d465 1037 * APB2LPENR TIM9LPEN LL_APB2_GRP1_EnableClockSleep\n
borlanic 0:02dd72d1d465 1038 * APB2LPENR TIM10LPEN LL_APB2_GRP1_EnableClockSleep\n
borlanic 0:02dd72d1d465 1039 * APB2LPENR TIM11LPEN LL_APB2_GRP1_EnableClockSleep\n
borlanic 0:02dd72d1d465 1040 * APB2LPENR ADC1LPEN LL_APB2_GRP1_EnableClockSleep\n
borlanic 0:02dd72d1d465 1041 * APB2LPENR SDIOLPEN LL_APB2_GRP1_EnableClockSleep\n
borlanic 0:02dd72d1d465 1042 * APB2LPENR SPI1LPEN LL_APB2_GRP1_EnableClockSleep\n
borlanic 0:02dd72d1d465 1043 * APB2LPENR USART1LPEN LL_APB2_GRP1_EnableClockSleep
borlanic 0:02dd72d1d465 1044 * @param Periphs This parameter can be a combination of the following values:
borlanic 0:02dd72d1d465 1045 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
borlanic 0:02dd72d1d465 1046 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
borlanic 0:02dd72d1d465 1047 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
borlanic 0:02dd72d1d465 1048 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
borlanic 0:02dd72d1d465 1049 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
borlanic 0:02dd72d1d465 1050 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
borlanic 0:02dd72d1d465 1051 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
borlanic 0:02dd72d1d465 1052 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
borlanic 0:02dd72d1d465 1053 *
borlanic 0:02dd72d1d465 1054 * (*) value not defined in all devices.
borlanic 0:02dd72d1d465 1055 * @retval None
borlanic 0:02dd72d1d465 1056 */
borlanic 0:02dd72d1d465 1057 __STATIC_INLINE void LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs)
borlanic 0:02dd72d1d465 1058 {
borlanic 0:02dd72d1d465 1059 __IO uint32_t tmpreg;
borlanic 0:02dd72d1d465 1060 SET_BIT(RCC->APB2LPENR, Periphs);
borlanic 0:02dd72d1d465 1061 /* Delay after an RCC peripheral clock enabling */
borlanic 0:02dd72d1d465 1062 tmpreg = READ_BIT(RCC->APB2LPENR, Periphs);
borlanic 0:02dd72d1d465 1063 (void)tmpreg;
borlanic 0:02dd72d1d465 1064 }
borlanic 0:02dd72d1d465 1065
borlanic 0:02dd72d1d465 1066 /**
borlanic 0:02dd72d1d465 1067 * @brief Disable APB2 peripherals clock during Low Power (Sleep) mode.
borlanic 0:02dd72d1d465 1068 * @rmtoll APB2LPENR SYSCFGLPEN LL_APB2_GRP1_DisableClockSleep\n
borlanic 0:02dd72d1d465 1069 * APB2LPENR TIM9LPEN LL_APB2_GRP1_DisableClockSleep\n
borlanic 0:02dd72d1d465 1070 * APB2LPENR TIM10LPEN LL_APB2_GRP1_DisableClockSleep\n
borlanic 0:02dd72d1d465 1071 * APB2LPENR TIM11LPEN LL_APB2_GRP1_DisableClockSleep\n
borlanic 0:02dd72d1d465 1072 * APB2LPENR ADC1LPEN LL_APB2_GRP1_DisableClockSleep\n
borlanic 0:02dd72d1d465 1073 * APB2LPENR SDIOLPEN LL_APB2_GRP1_DisableClockSleep\n
borlanic 0:02dd72d1d465 1074 * APB2LPENR SPI1LPEN LL_APB2_GRP1_DisableClockSleep\n
borlanic 0:02dd72d1d465 1075 * APB2LPENR USART1LPEN LL_APB2_GRP1_DisableClockSleep
borlanic 0:02dd72d1d465 1076 * @param Periphs This parameter can be a combination of the following values:
borlanic 0:02dd72d1d465 1077 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
borlanic 0:02dd72d1d465 1078 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
borlanic 0:02dd72d1d465 1079 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
borlanic 0:02dd72d1d465 1080 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
borlanic 0:02dd72d1d465 1081 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
borlanic 0:02dd72d1d465 1082 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
borlanic 0:02dd72d1d465 1083 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
borlanic 0:02dd72d1d465 1084 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
borlanic 0:02dd72d1d465 1085 *
borlanic 0:02dd72d1d465 1086 * (*) value not defined in all devices.
borlanic 0:02dd72d1d465 1087 * @retval None
borlanic 0:02dd72d1d465 1088 */
borlanic 0:02dd72d1d465 1089 __STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs)
borlanic 0:02dd72d1d465 1090 {
borlanic 0:02dd72d1d465 1091 CLEAR_BIT(RCC->APB2LPENR, Periphs);
borlanic 0:02dd72d1d465 1092 }
borlanic 0:02dd72d1d465 1093
borlanic 0:02dd72d1d465 1094 /**
borlanic 0:02dd72d1d465 1095 * @}
borlanic 0:02dd72d1d465 1096 */
borlanic 0:02dd72d1d465 1097
borlanic 0:02dd72d1d465 1098
borlanic 0:02dd72d1d465 1099 /**
borlanic 0:02dd72d1d465 1100 * @}
borlanic 0:02dd72d1d465 1101 */
borlanic 0:02dd72d1d465 1102
borlanic 0:02dd72d1d465 1103 /**
borlanic 0:02dd72d1d465 1104 * @}
borlanic 0:02dd72d1d465 1105 */
borlanic 0:02dd72d1d465 1106
borlanic 0:02dd72d1d465 1107 #endif /* defined(RCC) */
borlanic 0:02dd72d1d465 1108
borlanic 0:02dd72d1d465 1109 /**
borlanic 0:02dd72d1d465 1110 * @}
borlanic 0:02dd72d1d465 1111 */
borlanic 0:02dd72d1d465 1112
borlanic 0:02dd72d1d465 1113 #ifdef __cplusplus
borlanic 0:02dd72d1d465 1114 }
borlanic 0:02dd72d1d465 1115 #endif
borlanic 0:02dd72d1d465 1116
borlanic 0:02dd72d1d465 1117 #endif /* __STM32L1xx_LL_BUS_H */
borlanic 0:02dd72d1d465 1118
borlanic 0:02dd72d1d465 1119 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/