Arrow / FXPQ3115

Driver for FXPQ3115 sensor.

Example usage

main.cpp

#include "mbed.h"
#include "FXPQ3115.h"

FXPQ3115 pressure_sensor(P0_13, P0_14);

int main()
{
    pressure_sensor.sensor_init();

    while (1) {
        pressure_sensor.read_oneshotMode_bar();
        printf("Pressure in Pascals: %d\n", pressure_sensor.print_pressure());
        thread_sleep_for(20000);
    }
}

FXPQ3115_reg.h@0:0b221579ed52, 2020-03-05 (annotated)

Committer:
Pawel Zarembski
Date:
Thu Mar 05 11:13:50 2020 +0100
Revision:
0:0b221579ed52
initial version, one shot mode for pressure only

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:0b221579ed52 1 /*
Pawel Zarembski 0:0b221579ed52 2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
Pawel Zarembski 0:0b221579ed52 3 * Copyright 2016-2017 NXP
Pawel Zarembski 0:0b221579ed52 4 * All rights reserved.
Pawel Zarembski 0:0b221579ed52 5 *
Pawel Zarembski 0:0b221579ed52 6 * SPDX-License-Identifier: BSD-3-Clause
Pawel Zarembski 0:0b221579ed52 7 */
Pawel Zarembski 0:0b221579ed52 8
Pawel Zarembski 0:0b221579ed52 9 #include "mbed.h"
Pawel Zarembski 0:0b221579ed52 10
Pawel Zarembski 0:0b221579ed52 11 /**
Pawel Zarembski 0:0b221579ed52 12 * FXPQ3115 Sensor Internal Registers
Pawel Zarembski 0:0b221579ed52 13 */
Pawel Zarembski 0:0b221579ed52 14 enum {
Pawel Zarembski 0:0b221579ed52 15 FXPQ3115_STATUS = 0x00,
Pawel Zarembski 0:0b221579ed52 16 FXPQ3115_OUT_P_MSB = 0x01,
Pawel Zarembski 0:0b221579ed52 17 FXPQ3115_OUT_P_CSB = 0x02,
Pawel Zarembski 0:0b221579ed52 18 FXPQ3115_OUT_P_LSB = 0x03,
Pawel Zarembski 0:0b221579ed52 19 FXPQ3115_OUT_T_MSB = 0x04,
Pawel Zarembski 0:0b221579ed52 20 FXPQ3115_OUT_T_LSB = 0x05,
Pawel Zarembski 0:0b221579ed52 21 FXPQ3115_DR_STATUS = 0x06,
Pawel Zarembski 0:0b221579ed52 22 FXPQ3115_OUT_P_DELTA_MSB = 0x07,
Pawel Zarembski 0:0b221579ed52 23 FXPQ3115_OUT_P_DELTA_CSB = 0x08,
Pawel Zarembski 0:0b221579ed52 24 FXPQ3115_OUT_P_DELTA_LSB = 0x09,
Pawel Zarembski 0:0b221579ed52 25 FXPQ3115_OUT_T_DELTA_MSB = 0x0A,
Pawel Zarembski 0:0b221579ed52 26 FXPQ3115_OUT_T_DELTA_LSB = 0x0B,
Pawel Zarembski 0:0b221579ed52 27 FXPQ3115_WHO_AM_I = 0x0C,
Pawel Zarembski 0:0b221579ed52 28 FXPQ3115_F_STATUS = 0x0D,
Pawel Zarembski 0:0b221579ed52 29 FXPQ3115_F_DATA = 0x0E,
Pawel Zarembski 0:0b221579ed52 30 FXPQ3115_F_SETUP = 0x0F,
Pawel Zarembski 0:0b221579ed52 31 FXPQ3115_TIME_DLY = 0x10,
Pawel Zarembski 0:0b221579ed52 32 FXPQ3115_SYSMOD = 0x11,
Pawel Zarembski 0:0b221579ed52 33 FXPQ3115_INT_SOURCE = 0x12,
Pawel Zarembski 0:0b221579ed52 34 FXPQ3115_PT_DATA_CFG = 0x13,
Pawel Zarembski 0:0b221579ed52 35 FXPQ3115_BAR_IN_MSB = 0x14,
Pawel Zarembski 0:0b221579ed52 36 FXPQ3115_BAR_IN_LSB = 0x15,
Pawel Zarembski 0:0b221579ed52 37 FXPQ3115_P_TGT_MSB = 0x16,
Pawel Zarembski 0:0b221579ed52 38 FXPQ3115_P_TGT_LSB = 0x17,
Pawel Zarembski 0:0b221579ed52 39 FXPQ3115_T_TGT = 0x18,
Pawel Zarembski 0:0b221579ed52 40 FXPQ3115_P_WND_MSB = 0x19,
Pawel Zarembski 0:0b221579ed52 41 FXPQ3115_P_WND_LSB = 0x1A,
Pawel Zarembski 0:0b221579ed52 42 FXPQ3115_T_WND = 0x1B,
Pawel Zarembski 0:0b221579ed52 43 FXPQ3115_P_MIN_MSB = 0x1C,
Pawel Zarembski 0:0b221579ed52 44 FXPQ3115_P_MIN_CSB = 0x1D,
Pawel Zarembski 0:0b221579ed52 45 FXPQ3115_P_MIN_LSB = 0x1E,
Pawel Zarembski 0:0b221579ed52 46 FXPQ3115_T_MIN_MSB = 0x1F,
Pawel Zarembski 0:0b221579ed52 47 FXPQ3115_T_MIN_LSB = 0x20,
Pawel Zarembski 0:0b221579ed52 48 FXPQ3115_P_MAX_MSB = 0x21,
Pawel Zarembski 0:0b221579ed52 49 FXPQ3115_P_MAX_CSB = 0x22,
Pawel Zarembski 0:0b221579ed52 50 FXPQ3115_P_MAX_LSB = 0x23,
Pawel Zarembski 0:0b221579ed52 51 FXPQ3115_T_MAX_MSB = 0x24,
Pawel Zarembski 0:0b221579ed52 52 FXPQ3115_T_MAX_LSB = 0x25,
Pawel Zarembski 0:0b221579ed52 53 FXPQ3115_CTRL_REG1 = 0x26,
Pawel Zarembski 0:0b221579ed52 54 FXPQ3115_CTRL_REG2 = 0x27,
Pawel Zarembski 0:0b221579ed52 55 FXPQ3115_CTRL_REG3 = 0x28,
Pawel Zarembski 0:0b221579ed52 56 FXPQ3115_CTRL_REG4 = 0x29,
Pawel Zarembski 0:0b221579ed52 57 FXPQ3115_CTRL_REG5 = 0x2A,
Pawel Zarembski 0:0b221579ed52 58 FXPQ3115_OFF_P = 0x2B,
Pawel Zarembski 0:0b221579ed52 59 FXPQ3115_OFF_T = 0x2C,
Pawel Zarembski 0:0b221579ed52 60 FXPQ3115_OFF_H = 0x2D,
Pawel Zarembski 0:0b221579ed52 61 };
Pawel Zarembski 0:0b221579ed52 62
Pawel Zarembski 0:0b221579ed52 63 #define FXPQ3115_I2C_ADDRESS (0x60) /* FXPQ3115BV I2C Slave Address. */
Pawel Zarembski 0:0b221579ed52 64 #define FXPQ3115_WHOAMI_VALUE (0xC5) /* FXPQ3115BV WHO_AM_I Value. */
Pawel Zarembski 0:0b221579ed52 65
Pawel Zarembski 0:0b221579ed52 66 /*--------------------------------
Pawel Zarembski 0:0b221579ed52 67 ** Register: STATUS
Pawel Zarembski 0:0b221579ed52 68 ** Enum: FXPQ3115_STATUS
Pawel Zarembski 0:0b221579ed52 69 ** --
Pawel Zarembski 0:0b221579ed52 70 ** Offset : 0x00 - Alias for DR_STATUS or F_STATUS.
Pawel Zarembski 0:0b221579ed52 71 ** ------------------------------*/
Pawel Zarembski 0:0b221579ed52 72 typedef uint8_t FXPQ3115_STATUS_t;
Pawel Zarembski 0:0b221579ed52 73
Pawel Zarembski 0:0b221579ed52 74
Pawel Zarembski 0:0b221579ed52 75
Pawel Zarembski 0:0b221579ed52 76 /*--------------------------------
Pawel Zarembski 0:0b221579ed52 77 ** Register: OUT_P_MSB
Pawel Zarembski 0:0b221579ed52 78 ** Enum: FXPQ3115_OUT_P_MSB
Pawel Zarembski 0:0b221579ed52 79 ** --
Pawel Zarembski 0:0b221579ed52 80 ** Offset : 0x01 - Bits 12-19 of 20-bit real-time Pressure sample.
Pawel Zarembski 0:0b221579ed52 81 ** ------------------------------*/
Pawel Zarembski 0:0b221579ed52 82 typedef uint8_t FXPQ3115_OUT_P_MSB_t;
Pawel Zarembski 0:0b221579ed52 83
Pawel Zarembski 0:0b221579ed52 84
Pawel Zarembski 0:0b221579ed52 85 /*--------------------------------
Pawel Zarembski 0:0b221579ed52 86 ** Register: OUT_P_CSB
Pawel Zarembski 0:0b221579ed52 87 ** Enum: FXPQ3115_OUT_P_CSB
Pawel Zarembski 0:0b221579ed52 88 ** --
Pawel Zarembski 0:0b221579ed52 89 ** Offset : 0x02 - Bits 4-11 of 20-bit real-time Pressure sample.
Pawel Zarembski 0:0b221579ed52 90 ** ------------------------------*/
Pawel Zarembski 0:0b221579ed52 91 typedef uint8_t FXPQ3115_OUT_P_CSB_t;
Pawel Zarembski 0:0b221579ed52 92
Pawel Zarembski 0:0b221579ed52 93
Pawel Zarembski 0:0b221579ed52 94 /*--------------------------------
Pawel Zarembski 0:0b221579ed52 95 ** Register: OUT_P_LSB
Pawel Zarembski 0:0b221579ed52 96 ** Enum: FXPQ3115_OUT_P_LSB
Pawel Zarembski 0:0b221579ed52 97 ** --
Pawel Zarembski 0:0b221579ed52 98 ** Offset : 0x03 - Bits 0-3 of 20-bit real-time Pressure sample.
Pawel Zarembski 0:0b221579ed52 99 ** ------------------------------*/
Pawel Zarembski 0:0b221579ed52 100 typedef union {
Pawel Zarembski 0:0b221579ed52 101 struct {
Pawel Zarembski 0:0b221579ed52 102 uint8_t _reserved_ : 4;
Pawel Zarembski 0:0b221579ed52 103 uint8_t pd : 4; /* - 20-bit pressure sample measurement data bits 3:0 */
Pawel Zarembski 0:0b221579ed52 104
Pawel Zarembski 0:0b221579ed52 105 } b;
Pawel Zarembski 0:0b221579ed52 106 uint8_t w;
Pawel Zarembski 0:0b221579ed52 107 } FXPQ3115_OUT_P_LSB_t;
Pawel Zarembski 0:0b221579ed52 108
Pawel Zarembski 0:0b221579ed52 109
Pawel Zarembski 0:0b221579ed52 110 /*
Pawel Zarembski 0:0b221579ed52 111 ** OUT_P_LSB - Bit field mask definitions
Pawel Zarembski 0:0b221579ed52 112 */
Pawel Zarembski 0:0b221579ed52 113 #define FXPQ3115_OUT_P_LSB_PD_MASK ((uint8_t) 0xF0)
Pawel Zarembski 0:0b221579ed52 114 #define FXPQ3115_OUT_P_LSB_PD_SHIFT ((uint8_t) 4)
Pawel Zarembski 0:0b221579ed52 115
Pawel Zarembski 0:0b221579ed52 116
Pawel Zarembski 0:0b221579ed52 117 /*------------------------------*/
Pawel Zarembski 0:0b221579ed52 118
Pawel Zarembski 0:0b221579ed52 119
Pawel Zarembski 0:0b221579ed52 120
Pawel Zarembski 0:0b221579ed52 121 /*--------------------------------
Pawel Zarembski 0:0b221579ed52 122 ** Register: OUT_T_MSB
Pawel Zarembski 0:0b221579ed52 123 ** Enum: FXPQ3115_OUT_T_MSB
Pawel Zarembski 0:0b221579ed52 124 ** --
Pawel Zarembski 0:0b221579ed52 125 ** Offset : 0x04 - Bits 4-11 of 12-bit real-time Temperature sample.
Pawel Zarembski 0:0b221579ed52 126 ** ------------------------------*/
Pawel Zarembski 0:0b221579ed52 127 typedef uint8_t FXPQ3115_OUT_T_MSB_t;
Pawel Zarembski 0:0b221579ed52 128
Pawel Zarembski 0:0b221579ed52 129
Pawel Zarembski 0:0b221579ed52 130 /*--------------------------------
Pawel Zarembski 0:0b221579ed52 131 ** Register: OUT_T_LSB
Pawel Zarembski 0:0b221579ed52 132 ** Enum: FXPQ3115_OUT_T_LSB
Pawel Zarembski 0:0b221579ed52 133 ** --
Pawel Zarembski 0:0b221579ed52 134 ** Offset : 0x05 - Bits 0-3 of 12-bit real-time Temperature sample.
Pawel Zarembski 0:0b221579ed52 135 ** ------------------------------*/
Pawel Zarembski 0:0b221579ed52 136 typedef union {
Pawel Zarembski 0:0b221579ed52 137 struct {
Pawel Zarembski 0:0b221579ed52 138 uint8_t _reserved_ : 4;
Pawel Zarembski 0:0b221579ed52 139 uint8_t pd : 4; /* - 12-bit temperature sample measurement data bits 3:0 */
Pawel Zarembski 0:0b221579ed52 140
Pawel Zarembski 0:0b221579ed52 141 } b;
Pawel Zarembski 0:0b221579ed52 142 uint8_t w;
Pawel Zarembski 0:0b221579ed52 143 } FXPQ3115_OUT_T_LSB_t;
Pawel Zarembski 0:0b221579ed52 144
Pawel Zarembski 0:0b221579ed52 145
Pawel Zarembski 0:0b221579ed52 146 /*
Pawel Zarembski 0:0b221579ed52 147 ** OUT_T_LSB - Bit field mask definitions
Pawel Zarembski 0:0b221579ed52 148 */
Pawel Zarembski 0:0b221579ed52 149 #define FXPQ3115_OUT_T_LSB_PD_MASK ((uint8_t) 0xF0)
Pawel Zarembski 0:0b221579ed52 150 #define FXPQ3115_OUT_T_LSB_PD_SHIFT ((uint8_t) 4)
Pawel Zarembski 0:0b221579ed52 151
Pawel Zarembski 0:0b221579ed52 152
Pawel Zarembski 0:0b221579ed52 153 /*------------------------------*/
Pawel Zarembski 0:0b221579ed52 154
Pawel Zarembski 0:0b221579ed52 155
Pawel Zarembski 0:0b221579ed52 156
Pawel Zarembski 0:0b221579ed52 157 /*--------------------------------
Pawel Zarembski 0:0b221579ed52 158 ** Register: DR_STATUS
Pawel Zarembski 0:0b221579ed52 159 ** Enum: FXPQ3115_DR_STATUS
Pawel Zarembski 0:0b221579ed52 160 ** --
Pawel Zarembski 0:0b221579ed52 161 ** Offset : 0x06 - Data-ready status information
Pawel Zarembski 0:0b221579ed52 162 ** ------------------------------*/
Pawel Zarembski 0:0b221579ed52 163 typedef union {
Pawel Zarembski 0:0b221579ed52 164 struct {
Pawel Zarembski 0:0b221579ed52 165 uint8_t _reserved_ : 1;
Pawel Zarembski 0:0b221579ed52 166 uint8_t tdr : 1; /* Temperature new Data Available. */
Pawel Zarembski 0:0b221579ed52 167
Pawel Zarembski 0:0b221579ed52 168 uint8_t pdr : 1; /* Pressure/Altitude new data available. */
Pawel Zarembski 0:0b221579ed52 169
Pawel Zarembski 0:0b221579ed52 170 uint8_t ptdr : 1; /* Pressure/Altitude OR Temperature data ready. */
Pawel Zarembski 0:0b221579ed52 171
Pawel Zarembski 0:0b221579ed52 172 uint8_t _reserved_1 : 1;
Pawel Zarembski 0:0b221579ed52 173 uint8_t tow : 1; /* Temperature data overwrite. */
Pawel Zarembski 0:0b221579ed52 174
Pawel Zarembski 0:0b221579ed52 175 uint8_t pow : 1; /* Pressure/Altitude data overwrite. */
Pawel Zarembski 0:0b221579ed52 176
Pawel Zarembski 0:0b221579ed52 177 uint8_t ptow : 1; /* Pressure/Altitude OR Temperature data overwrite. */
Pawel Zarembski 0:0b221579ed52 178
Pawel Zarembski 0:0b221579ed52 179 } b;
Pawel Zarembski 0:0b221579ed52 180 uint8_t w;
Pawel Zarembski 0:0b221579ed52 181 } FXPQ3115_DR_STATUS_t;
Pawel Zarembski 0:0b221579ed52 182
Pawel Zarembski 0:0b221579ed52 183
Pawel Zarembski 0:0b221579ed52 184 /*
Pawel Zarembski 0:0b221579ed52 185 ** DR_STATUS - Bit field mask definitions
Pawel Zarembski 0:0b221579ed52 186 */
Pawel Zarembski 0:0b221579ed52 187 #define FXPQ3115_DR_STATUS_TDR_MASK ((uint8_t) 0x02)
Pawel Zarembski 0:0b221579ed52 188 #define FXPQ3115_DR_STATUS_TDR_SHIFT ((uint8_t) 1)
Pawel Zarembski 0:0b221579ed52 189
Pawel Zarembski 0:0b221579ed52 190 #define FXPQ3115_DR_STATUS_PDR_MASK ((uint8_t) 0x04)
Pawel Zarembski 0:0b221579ed52 191 #define FXPQ3115_DR_STATUS_PDR_SHIFT ((uint8_t) 2)
Pawel Zarembski 0:0b221579ed52 192
Pawel Zarembski 0:0b221579ed52 193 #define FXPQ3115_DR_STATUS_PTDR_MASK ((uint8_t) 0x08)
Pawel Zarembski 0:0b221579ed52 194 #define FXPQ3115_DR_STATUS_PTDR_SHIFT ((uint8_t) 3)
Pawel Zarembski 0:0b221579ed52 195
Pawel Zarembski 0:0b221579ed52 196 #define FXPQ3115_DR_STATUS_TOW_MASK ((uint8_t) 0x20)
Pawel Zarembski 0:0b221579ed52 197 #define FXPQ3115_DR_STATUS_TOW_SHIFT ((uint8_t) 5)
Pawel Zarembski 0:0b221579ed52 198
Pawel Zarembski 0:0b221579ed52 199 #define FXPQ3115_DR_STATUS_POW_MASK ((uint8_t) 0x40)
Pawel Zarembski 0:0b221579ed52 200 #define FXPQ3115_DR_STATUS_POW_SHIFT ((uint8_t) 6)
Pawel Zarembski 0:0b221579ed52 201
Pawel Zarembski 0:0b221579ed52 202 #define FXPQ3115_DR_STATUS_PTOW_MASK ((uint8_t) 0x80)
Pawel Zarembski 0:0b221579ed52 203 #define FXPQ3115_DR_STATUS_PTOW_SHIFT ((uint8_t) 7)
Pawel Zarembski 0:0b221579ed52 204
Pawel Zarembski 0:0b221579ed52 205
Pawel Zarembski 0:0b221579ed52 206 /*
Pawel Zarembski 0:0b221579ed52 207 ** DR_STATUS - Bit field value definitions
Pawel Zarembski 0:0b221579ed52 208 */
Pawel Zarembski 0:0b221579ed52 209 #define FXPQ3115_DR_STATUS_TDR_DRDY ((uint8_t) 0x02) /* Set to 1 whenever a Temperature data acquisition */
Pawel Zarembski 0:0b221579ed52 210 /* is completed. Cleared anytime OUT_T_MSB register */
Pawel Zarembski 0:0b221579ed52 211 /* is read, when F_MODE is zero */
Pawel Zarembski 0:0b221579ed52 212 #define FXPQ3115_DR_STATUS_PDR_DRDY ((uint8_t) 0x04) /* Set to 1 whenever a new Pressure/Altitude data */
Pawel Zarembski 0:0b221579ed52 213 /* acquisition is completed. Cleared anytime */
Pawel Zarembski 0:0b221579ed52 214 /* OUT_P_MSB register is read, when F_MODE is zero */
Pawel Zarembski 0:0b221579ed52 215 #define FXPQ3115_DR_STATUS_PTDR_DRDY ((uint8_t) 0x08) /* Signals that a new acquisition for either */
Pawel Zarembski 0:0b221579ed52 216 /* Pressure/Altitude or Temperature is available. */
Pawel Zarembski 0:0b221579ed52 217 /* Cleared anytime OUT_P_MSB or OUT_T_MSB register is */
Pawel Zarembski 0:0b221579ed52 218 /* read, when F_MODE is zero */
Pawel Zarembski 0:0b221579ed52 219 #define FXPQ3115_DR_STATUS_TOW_OWR ((uint8_t) 0x20) /* Set to 1 whenever a new Temperature acquisition is */
Pawel Zarembski 0:0b221579ed52 220 /* completed before the retrieval of the previous */
Pawel Zarembski 0:0b221579ed52 221 /* data. When this occurs the previous data is */
Pawel Zarembski 0:0b221579ed52 222 /* overwritten. Cleared anytime OUT_T_MSB register is */
Pawel Zarembski 0:0b221579ed52 223 /* read, when F_MODE is zero */
Pawel Zarembski 0:0b221579ed52 224 #define FXPQ3115_DR_STATUS_POW_OWR ((uint8_t) 0x40) /* Set to 1 whenever a new Pressure/Altitude */
Pawel Zarembski 0:0b221579ed52 225 /* acquisition is completed before the retrieval of */
Pawel Zarembski 0:0b221579ed52 226 /* the previous data. When this occurs the previous */
Pawel Zarembski 0:0b221579ed52 227 /* data is overwritten. POW is cleared anytime */
Pawel Zarembski 0:0b221579ed52 228 /* OUT_P_MSB register is read, when F_MODE is zero */
Pawel Zarembski 0:0b221579ed52 229 #define FXPQ3115_DR_STATUS_PTOW_OWR ((uint8_t) 0x80) /* Set to 1 whenever new data is acquired before */
Pawel Zarembski 0:0b221579ed52 230 /* completing the retrieval of the previous set. This */
Pawel Zarembski 0:0b221579ed52 231 /* event occurs when the content of at least one data */
Pawel Zarembski 0:0b221579ed52 232 /* register (i.e. OUT_P, OUT_T) has been overwritten. */
Pawel Zarembski 0:0b221579ed52 233 /* PTOW is cleared when the high-bytes of the data */
Pawel Zarembski 0:0b221579ed52 234 /* (OUT_P_MSB or OUT_T_MSB) are read, when F_MODE is */
Pawel Zarembski 0:0b221579ed52 235 /* zero */
Pawel Zarembski 0:0b221579ed52 236 /*------------------------------*/
Pawel Zarembski 0:0b221579ed52 237
Pawel Zarembski 0:0b221579ed52 238
Pawel Zarembski 0:0b221579ed52 239
Pawel Zarembski 0:0b221579ed52 240 /*--------------------------------
Pawel Zarembski 0:0b221579ed52 241 ** Register: OUT_P_DELTA_MSB
Pawel Zarembski 0:0b221579ed52 242 ** Enum: FXPQ3115_OUT_P_DELTA_MSB
Pawel Zarembski 0:0b221579ed52 243 ** --
Pawel Zarembski 0:0b221579ed52 244 ** Offset : 0x07 - Bits 12-19 of 20-bit Pressure change data.
Pawel Zarembski 0:0b221579ed52 245 ** ------------------------------*/
Pawel Zarembski 0:0b221579ed52 246 typedef uint8_t FXPQ3115_OUT_P_DELTA_MSB_t;
Pawel Zarembski 0:0b221579ed52 247
Pawel Zarembski 0:0b221579ed52 248
Pawel Zarembski 0:0b221579ed52 249 /*--------------------------------
Pawel Zarembski 0:0b221579ed52 250 ** Register: OUT_P_DELTA_CSB
Pawel Zarembski 0:0b221579ed52 251 ** Enum: FXPQ3115_OUT_P_DELTA_CSB
Pawel Zarembski 0:0b221579ed52 252 ** --
Pawel Zarembski 0:0b221579ed52 253 ** Offset : 0x08 - Bits 4-11 of 20-bit Pressure change data.
Pawel Zarembski 0:0b221579ed52 254 ** ------------------------------*/
Pawel Zarembski 0:0b221579ed52 255 typedef uint8_t FXPQ3115_OUT_P_DELTA_CSB_t;
Pawel Zarembski 0:0b221579ed52 256
Pawel Zarembski 0:0b221579ed52 257
Pawel Zarembski 0:0b221579ed52 258 /*--------------------------------
Pawel Zarembski 0:0b221579ed52 259 ** Register: OUT_P_DELTA_LSB
Pawel Zarembski 0:0b221579ed52 260 ** Enum: FXPQ3115_OUT_P_DELTA_LSB
Pawel Zarembski 0:0b221579ed52 261 ** --
Pawel Zarembski 0:0b221579ed52 262 ** Offset : 0x09 - Bits 0-3 of 20-bit Pressure change data.
Pawel Zarembski 0:0b221579ed52 263 ** ------------------------------*/
Pawel Zarembski 0:0b221579ed52 264 typedef union {
Pawel Zarembski 0:0b221579ed52 265 struct {
Pawel Zarembski 0:0b221579ed52 266 uint8_t _reserved_ : 4;
Pawel Zarembski 0:0b221579ed52 267 uint8_t pcd : 4; /* - 20-bit pressure change measurement data bits 3:0 */
Pawel Zarembski 0:0b221579ed52 268
Pawel Zarembski 0:0b221579ed52 269 } b;
Pawel Zarembski 0:0b221579ed52 270 uint8_t w;
Pawel Zarembski 0:0b221579ed52 271 } FXPQ3115_OUT_P_DELTA_LSB_t;
Pawel Zarembski 0:0b221579ed52 272
Pawel Zarembski 0:0b221579ed52 273
Pawel Zarembski 0:0b221579ed52 274 /*
Pawel Zarembski 0:0b221579ed52 275 ** OUT_P_DELTA_LSB - Bit field mask definitions
Pawel Zarembski 0:0b221579ed52 276 */
Pawel Zarembski 0:0b221579ed52 277 #define FXPQ3115_OUT_P_DELTA_LSB_PCD_MASK ((uint8_t) 0xF0)
Pawel Zarembski 0:0b221579ed52 278 #define FXPQ3115_OUT_P_DELTA_LSB_PCD_SHIFT ((uint8_t) 4)
Pawel Zarembski 0:0b221579ed52 279
Pawel Zarembski 0:0b221579ed52 280
Pawel Zarembski 0:0b221579ed52 281 /*------------------------------*/
Pawel Zarembski 0:0b221579ed52 282
Pawel Zarembski 0:0b221579ed52 283
Pawel Zarembski 0:0b221579ed52 284
Pawel Zarembski 0:0b221579ed52 285 /*--------------------------------
Pawel Zarembski 0:0b221579ed52 286 ** Register: OUT_T_DELTA_MSB
Pawel Zarembski 0:0b221579ed52 287 ** Enum: FXPQ3115_OUT_T_DELTA_MSB
Pawel Zarembski 0:0b221579ed52 288 ** --
Pawel Zarembski 0:0b221579ed52 289 ** Offset : 0x0A - Bits 4-11 of 12-bit Temperature change data.
Pawel Zarembski 0:0b221579ed52 290 ** ------------------------------*/
Pawel Zarembski 0:0b221579ed52 291 typedef uint8_t FXPQ3115_OUT_T_DELTA_MSB_t;
Pawel Zarembski 0:0b221579ed52 292
Pawel Zarembski 0:0b221579ed52 293
Pawel Zarembski 0:0b221579ed52 294 /*--------------------------------
Pawel Zarembski 0:0b221579ed52 295 ** Register: OUT_T_DELTA_LSB
Pawel Zarembski 0:0b221579ed52 296 ** Enum: FXPQ3115_OUT_T_DELTA_LSB
Pawel Zarembski 0:0b221579ed52 297 ** --
Pawel Zarembski 0:0b221579ed52 298 ** Offset : 0x0B - Bits 0-3 of 12-bit Temperature change data.
Pawel Zarembski 0:0b221579ed52 299 ** ------------------------------*/
Pawel Zarembski 0:0b221579ed52 300 typedef union {
Pawel Zarembski 0:0b221579ed52 301 struct {
Pawel Zarembski 0:0b221579ed52 302 uint8_t _reserved_ : 4;
Pawel Zarembski 0:0b221579ed52 303 uint8_t tcd : 4; /* - 12-bit temperature change measurement data bits 3:0 */
Pawel Zarembski 0:0b221579ed52 304
Pawel Zarembski 0:0b221579ed52 305 } b;
Pawel Zarembski 0:0b221579ed52 306 uint8_t w;
Pawel Zarembski 0:0b221579ed52 307 } FXPQ3115_OUT_T_DELTA_LSB_t;
Pawel Zarembski 0:0b221579ed52 308
Pawel Zarembski 0:0b221579ed52 309
Pawel Zarembski 0:0b221579ed52 310 /*
Pawel Zarembski 0:0b221579ed52 311 ** OUT_T_DELTA_LSB - Bit field mask definitions
Pawel Zarembski 0:0b221579ed52 312 */
Pawel Zarembski 0:0b221579ed52 313 #define FXPQ3115_OUT_T_DELTA_LSB_TCD_MASK ((uint8_t) 0xF0)
Pawel Zarembski 0:0b221579ed52 314 #define FXPQ3115_OUT_T_DELTA_LSB_TCD_SHIFT ((uint8_t) 4)
Pawel Zarembski 0:0b221579ed52 315
Pawel Zarembski 0:0b221579ed52 316
Pawel Zarembski 0:0b221579ed52 317 /*------------------------------*/
Pawel Zarembski 0:0b221579ed52 318
Pawel Zarembski 0:0b221579ed52 319
Pawel Zarembski 0:0b221579ed52 320
Pawel Zarembski 0:0b221579ed52 321 /*--------------------------------
Pawel Zarembski 0:0b221579ed52 322 ** Register: WHO_AM_I
Pawel Zarembski 0:0b221579ed52 323 ** Enum: FXPQ3115_WHO_AM_I
Pawel Zarembski 0:0b221579ed52 324 ** --
Pawel Zarembski 0:0b221579ed52 325 ** Offset : 0x0C - Fixed Device ID Number.
Pawel Zarembski 0:0b221579ed52 326 ** ------------------------------*/
Pawel Zarembski 0:0b221579ed52 327 typedef uint8_t FXPQ3115_WHO_AM_I_t;
Pawel Zarembski 0:0b221579ed52 328
Pawel Zarembski 0:0b221579ed52 329
Pawel Zarembski 0:0b221579ed52 330
Pawel Zarembski 0:0b221579ed52 331 /*--------------------------------
Pawel Zarembski 0:0b221579ed52 332 ** Register: F_STATUS
Pawel Zarembski 0:0b221579ed52 333 ** Enum: FXPQ3115_F_STATUS
Pawel Zarembski 0:0b221579ed52 334 ** --
Pawel Zarembski 0:0b221579ed52 335 ** Offset : 0x0D - FIFO Status: No FIFO event detected.
Pawel Zarembski 0:0b221579ed52 336 ** ------------------------------*/
Pawel Zarembski 0:0b221579ed52 337 typedef union {
Pawel Zarembski 0:0b221579ed52 338 struct {
Pawel Zarembski 0:0b221579ed52 339 uint8_t f_cnt : 6; /* FIFO sample counter. F_CNT[5:0] bits indicate the number of samples */
Pawel Zarembski 0:0b221579ed52 340 /* currently stored in the FIFO buffer */
Pawel Zarembski 0:0b221579ed52 341
Pawel Zarembski 0:0b221579ed52 342 uint8_t f_wmkf_flag : 1; /* FIFO Watermark event */
Pawel Zarembski 0:0b221579ed52 343
Pawel Zarembski 0:0b221579ed52 344 uint8_t f_ovf : 1; /* FIFO overflow event. */
Pawel Zarembski 0:0b221579ed52 345
Pawel Zarembski 0:0b221579ed52 346 } b;
Pawel Zarembski 0:0b221579ed52 347 uint8_t w;
Pawel Zarembski 0:0b221579ed52 348 } FXPQ3115_F_STATUS_t;
Pawel Zarembski 0:0b221579ed52 349
Pawel Zarembski 0:0b221579ed52 350
Pawel Zarembski 0:0b221579ed52 351 /*
Pawel Zarembski 0:0b221579ed52 352 ** F_STATUS - Bit field mask definitions
Pawel Zarembski 0:0b221579ed52 353 */
Pawel Zarembski 0:0b221579ed52 354 #define FXPQ3115_F_STATUS_F_CNT_MASK ((uint8_t) 0x3F)
Pawel Zarembski 0:0b221579ed52 355 #define FXPQ3115_F_STATUS_F_CNT_SHIFT ((uint8_t) 0)
Pawel Zarembski 0:0b221579ed52 356
Pawel Zarembski 0:0b221579ed52 357 #define FXPQ3115_F_STATUS_F_WMKF_FLAG_MASK ((uint8_t) 0x40)
Pawel Zarembski 0:0b221579ed52 358 #define FXPQ3115_F_STATUS_F_WMKF_FLAG_SHIFT ((uint8_t) 6)
Pawel Zarembski 0:0b221579ed52 359
Pawel Zarembski 0:0b221579ed52 360 #define FXPQ3115_F_STATUS_F_OVF_MASK ((uint8_t) 0x80)
Pawel Zarembski 0:0b221579ed52 361 #define FXPQ3115_F_STATUS_F_OVF_SHIFT ((uint8_t) 7)
Pawel Zarembski 0:0b221579ed52 362
Pawel Zarembski 0:0b221579ed52 363
Pawel Zarembski 0:0b221579ed52 364 /*
Pawel Zarembski 0:0b221579ed52 365 ** F_STATUS - Bit field value definitions
Pawel Zarembski 0:0b221579ed52 366 */
Pawel Zarembski 0:0b221579ed52 367 #define FXPQ3115_F_STATUS_F_WMKF_FLAG_NOEVT ((uint8_t) 0x00) /* No FIFO watermark event detected. */
Pawel Zarembski 0:0b221579ed52 368 #define FXPQ3115_F_STATUS_F_WMKF_FLAG_EVTDET ((uint8_t) 0x40) /* FIFO Watermark event has been detected. */
Pawel Zarembski 0:0b221579ed52 369 #define FXPQ3115_F_STATUS_F_OVF_NOOVFL ((uint8_t) 0x00) /* No FIFO overflow events detected. */
Pawel Zarembski 0:0b221579ed52 370 #define FXPQ3115_F_STATUS_F_OVF_OVFLDET ((uint8_t) 0x80) /* FIFO Overflow event has been detected. */
Pawel Zarembski 0:0b221579ed52 371 /*------------------------------*/
Pawel Zarembski 0:0b221579ed52 372
Pawel Zarembski 0:0b221579ed52 373
Pawel Zarembski 0:0b221579ed52 374
Pawel Zarembski 0:0b221579ed52 375 /*--------------------------------
Pawel Zarembski 0:0b221579ed52 376 ** Register: F_DATA
Pawel Zarembski 0:0b221579ed52 377 ** Enum: FXPQ3115_F_DATA
Pawel Zarembski 0:0b221579ed52 378 ** --
Pawel Zarembski 0:0b221579ed52 379 ** Offset : 0x0E - FIFO 8-bit data access.
Pawel Zarembski 0:0b221579ed52 380 ** ------------------------------*/
Pawel Zarembski 0:0b221579ed52 381 typedef uint8_t FXPQ3115_F_DATA_t;
Pawel Zarembski 0:0b221579ed52 382
Pawel Zarembski 0:0b221579ed52 383
Pawel Zarembski 0:0b221579ed52 384
Pawel Zarembski 0:0b221579ed52 385 /*--------------------------------
Pawel Zarembski 0:0b221579ed52 386 ** Register: F_SETUP
Pawel Zarembski 0:0b221579ed52 387 ** Enum: FXPQ3115_F_SETUP
Pawel Zarembski 0:0b221579ed52 388 ** --
Pawel Zarembski 0:0b221579ed52 389 ** Offset : 0x0F - FIFO setup.
Pawel Zarembski 0:0b221579ed52 390 ** ------------------------------*/
Pawel Zarembski 0:0b221579ed52 391 typedef union {
Pawel Zarembski 0:0b221579ed52 392 struct {
Pawel Zarembski 0:0b221579ed52 393 uint8_t f_wmrk : 6; /* FIFO Event Sample Count Watermark. */
Pawel Zarembski 0:0b221579ed52 394
Pawel Zarembski 0:0b221579ed52 395 uint8_t f_mode : 2; /* FIFO buffer overflow mode. */
Pawel Zarembski 0:0b221579ed52 396
Pawel Zarembski 0:0b221579ed52 397 } b;
Pawel Zarembski 0:0b221579ed52 398 uint8_t w;
Pawel Zarembski 0:0b221579ed52 399 } FXPQ3115_F_SETUP_t;
Pawel Zarembski 0:0b221579ed52 400
Pawel Zarembski 0:0b221579ed52 401
Pawel Zarembski 0:0b221579ed52 402 /*
Pawel Zarembski 0:0b221579ed52 403 ** F_SETUP - Bit field mask definitions
Pawel Zarembski 0:0b221579ed52 404 */
Pawel Zarembski 0:0b221579ed52 405 #define FXPQ3115_F_SETUP_F_WMRK_MASK ((uint8_t) 0x3F)
Pawel Zarembski 0:0b221579ed52 406 #define FXPQ3115_F_SETUP_F_WMRK_SHIFT ((uint8_t) 0)
Pawel Zarembski 0:0b221579ed52 407
Pawel Zarembski 0:0b221579ed52 408 #define FXPQ3115_F_SETUP_F_MODE_MASK ((uint8_t) 0xC0)
Pawel Zarembski 0:0b221579ed52 409 #define FXPQ3115_F_SETUP_F_MODE_SHIFT ((uint8_t) 6)
Pawel Zarembski 0:0b221579ed52 410
Pawel Zarembski 0:0b221579ed52 411
Pawel Zarembski 0:0b221579ed52 412 /*
Pawel Zarembski 0:0b221579ed52 413 ** F_SETUP - Bit field value definitions
Pawel Zarembski 0:0b221579ed52 414 */
Pawel Zarembski 0:0b221579ed52 415 #define FXPQ3115_F_SETUP_F_MODE_FIFO_OFF ((uint8_t) 0x00) /* FIFO is disabled. */
Pawel Zarembski 0:0b221579ed52 416 #define FXPQ3115_F_SETUP_F_MODE_CIR_MODE ((uint8_t) 0x40) /* FIFO contains the most recent samples when */
Pawel Zarembski 0:0b221579ed52 417 /* overflowed (circular buffer). */
Pawel Zarembski 0:0b221579ed52 418 #define FXPQ3115_F_SETUP_F_MODE_STOP_MODE ((uint8_t) 0x80) /* FIFO stops accepting new samples when overflowed. */
Pawel Zarembski 0:0b221579ed52 419 /*------------------------------*/
Pawel Zarembski 0:0b221579ed52 420
Pawel Zarembski 0:0b221579ed52 421
Pawel Zarembski 0:0b221579ed52 422
Pawel Zarembski 0:0b221579ed52 423 /*--------------------------------
Pawel Zarembski 0:0b221579ed52 424 ** Register: TIME_DLY
Pawel Zarembski 0:0b221579ed52 425 ** Enum: FXPQ3115_TIME_DLY
Pawel Zarembski 0:0b221579ed52 426 ** --
Pawel Zarembski 0:0b221579ed52 427 ** Offset : 0x10 - Time since FIFO overflow.
Pawel Zarembski 0:0b221579ed52 428 ** ------------------------------*/
Pawel Zarembski 0:0b221579ed52 429 typedef uint8_t FXPQ3115_TIME_DLY_t;
Pawel Zarembski 0:0b221579ed52 430
Pawel Zarembski 0:0b221579ed52 431
Pawel Zarembski 0:0b221579ed52 432
Pawel Zarembski 0:0b221579ed52 433 /*--------------------------------
Pawel Zarembski 0:0b221579ed52 434 ** Register: SYSMOD
Pawel Zarembski 0:0b221579ed52 435 ** Enum: FXPQ3115_SYSMOD
Pawel Zarembski 0:0b221579ed52 436 ** --
Pawel Zarembski 0:0b221579ed52 437 ** Offset : 0x11 - Current system mode.
Pawel Zarembski 0:0b221579ed52 438 ** ------------------------------*/
Pawel Zarembski 0:0b221579ed52 439 typedef union {
Pawel Zarembski 0:0b221579ed52 440 struct {
Pawel Zarembski 0:0b221579ed52 441 uint8_t sysmod : 1; /* - System mode data bit 0. (Bits 7-1 are reserved, will always read 0.) */
Pawel Zarembski 0:0b221579ed52 442
Pawel Zarembski 0:0b221579ed52 443 } b;
Pawel Zarembski 0:0b221579ed52 444 uint8_t w;
Pawel Zarembski 0:0b221579ed52 445 } FXPQ3115_SYSMOD_t;
Pawel Zarembski 0:0b221579ed52 446
Pawel Zarembski 0:0b221579ed52 447
Pawel Zarembski 0:0b221579ed52 448 /*
Pawel Zarembski 0:0b221579ed52 449 ** SYSMOD - Bit field mask definitions
Pawel Zarembski 0:0b221579ed52 450 */
Pawel Zarembski 0:0b221579ed52 451 #define FXPQ3115_SYSMOD_SYSMOD_MASK ((uint8_t) 0x01)
Pawel Zarembski 0:0b221579ed52 452 #define FXPQ3115_SYSMOD_SYSMOD_SHIFT ((uint8_t) 0)
Pawel Zarembski 0:0b221579ed52 453
Pawel Zarembski 0:0b221579ed52 454
Pawel Zarembski 0:0b221579ed52 455 /*
Pawel Zarembski 0:0b221579ed52 456 ** SYSMOD - Bit field value definitions
Pawel Zarembski 0:0b221579ed52 457 */
Pawel Zarembski 0:0b221579ed52 458 #define FXPQ3115_SYSMOD_SYSMOD_STANDBY ((uint8_t) 0x00) /* STANDBY Mode. */
Pawel Zarembski 0:0b221579ed52 459 #define FXPQ3115_SYSMOD_SYSMOD_ACTIVE ((uint8_t) 0x01) /* ACTIVE Mode. */
Pawel Zarembski 0:0b221579ed52 460 /*------------------------------*/
Pawel Zarembski 0:0b221579ed52 461
Pawel Zarembski 0:0b221579ed52 462
Pawel Zarembski 0:0b221579ed52 463
Pawel Zarembski 0:0b221579ed52 464 /*--------------------------------
Pawel Zarembski 0:0b221579ed52 465 ** Register: INT_SOURCE
Pawel Zarembski 0:0b221579ed52 466 ** Enum: FXPQ3115_INT_SOURCE
Pawel Zarembski 0:0b221579ed52 467 ** --
Pawel Zarembski 0:0b221579ed52 468 ** Offset : 0x12 - Interrupt status. The bits that are set (logic ‘1’) indicate which function has asserted its interrupt and conversely, bits that are cleared (logic ‘0’) indicate which function has not asserted its interrupt.
Pawel Zarembski 0:0b221579ed52 469 ** ------------------------------*/
Pawel Zarembski 0:0b221579ed52 470 typedef union {
Pawel Zarembski 0:0b221579ed52 471 struct {
Pawel Zarembski 0:0b221579ed52 472 uint8_t src_tchg : 1; /* Delta T interrupt status bit. */
Pawel Zarembski 0:0b221579ed52 473
Pawel Zarembski 0:0b221579ed52 474 uint8_t src_pchg : 1; /* Delta P interrupt status bit. */
Pawel Zarembski 0:0b221579ed52 475
Pawel Zarembski 0:0b221579ed52 476 uint8_t src_tth : 1; /* Temperature threshold interrupt. */
Pawel Zarembski 0:0b221579ed52 477
Pawel Zarembski 0:0b221579ed52 478 uint8_t src_pth : 1; /* Altitude/Pressure threshold interrupt. */
Pawel Zarembski 0:0b221579ed52 479
Pawel Zarembski 0:0b221579ed52 480 uint8_t src_tw : 1; /* Temperature alerter status bit near or equal to target temperature. */
Pawel Zarembski 0:0b221579ed52 481
Pawel Zarembski 0:0b221579ed52 482 uint8_t src_pw : 1; /* Altitude/Pressure alerter status bit near or equal to target */
Pawel Zarembski 0:0b221579ed52 483 /* Pressure/Altitude. */
Pawel Zarembski 0:0b221579ed52 484
Pawel Zarembski 0:0b221579ed52 485 uint8_t src_fifo : 1; /* FIFO interrupt status bit. */
Pawel Zarembski 0:0b221579ed52 486
Pawel Zarembski 0:0b221579ed52 487 uint8_t src_drdy : 1; /* Data ready interrupt status bit. */
Pawel Zarembski 0:0b221579ed52 488
Pawel Zarembski 0:0b221579ed52 489 } b;
Pawel Zarembski 0:0b221579ed52 490 uint8_t w;
Pawel Zarembski 0:0b221579ed52 491 } FXPQ3115_INT_SOURCE_t;
Pawel Zarembski 0:0b221579ed52 492
Pawel Zarembski 0:0b221579ed52 493
Pawel Zarembski 0:0b221579ed52 494 /*
Pawel Zarembski 0:0b221579ed52 495 ** INT_SOURCE - Bit field mask definitions
Pawel Zarembski 0:0b221579ed52 496 */
Pawel Zarembski 0:0b221579ed52 497 #define FXPQ3115_INT_SOURCE_SRC_TCHG_MASK ((uint8_t) 0x01)
Pawel Zarembski 0:0b221579ed52 498 #define FXPQ3115_INT_SOURCE_SRC_TCHG_SHIFT ((uint8_t) 0)
Pawel Zarembski 0:0b221579ed52 499
Pawel Zarembski 0:0b221579ed52 500 #define FXPQ3115_INT_SOURCE_SRC_PCHG_MASK ((uint8_t) 0x02)
Pawel Zarembski 0:0b221579ed52 501 #define FXPQ3115_INT_SOURCE_SRC_PCHG_SHIFT ((uint8_t) 1)
Pawel Zarembski 0:0b221579ed52 502
Pawel Zarembski 0:0b221579ed52 503 #define FXPQ3115_INT_SOURCE_SRC_TTH_MASK ((uint8_t) 0x04)
Pawel Zarembski 0:0b221579ed52 504 #define FXPQ3115_INT_SOURCE_SRC_TTH_SHIFT ((uint8_t) 2)
Pawel Zarembski 0:0b221579ed52 505
Pawel Zarembski 0:0b221579ed52 506 #define FXPQ3115_INT_SOURCE_SRC_PTH_MASK ((uint8_t) 0x08)
Pawel Zarembski 0:0b221579ed52 507 #define FXPQ3115_INT_SOURCE_SRC_PTH_SHIFT ((uint8_t) 3)
Pawel Zarembski 0:0b221579ed52 508
Pawel Zarembski 0:0b221579ed52 509 #define FXPQ3115_INT_SOURCE_SRC_TW_MASK ((uint8_t) 0x10)
Pawel Zarembski 0:0b221579ed52 510 #define FXPQ3115_INT_SOURCE_SRC_TW_SHIFT ((uint8_t) 4)
Pawel Zarembski 0:0b221579ed52 511
Pawel Zarembski 0:0b221579ed52 512 #define FXPQ3115_INT_SOURCE_SRC_PW_MASK ((uint8_t) 0x20)
Pawel Zarembski 0:0b221579ed52 513 #define FXPQ3115_INT_SOURCE_SRC_PW_SHIFT ((uint8_t) 5)
Pawel Zarembski 0:0b221579ed52 514
Pawel Zarembski 0:0b221579ed52 515 #define FXPQ3115_INT_SOURCE_SRC_FIFO_MASK ((uint8_t) 0x40)
Pawel Zarembski 0:0b221579ed52 516 #define FXPQ3115_INT_SOURCE_SRC_FIFO_SHIFT ((uint8_t) 6)
Pawel Zarembski 0:0b221579ed52 517
Pawel Zarembski 0:0b221579ed52 518 #define FXPQ3115_INT_SOURCE_SRC_DRDY_MASK ((uint8_t) 0x80)
Pawel Zarembski 0:0b221579ed52 519 #define FXPQ3115_INT_SOURCE_SRC_DRDY_SHIFT ((uint8_t) 7)
Pawel Zarembski 0:0b221579ed52 520
Pawel Zarembski 0:0b221579ed52 521
Pawel Zarembski 0:0b221579ed52 522 /*------------------------------*/
Pawel Zarembski 0:0b221579ed52 523
Pawel Zarembski 0:0b221579ed52 524
Pawel Zarembski 0:0b221579ed52 525
Pawel Zarembski 0:0b221579ed52 526 /*--------------------------------
Pawel Zarembski 0:0b221579ed52 527 ** Register: PT_DATA_CFG
Pawel Zarembski 0:0b221579ed52 528 ** Enum: FXPQ3115_PT_DATA_CFG
Pawel Zarembski 0:0b221579ed52 529 ** --
Pawel Zarembski 0:0b221579ed52 530 ** Offset : 0x13 - Data event flag configuration.
Pawel Zarembski 0:0b221579ed52 531 ** ------------------------------*/
Pawel Zarembski 0:0b221579ed52 532 typedef union {
Pawel Zarembski 0:0b221579ed52 533 struct {
Pawel Zarembski 0:0b221579ed52 534 uint8_t tdefe : 1; /* Data event flag enable on new Temperature data. */
Pawel Zarembski 0:0b221579ed52 535
Pawel Zarembski 0:0b221579ed52 536 uint8_t pdefe : 1; /* Data event flag enable on new Pressure/Altitude data. */
Pawel Zarembski 0:0b221579ed52 537
Pawel Zarembski 0:0b221579ed52 538 uint8_t drem : 1; /* Data ready event mode. */
Pawel Zarembski 0:0b221579ed52 539
Pawel Zarembski 0:0b221579ed52 540 } b;
Pawel Zarembski 0:0b221579ed52 541 uint8_t w;
Pawel Zarembski 0:0b221579ed52 542 } FXPQ3115_PT_DATA_CFG_t;
Pawel Zarembski 0:0b221579ed52 543
Pawel Zarembski 0:0b221579ed52 544
Pawel Zarembski 0:0b221579ed52 545 /*
Pawel Zarembski 0:0b221579ed52 546 ** PT_DATA_CFG - Bit field mask definitions
Pawel Zarembski 0:0b221579ed52 547 */
Pawel Zarembski 0:0b221579ed52 548 #define FXPQ3115_PT_DATA_CFG_TDEFE_MASK ((uint8_t) 0x01)
Pawel Zarembski 0:0b221579ed52 549 #define FXPQ3115_PT_DATA_CFG_TDEFE_SHIFT ((uint8_t) 0)
Pawel Zarembski 0:0b221579ed52 550
Pawel Zarembski 0:0b221579ed52 551 #define FXPQ3115_PT_DATA_CFG_PDEFE_MASK ((uint8_t) 0x02)
Pawel Zarembski 0:0b221579ed52 552 #define FXPQ3115_PT_DATA_CFG_PDEFE_SHIFT ((uint8_t) 1)
Pawel Zarembski 0:0b221579ed52 553
Pawel Zarembski 0:0b221579ed52 554 #define FXPQ3115_PT_DATA_CFG_DREM_MASK ((uint8_t) 0x04)
Pawel Zarembski 0:0b221579ed52 555 #define FXPQ3115_PT_DATA_CFG_DREM_SHIFT ((uint8_t) 2)
Pawel Zarembski 0:0b221579ed52 556
Pawel Zarembski 0:0b221579ed52 557
Pawel Zarembski 0:0b221579ed52 558 /*
Pawel Zarembski 0:0b221579ed52 559 ** PT_DATA_CFG - Bit field value definitions
Pawel Zarembski 0:0b221579ed52 560 */
Pawel Zarembski 0:0b221579ed52 561 #define FXPQ3115_PT_DATA_CFG_TDEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
Pawel Zarembski 0:0b221579ed52 562 #define FXPQ3115_PT_DATA_CFG_TDEFE_ENABLED ((uint8_t) 0x01) /* Event detection enabled. Raise event flag on new */
Pawel Zarembski 0:0b221579ed52 563 /* Temperature data. */
Pawel Zarembski 0:0b221579ed52 564 #define FXPQ3115_PT_DATA_CFG_PDEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
Pawel Zarembski 0:0b221579ed52 565 #define FXPQ3115_PT_DATA_CFG_PDEFE_ENABLED ((uint8_t) 0x02) /* Event detection enabled. Raise event flag on new */
Pawel Zarembski 0:0b221579ed52 566 /* Pressure/Altitude data. */
Pawel Zarembski 0:0b221579ed52 567 #define FXPQ3115_PT_DATA_CFG_DREM_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
Pawel Zarembski 0:0b221579ed52 568 #define FXPQ3115_PT_DATA_CFG_DREM_ENABLED ((uint8_t) 0x04) /* Event detection enabled. Generate data ready */
Pawel Zarembski 0:0b221579ed52 569 /* event flag on new Pressure/Altitude or */
Pawel Zarembski 0:0b221579ed52 570 /* Temperature data. */
Pawel Zarembski 0:0b221579ed52 571 /*------------------------------*/
Pawel Zarembski 0:0b221579ed52 572
Pawel Zarembski 0:0b221579ed52 573
Pawel Zarembski 0:0b221579ed52 574
Pawel Zarembski 0:0b221579ed52 575 /*--------------------------------
Pawel Zarembski 0:0b221579ed52 576 ** Register: BAR_IN_MSB
Pawel Zarembski 0:0b221579ed52 577 ** Enum: FXPQ3115_BAR_IN_MSB
Pawel Zarembski 0:0b221579ed52 578 ** --
Pawel Zarembski 0:0b221579ed52 579 ** Offset : 0x14 - Bits 8-15 of Barometric input for Altitude calculation.
Pawel Zarembski 0:0b221579ed52 580 ** ------------------------------*/
Pawel Zarembski 0:0b221579ed52 581 typedef uint8_t FXPQ3115_BAR_IN_MSB_t;
Pawel Zarembski 0:0b221579ed52 582
Pawel Zarembski 0:0b221579ed52 583
Pawel Zarembski 0:0b221579ed52 584 /*--------------------------------
Pawel Zarembski 0:0b221579ed52 585 ** Register: BAR_IN_LSB
Pawel Zarembski 0:0b221579ed52 586 ** Enum: FXPQ3115_BAR_IN_LSB
Pawel Zarembski 0:0b221579ed52 587 ** --
Pawel Zarembski 0:0b221579ed52 588 ** Offset : 0x15 - Bits 0-7 of Barometric input for Altitude calculation.
Pawel Zarembski 0:0b221579ed52 589 ** ------------------------------*/
Pawel Zarembski 0:0b221579ed52 590 typedef uint8_t FXPQ3115_BAR_IN_LSB_t;
Pawel Zarembski 0:0b221579ed52 591
Pawel Zarembski 0:0b221579ed52 592
Pawel Zarembski 0:0b221579ed52 593
Pawel Zarembski 0:0b221579ed52 594 /*--------------------------------
Pawel Zarembski 0:0b221579ed52 595 ** Register: P_TGT_MSB
Pawel Zarembski 0:0b221579ed52 596 ** Enum: FXPQ3115_P_TGT_MSB
Pawel Zarembski 0:0b221579ed52 597 ** --
Pawel Zarembski 0:0b221579ed52 598 ** Offset : 0x16 - Bits 8-15 of Pressure/Altitude target value.
Pawel Zarembski 0:0b221579ed52 599 ** ------------------------------*/
Pawel Zarembski 0:0b221579ed52 600 typedef uint8_t FXPQ3115_P_TGT_MSB_t;
Pawel Zarembski 0:0b221579ed52 601
Pawel Zarembski 0:0b221579ed52 602
Pawel Zarembski 0:0b221579ed52 603 /*--------------------------------
Pawel Zarembski 0:0b221579ed52 604 ** Register: P_TGT_LSB
Pawel Zarembski 0:0b221579ed52 605 ** Enum: FXPQ3115_P_TGT_LSB
Pawel Zarembski 0:0b221579ed52 606 ** --
Pawel Zarembski 0:0b221579ed52 607 ** Offset : 0x17 - Bits 0-7 of Pressure/Altitude target value.
Pawel Zarembski 0:0b221579ed52 608 ** ------------------------------*/
Pawel Zarembski 0:0b221579ed52 609 typedef uint8_t FXPQ3115_P_TGT_LSB_t;
Pawel Zarembski 0:0b221579ed52 610
Pawel Zarembski 0:0b221579ed52 611
Pawel Zarembski 0:0b221579ed52 612
Pawel Zarembski 0:0b221579ed52 613 /*--------------------------------
Pawel Zarembski 0:0b221579ed52 614 ** Register: T_TGT
Pawel Zarembski 0:0b221579ed52 615 ** Enum: FXPQ3115_T_TGT
Pawel Zarembski 0:0b221579ed52 616 ** --
Pawel Zarembski 0:0b221579ed52 617 ** Offset : 0x18 - Temperature target value.
Pawel Zarembski 0:0b221579ed52 618 ** ------------------------------*/
Pawel Zarembski 0:0b221579ed52 619 typedef uint8_t FXPQ3115_T_TGT_t;
Pawel Zarembski 0:0b221579ed52 620
Pawel Zarembski 0:0b221579ed52 621
Pawel Zarembski 0:0b221579ed52 622
Pawel Zarembski 0:0b221579ed52 623 /*--------------------------------
Pawel Zarembski 0:0b221579ed52 624 ** Register: P_WND_MSB
Pawel Zarembski 0:0b221579ed52 625 ** Enum: FXPQ3115_P_WND_MSB
Pawel Zarembski 0:0b221579ed52 626 ** --
Pawel Zarembski 0:0b221579ed52 627 ** Offset : 0x19 - Bits 8-15 of Pressure/Altitude window value.
Pawel Zarembski 0:0b221579ed52 628 ** ------------------------------*/
Pawel Zarembski 0:0b221579ed52 629 typedef uint8_t FXPQ3115_P_WND_MSB_t;
Pawel Zarembski 0:0b221579ed52 630
Pawel Zarembski 0:0b221579ed52 631
Pawel Zarembski 0:0b221579ed52 632 /*--------------------------------
Pawel Zarembski 0:0b221579ed52 633 ** Register: P_WND_LSB
Pawel Zarembski 0:0b221579ed52 634 ** Enum: FXPQ3115_P_WND_LSB
Pawel Zarembski 0:0b221579ed52 635 ** --
Pawel Zarembski 0:0b221579ed52 636 ** Offset : 0x1A - Bits 0-7 of Pressure/Altitude window value.
Pawel Zarembski 0:0b221579ed52 637 ** ------------------------------*/
Pawel Zarembski 0:0b221579ed52 638 typedef uint8_t FXPQ3115_P_WND_LSB_t;
Pawel Zarembski 0:0b221579ed52 639
Pawel Zarembski 0:0b221579ed52 640
Pawel Zarembski 0:0b221579ed52 641
Pawel Zarembski 0:0b221579ed52 642 /*--------------------------------
Pawel Zarembski 0:0b221579ed52 643 ** Register: T_WND
Pawel Zarembski 0:0b221579ed52 644 ** Enum: FXPQ3115_T_WND
Pawel Zarembski 0:0b221579ed52 645 ** --
Pawel Zarembski 0:0b221579ed52 646 ** Offset : 0x1B - Temperature window value.
Pawel Zarembski 0:0b221579ed52 647 ** ------------------------------*/
Pawel Zarembski 0:0b221579ed52 648 typedef uint8_t FXPQ3115_T_WND_t;
Pawel Zarembski 0:0b221579ed52 649
Pawel Zarembski 0:0b221579ed52 650
Pawel Zarembski 0:0b221579ed52 651
Pawel Zarembski 0:0b221579ed52 652 /*--------------------------------
Pawel Zarembski 0:0b221579ed52 653 ** Register: P_MIN_MSB
Pawel Zarembski 0:0b221579ed52 654 ** Enum: FXPQ3115_P_MIN_MSB
Pawel Zarembski 0:0b221579ed52 655 ** --
Pawel Zarembski 0:0b221579ed52 656 ** Offset : 0x1C - Bits 12-19 of 20-bit Minimum Pressure/Altitude data.
Pawel Zarembski 0:0b221579ed52 657 ** ------------------------------*/
Pawel Zarembski 0:0b221579ed52 658 typedef uint8_t FXPQ3115_P_MIN_MSB_t;
Pawel Zarembski 0:0b221579ed52 659
Pawel Zarembski 0:0b221579ed52 660
Pawel Zarembski 0:0b221579ed52 661 /*--------------------------------
Pawel Zarembski 0:0b221579ed52 662 ** Register: P_MIN_CSB
Pawel Zarembski 0:0b221579ed52 663 ** Enum: FXPQ3115_P_MIN_CSB
Pawel Zarembski 0:0b221579ed52 664 ** --
Pawel Zarembski 0:0b221579ed52 665 ** Offset : 0x1D - Bits 4-11 of 20-bit Minimum Pressure/Altitude data.
Pawel Zarembski 0:0b221579ed52 666 ** ------------------------------*/
Pawel Zarembski 0:0b221579ed52 667 typedef uint8_t FXPQ3115_P_MIN_CSB_t;
Pawel Zarembski 0:0b221579ed52 668
Pawel Zarembski 0:0b221579ed52 669
Pawel Zarembski 0:0b221579ed52 670 /*--------------------------------
Pawel Zarembski 0:0b221579ed52 671 ** Register: P_MIN_LSB
Pawel Zarembski 0:0b221579ed52 672 ** Enum: FXPQ3115_P_MIN_LSB
Pawel Zarembski 0:0b221579ed52 673 ** --
Pawel Zarembski 0:0b221579ed52 674 ** Offset : 0x1E - Bits 0-3 of 20-bit Minimum Pressure/Altitude data.
Pawel Zarembski 0:0b221579ed52 675 ** ------------------------------*/
Pawel Zarembski 0:0b221579ed52 676 typedef union {
Pawel Zarembski 0:0b221579ed52 677 struct {
Pawel Zarembski 0:0b221579ed52 678 uint8_t _reserved_ : 4;
Pawel Zarembski 0:0b221579ed52 679 uint8_t minpad : 4; /* - 20-bit Minimum Pressure/Altitude data bits 3:0. */
Pawel Zarembski 0:0b221579ed52 680
Pawel Zarembski 0:0b221579ed52 681 } b;
Pawel Zarembski 0:0b221579ed52 682 uint8_t w;
Pawel Zarembski 0:0b221579ed52 683 } FXPQ3115_P_MIN_LSB_t;
Pawel Zarembski 0:0b221579ed52 684
Pawel Zarembski 0:0b221579ed52 685
Pawel Zarembski 0:0b221579ed52 686 /*
Pawel Zarembski 0:0b221579ed52 687 ** P_MIN_LSB - Bit field mask definitions
Pawel Zarembski 0:0b221579ed52 688 */
Pawel Zarembski 0:0b221579ed52 689 #define FXPQ3115_P_MIN_LSB_MINPAD_MASK ((uint8_t) 0xF0)
Pawel Zarembski 0:0b221579ed52 690 #define FXPQ3115_P_MIN_LSB_MINPAD_SHIFT ((uint8_t) 4)
Pawel Zarembski 0:0b221579ed52 691
Pawel Zarembski 0:0b221579ed52 692
Pawel Zarembski 0:0b221579ed52 693 /*------------------------------*/
Pawel Zarembski 0:0b221579ed52 694
Pawel Zarembski 0:0b221579ed52 695
Pawel Zarembski 0:0b221579ed52 696
Pawel Zarembski 0:0b221579ed52 697 /*--------------------------------
Pawel Zarembski 0:0b221579ed52 698 ** Register: T_MIN_MSB
Pawel Zarembski 0:0b221579ed52 699 ** Enum: FXPQ3115_T_MIN_MSB
Pawel Zarembski 0:0b221579ed52 700 ** --
Pawel Zarembski 0:0b221579ed52 701 ** Offset : 0x1F - Bits 4-11 of 12-bit Minimum Temperature data.
Pawel Zarembski 0:0b221579ed52 702 ** ------------------------------*/
Pawel Zarembski 0:0b221579ed52 703 typedef uint8_t FXPQ3115_T_MIN_MSB_t;
Pawel Zarembski 0:0b221579ed52 704
Pawel Zarembski 0:0b221579ed52 705
Pawel Zarembski 0:0b221579ed52 706 /*--------------------------------
Pawel Zarembski 0:0b221579ed52 707 ** Register: T_MIN_LSB
Pawel Zarembski 0:0b221579ed52 708 ** Enum: FXPQ3115_T_MIN_LSB
Pawel Zarembski 0:0b221579ed52 709 ** --
Pawel Zarembski 0:0b221579ed52 710 ** Offset : 0x20 - Bits 0-3 of 12-bit Minimum Temperature data.
Pawel Zarembski 0:0b221579ed52 711 ** ------------------------------*/
Pawel Zarembski 0:0b221579ed52 712 typedef union {
Pawel Zarembski 0:0b221579ed52 713 struct {
Pawel Zarembski 0:0b221579ed52 714 uint8_t _reserved_ : 4;
Pawel Zarembski 0:0b221579ed52 715 uint8_t mintd : 4; /* - 12-bit Minimum Temperature data bits 3:0. */
Pawel Zarembski 0:0b221579ed52 716
Pawel Zarembski 0:0b221579ed52 717 } b;
Pawel Zarembski 0:0b221579ed52 718 uint8_t w;
Pawel Zarembski 0:0b221579ed52 719 } FXPQ3115_T_MIN_LSB_t;
Pawel Zarembski 0:0b221579ed52 720
Pawel Zarembski 0:0b221579ed52 721
Pawel Zarembski 0:0b221579ed52 722 /*
Pawel Zarembski 0:0b221579ed52 723 ** T_MIN_LSB - Bit field mask definitions
Pawel Zarembski 0:0b221579ed52 724 */
Pawel Zarembski 0:0b221579ed52 725 #define FXPQ3115_T_MIN_LSB_MINTD_MASK ((uint8_t) 0xF0)
Pawel Zarembski 0:0b221579ed52 726 #define FXPQ3115_T_MIN_LSB_MINTD_SHIFT ((uint8_t) 4)
Pawel Zarembski 0:0b221579ed52 727
Pawel Zarembski 0:0b221579ed52 728
Pawel Zarembski 0:0b221579ed52 729 /*------------------------------*/
Pawel Zarembski 0:0b221579ed52 730
Pawel Zarembski 0:0b221579ed52 731
Pawel Zarembski 0:0b221579ed52 732
Pawel Zarembski 0:0b221579ed52 733 /*--------------------------------
Pawel Zarembski 0:0b221579ed52 734 ** Register: P_MAX_MSB
Pawel Zarembski 0:0b221579ed52 735 ** Enum: FXPQ3115_P_MAX_MSB
Pawel Zarembski 0:0b221579ed52 736 ** --
Pawel Zarembski 0:0b221579ed52 737 ** Offset : 0x21 - Bits 12-19 of 20-bit Maximum Pressure/Altitude data.
Pawel Zarembski 0:0b221579ed52 738 ** ------------------------------*/
Pawel Zarembski 0:0b221579ed52 739 typedef uint8_t FXPQ3115_P_MAX_MSB_t;
Pawel Zarembski 0:0b221579ed52 740
Pawel Zarembski 0:0b221579ed52 741
Pawel Zarembski 0:0b221579ed52 742 /*--------------------------------
Pawel Zarembski 0:0b221579ed52 743 ** Register: P_MAX_CSB
Pawel Zarembski 0:0b221579ed52 744 ** Enum: FXPQ3115_P_MAX_CSB
Pawel Zarembski 0:0b221579ed52 745 ** --
Pawel Zarembski 0:0b221579ed52 746 ** Offset : 0x22 - Bits 4-11 of 20-bit Maximum Pressure/Altitude data.
Pawel Zarembski 0:0b221579ed52 747 ** ------------------------------*/
Pawel Zarembski 0:0b221579ed52 748 typedef uint8_t FXPQ3115_P_MAX_CSB_t;
Pawel Zarembski 0:0b221579ed52 749
Pawel Zarembski 0:0b221579ed52 750
Pawel Zarembski 0:0b221579ed52 751 /*--------------------------------
Pawel Zarembski 0:0b221579ed52 752 ** Register: P_MAX_LSB
Pawel Zarembski 0:0b221579ed52 753 ** Enum: FXPQ3115_P_MAX_LSB
Pawel Zarembski 0:0b221579ed52 754 ** --
Pawel Zarembski 0:0b221579ed52 755 ** Offset : 0x23 - Bits 0-3 of 20-bit Maximum Pressure/Altitude data.
Pawel Zarembski 0:0b221579ed52 756 ** ------------------------------*/
Pawel Zarembski 0:0b221579ed52 757 typedef union {
Pawel Zarembski 0:0b221579ed52 758 struct {
Pawel Zarembski 0:0b221579ed52 759 uint8_t _reserved_ : 4;
Pawel Zarembski 0:0b221579ed52 760 uint8_t maxpad : 4; /* - 20-bit Maximum Pressure/Altitude data bits 3:0. */
Pawel Zarembski 0:0b221579ed52 761
Pawel Zarembski 0:0b221579ed52 762 } b;
Pawel Zarembski 0:0b221579ed52 763 uint8_t w;
Pawel Zarembski 0:0b221579ed52 764 } FXPQ3115_P_MAX_LSB_t;
Pawel Zarembski 0:0b221579ed52 765
Pawel Zarembski 0:0b221579ed52 766
Pawel Zarembski 0:0b221579ed52 767 /*
Pawel Zarembski 0:0b221579ed52 768 ** P_MAX_LSB - Bit field mask definitions
Pawel Zarembski 0:0b221579ed52 769 */
Pawel Zarembski 0:0b221579ed52 770 #define FXPQ3115_P_MAX_LSB_MAXPAD_MASK ((uint8_t) 0xF0)
Pawel Zarembski 0:0b221579ed52 771 #define FXPQ3115_P_MAX_LSB_MAXPAD_SHIFT ((uint8_t) 4)
Pawel Zarembski 0:0b221579ed52 772
Pawel Zarembski 0:0b221579ed52 773
Pawel Zarembski 0:0b221579ed52 774 /*------------------------------*/
Pawel Zarembski 0:0b221579ed52 775
Pawel Zarembski 0:0b221579ed52 776
Pawel Zarembski 0:0b221579ed52 777
Pawel Zarembski 0:0b221579ed52 778 /*--------------------------------
Pawel Zarembski 0:0b221579ed52 779 ** Register: T_MAX_MSB
Pawel Zarembski 0:0b221579ed52 780 ** Enum: FXPQ3115_T_MAX_MSB
Pawel Zarembski 0:0b221579ed52 781 ** --
Pawel Zarembski 0:0b221579ed52 782 ** Offset : 0x24 - Bits 4-11 of 12-bit Maximum Temperature data.
Pawel Zarembski 0:0b221579ed52 783 ** ------------------------------*/
Pawel Zarembski 0:0b221579ed52 784 typedef uint8_t FXPQ3115_T_MAX_MSB_t;
Pawel Zarembski 0:0b221579ed52 785
Pawel Zarembski 0:0b221579ed52 786
Pawel Zarembski 0:0b221579ed52 787 /*--------------------------------
Pawel Zarembski 0:0b221579ed52 788 ** Register: T_MAX_LSB
Pawel Zarembski 0:0b221579ed52 789 ** Enum: FXPQ3115_T_MAX_LSB
Pawel Zarembski 0:0b221579ed52 790 ** --
Pawel Zarembski 0:0b221579ed52 791 ** Offset : 0x25 - Bits 0-3 of 12-bit Maximum Temperature data.
Pawel Zarembski 0:0b221579ed52 792 ** ------------------------------*/
Pawel Zarembski 0:0b221579ed52 793 typedef union {
Pawel Zarembski 0:0b221579ed52 794 struct {
Pawel Zarembski 0:0b221579ed52 795 uint8_t _reserved_ : 4;
Pawel Zarembski 0:0b221579ed52 796 uint8_t maxtd : 4; /* - 12-bit Maximum Temperature data bits 3:0. */
Pawel Zarembski 0:0b221579ed52 797
Pawel Zarembski 0:0b221579ed52 798 } b;
Pawel Zarembski 0:0b221579ed52 799 uint8_t w;
Pawel Zarembski 0:0b221579ed52 800 } FXPQ3115_T_MAX_LSB_t;
Pawel Zarembski 0:0b221579ed52 801
Pawel Zarembski 0:0b221579ed52 802
Pawel Zarembski 0:0b221579ed52 803 /*
Pawel Zarembski 0:0b221579ed52 804 ** T_MAX_LSB - Bit field mask definitions
Pawel Zarembski 0:0b221579ed52 805 */
Pawel Zarembski 0:0b221579ed52 806 #define FXPQ3115_T_MAX_LSB_MAXTD_MASK ((uint8_t) 0xF0)
Pawel Zarembski 0:0b221579ed52 807 #define FXPQ3115_T_MAX_LSB_MAXTD_SHIFT ((uint8_t) 4)
Pawel Zarembski 0:0b221579ed52 808
Pawel Zarembski 0:0b221579ed52 809
Pawel Zarembski 0:0b221579ed52 810 /*------------------------------*/
Pawel Zarembski 0:0b221579ed52 811
Pawel Zarembski 0:0b221579ed52 812
Pawel Zarembski 0:0b221579ed52 813
Pawel Zarembski 0:0b221579ed52 814 /*--------------------------------
Pawel Zarembski 0:0b221579ed52 815 ** Register: CTRL_REG1
Pawel Zarembski 0:0b221579ed52 816 ** Enum: FXPQ3115_CTRL_REG1
Pawel Zarembski 0:0b221579ed52 817 ** --
Pawel Zarembski 0:0b221579ed52 818 ** Offset : 0x26 - Control Register 1: Modes, Oversampling.
Pawel Zarembski 0:0b221579ed52 819 ** ------------------------------*/
Pawel Zarembski 0:0b221579ed52 820 typedef union {
Pawel Zarembski 0:0b221579ed52 821 struct {
Pawel Zarembski 0:0b221579ed52 822 uint8_t sbyb : 1; /* Operation Mode. */
Pawel Zarembski 0:0b221579ed52 823
Pawel Zarembski 0:0b221579ed52 824 uint8_t ost : 1; /* OST bit to initiate a measurement immediately, If the SBYB bit is set to */
Pawel Zarembski 0:0b221579ed52 825 /* active. */
Pawel Zarembski 0:0b221579ed52 826
Pawel Zarembski 0:0b221579ed52 827 uint8_t rst : 1; /* Software Reset. This bit is used to activate the software reset. */
Pawel Zarembski 0:0b221579ed52 828
Pawel Zarembski 0:0b221579ed52 829 uint8_t os : 3; /* Oversample Ratio. These bits select the oversampling ratio. */
Pawel Zarembski 0:0b221579ed52 830
Pawel Zarembski 0:0b221579ed52 831 uint8_t raw : 1; /* RAW output mode. RAW bit will output ADC data with no post processing, */
Pawel Zarembski 0:0b221579ed52 832 /* except for oversampling. */
Pawel Zarembski 0:0b221579ed52 833
Pawel Zarembski 0:0b221579ed52 834 uint8_t alt : 1; /* Altimeter-Barometer mode. */
Pawel Zarembski 0:0b221579ed52 835
Pawel Zarembski 0:0b221579ed52 836 } b;
Pawel Zarembski 0:0b221579ed52 837 uint8_t w;
Pawel Zarembski 0:0b221579ed52 838 } FXPQ3115_CTRL_REG1_t;
Pawel Zarembski 0:0b221579ed52 839
Pawel Zarembski 0:0b221579ed52 840
Pawel Zarembski 0:0b221579ed52 841 /*
Pawel Zarembski 0:0b221579ed52 842 ** CTRL_REG1 - Bit field mask definitions
Pawel Zarembski 0:0b221579ed52 843 */
Pawel Zarembski 0:0b221579ed52 844 #define FXPQ3115_CTRL_REG1_SBYB_MASK ((uint8_t) 0x01)
Pawel Zarembski 0:0b221579ed52 845 #define FXPQ3115_CTRL_REG1_SBYB_SHIFT ((uint8_t) 0)
Pawel Zarembski 0:0b221579ed52 846
Pawel Zarembski 0:0b221579ed52 847 #define FXPQ3115_CTRL_REG1_OST_MASK ((uint8_t) 0x02)
Pawel Zarembski 0:0b221579ed52 848 #define FXPQ3115_CTRL_REG1_OST_SHIFT ((uint8_t) 1)
Pawel Zarembski 0:0b221579ed52 849
Pawel Zarembski 0:0b221579ed52 850 #define FXPQ3115_CTRL_REG1_RST_MASK ((uint8_t) 0x04)
Pawel Zarembski 0:0b221579ed52 851 #define FXPQ3115_CTRL_REG1_RST_SHIFT ((uint8_t) 2)
Pawel Zarembski 0:0b221579ed52 852
Pawel Zarembski 0:0b221579ed52 853 #define FXPQ3115_CTRL_REG1_OS_MASK ((uint8_t) 0x38)
Pawel Zarembski 0:0b221579ed52 854 #define FXPQ3115_CTRL_REG1_OS_SHIFT ((uint8_t) 3)
Pawel Zarembski 0:0b221579ed52 855
Pawel Zarembski 0:0b221579ed52 856 #define FXPQ3115_CTRL_REG1_RAW_MASK ((uint8_t) 0x40)
Pawel Zarembski 0:0b221579ed52 857 #define FXPQ3115_CTRL_REG1_RAW_SHIFT ((uint8_t) 6)
Pawel Zarembski 0:0b221579ed52 858
Pawel Zarembski 0:0b221579ed52 859 #define FXPQ3115_CTRL_REG1_ALT_MASK ((uint8_t) 0x80)
Pawel Zarembski 0:0b221579ed52 860 #define FXPQ3115_CTRL_REG1_ALT_SHIFT ((uint8_t) 7)
Pawel Zarembski 0:0b221579ed52 861
Pawel Zarembski 0:0b221579ed52 862
Pawel Zarembski 0:0b221579ed52 863 /*
Pawel Zarembski 0:0b221579ed52 864 ** CTRL_REG1 - Bit field value definitions
Pawel Zarembski 0:0b221579ed52 865 */
Pawel Zarembski 0:0b221579ed52 866 #define FXPQ3115_CTRL_REG1_SBYB_STANDBY ((uint8_t) 0x00) /* Standby Mode. */
Pawel Zarembski 0:0b221579ed52 867 #define FXPQ3115_CTRL_REG1_SBYB_ACTIVE ((uint8_t) 0x01) /* Active Mode. */
Pawel Zarembski 0:0b221579ed52 868 #define FXPQ3115_CTRL_REG1_OST_RESET ((uint8_t) 0x00) /* Reset OST Bit. */
Pawel Zarembski 0:0b221579ed52 869 #define FXPQ3115_CTRL_REG1_OST_SET ((uint8_t) 0x02) /* SET OST Bit. */
Pawel Zarembski 0:0b221579ed52 870 #define FXPQ3115_CTRL_REG1_RST_DIS ((uint8_t) 0x00) /* Device reset disabled. */
Pawel Zarembski 0:0b221579ed52 871 #define FXPQ3115_CTRL_REG1_RST_EN ((uint8_t) 0x04) /* Device reset enabled. */
Pawel Zarembski 0:0b221579ed52 872 #define FXPQ3115_CTRL_REG1_OS_OSR_1 ((uint8_t) 0x00) /* OSR = 1 and Minimum Time Between Data Samples 6 ms */
Pawel Zarembski 0:0b221579ed52 873 #define FXPQ3115_CTRL_REG1_OS_OSR_2 ((uint8_t) 0x08) /* OSR = 2 and Minimum Time Between Data Samples 10 */
Pawel Zarembski 0:0b221579ed52 874 /* ms */
Pawel Zarembski 0:0b221579ed52 875 #define FXPQ3115_CTRL_REG1_OS_OSR_4 ((uint8_t) 0x10) /* OSR = 4 and Minimum Time Between Data Samples 18 */
Pawel Zarembski 0:0b221579ed52 876 /* ms */
Pawel Zarembski 0:0b221579ed52 877 #define FXPQ3115_CTRL_REG1_OS_OSR_8 ((uint8_t) 0x18) /* OSR = 8 and Minimum Time Between Data Samples 34 */
Pawel Zarembski 0:0b221579ed52 878 /* ms */
Pawel Zarembski 0:0b221579ed52 879 #define FXPQ3115_CTRL_REG1_OS_OSR_16 ((uint8_t) 0x20) /* OSR = 16 and Minimum Time Between Data Samples 66 */
Pawel Zarembski 0:0b221579ed52 880 /* ms */
Pawel Zarembski 0:0b221579ed52 881 #define FXPQ3115_CTRL_REG1_OS_OSR_32 ((uint8_t) 0x28) /* OSR = 32 and Minimum Time Between Data Samples 130 */
Pawel Zarembski 0:0b221579ed52 882 /* ms */
Pawel Zarembski 0:0b221579ed52 883 #define FXPQ3115_CTRL_REG1_OS_OSR_64 ((uint8_t) 0x30) /* OSR = 64 and Minimum Time Between Data Samples 258 */
Pawel Zarembski 0:0b221579ed52 884 /* ms */
Pawel Zarembski 0:0b221579ed52 885 #define FXPQ3115_CTRL_REG1_OS_OSR_128 ((uint8_t) 0x38) /* OSR = 128 and Minimum Time Between Data Samples */
Pawel Zarembski 0:0b221579ed52 886 /* 512 ms */
Pawel Zarembski 0:0b221579ed52 887 #define FXPQ3115_CTRL_REG1_RAW_DIS ((uint8_t) 0x00) /* Raw output disabled. */
Pawel Zarembski 0:0b221579ed52 888 #define FXPQ3115_CTRL_REG1_RAW_EN ((uint8_t) 0x40) /* Raw output enabled. */
Pawel Zarembski 0:0b221579ed52 889 #define FXPQ3115_CTRL_REG1_ALT_ALT ((uint8_t) 0x80) /* Altimeter Mode. */
Pawel Zarembski 0:0b221579ed52 890 #define FXPQ3115_CTRL_REG1_ALT_BAR ((uint8_t) 0x00) /* Barometer Mode. */
Pawel Zarembski 0:0b221579ed52 891 /*------------------------------*/
Pawel Zarembski 0:0b221579ed52 892
Pawel Zarembski 0:0b221579ed52 893
Pawel Zarembski 0:0b221579ed52 894
Pawel Zarembski 0:0b221579ed52 895 /*--------------------------------
Pawel Zarembski 0:0b221579ed52 896 ** Register: CTRL_REG2
Pawel Zarembski 0:0b221579ed52 897 ** Enum: FXPQ3115_CTRL_REG2
Pawel Zarembski 0:0b221579ed52 898 ** --
Pawel Zarembski 0:0b221579ed52 899 ** Offset : 0x27 - Control Register 2: Acquisition time step.
Pawel Zarembski 0:0b221579ed52 900 ** ------------------------------*/
Pawel Zarembski 0:0b221579ed52 901 typedef union {
Pawel Zarembski 0:0b221579ed52 902 struct {
Pawel Zarembski 0:0b221579ed52 903 uint8_t st : 4; /* Auto acquisition time step.. */
Pawel Zarembski 0:0b221579ed52 904
Pawel Zarembski 0:0b221579ed52 905 uint8_t alarm_sel : 1; /* The bit selects the Target value for SRC_PW/SRC_TW and SRC_PTH/SRC_TTH. */
Pawel Zarembski 0:0b221579ed52 906
Pawel Zarembski 0:0b221579ed52 907 uint8_t load_output : 1; /* This is to load the target values for SRC_PW/SRC_TW and SRC_PTH/SRC_TTH. */
Pawel Zarembski 0:0b221579ed52 908
Pawel Zarembski 0:0b221579ed52 909 } b;
Pawel Zarembski 0:0b221579ed52 910 uint8_t w;
Pawel Zarembski 0:0b221579ed52 911 } FXPQ3115_CTRL_REG2_t;
Pawel Zarembski 0:0b221579ed52 912
Pawel Zarembski 0:0b221579ed52 913
Pawel Zarembski 0:0b221579ed52 914 /*
Pawel Zarembski 0:0b221579ed52 915 ** CTRL_REG2 - Bit field mask definitions
Pawel Zarembski 0:0b221579ed52 916 */
Pawel Zarembski 0:0b221579ed52 917 #define FXPQ3115_CTRL_REG2_ST_MASK ((uint8_t) 0x0F)
Pawel Zarembski 0:0b221579ed52 918 #define FXPQ3115_CTRL_REG2_ST_SHIFT ((uint8_t) 0)
Pawel Zarembski 0:0b221579ed52 919
Pawel Zarembski 0:0b221579ed52 920 #define FXPQ3115_CTRL_REG2_ALARM_SEL_MASK ((uint8_t) 0x10)
Pawel Zarembski 0:0b221579ed52 921 #define FXPQ3115_CTRL_REG2_ALARM_SEL_SHIFT ((uint8_t) 4)
Pawel Zarembski 0:0b221579ed52 922
Pawel Zarembski 0:0b221579ed52 923 #define FXPQ3115_CTRL_REG2_LOAD_OUTPUT_MASK ((uint8_t) 0x20)
Pawel Zarembski 0:0b221579ed52 924 #define FXPQ3115_CTRL_REG2_LOAD_OUTPUT_SHIFT ((uint8_t) 5)
Pawel Zarembski 0:0b221579ed52 925
Pawel Zarembski 0:0b221579ed52 926
Pawel Zarembski 0:0b221579ed52 927 /*
Pawel Zarembski 0:0b221579ed52 928 ** CTRL_REG2 - Bit field value definitions
Pawel Zarembski 0:0b221579ed52 929 */
Pawel Zarembski 0:0b221579ed52 930 #define FXPQ3115_CTRL_REG2_ALARM_SEL_USE_TGT ((uint8_t) 0x00) /* The values in P_TGT_MSB, P_TGT_LSB and T_TGT are */
Pawel Zarembski 0:0b221579ed52 931 /* used. */
Pawel Zarembski 0:0b221579ed52 932 #define FXPQ3115_CTRL_REG2_ALARM_SEL_USE_OUT ((uint8_t) 0x10) /* The values in OUT_P/OUT_T are used for calculating */
Pawel Zarembski 0:0b221579ed52 933 /* the interrupts SRC_PW/SRC_TW and SRC_PTH/SRC_TTH. */
Pawel Zarembski 0:0b221579ed52 934 #define FXPQ3115_CTRL_REG2_LOAD_OUTPUT_DNL ((uint8_t) 0x00) /* Do not load OUT_P/OUT_T as target values. */
Pawel Zarembski 0:0b221579ed52 935 #define FXPQ3115_CTRL_REG2_LOAD_OUTPUT_NXT_VAL ((uint8_t) 0x20) /* The next values of OUT_P/OUT_T are used to set the */
Pawel Zarembski 0:0b221579ed52 936 /* target values for the interrupts. */
Pawel Zarembski 0:0b221579ed52 937 /*------------------------------*/
Pawel Zarembski 0:0b221579ed52 938
Pawel Zarembski 0:0b221579ed52 939
Pawel Zarembski 0:0b221579ed52 940
Pawel Zarembski 0:0b221579ed52 941 /*--------------------------------
Pawel Zarembski 0:0b221579ed52 942 ** Register: CTRL_REG3
Pawel Zarembski 0:0b221579ed52 943 ** Enum: FXPQ3115_CTRL_REG3
Pawel Zarembski 0:0b221579ed52 944 ** --
Pawel Zarembski 0:0b221579ed52 945 ** Offset : 0x28 - Control Register 3: Interrupt pin configuration.
Pawel Zarembski 0:0b221579ed52 946 ** ------------------------------*/
Pawel Zarembski 0:0b221579ed52 947 typedef union {
Pawel Zarembski 0:0b221579ed52 948 struct {
Pawel Zarembski 0:0b221579ed52 949 uint8_t pp_od2 : 1; /* This bit configures the interrupt pad INT2 to Push-Pull or in Open Drain */
Pawel Zarembski 0:0b221579ed52 950 /* mode. */
Pawel Zarembski 0:0b221579ed52 951
Pawel Zarembski 0:0b221579ed52 952 uint8_t ipol2 : 1; /* Interrupt Polarity active high, or active low on interrupt pad INT2. */
Pawel Zarembski 0:0b221579ed52 953
Pawel Zarembski 0:0b221579ed52 954 uint8_t _reserved_ : 2;
Pawel Zarembski 0:0b221579ed52 955 uint8_t pp_od1 : 1; /* This bit configures the interrupt pad INT1 to Push-Pull or in Open Drain */
Pawel Zarembski 0:0b221579ed52 956 /* mode. */
Pawel Zarembski 0:0b221579ed52 957
Pawel Zarembski 0:0b221579ed52 958 uint8_t ipol1 : 1; /* Interrupt Polarity active high, or active low on interrupt pad INT1. */
Pawel Zarembski 0:0b221579ed52 959
Pawel Zarembski 0:0b221579ed52 960 } b;
Pawel Zarembski 0:0b221579ed52 961 uint8_t w;
Pawel Zarembski 0:0b221579ed52 962 } FXPQ3115_CTRL_REG3_t;
Pawel Zarembski 0:0b221579ed52 963
Pawel Zarembski 0:0b221579ed52 964
Pawel Zarembski 0:0b221579ed52 965 /*
Pawel Zarembski 0:0b221579ed52 966 ** CTRL_REG3 - Bit field mask definitions
Pawel Zarembski 0:0b221579ed52 967 */
Pawel Zarembski 0:0b221579ed52 968 #define FXPQ3115_CTRL_REG3_PP_OD2_MASK ((uint8_t) 0x01)
Pawel Zarembski 0:0b221579ed52 969 #define FXPQ3115_CTRL_REG3_PP_OD2_SHIFT ((uint8_t) 0)
Pawel Zarembski 0:0b221579ed52 970
Pawel Zarembski 0:0b221579ed52 971 #define FXPQ3115_CTRL_REG3_IPOL2_MASK ((uint8_t) 0x02)
Pawel Zarembski 0:0b221579ed52 972 #define FXPQ3115_CTRL_REG3_IPOL2_SHIFT ((uint8_t) 1)
Pawel Zarembski 0:0b221579ed52 973
Pawel Zarembski 0:0b221579ed52 974 #define FXPQ3115_CTRL_REG3_PP_OD1_MASK ((uint8_t) 0x10)
Pawel Zarembski 0:0b221579ed52 975 #define FXPQ3115_CTRL_REG3_PP_OD1_SHIFT ((uint8_t) 4)
Pawel Zarembski 0:0b221579ed52 976
Pawel Zarembski 0:0b221579ed52 977 #define FXPQ3115_CTRL_REG3_IPOL1_MASK ((uint8_t) 0x20)
Pawel Zarembski 0:0b221579ed52 978 #define FXPQ3115_CTRL_REG3_IPOL1_SHIFT ((uint8_t) 5)
Pawel Zarembski 0:0b221579ed52 979
Pawel Zarembski 0:0b221579ed52 980
Pawel Zarembski 0:0b221579ed52 981 /*
Pawel Zarembski 0:0b221579ed52 982 ** CTRL_REG3 - Bit field value definitions
Pawel Zarembski 0:0b221579ed52 983 */
Pawel Zarembski 0:0b221579ed52 984 #define FXPQ3115_CTRL_REG3_PP_OD2_INTPULLUP ((uint8_t) 0x00) /* Internal Pull-up. */
Pawel Zarembski 0:0b221579ed52 985 #define FXPQ3115_CTRL_REG3_PP_OD2_OPENDRAIN ((uint8_t) 0x01) /* Open drain. */
Pawel Zarembski 0:0b221579ed52 986 #define FXPQ3115_CTRL_REG3_IPOL2_LOW ((uint8_t) 0x00) /* Active low. */
Pawel Zarembski 0:0b221579ed52 987 #define FXPQ3115_CTRL_REG3_IPOL2_HIGH ((uint8_t) 0x02) /* Active high. */
Pawel Zarembski 0:0b221579ed52 988 #define FXPQ3115_CTRL_REG3_PP_OD1_INTPULLUP ((uint8_t) 0x00) /* Internal Pull-up. */
Pawel Zarembski 0:0b221579ed52 989 #define FXPQ3115_CTRL_REG3_PP_OD1_OPENDRAIN ((uint8_t) 0x10) /* Open drain. */
Pawel Zarembski 0:0b221579ed52 990 #define FXPQ3115_CTRL_REG3_IPOL1_LOW ((uint8_t) 0x00) /* Active low. */
Pawel Zarembski 0:0b221579ed52 991 #define FXPQ3115_CTRL_REG3_IPOL1_HIGH ((uint8_t) 0x20) /* Active high. */
Pawel Zarembski 0:0b221579ed52 992 /*------------------------------*/
Pawel Zarembski 0:0b221579ed52 993
Pawel Zarembski 0:0b221579ed52 994
Pawel Zarembski 0:0b221579ed52 995
Pawel Zarembski 0:0b221579ed52 996 /*--------------------------------
Pawel Zarembski 0:0b221579ed52 997 ** Register: CTRL_REG4
Pawel Zarembski 0:0b221579ed52 998 ** Enum: FXPQ3115_CTRL_REG4
Pawel Zarembski 0:0b221579ed52 999 ** --
Pawel Zarembski 0:0b221579ed52 1000 ** Offset : 0x29 - Control Register 4: Interrupt enables.
Pawel Zarembski 0:0b221579ed52 1001 ** ------------------------------*/
Pawel Zarembski 0:0b221579ed52 1002 typedef union {
Pawel Zarembski 0:0b221579ed52 1003 struct {
Pawel Zarembski 0:0b221579ed52 1004 uint8_t int_en_tchg : 1; /* Temperature Change Interrupt Enable. */
Pawel Zarembski 0:0b221579ed52 1005
Pawel Zarembski 0:0b221579ed52 1006 uint8_t int_en_pchg : 1; /* Pressure Change Interrupt Enable. */
Pawel Zarembski 0:0b221579ed52 1007
Pawel Zarembski 0:0b221579ed52 1008 uint8_t int_en_tth : 1; /* Temperature Threshold Interrupt Enable. */
Pawel Zarembski 0:0b221579ed52 1009
Pawel Zarembski 0:0b221579ed52 1010 uint8_t int_en_pth : 1; /* Pressure Threshold Interrupt Enable. */
Pawel Zarembski 0:0b221579ed52 1011
Pawel Zarembski 0:0b221579ed52 1012 uint8_t int_en_tw : 1; /* Temperature window Interrupt Enable. */
Pawel Zarembski 0:0b221579ed52 1013
Pawel Zarembski 0:0b221579ed52 1014 uint8_t int_en_pw : 1; /* Pressure window Interrupt Enable. */
Pawel Zarembski 0:0b221579ed52 1015
Pawel Zarembski 0:0b221579ed52 1016 uint8_t int_en_fifo : 1; /* FIFO Interrupt Enable. */
Pawel Zarembski 0:0b221579ed52 1017
Pawel Zarembski 0:0b221579ed52 1018 uint8_t int_en_drdy : 1; /* Data Ready Interrupt Enable. */
Pawel Zarembski 0:0b221579ed52 1019
Pawel Zarembski 0:0b221579ed52 1020 } b;
Pawel Zarembski 0:0b221579ed52 1021 uint8_t w;
Pawel Zarembski 0:0b221579ed52 1022 } FXPQ3115_CTRL_REG4_t;
Pawel Zarembski 0:0b221579ed52 1023
Pawel Zarembski 0:0b221579ed52 1024
Pawel Zarembski 0:0b221579ed52 1025 /*
Pawel Zarembski 0:0b221579ed52 1026 ** CTRL_REG4 - Bit field mask definitions
Pawel Zarembski 0:0b221579ed52 1027 */
Pawel Zarembski 0:0b221579ed52 1028 #define FXPQ3115_CTRL_REG4_INT_EN_TCHG_MASK ((uint8_t) 0x01)
Pawel Zarembski 0:0b221579ed52 1029 #define FXPQ3115_CTRL_REG4_INT_EN_TCHG_SHIFT ((uint8_t) 0)
Pawel Zarembski 0:0b221579ed52 1030
Pawel Zarembski 0:0b221579ed52 1031 #define FXPQ3115_CTRL_REG4_INT_EN_PCHG_MASK ((uint8_t) 0x02)
Pawel Zarembski 0:0b221579ed52 1032 #define FXPQ3115_CTRL_REG4_INT_EN_PCHG_SHIFT ((uint8_t) 1)
Pawel Zarembski 0:0b221579ed52 1033
Pawel Zarembski 0:0b221579ed52 1034 #define FXPQ3115_CTRL_REG4_INT_EN_TTH_MASK ((uint8_t) 0x04)
Pawel Zarembski 0:0b221579ed52 1035 #define FXPQ3115_CTRL_REG4_INT_EN_TTH_SHIFT ((uint8_t) 2)
Pawel Zarembski 0:0b221579ed52 1036
Pawel Zarembski 0:0b221579ed52 1037 #define FXPQ3115_CTRL_REG4_INT_EN_PTH_MASK ((uint8_t) 0x08)
Pawel Zarembski 0:0b221579ed52 1038 #define FXPQ3115_CTRL_REG4_INT_EN_PTH_SHIFT ((uint8_t) 3)
Pawel Zarembski 0:0b221579ed52 1039
Pawel Zarembski 0:0b221579ed52 1040 #define FXPQ3115_CTRL_REG4_INT_EN_TW_MASK ((uint8_t) 0x10)
Pawel Zarembski 0:0b221579ed52 1041 #define FXPQ3115_CTRL_REG4_INT_EN_TW_SHIFT ((uint8_t) 4)
Pawel Zarembski 0:0b221579ed52 1042
Pawel Zarembski 0:0b221579ed52 1043 #define FXPQ3115_CTRL_REG4_INT_EN_PW_MASK ((uint8_t) 0x20)
Pawel Zarembski 0:0b221579ed52 1044 #define FXPQ3115_CTRL_REG4_INT_EN_PW_SHIFT ((uint8_t) 5)
Pawel Zarembski 0:0b221579ed52 1045
Pawel Zarembski 0:0b221579ed52 1046 #define FXPQ3115_CTRL_REG4_INT_EN_FIFO_MASK ((uint8_t) 0x40)
Pawel Zarembski 0:0b221579ed52 1047 #define FXPQ3115_CTRL_REG4_INT_EN_FIFO_SHIFT ((uint8_t) 6)
Pawel Zarembski 0:0b221579ed52 1048
Pawel Zarembski 0:0b221579ed52 1049 #define FXPQ3115_CTRL_REG4_INT_EN_DRDY_MASK ((uint8_t) 0x80)
Pawel Zarembski 0:0b221579ed52 1050 #define FXPQ3115_CTRL_REG4_INT_EN_DRDY_SHIFT ((uint8_t) 7)
Pawel Zarembski 0:0b221579ed52 1051
Pawel Zarembski 0:0b221579ed52 1052
Pawel Zarembski 0:0b221579ed52 1053 /*
Pawel Zarembski 0:0b221579ed52 1054 ** CTRL_REG4 - Bit field value definitions
Pawel Zarembski 0:0b221579ed52 1055 */
Pawel Zarembski 0:0b221579ed52 1056 #define FXPQ3115_CTRL_REG4_INT_EN_TCHG_INTDISABLED ((uint8_t) 0x00) /* Temperature Change interrupt disabled. */
Pawel Zarembski 0:0b221579ed52 1057 #define FXPQ3115_CTRL_REG4_INT_EN_TCHG_INTENABLED ((uint8_t) 0x01) /* Temperature Change interrupt enabled */
Pawel Zarembski 0:0b221579ed52 1058 #define FXPQ3115_CTRL_REG4_INT_EN_PCHG_INTDISABLED ((uint8_t) 0x00) /* Pressure Change interrupt disabled. */
Pawel Zarembski 0:0b221579ed52 1059 #define FXPQ3115_CTRL_REG4_INT_EN_PCHG_INTENABLED ((uint8_t) 0x02) /* Pressure Change interrupt enabled */
Pawel Zarembski 0:0b221579ed52 1060 #define FXPQ3115_CTRL_REG4_INT_EN_TTH_INTDISABLED ((uint8_t) 0x00) /* Temperature Threshold interrupt disabled. */
Pawel Zarembski 0:0b221579ed52 1061 #define FXPQ3115_CTRL_REG4_INT_EN_TTH_INTENABLED ((uint8_t) 0x04) /* Temperature Threshold interrupt enabled */
Pawel Zarembski 0:0b221579ed52 1062 #define FXPQ3115_CTRL_REG4_INT_EN_PTH_INTDISABLED ((uint8_t) 0x00) /* Pressure Threshold interrupt disabled. */
Pawel Zarembski 0:0b221579ed52 1063 #define FXPQ3115_CTRL_REG4_INT_EN_PTH_INTENABLED ((uint8_t) 0x08) /* Pressure Threshold interrupt enabled */
Pawel Zarembski 0:0b221579ed52 1064 #define FXPQ3115_CTRL_REG4_INT_EN_TW_INTDISABLED ((uint8_t) 0x00) /* Temperature window interrupt disabled. */
Pawel Zarembski 0:0b221579ed52 1065 #define FXPQ3115_CTRL_REG4_INT_EN_TW_INTENABLED ((uint8_t) 0x10) /* Temperature window interrupt enabled */
Pawel Zarembski 0:0b221579ed52 1066 #define FXPQ3115_CTRL_REG4_INT_EN_PW_INTDISABLED ((uint8_t) 0x00) /* Pressure window interrupt disabled. */
Pawel Zarembski 0:0b221579ed52 1067 #define FXPQ3115_CTRL_REG4_INT_EN_PW_INTENABLED ((uint8_t) 0x20) /* Pressure window interrupt enabled */
Pawel Zarembski 0:0b221579ed52 1068 #define FXPQ3115_CTRL_REG4_INT_EN_FIFO_INTDISABLED ((uint8_t) 0x00) /* FIFO interrupt disabled. */
Pawel Zarembski 0:0b221579ed52 1069 #define FXPQ3115_CTRL_REG4_INT_EN_FIFO_INTENABLED ((uint8_t) 0x40) /* FIFO interrupt enabled */
Pawel Zarembski 0:0b221579ed52 1070 #define FXPQ3115_CTRL_REG4_INT_EN_DRDY_INTDISABLED ((uint8_t) 0x00) /* Data Ready interrupt disabled. */
Pawel Zarembski 0:0b221579ed52 1071 #define FXPQ3115_CTRL_REG4_INT_EN_DRDY_INTENABLED ((uint8_t) 0x80) /* Data Ready interrupt enabled. */
Pawel Zarembski 0:0b221579ed52 1072 /*------------------------------*/
Pawel Zarembski 0:0b221579ed52 1073
Pawel Zarembski 0:0b221579ed52 1074
Pawel Zarembski 0:0b221579ed52 1075
Pawel Zarembski 0:0b221579ed52 1076 /*--------------------------------
Pawel Zarembski 0:0b221579ed52 1077 ** Register: CTRL_REG5
Pawel Zarembski 0:0b221579ed52 1078 ** Enum: FXPQ3115_CTRL_REG5
Pawel Zarembski 0:0b221579ed52 1079 ** --
Pawel Zarembski 0:0b221579ed52 1080 ** Offset : 0x2A - Control Register 5: Interrupt output pin assignment.
Pawel Zarembski 0:0b221579ed52 1081 ** ------------------------------*/
Pawel Zarembski 0:0b221579ed52 1082 typedef union {
Pawel Zarembski 0:0b221579ed52 1083 struct {
Pawel Zarembski 0:0b221579ed52 1084 uint8_t int_cfg_tchg : 1; /* Temperature Change INT1/INT2 Configuration. */
Pawel Zarembski 0:0b221579ed52 1085
Pawel Zarembski 0:0b221579ed52 1086 uint8_t int_cfg_pchg : 1; /* Pressure Change INT1/INT2 Configuration. */
Pawel Zarembski 0:0b221579ed52 1087
Pawel Zarembski 0:0b221579ed52 1088 uint8_t int_cfg_tth : 1; /* Temperature Threshold INT1/INT2 Configuration. */
Pawel Zarembski 0:0b221579ed52 1089
Pawel Zarembski 0:0b221579ed52 1090 uint8_t int_cfg_pth : 1; /* Pressure Threshold INT1/INT2 Configuration. */
Pawel Zarembski 0:0b221579ed52 1091
Pawel Zarembski 0:0b221579ed52 1092 uint8_t int_cfg_tw : 1; /* Temperature window INT1/INT2 Configuration. */
Pawel Zarembski 0:0b221579ed52 1093
Pawel Zarembski 0:0b221579ed52 1094 uint8_t int_cfg_pw : 1; /* Pressure window INT1/INT2 Configuration. */
Pawel Zarembski 0:0b221579ed52 1095
Pawel Zarembski 0:0b221579ed52 1096 uint8_t int_cfg_fifo : 1; /* FIFO INT1/INT2 Configuration. */
Pawel Zarembski 0:0b221579ed52 1097
Pawel Zarembski 0:0b221579ed52 1098 uint8_t int_cfg_drdy : 1; /* Data Ready INT1/INT2 Configuration. */
Pawel Zarembski 0:0b221579ed52 1099
Pawel Zarembski 0:0b221579ed52 1100 } b;
Pawel Zarembski 0:0b221579ed52 1101 uint8_t w;
Pawel Zarembski 0:0b221579ed52 1102 } FXPQ3115_CTRL_REG5_t;
Pawel Zarembski 0:0b221579ed52 1103
Pawel Zarembski 0:0b221579ed52 1104
Pawel Zarembski 0:0b221579ed52 1105 /*
Pawel Zarembski 0:0b221579ed52 1106 ** CTRL_REG5 - Bit field mask definitions
Pawel Zarembski 0:0b221579ed52 1107 */
Pawel Zarembski 0:0b221579ed52 1108 #define FXPQ3115_CTRL_REG5_INT_CFG_TCHG_MASK ((uint8_t) 0x01)
Pawel Zarembski 0:0b221579ed52 1109 #define FXPQ3115_CTRL_REG5_INT_CFG_TCHG_SHIFT ((uint8_t) 0)
Pawel Zarembski 0:0b221579ed52 1110
Pawel Zarembski 0:0b221579ed52 1111 #define FXPQ3115_CTRL_REG5_INT_CFG_PCHG_MASK ((uint8_t) 0x02)
Pawel Zarembski 0:0b221579ed52 1112 #define FXPQ3115_CTRL_REG5_INT_CFG_PCHG_SHIFT ((uint8_t) 1)
Pawel Zarembski 0:0b221579ed52 1113
Pawel Zarembski 0:0b221579ed52 1114 #define FXPQ3115_CTRL_REG5_INT_CFG_TTH_MASK ((uint8_t) 0x04)
Pawel Zarembski 0:0b221579ed52 1115 #define FXPQ3115_CTRL_REG5_INT_CFG_TTH_SHIFT ((uint8_t) 2)
Pawel Zarembski 0:0b221579ed52 1116
Pawel Zarembski 0:0b221579ed52 1117 #define FXPQ3115_CTRL_REG5_INT_CFG_PTH_MASK ((uint8_t) 0x08)
Pawel Zarembski 0:0b221579ed52 1118 #define FXPQ3115_CTRL_REG5_INT_CFG_PTH_SHIFT ((uint8_t) 3)
Pawel Zarembski 0:0b221579ed52 1119
Pawel Zarembski 0:0b221579ed52 1120 #define FXPQ3115_CTRL_REG5_INT_CFG_TW_MASK ((uint8_t) 0x10)
Pawel Zarembski 0:0b221579ed52 1121 #define FXPQ3115_CTRL_REG5_INT_CFG_TW_SHIFT ((uint8_t) 4)
Pawel Zarembski 0:0b221579ed52 1122
Pawel Zarembski 0:0b221579ed52 1123 #define FXPQ3115_CTRL_REG5_INT_CFG_PW_MASK ((uint8_t) 0x20)
Pawel Zarembski 0:0b221579ed52 1124 #define FXPQ3115_CTRL_REG5_INT_CFG_PW_SHIFT ((uint8_t) 5)
Pawel Zarembski 0:0b221579ed52 1125
Pawel Zarembski 0:0b221579ed52 1126 #define FXPQ3115_CTRL_REG5_INT_CFG_FIFO_MASK ((uint8_t) 0x40)
Pawel Zarembski 0:0b221579ed52 1127 #define FXPQ3115_CTRL_REG5_INT_CFG_FIFO_SHIFT ((uint8_t) 6)
Pawel Zarembski 0:0b221579ed52 1128
Pawel Zarembski 0:0b221579ed52 1129 #define FXPQ3115_CTRL_REG5_INT_CFG_DRDY_MASK ((uint8_t) 0x80)
Pawel Zarembski 0:0b221579ed52 1130 #define FXPQ3115_CTRL_REG5_INT_CFG_DRDY_SHIFT ((uint8_t) 7)
Pawel Zarembski 0:0b221579ed52 1131
Pawel Zarembski 0:0b221579ed52 1132
Pawel Zarembski 0:0b221579ed52 1133 /*
Pawel Zarembski 0:0b221579ed52 1134 ** CTRL_REG5 - Bit field value definitions
Pawel Zarembski 0:0b221579ed52 1135 */
Pawel Zarembski 0:0b221579ed52 1136 #define FXPQ3115_CTRL_REG5_INT_CFG_TCHG_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
Pawel Zarembski 0:0b221579ed52 1137 #define FXPQ3115_CTRL_REG5_INT_CFG_TCHG_INT1 ((uint8_t) 0x01) /* Interrupt is routed to INT1 Pin. */
Pawel Zarembski 0:0b221579ed52 1138 #define FXPQ3115_CTRL_REG5_INT_CFG_PCHG_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
Pawel Zarembski 0:0b221579ed52 1139 #define FXPQ3115_CTRL_REG5_INT_CFG_PCHG_INT1 ((uint8_t) 0x02) /* Interrupt is routed to INT1 Pin. */
Pawel Zarembski 0:0b221579ed52 1140 #define FXPQ3115_CTRL_REG5_INT_CFG_TTH_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
Pawel Zarembski 0:0b221579ed52 1141 #define FXPQ3115_CTRL_REG5_INT_CFG_TTH_INT1 ((uint8_t) 0x04) /* Interrupt is routed to INT1 Pin. */
Pawel Zarembski 0:0b221579ed52 1142 #define FXPQ3115_CTRL_REG5_INT_CFG_PTH_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
Pawel Zarembski 0:0b221579ed52 1143 #define FXPQ3115_CTRL_REG5_INT_CFG_PTH_INT1 ((uint8_t) 0x08) /* Interrupt is routed to INT1 Pin. */
Pawel Zarembski 0:0b221579ed52 1144 #define FXPQ3115_CTRL_REG5_INT_CFG_TW_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
Pawel Zarembski 0:0b221579ed52 1145 #define FXPQ3115_CTRL_REG5_INT_CFG_TW_INT1 ((uint8_t) 0x10) /* Interrupt is routed to INT1 Pin. */
Pawel Zarembski 0:0b221579ed52 1146 #define FXPQ3115_CTRL_REG5_INT_CFG_PW_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
Pawel Zarembski 0:0b221579ed52 1147 #define FXPQ3115_CTRL_REG5_INT_CFG_PW_INT1 ((uint8_t) 0x20) /* Interrupt is routed to INT1 Pin. */
Pawel Zarembski 0:0b221579ed52 1148 #define FXPQ3115_CTRL_REG5_INT_CFG_FIFO_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
Pawel Zarembski 0:0b221579ed52 1149 #define FXPQ3115_CTRL_REG5_INT_CFG_FIFO_INT1 ((uint8_t) 0x40) /* Interrupt is routed to INT1 Pin. */
Pawel Zarembski 0:0b221579ed52 1150 #define FXPQ3115_CTRL_REG5_INT_CFG_DRDY_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
Pawel Zarembski 0:0b221579ed52 1151 #define FXPQ3115_CTRL_REG5_INT_CFG_DRDY_INT1 ((uint8_t) 0x80) /* Interrupt is routed to INT1 Pin. */
Pawel Zarembski 0:0b221579ed52 1152 /*------------------------------*/
Pawel Zarembski 0:0b221579ed52 1153
Pawel Zarembski 0:0b221579ed52 1154
Pawel Zarembski 0:0b221579ed52 1155
Pawel Zarembski 0:0b221579ed52 1156 /*--------------------------------
Pawel Zarembski 0:0b221579ed52 1157 ** Register: OFF_P
Pawel Zarembski 0:0b221579ed52 1158 ** Enum: FXPQ3115_OFF_P
Pawel Zarembski 0:0b221579ed52 1159 ** --
Pawel Zarembski 0:0b221579ed52 1160 ** Offset : 0x2B - Pressure data offset.
Pawel Zarembski 0:0b221579ed52 1161 ** ------------------------------*/
Pawel Zarembski 0:0b221579ed52 1162 typedef uint8_t FXPQ3115_OFF_P_t;
Pawel Zarembski 0:0b221579ed52 1163
Pawel Zarembski 0:0b221579ed52 1164
Pawel Zarembski 0:0b221579ed52 1165
Pawel Zarembski 0:0b221579ed52 1166 /*--------------------------------
Pawel Zarembski 0:0b221579ed52 1167 ** Register: OFF_T
Pawel Zarembski 0:0b221579ed52 1168 ** Enum: FXPQ3115_OFF_T
Pawel Zarembski 0:0b221579ed52 1169 ** --
Pawel Zarembski 0:0b221579ed52 1170 ** Offset : 0x2C - Temperature data offset.
Pawel Zarembski 0:0b221579ed52 1171 ** ------------------------------*/
Pawel Zarembski 0:0b221579ed52 1172 typedef uint8_t FXPQ3115_OFF_T_t;
Pawel Zarembski 0:0b221579ed52 1173
Pawel Zarembski 0:0b221579ed52 1174
Pawel Zarembski 0:0b221579ed52 1175
Pawel Zarembski 0:0b221579ed52 1176 /*--------------------------------
Pawel Zarembski 0:0b221579ed52 1177 ** Register: OFF_H
Pawel Zarembski 0:0b221579ed52 1178 ** Enum: FXPQ3115_OFF_H
Pawel Zarembski 0:0b221579ed52 1179 ** --
Pawel Zarembski 0:0b221579ed52 1180 ** Offset : 0x2D - Altitude data offset.
Pawel Zarembski 0:0b221579ed52 1181 ** ------------------------------*/
Pawel Zarembski 0:0b221579ed52 1182 typedef uint8_t FXPQ3115_OFF_H_t;