usbreg.h

00001 /*
00002  * Copyright (c) 2004-2016 ARM Limited. All rights reserved.
00003  *
00004  * SPDX-License-Identifier: Apache-2.0
00005  *
00006  * Licensed under the Apache License, Version 2.0 (the License); you may
00007  * not use this file except in compliance with the License.
00008  * You may obtain a copy of the License at
00009  *
00010  * http://www.apache.org/licenses/LICENSE-2.0
00011  *
00012  * Unless required by applicable law or agreed to in writing, software
00013  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
00014  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00015  * See the License for the specific language governing permissions and
00016  * limitations under the License.
00017  */
00018 
00019 /*----------------------------------------------------------------------------
00020  *      RL-ARM - USB
00021  *----------------------------------------------------------------------------
00022  *      Name:    usbreg.h
00023  *      Purpose: Hardware Layer Definitions for ST STM32F10x
00024  *---------------------------------------------------------------------------*/
00025 
00026 #ifndef __USBREG_H
00027 #define __USBREG_H
00028 
00029 
00030 #define REG(x)  (*((volatile unsigned int *)(x)))
00031 
00032 #define USB_BASE_ADDR   0x40005C00  /* USB Registers Base Address */
00033 #define USB_PMA_ADDR    0x40006000  /* USB Packet Memory Area Address */
00034 
00035 
00036 /* Common Registers */
00037 #define CNTR    REG(USB_BASE_ADDR + 0x40)   /* Control Register */
00038 #define ISTR    REG(USB_BASE_ADDR + 0x44)   /* Interrupt Status Register */
00039 #define FNR     REG(USB_BASE_ADDR + 0x48)   /* Frame Number Register */
00040 #define DADDR   REG(USB_BASE_ADDR + 0x4C)   /* Device Address Register */
00041 #define BTABLE  REG(USB_BASE_ADDR + 0x50)   /* Buffer Table Address Register */
00042 
00043 /* CNTR: Control Register Bit Definitions */
00044 #define CNTR_CTRM       0x8000      /* Correct Transfer Interrupt Mask */
00045 #define CNTR_PMAOVRM    0x4000      /* Packet Memory Aerea Over/underrun Interrupt Mask */
00046 #define CNTR_ERRM       0x2000      /* Error Interrupt Mask */
00047 #define CNTR_WKUPM      0x1000      /* Wake-up Interrupt Mask */
00048 #define CNTR_SUSPM      0x0800      /* Suspend Mode Interrupt Mask  */
00049 #define CNTR_RESETM     0x0400      /* USB Reset Interrupt Mask   */
00050 #define CNTR_SOFM       0x0200      /* Start of Frame Interrupt Mask */
00051 #define CNTR_ESOFM      0x0100      /* Expected Start of Frame Interrupt Mask */
00052 #define CNTR_RESUME     0x0010      /* Resume Request */
00053 #define CNTR_FSUSP      0x0008      /* Force Suspend */
00054 #define CNTR_LPMODE     0x0004      /* Low-power Mode */
00055 #define CNTR_PDWN       0x0002      /* Power Down */
00056 #define CNTR_FRES       0x0001      /* Force USB Reset */
00057 
00058 /* ISTR: Interrupt Status Register Bit Definitions */
00059 #define ISTR_CTR        0x8000      /* Correct Transfer */
00060 #define ISTR_PMAOVR     0x4000      /* Packet Memory Aerea Over/underrun */
00061 #define ISTR_ERR        0x2000      /* Error */
00062 #define ISTR_WKUP       0x1000      /* Wake-up */
00063 #define ISTR_SUSP       0x0800      /* Suspend Mode */
00064 #define ISTR_RESET      0x0400      /* USB Reset */
00065 #define ISTR_SOF        0x0200      /* Start of Frame */
00066 #define ISTR_ESOF       0x0100      /* Expected Start of Frame */
00067 #define ISTR_DIR        0x0010      /* Direction of Transaction */
00068 #define ISTR_EP_ID      0x000F      /* EndPoint Identifier */
00069 
00070 /* FNR: Frame Number Register Bit Definitions */
00071 #define FNR_RXDP        0x8000      /* D+ Data Line Status */
00072 #define FNR_RXDM        0x4000      /* D- Data Line Status */
00073 #define FNR_LCK         0x2000      /* Locked */
00074 #define FNR_LSOF        0x1800      /* Lost SOF */
00075 #define FNR_FN          0x07FF      /* Frame Number */
00076 
00077 /* DADDR: Device Address Register Bit Definitions */
00078 #define DADDR_EF        0x0080      /* Enable Function */
00079 #define DADDR_ADD       0x007F      /* Device Address */
00080 
00081 
00082 /* EndPoint Registers */
00083 #define EPxREG(x)       REG(USB_BASE_ADDR + 4*(x))
00084 
00085 /* EPxREG: EndPoint Registers Bit Definitions */
00086 #define EP_CTR_RX       0x8000      /* Correct RX Transfer */
00087 #define EP_DTOG_RX      0x4000      /* RX Data Toggle */
00088 #define EP_STAT_RX      0x3000      /* RX Status */
00089 #define EP_SETUP        0x0800      /* EndPoint Setup */
00090 #define EP_TYPE         0x0600      /* EndPoint Type */
00091 #define EP_KIND         0x0100      /* EndPoint Kind */
00092 #define EP_CTR_TX       0x0080      /* Correct TX Transfer */
00093 #define EP_DTOG_TX      0x0040      /* TX Data Toggle */
00094 #define EP_STAT_TX      0x0030      /* TX Status */
00095 #define EP_EA           0x000F      /* EndPoint Address */
00096 
00097 /* EndPoint Register Mask (No Toggle Fields) */
00098 #define EP_MASK         (EP_CTR_RX|EP_SETUP|EP_TYPE|EP_KIND|EP_CTR_TX|EP_EA)
00099 /* EndPoint Register Mask (Write zero to clear) */
00100 #define EP_MASK_RC_W0   (EP_CTR_RX|EP_CTR_TX)
00101 /* Mask off all toggle bits and set write zero to clear bits to 1.          */
00102 /* This creates a value that can be written back to the EndPoint register   */
00103 /* which does not change any status bits.                                   */
00104 #define EP_VAL_UNCHANGED(val)       (((val) & EP_MASK) | EP_MASK_RC_W0)
00105 
00106 /* EP_TYPE: EndPoint Types */
00107 #define EP_BULK         0x0000      /* BULK EndPoint */
00108 #define EP_CONTROL      0x0200      /* CONTROL EndPoint */
00109 #define EP_ISOCHRONOUS  0x0400      /* ISOCHRONOUS EndPoint */
00110 #define EP_INTERRUPT    0x0600      /* INTERRUPT EndPoint */
00111 
00112 /* EP_KIND: EndPoint Kind */
00113 #define EP_DBL_BUF      EP_KIND     /* Double Buffer for Bulk Endpoint */
00114 #define EP_STATUS_OUT   EP_KIND     /* Status Out for Control Endpoint */
00115 
00116 /* EP_STAT_TX: TX Status */
00117 #define EP_TX_DIS       0x0000      /* Disabled */
00118 #define EP_TX_STALL     0x0010      /* Stalled */
00119 #define EP_TX_NAK       0x0020      /* NAKed */
00120 #define EP_TX_VALID     0x0030      /* Valid */
00121 
00122 /* EP_STAT_RX: RX Status */
00123 #define EP_RX_DIS       0x0000      /* Disabled */
00124 #define EP_RX_STALL     0x1000      /* Stalled */
00125 #define EP_RX_NAK       0x2000      /* NAKed */
00126 #define EP_RX_VALID     0x3000      /* Valid */
00127 
00128 
00129 /* Endpoint Buffer Descriptor */
00130 typedef struct _EP_BUF_DSCR {
00131     U32 ADDR_TX;
00132     U32 COUNT_TX;
00133     U32 ADDR_RX;
00134     U32 COUNT_RX;
00135 } EP_BUF_DSCR;
00136 
00137 #define EP_ADDR_MASK    0xFFFE      /* Address Mask */
00138 #define EP_COUNT_MASK   0x03FF      /* Count Mask */
00139 
00140 
00141 #endif  /* __USBREG_H */