usbd_m480.c

00001 /*
00002  * Copyright (c) 2004-2016 ARM Limited. All rights reserved.
00003  *
00004  * SPDX-License-Identifier: Apache-2.0
00005  *
00006  * Licensed under the Apache License, Version 2.0 (the License); you may
00007  * not use this file except in compliance with the License.
00008  * You may obtain a copy of the License at
00009  *
00010  * http://www.apache.org/licenses/LICENSE-2.0
00011  *
00012  * Unless required by applicable law or agreed to in writing, software
00013  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
00014  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00015  * See the License for the specific language governing permissions and
00016  * limitations under the License.
00017  */
00018 
00019 #include <rl_usb.h>
00020 #include "NuMicro.h"
00021 
00022 #define __NO_USB_LIB_C
00023 #include "usb_config.c"
00024 
00025 /* Bit definition of CEPCTL register */
00026 #define HSUSBD_CEPCTL_NAKCLR               ((uint32_t)0x00000000UL)
00027 #define HSUSBD_CEPCTL_STALL                ((uint32_t)0x00000002UL)
00028 #define HSUSBD_CEPCTL_ZEROLEN              ((uint32_t)0x00000004UL)
00029 #define HSUSBD_CEPCTL_FLUSH                ((uint32_t)0x00000008UL)
00030 
00031 /* Bit definition of EPxRSPCTL register */
00032 #define HSUSBD_EP_RSPCTL_FLUSH             ((uint32_t)0x00000001UL)
00033 #define HSUSBD_EP_RSPCTL_MODE_AUTO         ((uint32_t)0x00000000UL)
00034 #define HSUSBD_EP_RSPCTL_MODE_MANUAL       ((uint32_t)0x00000002UL)
00035 #define HSUSBD_EP_RSPCTL_MODE_FLY          ((uint32_t)0x00000004UL)
00036 #define HSUSBD_EP_RSPCTL_MODE_MASK         ((uint32_t)0x00000006UL)
00037 #define HSUSBD_EP_RSPCTL_TOGGLE            ((uint32_t)0x00000008UL)
00038 #define HSUSBD_EP_RSPCTL_HALT              ((uint32_t)0x00000010UL)
00039 #define HSUSBD_EP_RSPCTL_ZEROLEN           ((uint32_t)0x00000020UL)
00040 #define HSUSBD_EP_RSPCTL_SHORTTXEN         ((uint32_t)0x00000040UL)
00041 #define HSUSBD_EP_RSPCTL_DISBUF            ((uint32_t)0x00000080UL)
00042 
00043 /* Bit definition of EPxCFG register */
00044 #define HSUSBD_EP_CFG_VALID                ((uint32_t)0x00000001UL)
00045 #define HSUSBD_EP_CFG_TYPE_BULK            ((uint32_t)0x00000002UL)
00046 #define HSUSBD_EP_CFG_TYPE_INT             ((uint32_t)0x00000004UL)
00047 #define HSUSBD_EP_CFG_TYPE_ISO             ((uint32_t)0x00000006UL)
00048 #define HSUSBD_EP_CFG_TYPE_MASK            ((uint32_t)0x00000006UL)
00049 #define HSUSBD_EP_CFG_DIR_OUT              ((uint32_t)0x00000000UL)
00050 #define HSUSBD_EP_CFG_DIR_IN               ((uint32_t)0x00000008UL)
00051 
00052 #define HSUSBD_ENABLE_USB()               ((uint32_t)(HSUSBD->PHYCTL |= (HSUSBD_PHYCTL_PHYEN_Msk|HSUSBD_PHYCTL_DPPUEN_Msk)))
00053 #define HSUSBD_DISABLE_USB()              ((uint32_t)(HSUSBD->PHYCTL &= ~HSUSBD_PHYCTL_DPPUEN_Msk))
00054 #define HSUSBD_ENABLE_PHY()               ((uint32_t)(HSUSBD->PHYCTL |= HSUSBD_PHYCTL_PHYEN_Msk))
00055 #define HSUSBD_DISABLE_PHY()              ((uint32_t)(HSUSBD->PHYCTL &= ~HSUSBD_PHYCTL_PHYEN_Msk))
00056 #define HSUSBD_SET_SE0()                  ((uint32_t)(HSUSBD->PHYCTL &= ~HSUSBD_PHYCTL_DPPUEN_Msk))
00057 #define HSUSBD_CLR_SE0()                  ((uint32_t)(HSUSBD->PHYCTL |= HSUSBD_PHYCTL_DPPUEN_Msk))
00058 #define HSUSBD_SET_ADDR(addr)             (HSUSBD->FADDR = (addr))
00059 #define HSUSBD_GET_ADDR()                 ((uint32_t)(HSUSBD->FADDR))
00060 #define HSUSBD_ENABLE_USB_INT(intr)       (HSUSBD->GINTEN = (intr))
00061 #define HSUSBD_ENABLE_BUS_INT(intr)       (HSUSBD->BUSINTEN = (intr))
00062 #define HSUSBD_GET_BUS_INT_FLAG()         (HSUSBD->BUSINTSTS)
00063 #define HSUSBD_CLR_BUS_INT_FLAG(flag)     (HSUSBD->BUSINTSTS = (flag))
00064 #define HSUSBD_ENABLE_CEP_INT(intr)       (HSUSBD->CEPINTEN = (intr))
00065 #define HSUSBD_CLR_CEP_INT_FLAG(flag)     (HSUSBD->CEPINTSTS = (flag))
00066 #define HSUSBD_SET_CEP_STATE(flag)        (HSUSBD->CEPCTL = (flag))
00067 #define HSUSBD_START_CEP_IN(size)         (HSUSBD->CEPTXCNT = (size))
00068 #define HSUSBD_SET_MAX_PAYLOAD(ep, size)  (HSUSBD->EP[(ep)].EPMPS = (size))
00069 #define HSUSBD_ENABLE_EP_INT(ep, intr)    (HSUSBD->EP[(ep)].EPINTEN = (intr))
00070 #define HSUSBD_GET_EP_INT_FLAG(ep)        (HSUSBD->EP[(ep)].EPINTSTS)
00071 #define HSUSBD_CLR_EP_INT_FLAG(ep, flag)  (HSUSBD->EP[(ep)].EPINTSTS = (flag))
00072 #define HSUSBD_SET_DMA_LEN(len)           (HSUSBD->DMACNT = (len))
00073 #define HSUSBD_SET_DMA_ADDR(addr)         (HSUSBD->DMAADDR = (addr))
00074 #define HSUSBD_SET_DMA_READ(epnum)        (HSUSBD->DMACTL = (HSUSBD->DMACTL & ~HSUSBD_DMACTL_EPNUM_Msk) | HSUSBD_DMACTL_DMARD_Msk | (epnum) | 0x100)
00075 #define HSUSBD_SET_DMA_WRITE(epnum)       (HSUSBD->DMACTL = (HSUSBD->DMACTL & ~(HSUSBD_DMACTL_EPNUM_Msk | HSUSBD_DMACTL_DMARD_Msk | 0x100)) | (epnum))
00076 #define HSUSBD_ENABLE_DMA()               (HSUSBD->DMACTL |= HSUSBD_DMACTL_DMAEN_Msk)
00077 #define HSUSBD_IS_ATTACHED()              ((uint32_t)(HSUSBD->PHYCTL & HSUSBD_PHYCTL_VBUSDET_Msk))
00078 
00079 #define HSUSBD_MAX_EP       12UL
00080 #define CEP                 0xFFUL
00081 #define EPA                 0UL
00082 #define EPB                 1UL
00083 #define EPC                 2UL
00084 #define EPD                 3UL
00085 #define EPE                 4UL
00086 #define EPF                 5UL
00087 #define EPG                 6UL
00088 #define EPH                 7UL
00089 #define EPI                 8UL
00090 #define EPJ                 9UL
00091 #define EPK                 10UL
00092 #define EPL                 11UL
00093 
00094 #define USBD_EP_TO_NUM(ep)  ((ep == CEP) ? (0) : (1 + (ep - EPA)))
00095 #define USBD_NUM_TO_EP(num) ((num == 0) ? (CEP) : (EPA + (num - 1)))
00096 
00097 #define CEP_BUF_BASE        0
00098 #define CEP_BUF_LEN         USBD_MAX_PACKET0
00099 
00100 static uint32_t g_u32FreeBufAddr;
00101 static uint8_t g_u8StatusIn;
00102 
00103 /*
00104  *  USB Device Interrupt enable
00105  *   Called by USBD_Init to enable the USB Interrupt
00106  *    Return Value:    None
00107  */
00108 
00109 #ifdef __RTX
00110 void __svc(1) USBD_IntrEna(void);
00111 void __SVC_1(void)
00112 {
00113 #else
00114 void          USBD_IntrEna(void)
00115 {
00116 #endif
00117     NVIC_EnableIRQ(USBD20_IRQn );
00118 }
00119 
00120 
00121 /*
00122  *  USB Device Initialize Function
00123  *   Called by the User to initialize USB
00124  *    Return Value:    None
00125  */
00126 
00127 void USBD_Init(void)
00128 {
00129     uint32_t volatile i;
00130     /* Initial USB engine */
00131     HSUSBD_ENABLE_PHY();
00132 
00133     /* wait PHY clock ready */
00134     while (1) {
00135         HSUSBD->EP[EPA].EPMPS = 0x20UL;
00136 
00137         if (HSUSBD->EP[EPA].EPMPS == 0x20UL) {
00138             break;
00139         }
00140     }
00141 
00142     for (i = 0; i < 0x10000; i++);
00143 
00144     if (HSUSBD->OPER & HSUSBD_OPER_CURSPD_Msk) {
00145         USBD_HighSpeed = __TRUE;
00146     } else {
00147         USBD_HighSpeed = __FALSE;
00148     }
00149 
00150     /* Enable USB BUS, CEP global interrupt */
00151     HSUSBD_ENABLE_USB_INT(HSUSBD_GINTEN_USBIEN_Msk | HSUSBD_GINTEN_CEPIEN_Msk);
00152     /* Enable BUS interrupt */
00153     HSUSBD_ENABLE_BUS_INT(HSUSBD_BUSINTEN_RESUMEIEN_Msk | HSUSBD_BUSINTEN_RSTIEN_Msk | HSUSBD_BUSINTEN_VBUSDETIEN_Msk | HSUSBD_BUSINTEN_SOFIEN_Msk);
00154     /* Reset Address to 0 */
00155     HSUSBD_SET_ADDR(0);
00156     /* Control endpoint */
00157     HSUSBD->CEPBUFST = CEP_BUF_BASE;
00158     HSUSBD->CEPBUFEND = CEP_BUF_BASE + CEP_BUF_LEN - 1UL;
00159     HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_SETUPPKIEN_Msk | HSUSBD_CEPINTEN_STSDONEIEN_Msk | HSUSBD_CEPINTEN_RXPKIEN_Msk | HSUSBD_CEPINTEN_TXPKIEN_Msk);
00160     USBD_IntrEna();
00161 }
00162 
00163 
00164 /*
00165  *  USB Device Connect Function
00166  *   Called by the User to Connect/Disconnect USB Device
00167  *    Parameters:      con:   Connect/Disconnect
00168  *    Return Value:    None
00169  */
00170 
00171 void USBD_Connect(BOOL con)
00172 {
00173     if (con) {
00174         HSUSBD_CLR_SE0();
00175     } else {
00176         HSUSBD_SET_SE0();
00177     }
00178 }
00179 
00180 
00181 /*
00182  *  USB Device Reset Function
00183  *   Called automatically on USB Device Reset
00184  *    Return Value:    None
00185  */
00186 
00187 void USBD_Reset(void)
00188 {
00189     uint32_t i;
00190 
00191     for (i = 0; i < HSUSBD_MAX_EP; i++) {
00192         HSUSBD->EP[EPA + i].EPRSPCTL = HSUSBD_EPRSPCTL_FLUSH_Msk;
00193     }
00194 
00195     if (HSUSBD->OPER & HSUSBD_OPER_CURSPD_Msk) {
00196         USBD_HighSpeed = __TRUE;
00197     } else {
00198         USBD_HighSpeed = __FALSE;
00199     }
00200 
00201     g_u32FreeBufAddr = CEP_BUF_BASE + CEP_BUF_LEN;
00202     g_u8StatusIn = 0;
00203     HSUSBD_SET_ADDR(0);
00204 }
00205 
00206 
00207 /*
00208  *  USB Device Suspend Function
00209  *   Called automatically on USB Device Suspend
00210  *    Return Value:    None
00211  */
00212 
00213 void USBD_Suspend(void)
00214 {
00215 }
00216 
00217 
00218 /*
00219  *  USB Device Resume Function
00220  *   Called automatically on USB Device Resume
00221  *    Return Value:    None
00222  */
00223 
00224 void USBD_Resume(void)
00225 {
00226 }
00227 
00228 
00229 /*
00230  *  USB Device Remote Wakeup Function
00231  *   Called automatically on USB Device Remote Wakeup
00232  *    Return Value:    None
00233  */
00234 
00235 void USBD_WakeUp(void)
00236 {
00237 }
00238 
00239 
00240 /*
00241  *  USB Device Remote Wakeup Configuration Function
00242  *    Parameters:      cfg:   Device Enable/Disable
00243  *    Return Value:    None
00244  */
00245 
00246 void USBD_WakeUpCfg(BOOL cfg)
00247 {
00248 }
00249 
00250 
00251 /*
00252  *  USB Device Set Address Function
00253  *    Parameters:      adr:   USB Device Address
00254  *                     setup: Called in setup stage (!=0), else after status stage
00255  *    Return Value:    None
00256  */
00257 
00258 void USBD_SetAddress(U32 adr, U32 setup)
00259 {
00260     if (setup) {
00261         return;
00262     }
00263 
00264     HSUSBD_SET_ADDR(adr);
00265 }
00266 
00267 
00268 /*
00269  *  USB Device Configure Function
00270  *    Parameters:      cfg:   Device Configure/Deconfigure
00271  *    Return Value:    None
00272  */
00273 
00274 void USBD_Configure(BOOL cfg)
00275 {
00276     if (cfg == __FALSE) {
00277         g_u32FreeBufAddr = CEP_BUF_BASE + CEP_BUF_LEN;
00278     }
00279 }
00280 
00281 
00282 /*
00283  *  Configure USB Device Endpoint according to Descriptor
00284  *    Parameters:      pEPD:  Pointer to Device Endpoint Descriptor
00285  *    Return Value:    None
00286  */
00287 
00288 void USBD_ConfigEP(USB_ENDPOINT_DESCRIPTOR *pEPD)
00289 {
00290     uint32_t u32Num, u32Ep, u32Size, u32Type, u32Dir;
00291     u32Num = pEPD->bEndpointAddress & 0x0F;
00292     u32Ep = USBD_NUM_TO_EP(u32Num);
00293     u32Size = pEPD->wMaxPacketSize;
00294 
00295     switch (pEPD->bmAttributes & USB_ENDPOINT_TYPE_MASK) {
00296         case USB_ENDPOINT_TYPE_ISOCHRONOUS:
00297             u32Type = HSUSBD_EP_CFG_TYPE_ISO;
00298             break;
00299 
00300         case USB_ENDPOINT_TYPE_BULK:
00301             u32Type = HSUSBD_EP_CFG_TYPE_BULK;
00302             break;
00303 
00304         case USB_ENDPOINT_TYPE_INTERRUPT:
00305             u32Type = HSUSBD_EP_CFG_TYPE_INT;
00306             break;
00307     }
00308 
00309     if (pEPD->bEndpointAddress & USB_ENDPOINT_DIRECTION_MASK) {
00310         u32Dir = HSUSBD_EP_CFG_DIR_IN;
00311     } else {
00312         u32Dir = HSUSBD_EP_CFG_DIR_OUT;
00313     }
00314 
00315     HSUSBD->EP[u32Ep].EPBUFST = g_u32FreeBufAddr;
00316     HSUSBD->EP[u32Ep].EPBUFEND = g_u32FreeBufAddr + u32Size - 1UL;
00317     HSUSBD_SET_MAX_PAYLOAD(u32Ep, u32Size);
00318     HSUSBD->EP[u32Ep].EPRSPCTL = (HSUSBD_EP_RSPCTL_FLUSH | HSUSBD_EP_RSPCTL_MODE_AUTO);
00319     HSUSBD->EP[u32Ep].EPCFG = (u32Type | u32Dir | HSUSBD_EP_CFG_VALID | (u32Num << 4));
00320     g_u32FreeBufAddr += u32Size;
00321 }
00322 
00323 
00324 /*
00325  *  Set Direction for USB Device Control Endpoint
00326  *    Parameters:      dir:   Out (dir == 0), In (dir <> 0)
00327  *    Return Value:    None
00328  */
00329 
00330 void USBD_DirCtrlEP(U32 dir)
00331 {
00332 }
00333 
00334 
00335 /*
00336  *  Enable USB Device Endpoint
00337  *    Parameters:      EPNum: Device Endpoint Number
00338  *                       EPNum.0..3: Address
00339  *                       EPNum.7:    Dir
00340  *    Return Value:    None
00341  */
00342 
00343 void USBD_EnableEP(U32 EPNum)
00344 {
00345     uint32_t u32Ep, u32Num, u32Intr;
00346     u32Num = EPNum & 0x0F;
00347     u32Ep = USBD_NUM_TO_EP(u32Num);
00348     HSUSBD->GINTEN |= (0x1UL << (HSUSBD_GINTEN_EPAIEN_Pos + (u32Num - USBD_EP_TO_NUM(EPA))));
00349 
00350     if (EPNum & 0x80) {
00351         u32Intr = HSUSBD_EPINTEN_TXPKIEN_Msk;
00352     } else {
00353         u32Intr = HSUSBD_EPINTEN_RXPKIEN_Msk | HSUSBD_EPINTEN_SHORTRXIEN_Msk | HSUSBD_EPINTEN_BUFFULLIEN_Msk;
00354     }
00355 
00356     HSUSBD_ENABLE_EP_INT(u32Ep, u32Intr);
00357 }
00358 
00359 
00360 /*
00361  *  Disable USB Endpoint
00362  *    Parameters:      EPNum: Endpoint Number
00363  *                       EPNum.0..3: Address
00364  *                       EPNum.7:    Dir
00365  *    Return Value:    None
00366  */
00367 
00368 void USBD_DisableEP(U32 EPNum)
00369 {
00370     uint32_t u32Ep, u32Num;
00371     u32Num = EPNum & 0x0F;
00372     u32Ep = USBD_NUM_TO_EP(u32Num);
00373     HSUSBD->GINTEN &= ~(0x1UL << (HSUSBD_GINTEN_EPAIEN_Pos + (u32Num - USBD_EP_TO_NUM(EPA))));
00374     HSUSBD_ENABLE_EP_INT(u32Ep, 0);
00375 }
00376 
00377 
00378 /*
00379  *  Reset USB Device Endpoint
00380  *    Parameters:      EPNum: Device Endpoint Number
00381  *                       EPNum.0..3: Address
00382  *                       EPNum.7:    Dir
00383  *    Return Value:    None
00384  */
00385 
00386 void USBD_ResetEP(U32 EPNum)
00387 {
00388     uint32_t u32Ep, u32Num;
00389     u32Num = EPNum & 0x0F;
00390     u32Ep = USBD_NUM_TO_EP(u32Num);
00391     HSUSBD->EP[u32Ep].EPRSPCTL = (HSUSBD->EP[u32Ep].EPRSPCTL & HSUSBD_EP_RSPCTL_MODE_MASK) | HSUSBD_EPRSPCTL_FLUSH_Msk;
00392 }
00393 
00394 
00395 /*
00396  *  Set Stall for USB Device Endpoint
00397  *    Parameters:      EPNum: Device Endpoint Number
00398  *                       EPNum.0..3: Address
00399  *                       EPNum.7:    Dir
00400  *    Return Value:    None
00401  */
00402 
00403 void USBD_SetStallEP(U32 EPNum)
00404 {
00405     uint32_t u32Ep, u32Num;
00406     u32Num = EPNum & 0x0F;
00407     u32Ep = USBD_NUM_TO_EP(u32Num);
00408 
00409     if (u32Ep == CEP) {
00410         HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_STALL);
00411     } else {
00412         HSUSBD->EP[u32Ep].EPRSPCTL = (HSUSBD->EP[u32Ep].EPRSPCTL & 0xF7UL) | HSUSBD_EP_RSPCTL_HALT;
00413     }
00414 }
00415 
00416 
00417 /*
00418  *  Clear Stall for USB Device Endpoint
00419  *    Parameters:      EPNum: Device Endpoint Number
00420  *                       EPNum.0..3: Address
00421  *                       EPNum.7:    Dir
00422  *    Return Value:    None
00423  */
00424 
00425 void USBD_ClrStallEP(U32 EPNum)
00426 {
00427     uint32_t u32Ep, u32Num;
00428     u32Num = EPNum & 0x0F;
00429     u32Ep = USBD_NUM_TO_EP(u32Num);
00430 
00431     if (u32Ep == CEP) {
00432         HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_NAKCLR_Msk);
00433     } else {
00434         HSUSBD->EP[u32Ep].EPRSPCTL = (HSUSBD->EP[u32Ep].EPRSPCTL & HSUSBD_EP_RSPCTL_MODE_MASK) | HSUSBD_EP_RSPCTL_TOGGLE;
00435     }
00436 }
00437 
00438 
00439 /*
00440  *  Clear USB Device Endpoint Buffer
00441  *    Parameters:      EPNum: Device Endpoint Number
00442  *                       EPNum.0..3: Address
00443  *                       EPNum.7:    Dir
00444  *    Return Value:    None
00445  */
00446 
00447 void USBD_ClearEPBuf(U32 EPNum)
00448 {
00449 }
00450 
00451 
00452 /*
00453  *  Read USB Device Endpoint Data
00454  *    Parameters:      EPNum: Device Endpoint Number
00455  *                       EPNum.0..3: Address
00456  *                       EPNum.7:    Dir
00457  *                     pData: Pointer to Data Buffer
00458  *    Return Value:    Number of bytes read
00459  */
00460 
00461 U32 USBD_ReadEP(U32 EPNum, U8 *pData, U32 bufsz)
00462 {
00463     uint32_t u32Ep, u32Num, u32Len, i;
00464     u32Num = EPNum & 0x0F;
00465     u32Ep = USBD_NUM_TO_EP(u32Num);
00466 
00467     if (u32Num == 0) {
00468         if (pData == (uint8_t *)&USBD_SetupPacket) {
00469             *((uint16_t *)(pData + 0)) = (uint16_t)(HSUSBD->SETUP1_0 & 0xFFFFUL);
00470             *((uint16_t *)(pData + 2)) = (uint16_t)(HSUSBD->SETUP3_2 & 0xFFFFUL);
00471             *((uint16_t *)(pData + 4)) = (uint16_t)(HSUSBD->SETUP5_4 & 0xFFFFUL);
00472             *((uint16_t *)(pData + 6)) = (uint16_t)(HSUSBD->SETUP7_6 & 0xFFFFUL);
00473             return 8;
00474         } else {
00475             u32Len = HSUSBD->CEPDATCNT & 0xFFFFUL;
00476 
00477             if (u32Len > bufsz) {
00478                 u32Len = bufsz;
00479             }
00480 
00481             for (i = 0; i < bufsz; i++) {
00482                 pData[i] = inpb(&HSUSBD->CEPDAT);
00483             }
00484 
00485             return u32Len;
00486         }
00487     } else {
00488         u32Len = HSUSBD->EP[u32Ep].EPDATCNT & 0xFFFFUL;
00489 
00490         if (u32Len > bufsz) {
00491             u32Len = bufsz;
00492         }
00493 
00494         for (i = 0; i < u32Len; i++) {
00495             pData[i] = HSUSBD->EP[u32Ep].EPDAT_BYTE;
00496         }
00497 
00498         return u32Len;
00499     }
00500 }
00501 
00502 
00503 /*
00504  *  Write USB Device Endpoint Data
00505  *    Parameters:      EPNum: Device Endpoint Number
00506  *                       EPNum.0..3: Address
00507  *                       EPNum.7:    Dir
00508  *                     pData: Pointer to Data Buffer
00509  *                     cnt:   Number of bytes to write
00510  *    Return Value:    Number of bytes written
00511  */
00512 
00513 U32 USBD_WriteEP(U32 EPNum, U8 *pData, U32 cnt)
00514 {
00515     uint32_t u32Ep, u32Num, i;
00516     u32Num = EPNum & 0x0F;
00517     u32Ep = USBD_NUM_TO_EP(u32Num);
00518 
00519     if (u32Num == 0) {
00520         if (pData != NULL) {
00521             if (cnt > 0) {
00522                 for (i = 0; i < cnt; i++) {
00523                     HSUSBD->CEPDAT_BYTE = pData[i];
00524                 }
00525 
00526                 HSUSBD_START_CEP_IN(cnt);
00527             } else {
00528                 HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_ZEROLEN);
00529             }
00530         } else if (cnt == 0) {
00531             g_u8StatusIn = 1;
00532             HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_STSDONEIF_Msk);
00533             HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_NAKCLR);
00534         }
00535 
00536         return cnt;
00537     } else {
00538         if (cnt > 0) {
00539             for (i = 0; i < cnt; i++) {
00540                 HSUSBD->EP[u32Ep].EPDAT_BYTE = pData[i];
00541             }
00542 
00543             HSUSBD->EP[u32Ep].EPRSPCTL = (HSUSBD->EP[u32Ep].EPRSPCTL & HSUSBD_EP_RSPCTL_HALT) | HSUSBD_EP_RSPCTL_SHORTTXEN;
00544         } else {
00545             HSUSBD->EP[u32Ep].EPRSPCTL = (HSUSBD->EP[u32Ep].EPRSPCTL & HSUSBD_EP_RSPCTL_HALT) | HSUSBD_EP_RSPCTL_ZEROLEN;
00546         }
00547 
00548         return cnt;
00549     }
00550 }
00551 
00552 
00553 /*
00554  *  Get USB Device Last Frame Number
00555  *    Parameters:      None
00556  *    Return Value:    Frame Number
00557  */
00558 
00559 U32 USBD_GetFrame(void)
00560 {
00561     return 0;
00562 }
00563 
00564 
00565 #ifdef __RTX
00566 U32 LastError;
00567 
00568 /*
00569  *  Get USB Last Error Code
00570  *    Parameters:      None
00571  *    Return Value:    Error Code
00572  */
00573 
00574 U32 USBD_GetError(void)
00575 {
00576     return (LastError);
00577 }
00578 #endif
00579 
00580 
00581 /*
00582  *  USB Device Interrupt Service Routine
00583  */
00584 
00585 void USBD20_IRQHandler(void)
00586 {
00587     NVIC_DisableIRQ(USBD20_IRQn );
00588     USBD_SignalHandler();
00589 }
00590 
00591 void USBD_Handler_Main()
00592 {
00593     __IO uint32_t IrqStL, IrqSt;
00594     uint32_t u32Ep, u32Num, i;
00595     IrqStL = HSUSBD->GINTSTS & HSUSBD->GINTEN;
00596 
00597     if (!IrqStL) {
00598         return;
00599     }
00600 
00601     if (IrqStL & HSUSBD_GINTSTS_USBIF_Msk) {
00602         IrqSt = HSUSBD->BUSINTSTS & HSUSBD->BUSINTEN;
00603 
00604         if (IrqSt & HSUSBD_BUSINTSTS_SOFIF_Msk) {
00605 #ifdef __RTX
00606 
00607             if (USBD_RTX_DevTask) {
00608                 isr_evt_set(USBD_EVT_SOF, USBD_RTX_DevTask);
00609             }
00610 
00611 #else
00612 
00613             if (USBD_P_SOF_Event) {
00614                 USBD_P_SOF_Event();
00615             }
00616 
00617 #endif
00618             HSUSBD_CLR_BUS_INT_FLAG(HSUSBD_BUSINTSTS_SOFIF_Msk);
00619         }
00620 
00621         if (IrqSt & HSUSBD_BUSINTSTS_RSTIF_Msk) {
00622             USBD_Reset();
00623             usbd_reset_core();
00624 #ifdef __RTX
00625 
00626             if (USBD_RTX_DevTask) {
00627                 isr_evt_set(USBD_EVT_RESET, USBD_RTX_DevTask);
00628             }
00629 
00630 #else
00631 
00632             if (USBD_P_Reset_Event) {
00633                 USBD_P_Reset_Event();
00634             }
00635 
00636 #endif
00637             HSUSBD_ENABLE_BUS_INT(HSUSBD_BUSINTEN_RSTIEN_Msk | HSUSBD_BUSINTEN_RESUMEIEN_Msk | HSUSBD_BUSINTEN_SUSPENDIEN_Msk | HSUSBD_BUSINTEN_SOFIEN_Msk);
00638             HSUSBD_CLR_BUS_INT_FLAG(HSUSBD_BUSINTSTS_RSTIF_Msk);
00639             HSUSBD_CLR_CEP_INT_FLAG(0x1FFC);
00640         }
00641 
00642         if (IrqSt & HSUSBD_BUSINTSTS_RESUMEIF_Msk) {
00643             USBD_WakeUp();
00644 #ifdef __RTX
00645 
00646             if (USBD_RTX_DevTask) {
00647                 isr_evt_set(USBD_EVT_RESUME,  USBD_RTX_DevTask);
00648             }
00649 
00650 #else
00651 
00652             if (USBD_P_Resume_Event) {
00653                 USBD_P_Resume_Event();
00654             }
00655 
00656 #endif
00657             HSUSBD_ENABLE_BUS_INT(HSUSBD_BUSINTEN_RSTIEN_Msk | HSUSBD_BUSINTEN_SUSPENDIEN_Msk | HSUSBD_BUSINTEN_SOFIEN_Msk);
00658             HSUSBD_CLR_BUS_INT_FLAG(HSUSBD_BUSINTSTS_RESUMEIF_Msk);
00659         }
00660 
00661         if (IrqSt & HSUSBD_BUSINTSTS_SUSPENDIF_Msk) {
00662             USBD_Suspend();
00663 #ifdef __RTX
00664 
00665             if (USBD_RTX_DevTask) {
00666                 isr_evt_set(USBD_EVT_SUSPEND, USBD_RTX_DevTask);
00667             }
00668 
00669 #else
00670 
00671             if (USBD_P_Suspend_Event) {
00672                 USBD_P_Suspend_Event();
00673             }
00674 
00675 #endif
00676             HSUSBD_ENABLE_BUS_INT(HSUSBD_BUSINTEN_RSTIEN_Msk | HSUSBD_BUSINTEN_RESUMEIEN_Msk | HSUSBD_BUSINTEN_SOFIEN_Msk);
00677             HSUSBD_CLR_BUS_INT_FLAG(HSUSBD_BUSINTSTS_SUSPENDIF_Msk);
00678         }
00679 
00680         if (IrqSt & HSUSBD_BUSINTSTS_VBUSDETIF_Msk) {
00681             if (HSUSBD_IS_ATTACHED()) {
00682                 HSUSBD_ENABLE_USB();
00683             } else {
00684                 HSUSBD_DISABLE_USB();
00685             }
00686 
00687             HSUSBD_CLR_BUS_INT_FLAG(HSUSBD_BUSINTSTS_VBUSDETIF_Msk);
00688         }
00689     }
00690 
00691     if (IrqStL & HSUSBD_GINTSTS_CEPIF_Msk) {
00692         IrqSt = HSUSBD->CEPINTSTS & HSUSBD->CEPINTEN;
00693 
00694         if (IrqSt & HSUSBD_CEPINTSTS_SETUPPKIF_Msk) {
00695 #ifdef __RTX
00696 
00697             if (USBD_RTX_EPTask[0]) {
00698                 isr_evt_set(USBD_EVT_SETUP, USBD_RTX_EPTask[0]);
00699             }
00700 
00701 #else
00702 
00703             if (USBD_P_EP[0]) {
00704                 USBD_P_EP[0](USBD_EVT_SETUP);
00705             }
00706 
00707 #endif
00708             HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_SETUPPKIF_Msk);
00709             return;
00710         }
00711 
00712         if (IrqSt & HSUSBD_CEPINTSTS_TXPKIF_Msk) {
00713             HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_STSDONEIF_Msk);
00714             HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_NAKCLR);
00715 #ifdef __RTX
00716 
00717             if (USBD_RTX_EPTask[0]) {
00718                 isr_evt_set(USBD_EVT_IN, USBD_RTX_EPTask[0]);
00719             }
00720 
00721 #else
00722 
00723             if (USBD_P_EP[0]) {
00724                 USBD_P_EP[0](USBD_EVT_IN);
00725             }
00726 
00727 #endif
00728             HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_TXPKIF_Msk);
00729             return;
00730         }
00731 
00732         if (IrqSt & HSUSBD_CEPINTSTS_RXPKIF_Msk) {
00733 #ifdef __RTX
00734 
00735             if (USBD_RTX_EPTask[0]) {
00736                 isr_evt_set(USBD_EVT_OUT, USBD_RTX_EPTask[0]);
00737             }
00738 
00739 #else
00740 
00741             if (USBD_P_EP[0]) {
00742                 USBD_P_EP[0](USBD_EVT_OUT);
00743             }
00744 
00745 #endif
00746             HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_RXPKIF_Msk);
00747             return;
00748         }
00749 
00750         if (IrqSt & HSUSBD_CEPINTSTS_STSDONEIF_Msk) {
00751             if (g_u8StatusIn == 0) {
00752 #ifdef __RTX
00753 
00754                 if (USBD_RTX_EPTask[0]) {
00755                     isr_evt_set(USBD_EVT_OUT, USBD_RTX_EPTask[0]);
00756                 }
00757 
00758 #else
00759 
00760                 if (USBD_P_EP[0]) {
00761                     USBD_P_EP[0](USBD_EVT_OUT);
00762                 }
00763 
00764 #endif
00765             } else {
00766 #ifdef __RTX
00767 
00768                 if (USBD_RTX_EPTask[0]) {
00769                     isr_evt_set(USBD_EVT_IN, USBD_RTX_EPTask[0]);
00770                 }
00771 
00772 #else
00773 
00774                 if (USBD_P_EP[0]) {
00775                     USBD_P_EP[0](USBD_EVT_IN);
00776                 }
00777 
00778 #endif
00779             }
00780 
00781             g_u8StatusIn = 0;
00782             HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_STSDONEIF_Msk);
00783             return;
00784         }
00785     }
00786 
00787     for (i = 0; i < HSUSBD_MAX_EP; i++) {
00788         u32Ep = EPA + i;
00789         u32Num = USBD_EP_TO_NUM(u32Ep);
00790 
00791         if (IrqStL & (0x1UL << (HSUSBD_GINTSTS_EPAIF_Pos + i))) {
00792             IrqSt = HSUSBD->EP[u32Ep].EPINTSTS & HSUSBD->EP[u32Ep].EPINTEN;
00793 
00794             if (IrqSt & HSUSBD_EPINTSTS_TXPKIF_Msk) {
00795 #ifdef __RTX
00796 
00797                 if (USBD_RTX_EPTask[u32Num]) {
00798                     isr_evt_set(USBD_EVT_IN, USBD_RTX_EPTask[u32Num]);
00799                 }
00800 
00801 #else
00802 
00803                 if (USBD_P_EP[u32Num]) {
00804                     USBD_P_EP[u32Num](USBD_EVT_IN);
00805                 }
00806 
00807 #endif
00808             }
00809 
00810             if (IrqSt & (HSUSBD_EPINTSTS_RXPKIF_Msk | HSUSBD_EPINTSTS_SHORTRXIF_Msk | HSUSBD_EPINTEN_BUFFULLIEN_Msk)) {
00811 #ifdef __RTX
00812 
00813                 if (USBD_RTX_EPTask[u32Num]) {
00814                     isr_evt_set(USBD_EVT_OUT, USBD_RTX_EPTask[u32Num]);
00815                 }
00816 
00817 #else
00818 
00819                 if (USBD_P_EP[u32Num]) {
00820                     USBD_P_EP[u32Num](USBD_EVT_OUT);
00821                 }
00822 
00823 #endif
00824             }
00825 
00826             HSUSBD_CLR_EP_INT_FLAG(u32Ep, IrqSt);
00827         }
00828     }
00829 }
00830 
00831 void USBD_Handler(void)
00832 {
00833     USBD_Handler_Main();
00834     NVIC_EnableIRQ(USBD20_IRQn );
00835 }