usbd_STM32F103.c

00001 /*
00002  * Copyright (c) 2004-2016 ARM Limited. All rights reserved.
00003  *
00004  * SPDX-License-Identifier: Apache-2.0
00005  *
00006  * Licensed under the Apache License, Version 2.0 (the License); you may
00007  * not use this file except in compliance with the License.
00008  * You may obtain a copy of the License at
00009  *
00010  * http://www.apache.org/licenses/LICENSE-2.0
00011  *
00012  * Unless required by applicable law or agreed to in writing, software
00013  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
00014  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00015  * See the License for the specific language governing permissions and
00016  * limitations under the License.
00017  */
00018 
00019 /*----------------------------------------------------------------------------
00020 *      RL-ARM - USB
00021 *----------------------------------------------------------------------------
00022 *      Name:    usbd_STM32F103.c
00023 *      Purpose: Hardware Layer module for ST STM32F103
00024 *      Rev.:    V4.70
00025 *---------------------------------------------------------------------------*/
00026 
00027 /* Double Buffering is not supported                                         */
00028 
00029 #include <rl_usb.h>
00030 #include "stm32f1xx.h"
00031 #include "usbreg.h"
00032 #include "IO_Config.h"
00033 #include "cortex_m.h"
00034 #include "string.h"
00035 
00036 #define __NO_USB_LIB_C
00037 #include "usb_config.c"
00038 
00039 #define USB_ISTR_W0C_MASK   (ISTR_PMAOVR | ISTR_ERR | ISTR_WKUP | ISTR_SUSP | ISTR_RESET | ISTR_SOF | ISTR_ESOF)
00040 #define VAL_MASK            0xFFFF
00041 #define VAL_SHIFT           16 
00042 #define EP_NUM_MASK         0xFFFF
00043 #define EP_NUM_SHIFT        0
00044 
00045 #define USB_DBL_BUF_EP      0x0000
00046 
00047 #define EP_BUF_ADDR (sizeof(EP_BUF_DSCR)*(USBD_EP_NUM+1)) /* Endpoint Buf Adr */
00048 
00049 EP_BUF_DSCR *pBUF_DSCR = (EP_BUF_DSCR *)USB_PMA_ADDR; /* Ptr to EP Buf Desc   */
00050 
00051 U16 FreeBufAddr;                        /* Endpoint Free Buffer Address       */
00052 
00053 uint32_t StatQueue[(USBD_EP_NUM + 1) * 2 + 1];
00054 uint32_t StatQueueHead = 0;
00055 uint32_t StatQueueTail = 0;
00056 uint32_t LastIstr = 0;
00057 
00058 
00059 inline static void stat_enque(uint32_t stat)
00060 {
00061     cortex_int_state_t state;
00062     state = cortex_int_get_and_disable();
00063     StatQueue[StatQueueTail] = stat;
00064     StatQueueTail = (StatQueueTail + 1) % (sizeof(StatQueue) / sizeof(StatQueue[0]));
00065     cortex_int_restore(state);
00066 }
00067 
00068 inline static uint32_t stat_deque()
00069 {
00070     cortex_int_state_t state;
00071     uint32_t stat;
00072     state = cortex_int_get_and_disable();
00073     stat = StatQueue[StatQueueHead];
00074     StatQueueHead = (StatQueueHead + 1) % (sizeof(StatQueue) / sizeof(StatQueue[0]));
00075     cortex_int_restore(state);
00076 
00077     return stat;
00078 }
00079 
00080 inline static uint32_t stat_is_empty()
00081 {
00082     cortex_int_state_t state;
00083     uint32_t empty;
00084     state = cortex_int_get_and_disable();
00085     empty = StatQueueHead == StatQueueTail;
00086     cortex_int_restore(state);
00087     return empty;
00088 }
00089 
00090 
00091 /*
00092  *  Reset Endpoint
00093  *    Parameters:      EPNum: Endpoint Number
00094  *                       EPNum.0..3: Address
00095  *                       EPNum.7:    Dir
00096  *    Return Value:    None
00097  */
00098 
00099 void EP_Reset(U32 EPNum)
00100 {
00101     U32 num, val;
00102     num = EPNum & 0x0F;
00103     val = EPxREG(num);
00104 
00105     if (EPNum & 0x80) {                   /* IN Endpoint                        */
00106         EPxREG(num) = val & (EP_MASK | EP_DTOG_TX);
00107     } else {                              /* OUT Endpoint                       */
00108         EPxREG(num) = val & (EP_MASK | EP_DTOG_RX);
00109     }
00110 }
00111 
00112 
00113 /*
00114  *  Set Endpoint Status
00115  *    Parameters:      EPNum: Endpoint Number
00116  *                       EPNum.0..3: Address
00117  *                       EPNum.7:    Dir
00118  *                     stat: New Status
00119  *    Return Value:    None
00120  */
00121 
00122 void EP_Status(U32 EPNum, U32 stat)
00123 {
00124     U32 num, val;
00125     num = EPNum & 0x0F;
00126     val = EPxREG(num);
00127 
00128     if (EPNum & 0x80) {                   /* IN Endpoint                        */
00129         EPxREG(num) = EP_VAL_UNCHANGED(val) | ((val ^ stat) & EP_STAT_TX);
00130     } else {                              /* OUT Endpoint                       */
00131         EPxREG(num) = EP_VAL_UNCHANGED(val) | ((val ^ stat) & EP_STAT_RX);
00132     }
00133 }
00134 
00135 
00136 /*
00137  *  USB Device Interrupt enable
00138  *   Called by USBD_Init to enable the USB Interrupt
00139  *    Return Value:    None
00140  */
00141 
00142 #ifdef __RTX
00143 void __svc(1) USBD_IntrEna(void);
00144 void __SVC_1(void)
00145 {
00146 #else
00147 void          USBD_IntrEna(void)
00148 {
00149 #endif
00150     NVIC_EnableIRQ(USB_LP_CAN1_RX0_IRQn );
00151 }
00152 
00153 
00154 /*
00155  *  USB Device Initialize Function
00156  *   Called by the User to initialize USB
00157  *    Return Value:    None
00158  */
00159 
00160 void USBD_Init(void)
00161 {
00162     RCC->APB1ENR |= (1 << 23);            /* enable clock for USB               */
00163     USBD_IntrEna();                       /* Enable USB Interrupts              */
00164     /* Control USB connecting via SW                                            */
00165     USB_CONNECT_OFF();
00166 }
00167 
00168 
00169 /*
00170  *  USB Device Connect Function
00171  *   Called by the User to Connect/Disconnect USB Device
00172  *    Parameters:      con:   Connect/Disconnect
00173  *    Return Value:    None
00174  */
00175 
00176 void USBD_Connect(BOOL con)
00177 {
00178     if (con) {
00179         CNTR = CNTR_FRES;                   /* Force USB Reset                    */
00180         CNTR = 0;
00181         ISTR = 0;                           /* Clear Interrupt Status             */
00182         CNTR = CNTR_RESETM | CNTR_SUSPM | CNTR_WKUPM; /* USB Interrupt Mask       */
00183         USB_CONNECT_ON();
00184     } else {
00185         CNTR = CNTR_FRES | CNTR_PDWN;       /* Switch Off USB Device              */
00186         USB_CONNECT_OFF();
00187     }
00188 }
00189 
00190 
00191 /*
00192  *  USB Device Reset Function
00193  *   Called automatically on USB Device Reset
00194  *    Return Value:    None
00195  */
00196 
00197 void USBD_Reset(void)
00198 {
00199     NVIC_DisableIRQ(USB_LP_CAN1_RX0_IRQn );
00200 
00201     /* Double Buffering is not yet supported                                    */
00202     ISTR = 0;                             /* Clear Interrupt Status             */
00203     CNTR = CNTR_CTRM | CNTR_RESETM | CNTR_SUSPM | CNTR_WKUPM |
00204 #ifdef __RTX
00205            ((USBD_RTX_DevTask   != 0) ? CNTR_ERRM    : 0) |
00206            ((USBD_RTX_DevTask   != 0) ? CNTR_PMAOVRM : 0) |
00207            ((USBD_RTX_DevTask   != 0) ? CNTR_SOFM    : 0) |
00208            ((USBD_RTX_DevTask   != 0) ? CNTR_ESOFM   : 0);
00209 #else
00210            ((USBD_P_Error_Event != 0) ? CNTR_ERRM    : 0) |
00211            ((USBD_P_Error_Event != 0) ? CNTR_PMAOVRM : 0) |
00212            ((USBD_P_SOF_Event   != 0) ? CNTR_SOFM    : 0) |
00213            ((USBD_P_SOF_Event   != 0) ? CNTR_ESOFM   : 0);
00214 #endif
00215     FreeBufAddr = EP_BUF_ADDR;
00216     BTABLE = 0x00;                        /* set BTABLE Address                 */
00217     /* Setup Control Endpoint 0 */
00218     pBUF_DSCR->ADDR_TX = FreeBufAddr;
00219     FreeBufAddr += USBD_MAX_PACKET0;
00220     pBUF_DSCR->ADDR_RX = FreeBufAddr;
00221     FreeBufAddr += USBD_MAX_PACKET0;
00222 
00223     if (USBD_MAX_PACKET0 > 62) {
00224         pBUF_DSCR->COUNT_RX = ((USBD_MAX_PACKET0 << 5) - 1) | 0x8000;
00225     } else {
00226         pBUF_DSCR->COUNT_RX =   USBD_MAX_PACKET0 << 9;
00227     }
00228 
00229     EPxREG(0) = EP_CONTROL | EP_RX_VALID;
00230     DADDR = DADDR_EF | 0;                 /* Enable USB Default Address         */
00231 
00232     NVIC_EnableIRQ(USB_LP_CAN1_RX0_IRQn );
00233 }
00234 
00235 
00236 /*
00237  *  USB Device Suspend Function
00238  *   Called automatically on USB Device Suspend
00239  *    Return Value:    None
00240  */
00241 
00242 void USBD_Suspend(void)
00243 {
00244     CNTR |= CNTR_FSUSP;                   /* Force Suspend                      */
00245     CNTR |= CNTR_LPMODE;                  /* Low Power Mode                     */
00246 }
00247 
00248 
00249 /*
00250  *  USB Device Resume Function
00251  *   Called automatically on USB Device Resume
00252  *    Return Value:    None
00253  */
00254 
00255 void USBD_Resume(void)
00256 {
00257     /* Performed by Hardware                                                    */
00258 }
00259 
00260 
00261 /*
00262  *  USB Device Remote Wakeup Function
00263  *   Called automatically on USB Device Remote Wakeup
00264  *    Return Value:    None
00265  */
00266 
00267 void USBD_WakeUp(void)
00268 {
00269     CNTR &= ~CNTR_FSUSP;                  /* Clear Suspend                      */
00270 }
00271 
00272 
00273 /*
00274  *  USB Device Remote Wakeup Configuration Function
00275  *    Parameters:      cfg:   Device Enable/Disable
00276  *    Return Value:    None
00277  */
00278 
00279 void USBD_WakeUpCfg(BOOL cfg)
00280 {
00281     /* Not needed                                                               */
00282 }
00283 
00284 
00285 /*
00286  *  USB Device Set Address Function
00287  *    Parameters:      adr:   USB Device Address
00288  *                     setup: Called in setup stage (!=0), else after status stage
00289  *    Return Value:    None
00290  */
00291 
00292 void USBD_SetAddress(U32 adr, U32 setup)
00293 {
00294     if (setup) {
00295         return;
00296     }
00297 
00298     DADDR = DADDR_EF | adr;
00299 }
00300 
00301 
00302 /*
00303  *  USB Device Configure Function
00304  *    Parameters:      cfg:   Device Configure/Deconfigure
00305  *    Return Value:    None
00306  */
00307 
00308 void USBD_Configure(BOOL cfg)
00309 {
00310     if (cfg == __FALSE) {
00311         FreeBufAddr  = EP_BUF_ADDR;
00312         FreeBufAddr += 2 * USBD_MAX_PACKET0; /* reset Buffer address               */
00313     }
00314 }
00315 
00316 
00317 /*
00318  *  Configure USB Device Endpoint according to Descriptor
00319  *    Parameters:      pEPD:  Pointer to Device Endpoint Descriptor
00320  *    Return Value:    None
00321  */
00322 
00323 void USBD_ConfigEP(USB_ENDPOINT_DESCRIPTOR *pEPD)
00324 {
00325     /* Double Buffering is not yet supported                                    */
00326     U32 num, val;
00327     num = pEPD->bEndpointAddress & 0x0F;
00328     val = pEPD->wMaxPacketSize;
00329 
00330     if (pEPD->bEndpointAddress & USB_ENDPOINT_DIRECTION_MASK) {
00331         (pBUF_DSCR + num)->ADDR_TX = FreeBufAddr;
00332         val = (val + 1) & ~1;
00333     } else {
00334         (pBUF_DSCR + num)->ADDR_RX = FreeBufAddr;
00335 
00336         if (val > 62) {
00337             val = (val + 31) & ~31;
00338             (pBUF_DSCR + num)->COUNT_RX = ((val << 5) - 1) | 0x8000;
00339         } else {
00340             val = (val + 1)  & ~1;
00341             (pBUF_DSCR + num)->COUNT_RX =   val << 9;
00342         }
00343     }
00344 
00345     FreeBufAddr += val;
00346 
00347     switch (pEPD->bmAttributes & USB_ENDPOINT_TYPE_MASK) {
00348         case USB_ENDPOINT_TYPE_CONTROL:
00349             val = EP_CONTROL;
00350             break;
00351 
00352         case USB_ENDPOINT_TYPE_ISOCHRONOUS:
00353             val = EP_ISOCHRONOUS;
00354             break;
00355 
00356         case USB_ENDPOINT_TYPE_BULK:
00357             val = EP_BULK;
00358 
00359             if (USB_DBL_BUF_EP & (1 << num)) {
00360                 val |= EP_KIND;
00361             }
00362 
00363             break;
00364 
00365         case USB_ENDPOINT_TYPE_INTERRUPT:
00366             val = EP_INTERRUPT;
00367             break;
00368     }
00369 
00370     val |= num;
00371     EPxREG(num) = val;
00372 }
00373 
00374 
00375 /*
00376  *  Set Direction for USB Device Control Endpoint
00377  *    Parameters:      dir:   Out (dir == 0), In (dir <> 0)
00378  *    Return Value:    None
00379  */
00380 
00381 void USBD_DirCtrlEP(U32 dir)
00382 {
00383     /* Not needed                                                               */
00384 }
00385 
00386 
00387 /*
00388  *  Enable USB Device Endpoint
00389  *    Parameters:      EPNum: Device Endpoint Number
00390  *                       EPNum.0..3: Address
00391  *                       EPNum.7:    Dir
00392  *    Return Value:    None
00393  */
00394 
00395 void USBD_EnableEP(U32 EPNum)
00396 {
00397     EP_Status(EPNum, EP_TX_NAK | EP_RX_VALID);    /* EP is able to receive      */
00398 }
00399 
00400 
00401 /*
00402  *  Disable USB Endpoint
00403  *    Parameters:      EPNum: Endpoint Number
00404  *                       EPNum.0..3: Address
00405  *                       EPNum.7:    Dir
00406  *    Return Value:    None
00407  */
00408 
00409 void USBD_DisableEP(U32 EPNum)
00410 {
00411     EP_Status(EPNum, EP_TX_DIS | EP_RX_DIS);
00412 }
00413 
00414 
00415 /*
00416  *  Reset USB Device Endpoint
00417  *    Parameters:      EPNum: Device Endpoint Number
00418  *                       EPNum.0..3: Address
00419  *                       EPNum.7:    Dir
00420  *    Return Value:    None
00421  */
00422 
00423 void USBD_ResetEP(U32 EPNum)
00424 {
00425     EP_Reset(EPNum);
00426 }
00427 
00428 
00429 /*
00430  *  Set Stall for USB Device Endpoint
00431  *    Parameters:      EPNum: Device Endpoint Number
00432  *                       EPNum.0..3: Address
00433  *                       EPNum.7:    Dir
00434  *    Return Value:    None
00435  */
00436 
00437 void USBD_SetStallEP(U32 EPNum)
00438 {
00439     EP_Status(EPNum, EP_TX_STALL | EP_RX_STALL);
00440 }
00441 
00442 
00443 /*
00444  *  Clear Stall for USB Device Endpoint
00445  *    Parameters:      EPNum: Device Endpoint Number
00446  *                       EPNum.0..3: Address
00447  *                       EPNum.7:    Dir
00448  *    Return Value:    None
00449  */
00450 
00451 void USBD_ClrStallEP(U32 EPNum)
00452 {
00453     EP_Reset(EPNum);                      /* reset DTog Bits                    */
00454     EP_Status(EPNum, EP_TX_VALID | EP_RX_VALID);
00455 }
00456 
00457 
00458 /*
00459  *  Clear USB Device Endpoint Buffer
00460  *    Parameters:      EPNum: Device Endpoint Number
00461  *                       EPNum.0..3: Address
00462  *                       EPNum.7:    Dir
00463  *    Return Value:    None
00464  */
00465 
00466 void USBD_ClearEPBuf(U32 EPNum)
00467 {
00468     ;
00469 }
00470 
00471 
00472 /*
00473  *  Read USB Device Endpoint Data
00474  *    Parameters:      EPNum: Device Endpoint Number
00475  *                       EPNum.0..3: Address
00476  *                       EPNum.7:    Dir
00477  *                     pData: Pointer to Data Buffer
00478  *    Return Value:    Number of bytes read
00479  */
00480 
00481 U32 USBD_ReadEP(U32 EPNum, U8 *pData, U32 bufsz)
00482 {
00483     /* Double Buffering is not yet supported                                    */
00484     U32 num, cnt, *pv, n;
00485     num = EPNum & 0x0F;
00486     pv  = (U32 *)(USB_PMA_ADDR + 2 * ((pBUF_DSCR + num)->ADDR_RX));
00487     cnt = (pBUF_DSCR + num)->COUNT_RX & EP_COUNT_MASK;
00488     if (cnt > bufsz) {
00489         cnt = bufsz;
00490     }
00491 
00492     for (n = 0; n < (cnt + 1) / 2; n++) {
00493         *((__packed U16 *)pData) = *pv++;
00494         pData += 2;
00495     }
00496 
00497     EP_Status(EPNum, EP_RX_VALID);
00498     return (cnt);
00499 }
00500 
00501 
00502 /*
00503  *  Write USB Device Endpoint Data
00504  *    Parameters:      EPNum: Device Endpoint Number
00505  *                       EPNum.0..3: Address
00506  *                       EPNum.7:    Dir
00507  *                     pData: Pointer to Data Buffer
00508  *                     cnt:   Number of bytes to write
00509  *    Return Value:    Number of bytes written
00510  */
00511 
00512 U32 USBD_WriteEP(U32 EPNum, U8 *pData, U32 cnt)
00513 {
00514     /* Double Buffering is not yet supported                                    */
00515     U32 num, *pv, n;
00516     U16 statusEP;
00517     num = EPNum & 0x0F;
00518     pv  = (U32 *)(USB_PMA_ADDR + 2 * ((pBUF_DSCR + num)->ADDR_TX));
00519 
00520     for (n = 0; n < (cnt + 1) / 2; n++) {
00521         *pv++ = *((__packed U16 *)pData);
00522         pData += 2;
00523     }
00524 
00525     (pBUF_DSCR + num)->COUNT_TX = cnt;
00526     statusEP = EPxREG(num);
00527 
00528     if ((statusEP & EP_STAT_TX) != EP_TX_STALL) {
00529         EP_Status(EPNum, EP_TX_VALID);      /* do not make EP valid if stalled    */
00530     }
00531 
00532     return (cnt);
00533 }
00534 
00535 
00536 /*
00537  *  Get USB Device Last Frame Number
00538  *    Parameters:      None
00539  *    Return Value:    Frame Number
00540  */
00541 
00542 U32 USBD_GetFrame(void)
00543 {
00544     return (FNR & FNR_FN);
00545 }
00546 
00547 
00548 #ifdef __RTX
00549 U32 LastError;                          /* Last Error                         */
00550 
00551 /*
00552  *  Get USB Last Error Code
00553  *    Parameters:      None
00554  *    Return Value:    Error Code
00555  */
00556 
00557 U32 USBD_GetError(void)
00558 {
00559     return (LastError);
00560 }
00561 #endif
00562 
00563 
00564 /*
00565  *  USB Device Interrupt Service Routine
00566  */
00567 
00568 void USB_LP_CAN1_RX0_IRQHandler(void)
00569 {
00570     uint32_t istr;
00571     uint32_t num;
00572     uint32_t val;
00573 
00574     istr = ISTR;
00575     // Zero out endpoint ID since this is read from the queue
00576     LastIstr |= istr & ~(ISTR_DIR | ISTR_EP_ID);
00577     // Clear interrupts that are pending
00578     ISTR = ~(istr & USB_ISTR_W0C_MASK);
00579     if (istr & ISTR_CTR) {
00580         while ((istr = ISTR) & ISTR_CTR) {
00581             num = istr & ISTR_EP_ID;
00582             val = EPxREG(num);
00583 
00584             // Process and filter out the zero length status out endpoint to prevent
00585             // the next SETUP packet from being dropped.
00586             if ((0 == num) && (val & EP_CTR_RX) && !(val & EP_SETUP)
00587                     && (0 == ((pBUF_DSCR + num)->COUNT_RX & EP_COUNT_MASK))) {
00588                 if (val & EP_CTR_TX) {
00589                     // Drop the RX event but not TX
00590                     stat_enque((((val & VAL_MASK) & ~EP_CTR_RX) << VAL_SHIFT) | 
00591                                ((num & EP_NUM_MASK) << EP_NUM_SHIFT));
00592                 } else {
00593                     // Drop the event
00594                 }
00595             } else {
00596                 stat_enque(((val & VAL_MASK) << VAL_SHIFT) | 
00597                            ((num & EP_NUM_MASK) << EP_NUM_SHIFT));
00598             }
00599 
00600 
00601             if (val & EP_CTR_RX) {
00602                 EPxREG(num) = EP_VAL_UNCHANGED(val) & ~EP_CTR_RX;
00603             }
00604 
00605             if (val & EP_CTR_TX) {
00606                 EPxREG(num) = EP_VAL_UNCHANGED(val) & ~EP_CTR_TX;
00607             }
00608         }
00609     }
00610     
00611     USBD_SignalHandler();
00612 }
00613 
00614 void USBD_Handler(void)
00615 {
00616     U32 istr, num, val, num_val;
00617     cortex_int_state_t state;
00618 
00619     // Get ISTR
00620     state = cortex_int_get_and_disable();
00621     istr = LastIstr;
00622     LastIstr = 0;
00623     cortex_int_restore(state);
00624 
00625     /* USB Reset Request                                                        */
00626     if (istr & ISTR_RESET) {
00627         USBD_Reset();
00628         usbd_reset_core();
00629 #ifdef __RTX
00630 
00631         if (USBD_RTX_DevTask) {
00632             isr_evt_set(USBD_EVT_RESET, USBD_RTX_DevTask);
00633         }
00634 
00635 #else
00636 
00637         if (USBD_P_Reset_Event) {
00638             USBD_P_Reset_Event();
00639         }
00640 
00641 #endif
00642     }
00643 
00644     /* USB Suspend Request                                                      */
00645     if (istr & ISTR_SUSP) {
00646         USBD_Suspend();
00647 #ifdef __RTX
00648 
00649         if (USBD_RTX_DevTask) {
00650             isr_evt_set(USBD_EVT_SUSPEND, USBD_RTX_DevTask);
00651         }
00652 
00653 #else
00654 
00655         if (USBD_P_Suspend_Event) {
00656             USBD_P_Suspend_Event();
00657         }
00658 
00659 #endif
00660     }
00661 
00662     /* USB Wakeup                                                               */
00663     if (istr & ISTR_WKUP) {
00664         USBD_WakeUp();
00665 #ifdef __RTX
00666 
00667         if (USBD_RTX_DevTask) {
00668             isr_evt_set(USBD_EVT_RESUME,  USBD_RTX_DevTask);
00669         }
00670 
00671 #else
00672 
00673         if (USBD_P_Resume_Event) {
00674             USBD_P_Resume_Event();
00675         }
00676 
00677 #endif
00678     }
00679 
00680     /* Start of Frame                                                           */
00681     if (istr & ISTR_SOF) {
00682 #ifdef __RTX
00683 
00684         if (USBD_RTX_DevTask) {
00685             isr_evt_set(USBD_EVT_SOF, USBD_RTX_DevTask);
00686         }
00687 
00688 #else
00689 
00690         if (USBD_P_SOF_Event) {
00691             USBD_P_SOF_Event();
00692         }
00693 
00694 #endif
00695     }
00696 
00697     /* PMA Over/underrun                                                        */
00698     if (istr & ISTR_PMAOVR) {
00699 #ifdef __RTX
00700         LastError = 2;
00701 
00702         if (USBD_RTX_DevTask) {
00703             isr_evt_set(USBD_EVT_ERROR, USBD_RTX_DevTask);
00704         }
00705 
00706 #else
00707 
00708         if (USBD_P_Error_Event) {
00709             USBD_P_Error_Event(2);
00710         }
00711 
00712 #endif
00713     }
00714 
00715     /* Error: No Answer, CRC Error, Bit Stuff Error, Frame Format Error         */
00716     if (istr & ISTR_ERR) {
00717 #ifdef __RTX
00718         LastError = 1;
00719 
00720         if (USBD_RTX_DevTask) {
00721             isr_evt_set(USBD_EVT_ERROR, USBD_RTX_DevTask);
00722         }
00723 
00724 #else
00725 
00726         if (USBD_P_Error_Event) {
00727             USBD_P_Error_Event(1);
00728         }
00729 
00730 #endif
00731     }
00732 
00733     /* Endpoint Interrupts                                                      */
00734     while ((istr & ISTR_CTR) && !stat_is_empty()) {
00735         num_val = stat_deque();
00736         num = (num_val >> EP_NUM_SHIFT) & EP_NUM_MASK;
00737         val = (num_val >> VAL_SHIFT) & VAL_MASK;
00738         if (val & EP_CTR_TX) {
00739 #ifdef __RTX
00740 
00741             if (USBD_RTX_EPTask[num]) {
00742                 isr_evt_set(USBD_EVT_IN,  USBD_RTX_EPTask[num]);
00743             }
00744 
00745 #else
00746 
00747             if (USBD_P_EP[num]) {
00748                 USBD_P_EP[num](USBD_EVT_IN);
00749             }
00750 
00751 #endif
00752         }
00753 
00754         if (val & EP_CTR_RX) {
00755 #ifdef __RTX
00756 
00757             if (USBD_RTX_EPTask[num]) {
00758                 isr_evt_set((val & EP_SETUP) ? USBD_EVT_SETUP : USBD_EVT_OUT, USBD_RTX_EPTask[num]);
00759             }
00760 
00761 #else
00762 
00763             if (USBD_P_EP[num]) {
00764                 USBD_P_EP[num]((val & EP_SETUP) ? USBD_EVT_SETUP : USBD_EVT_OUT);
00765             }
00766 
00767 #endif
00768         }
00769     }
00770 }