usb_phy.c

00001 /*
00002  * Copyright (c) 2015, Freescale Semiconductor, Inc.
00003  * All rights reserved.
00004  *
00005  * Redistribution and use in source and binary forms, with or without modification,
00006  * are permitted provided that the following conditions are met:
00007  *
00008  * o Redistributions of source code must retain the above copyright notice, this list
00009  *   of conditions and the following disclaimer.
00010  *
00011  * o Redistributions in binary form must reproduce the above copyright notice, this
00012  *   list of conditions and the following disclaimer in the documentation and/or
00013  *   other materials provided with the distribution.
00014  *
00015  * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00016  *   contributors may be used to endorse or promote products derived from this
00017  *   software without specific prior written permission.
00018  *
00019  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00020  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00021  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00022  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00023  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00024  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00025  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00026  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00027  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00028  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00029  */
00030 
00031 #include "fsl_usb.h"
00032 #include "fsl_device_registers.h"
00033 
00034 /*!
00035  * @brief ehci phy initialization.
00036  *
00037  * This function initialize ehci phy IP.
00038  *
00039  * @param[in] controllerId   ehci controller id, please reference to #usb_controller_index_t.
00040  * @param[in] freq            the external input clock.
00041  *                            for example: if the external input clock is 16M, the parameter freq should be 16000000.
00042  *
00043  * @retval kStatus_USB_Success      cancel successfully.
00044  * @retval kStatus_USB_Error        the freq value is incorrect.
00045  */
00046 uint32_t USB_EhciPhyInit(uint8_t controllerId, uint32_t freq)
00047 {
00048 #if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U))
00049     USBPHY->TRIM_OVERRIDE_EN = 0x001fU;               /* override IFR value */
00050     USBPHY->CTRL &= ~USBPHY_CTRL_SFTRST_MASK;         /* release PHY from reset */
00051     USBPHY->PLL_SIC |= USBPHY_PLL_SIC_PLL_POWER_MASK; /* power up PLL */
00052     if (freq == 24000000U)
00053     {
00054         USBPHY->PLL_SIC |= USBPHY_PLL_SIC_PLL_DIV_SEL(0U);
00055     }
00056     else if (freq == 16000000U)
00057     {
00058         USBPHY->PLL_SIC |= USBPHY_PLL_SIC_PLL_DIV_SEL(1U);
00059     }
00060     else if (freq == 12000000U)
00061     {
00062         USBPHY->PLL_SIC |= USBPHY_PLL_SIC_PLL_DIV_SEL(2U);
00063     }
00064     else
00065     {
00066         return kStatus_USB_Error ; /* error */
00067     }
00068     USBPHY->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_BYPASS_MASK;     /* clear bypass bit */
00069     USBPHY->PLL_SIC |= USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK; /* enable USB clock output from USB PHY PLL */
00070     USBPHY->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK;              /* Clear to 0U to run clocks */
00071 
00072     USBPHY->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK; /* support LS device. */
00073     USBPHY->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL3_MASK; /* support external FS Hub with LS device connected. */
00074     /* PWD register provides overall control of the PHY power state */
00075     USBPHY->PWD = 0U;
00076 
00077     while (!(USBPHY->PLL_SIC & USBPHY_PLL_SIC_PLL_LOCK_MASK))
00078     {
00079     }
00080 
00081     /* Decode to trim the nominal 17.78mA current source for the High Speed TX drivers on USB_DP and USB_DM. */
00082     USBPHY->TX = ((USBPHY->TX & (~USBPHY_TX_D_CAL_MASK)) | USBPHY_TX_D_CAL(0xcU));
00083 #endif
00084 
00085     return kStatus_USB_Success ;
00086 }
00087 
00088 /*!
00089  * @brief ehci phy initialization for suspend and resume.
00090  *
00091  * This function initialize ehci phy IP for suspend and resume.
00092  *
00093  * @param[in] controllerId   ehci controller id, please reference to #usb_controller_index_t.
00094  * @param[in] freq            the external input clock.
00095  *                            for example: if the external input clock is 16M, the parameter freq should be 16000000.
00096  *
00097  * @retval kStatus_USB_Success      cancel successfully.
00098  * @retval kStatus_USB_Error        the freq value is incorrect.
00099  */
00100 uint32_t USB_EhciLowPowerPhyInit(uint8_t controllerId, uint32_t freq)
00101 {
00102 #if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U))
00103     USBPHY->TRIM_OVERRIDE_EN = 0x001fU;               /* override IFR value */
00104     USBPHY->CTRL &= ~USBPHY_CTRL_SFTRST_MASK;         /* release PHY from reset */
00105     USBPHY->PLL_SIC |= USBPHY_PLL_SIC_PLL_POWER_MASK; /* power up PLL */
00106     if (freq == 24000000U)
00107     {
00108         USBPHY->PLL_SIC |= USBPHY_PLL_SIC_PLL_DIV_SEL(0U);
00109     }
00110     else if (freq == 16000000U)
00111     {
00112         USBPHY->PLL_SIC |= USBPHY_PLL_SIC_PLL_DIV_SEL(1U);
00113     }
00114     else if (freq == 12000000U)
00115     {
00116         USBPHY->PLL_SIC |= USBPHY_PLL_SIC_PLL_DIV_SEL(2U);
00117     }
00118     else
00119     {
00120         return kStatus_USB_Error ; /* error */
00121     }
00122     USBPHY->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_BYPASS_MASK;     /* clear bypass bit */
00123     USBPHY->PLL_SIC |= USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK; /* enable USB clock output from USB PHY PLL */
00124     USBPHY->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK;              /* Clear to 0U to run clocks */
00125     USBPHY->CTRL |=
00126         USBPHY_CTRL_AUTORESUME_EN_MASK | USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK | USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK;
00127     USBPHY->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK; /* support LS device. */
00128     USBPHY->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL3_MASK; /* support external FS Hub with LS device connected. */
00129     /* PWD register provides overall control of the PHY power state */
00130     USBPHY->PWD = 0U;
00131 
00132     while (!(USBPHY->PLL_SIC & USBPHY_PLL_SIC_PLL_LOCK_MASK))
00133     {
00134     }
00135 
00136     /* now the 480MHz USB clock is up, then configure fractional divider after PLL with PFD
00137      * pfd clock = 480MHz*18/N, where N=18~35
00138      * Please note that USB1PFDCLK has to be less than 180MHz for RUN or HSRUN mode
00139      */
00140     USBPHY->ANACTRL |= USBPHY_ANACTRL_PFD_FRAC(24);   /* N=24 */
00141     USBPHY->ANACTRL |= USBPHY_ANACTRL_PFD_CLK_SEL(4); /* div by 4 */
00142 
00143     USBPHY->ANACTRL &= ~USBPHY_ANACTRL_DEV_PULLDOWN_MASK;
00144     USBPHY->ANACTRL &= ~USBPHY_ANACTRL_PFD_CLKGATE_MASK;
00145     while (!(USBPHY->ANACTRL & USBPHY_ANACTRL_PFD_STABLE_MASK))
00146     {
00147     }
00148 
00149     /* Decode to trim the nominal 17.78mA current source for the High Speed TX drivers on USB_DP and USB_DM. */
00150     USBPHY->TX = ((USBPHY->TX & (~USBPHY_TX_D_CAL_MASK)) | USBPHY_TX_D_CAL(0xcU));
00151 #endif
00152 
00153     return kStatus_USB_Success ;
00154 }
00155 
00156 /*!
00157  * @brief ehci phy de-initialization.
00158  *
00159  * This function de-initialize ehci phy IP.
00160  *
00161  * @param[in] controllerId   ehci controller id, please reference to #usb_controller_index_t.
00162  */
00163 void USB_EhciPhyDeinit(uint8_t controllerId)
00164 {
00165 #if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U))
00166     USBPHY->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_POWER_MASK;       /* power down PLL */
00167     USBPHY->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK; /* disable USB clock output from USB PHY PLL */
00168     USBPHY->CTRL |= USBPHY_CTRL_CLKGATE_MASK;                /* set to 1U to gate clocks */
00169 #endif
00170 }
00171 
00172 /*!
00173  * @brief ehci phy disconnect detection enable or disable.
00174  *
00175  * This function enable/disable host ehci disconnect detection.
00176  *
00177  * @param[in] controllerId   ehci controller id, please reference to #usb_controller_index_t.
00178  * @param[in] enable
00179  *            1U - enable;
00180  *            0U - disable;
00181  */
00182 void USB_EhcihostPhyDisconnectDetectCmd(uint8_t controllerId, uint8_t enable)
00183 {
00184 #if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U))
00185     if (enable)
00186     {
00187         USBPHY->CTRL |= USBPHY_CTRL_ENHOSTDISCONDETECT_MASK;
00188     }
00189     else
00190     {
00191         USBPHY->CTRL &= (~USBPHY_CTRL_ENHOSTDISCONDETECT_MASK);
00192     }
00193 #endif
00194 }