usart3.h

00001 /* ---------------------------------------------------------------------------- */
00002 /*                  Atmel Microcontroller Software Support                      */
00003 /*                       SAM Software Package License                           */
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00005 /* Copyright (c) %copyright_year%, Atmel Corporation                                        */
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00011 /*                                                                              */
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00029 
00030 #ifndef _SAM3U_USART3_INSTANCE_
00031 #define _SAM3U_USART3_INSTANCE_
00032 
00033 /* ========== Register definition for USART3 peripheral ========== */
00034 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
00035 #define REG_USART3_CR          (0x4009C000U) /**< \brief (USART3) Control Register */
00036 #define REG_USART3_MR          (0x4009C004U) /**< \brief (USART3) Mode Register */
00037 #define REG_USART3_IER          (0x4009C008U) /**< \brief (USART3) Interrupt Enable Register */
00038 #define REG_USART3_IDR          (0x4009C00CU) /**< \brief (USART3) Interrupt Disable Register */
00039 #define REG_USART3_IMR          (0x4009C010U) /**< \brief (USART3) Interrupt Mask Register */
00040 #define REG_USART3_CSR          (0x4009C014U) /**< \brief (USART3) Channel Status Register */
00041 #define REG_USART3_RHR          (0x4009C018U) /**< \brief (USART3) Receiver Holding Register */
00042 #define REG_USART3_THR          (0x4009C01CU) /**< \brief (USART3) Transmitter Holding Register */
00043 #define REG_USART3_BRGR          (0x4009C020U) /**< \brief (USART3) Baud Rate Generator Register */
00044 #define REG_USART3_RTOR          (0x4009C024U) /**< \brief (USART3) Receiver Time-out Register */
00045 #define REG_USART3_TTGR          (0x4009C028U) /**< \brief (USART3) Transmitter Timeguard Register */
00046 #define REG_USART3_FIDI          (0x4009C040U) /**< \brief (USART3) FI DI Ratio Register */
00047 #define REG_USART3_NER          (0x4009C044U) /**< \brief (USART3) Number of Errors Register */
00048 #define REG_USART3_IF          (0x4009C04CU) /**< \brief (USART3) IrDA Filter Register */
00049 #define REG_USART3_MAN          (0x4009C050U) /**< \brief (USART3) Manchester Encoder Decoder Register */
00050 #define REG_USART3_WPMR          (0x4009C0E4U) /**< \brief (USART3) Write Protect Mode Register */
00051 #define REG_USART3_WPSR          (0x4009C0E8U) /**< \brief (USART3) Write Protect Status Register */
00052 #define REG_USART3_RPR          (0x4009C100U) /**< \brief (USART3) Receive Pointer Register */
00053 #define REG_USART3_RCR          (0x4009C104U) /**< \brief (USART3) Receive Counter Register */
00054 #define REG_USART3_TPR          (0x4009C108U) /**< \brief (USART3) Transmit Pointer Register */
00055 #define REG_USART3_TCR          (0x4009C10CU) /**< \brief (USART3) Transmit Counter Register */
00056 #define REG_USART3_RNPR          (0x4009C110U) /**< \brief (USART3) Receive Next Pointer Register */
00057 #define REG_USART3_RNCR          (0x4009C114U) /**< \brief (USART3) Receive Next Counter Register */
00058 #define REG_USART3_TNPR          (0x4009C118U) /**< \brief (USART3) Transmit Next Pointer Register */
00059 #define REG_USART3_TNCR          (0x4009C11CU) /**< \brief (USART3) Transmit Next Counter Register */
00060 #define REG_USART3_PTCR          (0x4009C120U) /**< \brief (USART3) Transfer Control Register */
00061 #define REG_USART3_PTSR          (0x4009C124U) /**< \brief (USART3) Transfer Status Register */
00062 #else
00063 #define REG_USART3_CR (*(WoReg*)0x4009C000U) /**< \brief (USART3) Control Register */
00064 #define REG_USART3_MR (*(RwReg*)0x4009C004U) /**< \brief (USART3) Mode Register */
00065 #define REG_USART3_IER (*(WoReg*)0x4009C008U) /**< \brief (USART3) Interrupt Enable Register */
00066 #define REG_USART3_IDR (*(WoReg*)0x4009C00CU) /**< \brief (USART3) Interrupt Disable Register */
00067 #define REG_USART3_IMR (*(RoReg*)0x4009C010U) /**< \brief (USART3) Interrupt Mask Register */
00068 #define REG_USART3_CSR (*(RoReg*)0x4009C014U) /**< \brief (USART3) Channel Status Register */
00069 #define REG_USART3_RHR (*(RoReg*)0x4009C018U) /**< \brief (USART3) Receiver Holding Register */
00070 #define REG_USART3_THR (*(WoReg*)0x4009C01CU) /**< \brief (USART3) Transmitter Holding Register */
00071 #define REG_USART3_BRGR (*(RwReg*)0x4009C020U) /**< \brief (USART3) Baud Rate Generator Register */
00072 #define REG_USART3_RTOR (*(RwReg*)0x4009C024U) /**< \brief (USART3) Receiver Time-out Register */
00073 #define REG_USART3_TTGR (*(RwReg*)0x4009C028U) /**< \brief (USART3) Transmitter Timeguard Register */
00074 #define REG_USART3_FIDI (*(RwReg*)0x4009C040U) /**< \brief (USART3) FI DI Ratio Register */
00075 #define REG_USART3_NER (*(RoReg*)0x4009C044U) /**< \brief (USART3) Number of Errors Register */
00076 #define REG_USART3_IF (*(RwReg*)0x4009C04CU) /**< \brief (USART3) IrDA Filter Register */
00077 #define REG_USART3_MAN (*(RwReg*)0x4009C050U) /**< \brief (USART3) Manchester Encoder Decoder Register */
00078 #define REG_USART3_WPMR (*(RwReg*)0x4009C0E4U) /**< \brief (USART3) Write Protect Mode Register */
00079 #define REG_USART3_WPSR (*(RoReg*)0x4009C0E8U) /**< \brief (USART3) Write Protect Status Register */
00080 #define REG_USART3_RPR (*(RwReg*)0x4009C100U) /**< \brief (USART3) Receive Pointer Register */
00081 #define REG_USART3_RCR (*(RwReg*)0x4009C104U) /**< \brief (USART3) Receive Counter Register */
00082 #define REG_USART3_TPR (*(RwReg*)0x4009C108U) /**< \brief (USART3) Transmit Pointer Register */
00083 #define REG_USART3_TCR (*(RwReg*)0x4009C10CU) /**< \brief (USART3) Transmit Counter Register */
00084 #define REG_USART3_RNPR (*(RwReg*)0x4009C110U) /**< \brief (USART3) Receive Next Pointer Register */
00085 #define REG_USART3_RNCR (*(RwReg*)0x4009C114U) /**< \brief (USART3) Receive Next Counter Register */
00086 #define REG_USART3_TNPR (*(RwReg*)0x4009C118U) /**< \brief (USART3) Transmit Next Pointer Register */
00087 #define REG_USART3_TNCR (*(RwReg*)0x4009C11CU) /**< \brief (USART3) Transmit Next Counter Register */
00088 #define REG_USART3_PTCR (*(WoReg*)0x4009C120U) /**< \brief (USART3) Transfer Control Register */
00089 #define REG_USART3_PTSR (*(RoReg*)0x4009C124U) /**< \brief (USART3) Transfer Status Register */
00090 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
00091 
00092 #endif /* _SAM3U_USART3_INSTANCE_ */