usart2.h

00001 /* ---------------------------------------------------------------------------- */
00002 /*                  Atmel Microcontroller Software Support                      */
00003 /*                       SAM Software Package License                           */
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00005 /* Copyright (c) %copyright_year%, Atmel Corporation                                        */
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00011 /*                                                                              */
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00029 
00030 #ifndef _SAM3U_USART2_INSTANCE_
00031 #define _SAM3U_USART2_INSTANCE_
00032 
00033 /* ========== Register definition for USART2 peripheral ========== */
00034 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
00035 #define REG_USART2_CR          (0x40098000U) /**< \brief (USART2) Control Register */
00036 #define REG_USART2_MR          (0x40098004U) /**< \brief (USART2) Mode Register */
00037 #define REG_USART2_IER          (0x40098008U) /**< \brief (USART2) Interrupt Enable Register */
00038 #define REG_USART2_IDR          (0x4009800CU) /**< \brief (USART2) Interrupt Disable Register */
00039 #define REG_USART2_IMR          (0x40098010U) /**< \brief (USART2) Interrupt Mask Register */
00040 #define REG_USART2_CSR          (0x40098014U) /**< \brief (USART2) Channel Status Register */
00041 #define REG_USART2_RHR          (0x40098018U) /**< \brief (USART2) Receiver Holding Register */
00042 #define REG_USART2_THR          (0x4009801CU) /**< \brief (USART2) Transmitter Holding Register */
00043 #define REG_USART2_BRGR          (0x40098020U) /**< \brief (USART2) Baud Rate Generator Register */
00044 #define REG_USART2_RTOR          (0x40098024U) /**< \brief (USART2) Receiver Time-out Register */
00045 #define REG_USART2_TTGR          (0x40098028U) /**< \brief (USART2) Transmitter Timeguard Register */
00046 #define REG_USART2_FIDI          (0x40098040U) /**< \brief (USART2) FI DI Ratio Register */
00047 #define REG_USART2_NER          (0x40098044U) /**< \brief (USART2) Number of Errors Register */
00048 #define REG_USART2_IF          (0x4009804CU) /**< \brief (USART2) IrDA Filter Register */
00049 #define REG_USART2_MAN          (0x40098050U) /**< \brief (USART2) Manchester Encoder Decoder Register */
00050 #define REG_USART2_WPMR          (0x400980E4U) /**< \brief (USART2) Write Protect Mode Register */
00051 #define REG_USART2_WPSR          (0x400980E8U) /**< \brief (USART2) Write Protect Status Register */
00052 #define REG_USART2_RPR          (0x40098100U) /**< \brief (USART2) Receive Pointer Register */
00053 #define REG_USART2_RCR          (0x40098104U) /**< \brief (USART2) Receive Counter Register */
00054 #define REG_USART2_TPR          (0x40098108U) /**< \brief (USART2) Transmit Pointer Register */
00055 #define REG_USART2_TCR          (0x4009810CU) /**< \brief (USART2) Transmit Counter Register */
00056 #define REG_USART2_RNPR          (0x40098110U) /**< \brief (USART2) Receive Next Pointer Register */
00057 #define REG_USART2_RNCR          (0x40098114U) /**< \brief (USART2) Receive Next Counter Register */
00058 #define REG_USART2_TNPR          (0x40098118U) /**< \brief (USART2) Transmit Next Pointer Register */
00059 #define REG_USART2_TNCR          (0x4009811CU) /**< \brief (USART2) Transmit Next Counter Register */
00060 #define REG_USART2_PTCR          (0x40098120U) /**< \brief (USART2) Transfer Control Register */
00061 #define REG_USART2_PTSR          (0x40098124U) /**< \brief (USART2) Transfer Status Register */
00062 #else
00063 #define REG_USART2_CR (*(WoReg*)0x40098000U) /**< \brief (USART2) Control Register */
00064 #define REG_USART2_MR (*(RwReg*)0x40098004U) /**< \brief (USART2) Mode Register */
00065 #define REG_USART2_IER (*(WoReg*)0x40098008U) /**< \brief (USART2) Interrupt Enable Register */
00066 #define REG_USART2_IDR (*(WoReg*)0x4009800CU) /**< \brief (USART2) Interrupt Disable Register */
00067 #define REG_USART2_IMR (*(RoReg*)0x40098010U) /**< \brief (USART2) Interrupt Mask Register */
00068 #define REG_USART2_CSR (*(RoReg*)0x40098014U) /**< \brief (USART2) Channel Status Register */
00069 #define REG_USART2_RHR (*(RoReg*)0x40098018U) /**< \brief (USART2) Receiver Holding Register */
00070 #define REG_USART2_THR (*(WoReg*)0x4009801CU) /**< \brief (USART2) Transmitter Holding Register */
00071 #define REG_USART2_BRGR (*(RwReg*)0x40098020U) /**< \brief (USART2) Baud Rate Generator Register */
00072 #define REG_USART2_RTOR (*(RwReg*)0x40098024U) /**< \brief (USART2) Receiver Time-out Register */
00073 #define REG_USART2_TTGR (*(RwReg*)0x40098028U) /**< \brief (USART2) Transmitter Timeguard Register */
00074 #define REG_USART2_FIDI (*(RwReg*)0x40098040U) /**< \brief (USART2) FI DI Ratio Register */
00075 #define REG_USART2_NER (*(RoReg*)0x40098044U) /**< \brief (USART2) Number of Errors Register */
00076 #define REG_USART2_IF (*(RwReg*)0x4009804CU) /**< \brief (USART2) IrDA Filter Register */
00077 #define REG_USART2_MAN (*(RwReg*)0x40098050U) /**< \brief (USART2) Manchester Encoder Decoder Register */
00078 #define REG_USART2_WPMR (*(RwReg*)0x400980E4U) /**< \brief (USART2) Write Protect Mode Register */
00079 #define REG_USART2_WPSR (*(RoReg*)0x400980E8U) /**< \brief (USART2) Write Protect Status Register */
00080 #define REG_USART2_RPR (*(RwReg*)0x40098100U) /**< \brief (USART2) Receive Pointer Register */
00081 #define REG_USART2_RCR (*(RwReg*)0x40098104U) /**< \brief (USART2) Receive Counter Register */
00082 #define REG_USART2_TPR (*(RwReg*)0x40098108U) /**< \brief (USART2) Transmit Pointer Register */
00083 #define REG_USART2_TCR (*(RwReg*)0x4009810CU) /**< \brief (USART2) Transmit Counter Register */
00084 #define REG_USART2_RNPR (*(RwReg*)0x40098110U) /**< \brief (USART2) Receive Next Pointer Register */
00085 #define REG_USART2_RNCR (*(RwReg*)0x40098114U) /**< \brief (USART2) Receive Next Counter Register */
00086 #define REG_USART2_TNPR (*(RwReg*)0x40098118U) /**< \brief (USART2) Transmit Next Pointer Register */
00087 #define REG_USART2_TNCR (*(RwReg*)0x4009811CU) /**< \brief (USART2) Transmit Next Counter Register */
00088 #define REG_USART2_PTCR (*(WoReg*)0x40098120U) /**< \brief (USART2) Transfer Control Register */
00089 #define REG_USART2_PTSR (*(RoReg*)0x40098124U) /**< \brief (USART2) Transfer Status Register */
00090 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
00091 
00092 #endif /* _SAM3U_USART2_INSTANCE_ */