usart1.h

00001 /* ---------------------------------------------------------------------------- */
00002 /*                  Atmel Microcontroller Software Support                      */
00003 /*                       SAM Software Package License                           */
00004 /* ---------------------------------------------------------------------------- */
00005 /* Copyright (c) %copyright_year%, Atmel Corporation                                        */
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00011 /*                                                                              */
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00016 /* this software without specific prior written permission.                     */
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00029 
00030 #ifndef _SAM3U_USART1_INSTANCE_
00031 #define _SAM3U_USART1_INSTANCE_
00032 
00033 /* ========== Register definition for USART1 peripheral ========== */
00034 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
00035 #define REG_USART1_CR          (0x40094000U) /**< \brief (USART1) Control Register */
00036 #define REG_USART1_MR          (0x40094004U) /**< \brief (USART1) Mode Register */
00037 #define REG_USART1_IER          (0x40094008U) /**< \brief (USART1) Interrupt Enable Register */
00038 #define REG_USART1_IDR          (0x4009400CU) /**< \brief (USART1) Interrupt Disable Register */
00039 #define REG_USART1_IMR          (0x40094010U) /**< \brief (USART1) Interrupt Mask Register */
00040 #define REG_USART1_CSR          (0x40094014U) /**< \brief (USART1) Channel Status Register */
00041 #define REG_USART1_RHR          (0x40094018U) /**< \brief (USART1) Receiver Holding Register */
00042 #define REG_USART1_THR          (0x4009401CU) /**< \brief (USART1) Transmitter Holding Register */
00043 #define REG_USART1_BRGR          (0x40094020U) /**< \brief (USART1) Baud Rate Generator Register */
00044 #define REG_USART1_RTOR          (0x40094024U) /**< \brief (USART1) Receiver Time-out Register */
00045 #define REG_USART1_TTGR          (0x40094028U) /**< \brief (USART1) Transmitter Timeguard Register */
00046 #define REG_USART1_FIDI          (0x40094040U) /**< \brief (USART1) FI DI Ratio Register */
00047 #define REG_USART1_NER          (0x40094044U) /**< \brief (USART1) Number of Errors Register */
00048 #define REG_USART1_IF          (0x4009404CU) /**< \brief (USART1) IrDA Filter Register */
00049 #define REG_USART1_MAN          (0x40094050U) /**< \brief (USART1) Manchester Encoder Decoder Register */
00050 #define REG_USART1_WPMR          (0x400940E4U) /**< \brief (USART1) Write Protect Mode Register */
00051 #define REG_USART1_WPSR          (0x400940E8U) /**< \brief (USART1) Write Protect Status Register */
00052 #define REG_USART1_RPR          (0x40094100U) /**< \brief (USART1) Receive Pointer Register */
00053 #define REG_USART1_RCR          (0x40094104U) /**< \brief (USART1) Receive Counter Register */
00054 #define REG_USART1_TPR          (0x40094108U) /**< \brief (USART1) Transmit Pointer Register */
00055 #define REG_USART1_TCR          (0x4009410CU) /**< \brief (USART1) Transmit Counter Register */
00056 #define REG_USART1_RNPR          (0x40094110U) /**< \brief (USART1) Receive Next Pointer Register */
00057 #define REG_USART1_RNCR          (0x40094114U) /**< \brief (USART1) Receive Next Counter Register */
00058 #define REG_USART1_TNPR          (0x40094118U) /**< \brief (USART1) Transmit Next Pointer Register */
00059 #define REG_USART1_TNCR          (0x4009411CU) /**< \brief (USART1) Transmit Next Counter Register */
00060 #define REG_USART1_PTCR          (0x40094120U) /**< \brief (USART1) Transfer Control Register */
00061 #define REG_USART1_PTSR          (0x40094124U) /**< \brief (USART1) Transfer Status Register */
00062 #else
00063 #define REG_USART1_CR (*(WoReg*)0x40094000U) /**< \brief (USART1) Control Register */
00064 #define REG_USART1_MR (*(RwReg*)0x40094004U) /**< \brief (USART1) Mode Register */
00065 #define REG_USART1_IER (*(WoReg*)0x40094008U) /**< \brief (USART1) Interrupt Enable Register */
00066 #define REG_USART1_IDR (*(WoReg*)0x4009400CU) /**< \brief (USART1) Interrupt Disable Register */
00067 #define REG_USART1_IMR (*(RoReg*)0x40094010U) /**< \brief (USART1) Interrupt Mask Register */
00068 #define REG_USART1_CSR (*(RoReg*)0x40094014U) /**< \brief (USART1) Channel Status Register */
00069 #define REG_USART1_RHR (*(RoReg*)0x40094018U) /**< \brief (USART1) Receiver Holding Register */
00070 #define REG_USART1_THR (*(WoReg*)0x4009401CU) /**< \brief (USART1) Transmitter Holding Register */
00071 #define REG_USART1_BRGR (*(RwReg*)0x40094020U) /**< \brief (USART1) Baud Rate Generator Register */
00072 #define REG_USART1_RTOR (*(RwReg*)0x40094024U) /**< \brief (USART1) Receiver Time-out Register */
00073 #define REG_USART1_TTGR (*(RwReg*)0x40094028U) /**< \brief (USART1) Transmitter Timeguard Register */
00074 #define REG_USART1_FIDI (*(RwReg*)0x40094040U) /**< \brief (USART1) FI DI Ratio Register */
00075 #define REG_USART1_NER (*(RoReg*)0x40094044U) /**< \brief (USART1) Number of Errors Register */
00076 #define REG_USART1_IF (*(RwReg*)0x4009404CU) /**< \brief (USART1) IrDA Filter Register */
00077 #define REG_USART1_MAN (*(RwReg*)0x40094050U) /**< \brief (USART1) Manchester Encoder Decoder Register */
00078 #define REG_USART1_WPMR (*(RwReg*)0x400940E4U) /**< \brief (USART1) Write Protect Mode Register */
00079 #define REG_USART1_WPSR (*(RoReg*)0x400940E8U) /**< \brief (USART1) Write Protect Status Register */
00080 #define REG_USART1_RPR (*(RwReg*)0x40094100U) /**< \brief (USART1) Receive Pointer Register */
00081 #define REG_USART1_RCR (*(RwReg*)0x40094104U) /**< \brief (USART1) Receive Counter Register */
00082 #define REG_USART1_TPR (*(RwReg*)0x40094108U) /**< \brief (USART1) Transmit Pointer Register */
00083 #define REG_USART1_TCR (*(RwReg*)0x4009410CU) /**< \brief (USART1) Transmit Counter Register */
00084 #define REG_USART1_RNPR (*(RwReg*)0x40094110U) /**< \brief (USART1) Receive Next Pointer Register */
00085 #define REG_USART1_RNCR (*(RwReg*)0x40094114U) /**< \brief (USART1) Receive Next Counter Register */
00086 #define REG_USART1_TNPR (*(RwReg*)0x40094118U) /**< \brief (USART1) Transmit Next Pointer Register */
00087 #define REG_USART1_TNCR (*(RwReg*)0x4009411CU) /**< \brief (USART1) Transmit Next Counter Register */
00088 #define REG_USART1_PTCR (*(WoReg*)0x40094120U) /**< \brief (USART1) Transfer Control Register */
00089 #define REG_USART1_PTSR (*(RoReg*)0x40094124U) /**< \brief (USART1) Transfer Status Register */
00090 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
00091 
00092 #endif /* _SAM3U_USART1_INSTANCE_ */