twi1.h

00001 /* ---------------------------------------------------------------------------- */
00002 /*                  Atmel Microcontroller Software Support                      */
00003 /*                       SAM Software Package License                           */
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00005 /* Copyright (c) %copyright_year%, Atmel Corporation                                        */
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00011 /*                                                                              */
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00029 
00030 #ifndef _SAM3U_TWI1_INSTANCE_
00031 #define _SAM3U_TWI1_INSTANCE_
00032 
00033 /* ========== Register definition for TWI1 peripheral ========== */
00034 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
00035 #define REG_TWI1_CR            (0x40088000U) /**< \brief (TWI1) Control Register */
00036 #define REG_TWI1_MMR           (0x40088004U) /**< \brief (TWI1) Master Mode Register */
00037 #define REG_TWI1_SMR           (0x40088008U) /**< \brief (TWI1) Slave Mode Register */
00038 #define REG_TWI1_IADR          (0x4008800CU) /**< \brief (TWI1) Internal Address Register */
00039 #define REG_TWI1_CWGR          (0x40088010U) /**< \brief (TWI1) Clock Waveform Generator Register */
00040 #define REG_TWI1_SR            (0x40088020U) /**< \brief (TWI1) Status Register */
00041 #define REG_TWI1_IER           (0x40088024U) /**< \brief (TWI1) Interrupt Enable Register */
00042 #define REG_TWI1_IDR           (0x40088028U) /**< \brief (TWI1) Interrupt Disable Register */
00043 #define REG_TWI1_IMR           (0x4008802CU) /**< \brief (TWI1) Interrupt Mask Register */
00044 #define REG_TWI1_RHR           (0x40088030U) /**< \brief (TWI1) Receive Holding Register */
00045 #define REG_TWI1_THR           (0x40088034U) /**< \brief (TWI1) Transmit Holding Register */
00046 #define REG_TWI1_RPR           (0x40088100U) /**< \brief (TWI1) Receive Pointer Register */
00047 #define REG_TWI1_RCR           (0x40088104U) /**< \brief (TWI1) Receive Counter Register */
00048 #define REG_TWI1_TPR           (0x40088108U) /**< \brief (TWI1) Transmit Pointer Register */
00049 #define REG_TWI1_TCR           (0x4008810CU) /**< \brief (TWI1) Transmit Counter Register */
00050 #define REG_TWI1_RNPR          (0x40088110U) /**< \brief (TWI1) Receive Next Pointer Register */
00051 #define REG_TWI1_RNCR          (0x40088114U) /**< \brief (TWI1) Receive Next Counter Register */
00052 #define REG_TWI1_TNPR          (0x40088118U) /**< \brief (TWI1) Transmit Next Pointer Register */
00053 #define REG_TWI1_TNCR          (0x4008811CU) /**< \brief (TWI1) Transmit Next Counter Register */
00054 #define REG_TWI1_PTCR          (0x40088120U) /**< \brief (TWI1) Transfer Control Register */
00055 #define REG_TWI1_PTSR          (0x40088124U) /**< \brief (TWI1) Transfer Status Register */
00056 #else
00057 #define REG_TWI1_CR   (*(WoReg*)0x40088000U) /**< \brief (TWI1) Control Register */
00058 #define REG_TWI1_MMR  (*(RwReg*)0x40088004U) /**< \brief (TWI1) Master Mode Register */
00059 #define REG_TWI1_SMR  (*(RwReg*)0x40088008U) /**< \brief (TWI1) Slave Mode Register */
00060 #define REG_TWI1_IADR (*(RwReg*)0x4008800CU) /**< \brief (TWI1) Internal Address Register */
00061 #define REG_TWI1_CWGR (*(RwReg*)0x40088010U) /**< \brief (TWI1) Clock Waveform Generator Register */
00062 #define REG_TWI1_SR   (*(RoReg*)0x40088020U) /**< \brief (TWI1) Status Register */
00063 #define REG_TWI1_IER  (*(WoReg*)0x40088024U) /**< \brief (TWI1) Interrupt Enable Register */
00064 #define REG_TWI1_IDR  (*(WoReg*)0x40088028U) /**< \brief (TWI1) Interrupt Disable Register */
00065 #define REG_TWI1_IMR  (*(RoReg*)0x4008802CU) /**< \brief (TWI1) Interrupt Mask Register */
00066 #define REG_TWI1_RHR  (*(RoReg*)0x40088030U) /**< \brief (TWI1) Receive Holding Register */
00067 #define REG_TWI1_THR  (*(WoReg*)0x40088034U) /**< \brief (TWI1) Transmit Holding Register */
00068 #define REG_TWI1_RPR  (*(RwReg*)0x40088100U) /**< \brief (TWI1) Receive Pointer Register */
00069 #define REG_TWI1_RCR  (*(RwReg*)0x40088104U) /**< \brief (TWI1) Receive Counter Register */
00070 #define REG_TWI1_TPR  (*(RwReg*)0x40088108U) /**< \brief (TWI1) Transmit Pointer Register */
00071 #define REG_TWI1_TCR  (*(RwReg*)0x4008810CU) /**< \brief (TWI1) Transmit Counter Register */
00072 #define REG_TWI1_RNPR (*(RwReg*)0x40088110U) /**< \brief (TWI1) Receive Next Pointer Register */
00073 #define REG_TWI1_RNCR (*(RwReg*)0x40088114U) /**< \brief (TWI1) Receive Next Counter Register */
00074 #define REG_TWI1_TNPR (*(RwReg*)0x40088118U) /**< \brief (TWI1) Transmit Next Pointer Register */
00075 #define REG_TWI1_TNCR (*(RwReg*)0x4008811CU) /**< \brief (TWI1) Transmit Next Counter Register */
00076 #define REG_TWI1_PTCR (*(WoReg*)0x40088120U) /**< \brief (TWI1) Transfer Control Register */
00077 #define REG_TWI1_PTSR (*(RoReg*)0x40088124U) /**< \brief (TWI1) Transfer Status Register */
00078 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
00079 
00080 #endif /* _SAM3U_TWI1_INSTANCE_ */