system_stm32f1xx.c

00001 /**
00002   ******************************************************************************
00003   * @file    system_stm32f1xx.c
00004   * @author  MCD Application Team
00005   * @version V4.1.0
00006   * @date    29-April-2016
00007   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
00008   * 
00009   * 1.  This file provides two functions and one global variable to be called from 
00010   *     user application:
00011   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00012   *                      factors, AHB/APBx prescalers and Flash settings). 
00013   *                      This function is called at startup just after reset and 
00014   *                      before branch to main program. This call is made inside
00015   *                      the "startup_stm32f1xx_xx.s" file.
00016   *
00017   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00018   *                                  by the user application to setup the SysTick 
00019   *                                  timer or configure other parameters.
00020   *                                     
00021   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00022   *                                 be called whenever the core clock is changed
00023   *                                 during program execution.
00024   *
00025   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00026   *    Then SystemInit() function is called, in "startup_stm32f1xx_xx.s" file, to
00027   *    configure the system clock before to branch to main program.
00028   *
00029   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on
00030   *    the product used), refer to "HSE_VALUE". 
00031   *    When HSE is used as system clock source, directly or through PLL, and you
00032   *    are using different crystal you have to adapt the HSE value to your own
00033   *    configuration.
00034   *        
00035   ******************************************************************************
00036   * @attention
00037   *
00038   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00039   *
00040   * Redistribution and use in source and binary forms, with or without modification,
00041   * are permitted provided that the following conditions are met:
00042   *   1. Redistributions of source code must retain the above copyright notice,
00043   *      this list of conditions and the following disclaimer.
00044   *   2. Redistributions in binary form must reproduce the above copyright notice,
00045   *      this list of conditions and the following disclaimer in the documentation
00046   *      and/or other materials provided with the distribution.
00047   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00048   *      may be used to endorse or promote products derived from this software
00049   *      without specific prior written permission.
00050   *
00051   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00052   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00053   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00054   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00055   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00056   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00057   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00058   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00059   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00060   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00061   *
00062   ******************************************************************************
00063   */
00064 
00065 /** @addtogroup CMSIS
00066   * @{
00067   */
00068 
00069 /** @addtogroup stm32f1xx_system
00070   * @{
00071   */  
00072   
00073 /** @addtogroup STM32F1xx_System_Private_Includes
00074   * @{
00075   */
00076 
00077 #include "stm32f1xx.h"
00078 
00079 /**
00080   * @}
00081   */
00082 
00083 /** @addtogroup STM32F1xx_System_Private_TypesDefinitions
00084   * @{
00085   */
00086 
00087 /**
00088   * @}
00089   */
00090 
00091 /** @addtogroup STM32F1xx_System_Private_Defines
00092   * @{
00093   */
00094 
00095 #if !defined  (HSE_VALUE) 
00096   #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
00097                                                 This value can be provided and adapted by the user application. */
00098 #endif /* HSE_VALUE */
00099 
00100 #if !defined  (HSI_VALUE)
00101   #define HSI_VALUE    ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
00102                                                 This value can be provided and adapted by the user application. */
00103 #endif /* HSI_VALUE */
00104 
00105 /*!< Uncomment the following line if you need to use external SRAM  */ 
00106 #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
00107 /* #define DATA_IN_ExtSRAM */
00108 #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
00109 
00110 /*!< Uncomment the following line if you need to relocate your vector Table in
00111      Internal SRAM. */ 
00112 /* #define VECT_TAB_SRAM */
00113 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
00114                                   This value must be a multiple of 0x200. */
00115 
00116 
00117 /**
00118   * @}
00119   */
00120 
00121 /** @addtogroup STM32F1xx_System_Private_Macros
00122   * @{
00123   */
00124 
00125 /**
00126   * @}
00127   */
00128 
00129 /** @addtogroup STM32F1xx_System_Private_Variables
00130   * @{
00131   */
00132 
00133 /*******************************************************************************
00134 *  Clock Definitions
00135 *******************************************************************************/
00136 #if defined(STM32F100xB) ||defined(STM32F100xE)
00137   uint32_t SystemCoreClock         = 24000000;        /*!< System Clock Frequency (Core Clock) */
00138 #else /*!< HSI Selected as System Clock source */
00139   uint32_t SystemCoreClock         = 72000000;        /*!< System Clock Frequency (Core Clock) */
00140 #endif
00141 
00142 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00143 const uint8_t APBPrescTable[8] =  {0, 0, 0, 0, 1, 2, 3, 4};
00144 
00145 /**
00146   * @}
00147   */
00148 
00149 /** @addtogroup STM32F1xx_System_Private_FunctionPrototypes
00150   * @{
00151   */
00152 
00153 #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
00154 #ifdef DATA_IN_ExtSRAM
00155   static void SystemInit_ExtMemCtl(void); 
00156 #endif /* DATA_IN_ExtSRAM */
00157 #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
00158 
00159 /**
00160   * @}
00161   */
00162 
00163 /** @addtogroup STM32F1xx_System_Private_Functions
00164   * @{
00165   */
00166 
00167 /**
00168   * @brief  Setup the microcontroller system
00169   *         Initialize the Embedded Flash Interface, the PLL and update the 
00170   *         SystemCoreClock variable.
00171   * @note   This function should be used only after reset.
00172   * @param  None
00173   * @retval None
00174   */
00175 void SystemInit (void)
00176 {
00177   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
00178   /* Set HSION bit */
00179   RCC->CR |= (uint32_t)0x00000001;
00180 
00181   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00182 #if !defined(STM32F105xC) && !defined(STM32F107xC)
00183   RCC->CFGR &= (uint32_t)0xF8FF0000;
00184 #else
00185   RCC->CFGR &= (uint32_t)0xF0FF0000;
00186 #endif /* STM32F105xC */   
00187   
00188   /* Reset HSEON, CSSON and PLLON bits */
00189   RCC->CR &= (uint32_t)0xFEF6FFFF;
00190 
00191   /* Reset HSEBYP bit */
00192   RCC->CR &= (uint32_t)0xFFFBFFFF;
00193 
00194   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00195   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00196 
00197 #if defined(STM32F105xC) || defined(STM32F107xC)
00198   /* Reset PLL2ON and PLL3ON bits */
00199   RCC->CR &= (uint32_t)0xEBFFFFFF;
00200 
00201   /* Disable all interrupts and clear pending bits  */
00202   RCC->CIR = 0x00FF0000;
00203 
00204   /* Reset CFGR2 register */
00205   RCC->CFGR2 = 0x00000000;
00206 #elif defined(STM32F100xB) || defined(STM32F100xE)
00207   /* Disable all interrupts and clear pending bits  */
00208   RCC->CIR = 0x009F0000;
00209 
00210   /* Reset CFGR2 register */
00211   RCC->CFGR2 = 0x00000000;      
00212 #else
00213   /* Disable all interrupts and clear pending bits  */
00214   RCC->CIR = 0x009F0000;
00215 #endif /* STM32F105xC */
00216     
00217 #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
00218   #ifdef DATA_IN_ExtSRAM
00219     SystemInit_ExtMemCtl(); 
00220   #endif /* DATA_IN_ExtSRAM */
00221 #endif 
00222 
00223 #ifdef VECT_TAB_SRAM
00224   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00225 #else
00226   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00227 #endif 
00228 }
00229 
00230 /**
00231   * @brief  Update SystemCoreClock variable according to Clock Register Values.
00232   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00233   *         be used by the user application to setup the SysTick timer or configure
00234   *         other parameters.
00235   *           
00236   * @note   Each time the core clock (HCLK) changes, this function must be called
00237   *         to update SystemCoreClock variable value. Otherwise, any configuration
00238   *         based on this variable will be incorrect.         
00239   *     
00240   * @note   - The system frequency computed by this function is not the real 
00241   *           frequency in the chip. It is calculated based on the predefined 
00242   *           constant and the selected clock source:
00243   *             
00244   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00245   *                                              
00246   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00247   *                          
00248   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
00249   *             or HSI_VALUE(*) multiplied by the PLL factors.
00250   *         
00251   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
00252   *             8 MHz) but the real value may vary depending on the variations
00253   *             in voltage and temperature.   
00254   *    
00255   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
00256   *              8 MHz or 25 MHz, depending on the product used), user has to ensure
00257   *              that HSE_VALUE is same as the real frequency of the crystal used.
00258   *              Otherwise, this function may have wrong result.
00259   *                
00260   *         - The result of this function could be not correct when using fractional
00261   *           value for HSE crystal.
00262   * @param  None
00263   * @retval None
00264   */
00265 void SystemCoreClockUpdate (void)
00266 {
00267   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
00268 
00269 #if defined(STM32F105xC) || defined(STM32F107xC)
00270   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00271 #endif /* STM32F105xC */
00272 
00273 #if defined(STM32F100xB) || defined(STM32F100xE)
00274   uint32_t prediv1factor = 0;
00275 #endif /* STM32F100xB or STM32F100xE */
00276     
00277   /* Get SYSCLK source -------------------------------------------------------*/
00278   tmp = RCC->CFGR & RCC_CFGR_SWS;
00279   
00280   switch (tmp)
00281   {
00282     case 0x00:  /* HSI used as system clock */
00283       SystemCoreClock = HSI_VALUE;
00284       break;
00285     case 0x04:  /* HSE used as system clock */
00286       SystemCoreClock = HSE_VALUE;
00287       break;
00288     case 0x08:  /* PLL used as system clock */
00289 
00290       /* Get PLL clock source and multiplication factor ----------------------*/
00291       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00292       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00293       
00294 #if !defined(STM32F105xC) && !defined(STM32F107xC)      
00295       pllmull = ( pllmull >> 18) + 2;
00296       
00297       if (pllsource == 0x00)
00298       {
00299         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00300         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00301       }
00302       else
00303       {
00304  #if defined(STM32F100xB) || defined(STM32F100xE)
00305        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00306        /* HSE oscillator clock selected as PREDIV1 clock entry */
00307        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
00308  #else
00309         /* HSE selected as PLL clock entry */
00310         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00311         {/* HSE oscillator clock divided by 2 */
00312           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
00313         }
00314         else
00315         {
00316           SystemCoreClock = HSE_VALUE * pllmull;
00317         }
00318  #endif
00319       }
00320 #else
00321       pllmull = pllmull >> 18;
00322       
00323       if (pllmull != 0x0D)
00324       {
00325          pllmull += 2;
00326       }
00327       else
00328       { /* PLL multiplication factor = PLL input clock * 6.5 */
00329         pllmull = 13 / 2; 
00330       }
00331             
00332       if (pllsource == 0x00)
00333       {
00334         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00335         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00336       }
00337       else
00338       {/* PREDIV1 selected as PLL clock entry */
00339         
00340         /* Get PREDIV1 clock source and division factor */
00341         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
00342         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00343         
00344         if (prediv1source == 0)
00345         { 
00346           /* HSE oscillator clock selected as PREDIV1 clock entry */
00347           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
00348         }
00349         else
00350         {/* PLL2 clock selected as PREDIV1 clock entry */
00351           
00352           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00353           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
00354           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
00355           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
00356         }
00357       }
00358 #endif /* STM32F105xC */ 
00359       break;
00360 
00361     default:
00362       SystemCoreClock = HSI_VALUE;
00363       break;
00364   }
00365   
00366   /* Compute HCLK clock frequency ----------------*/
00367   /* Get HCLK prescaler */
00368   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00369   /* HCLK clock frequency */
00370   SystemCoreClock >>= tmp;  
00371 }
00372 
00373 #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
00374 /**
00375   * @brief  Setup the external memory controller. Called in startup_stm32f1xx.s 
00376   *          before jump to __main
00377   * @param  None
00378   * @retval None
00379   */ 
00380 #ifdef DATA_IN_ExtSRAM
00381 /**
00382   * @brief  Setup the external memory controller. 
00383   *         Called in startup_stm32f1xx_xx.s/.c before jump to main.
00384   *         This function configures the external SRAM mounted on STM3210E-EVAL
00385   *         board (STM32 High density devices). This SRAM will be used as program
00386   *         data memory (including heap and stack).
00387   * @param  None
00388   * @retval None
00389   */ 
00390 void SystemInit_ExtMemCtl(void) 
00391 {
00392   __IO uint32_t tmpreg;
00393   /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
00394     required, then adjust the Register Addresses */
00395 
00396   /* Enable FSMC clock */
00397   RCC->AHBENR = 0x00000114;
00398 
00399   /* Delay after an RCC peripheral clock enabling */
00400   tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);
00401   
00402   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
00403   RCC->APB2ENR = 0x000001E0;
00404   
00405   /* Delay after an RCC peripheral clock enabling */
00406   tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);
00407 
00408   (void)(tmpreg);
00409   
00410 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
00411 /*----------------  SRAM Address lines configuration -------------------------*/
00412 /*----------------  NOE and NWE configuration --------------------------------*/  
00413 /*----------------  NE3 configuration ----------------------------------------*/
00414 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
00415   
00416   GPIOD->CRL = 0x44BB44BB;  
00417   GPIOD->CRH = 0xBBBBBBBB;
00418 
00419   GPIOE->CRL = 0xB44444BB;  
00420   GPIOE->CRH = 0xBBBBBBBB;
00421 
00422   GPIOF->CRL = 0x44BBBBBB;  
00423   GPIOF->CRH = 0xBBBB4444;
00424 
00425   GPIOG->CRL = 0x44BBBBBB;  
00426   GPIOG->CRH = 0x444B4B44;
00427    
00428 /*----------------  FSMC Configuration ---------------------------------------*/  
00429 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
00430   
00431   FSMC_Bank1->BTCR[4] = 0x00001091;
00432   FSMC_Bank1->BTCR[5] = 0x00110212;
00433 }
00434 #endif /* DATA_IN_ExtSRAM */
00435 #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
00436 
00437 /**
00438   * @}
00439   */
00440 
00441 /**
00442   * @}
00443   */
00444   
00445 /**
00446   * @}
00447   */    
00448 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/