system_SAM3U.c

00001 /**************************************************************************//**
00002  * @file     system_SAM3U.c
00003  * @brief    CMSIS Cortex-M3 Device Peripheral Access Layer Source File
00004  *           for the Atmel SAM3U Device Series
00005  * @version  V1.10
00006  * @date     16. April 2013
00007  *
00008  * @note
00009  * Copyright (C) 2019-2013 ARM Limited. All rights reserved.
00010  *
00011  * @par
00012  * ARM Limited (ARM) is supplying this software for use with Cortex-M
00013  * processor based microcontrollers.  This file can be freely distributed
00014  * within development tools that are supporting such ARM based processors.
00015  *
00016  * @par
00017  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
00018  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
00019  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
00020  * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
00021  * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
00022  *
00023  ******************************************************************************/
00024 
00025 
00026 #include "sam3u.h"
00027 
00028 /*
00029 //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
00030 */
00031 
00032 /*--------------------- Embedded Flash Controllers Configuration -------------
00033 //
00034 // <e0> Embedded Flash Controller 0 (EEFC0)
00035 //   <o1.8..11>  FWS: Flash Wait State <1-16><#-1>
00036 //   <o1.24>     FAM: Flash Access Mode
00037 //                 <0=> 128-bit in read mode (enhance speed)
00038 //                 <1=> 64-bit in read mode (enhance power consumption)
00039 // </e0>
00040 //
00041 // <e2> Embedded Flash Controller 1 (EEFC1)
00042 //   <o3.8..11>  FWS: Flash Wait State <1-16><#-1>
00043 //   <o3.24>     FAM: Flash Access Mode
00044 //                 <0=> 128-bit in read mode (enhance speed)
00045 //                 <1=> 64-bit in read mode (enhance power consumption)
00046 // </e2>
00047 */
00048 #define EEFC0_SETUP     1               // Reset values:
00049 #define EEFC0_FMR_Val   0x00000300      // 0x00000000
00050 #define EEFC1_SETUP     1               // Reset values:
00051 #define EEFC1_FMR_Val   0x00000300      // 0x00000000
00052 
00053 
00054 /*--------------------- Power Management Controller Configuration ------------
00055 //
00056 // <e> Power Management Controller (PMC)
00057 //   <h> System Clock Enable Register (PMC_SCER)
00058 //     <o1.8>      PCK0: Programmable Clock 0 Output Enable
00059 //     <o1.9>      PCK1: Programmable Clock 1 Output Enable
00060 //     <o1.10>     PCK2: Programmable Clock 2 Output Enable
00061 //   </h>
00062 //
00063 //   <h> Peripheral Clock Enable Register (PMC_PCER)
00064 //     <o2.2>      PID2:  Real Time Clock Clock Enable
00065 //     <o2.3>      PID3:  Real Time Timer Clock Enable
00066 //     <o2.4>      PID4:  Watchdog Timer Clock Enable
00067 //     <o2.5>      PID5:  Power Management Controller Clock Enable
00068 //     <o2.6>      PID6:  Enhanced Embedded Flash Controller 0 Clock Enable
00069 //     <o2.7>      PID7:  Enhanced Embedded Flash Controller 1 Clock Enable
00070 //     <o2.8>      PID8:  UART Clock Enable
00071 //     <o2.9>      PID9:  Static Memory Controller Clock Enable
00072 //     <o2.10>     PID10: Parallel I/O Controller A Clock Enable
00073 //     <o2.11>     PID11: Parallel I/O Controller B Clock Enable
00074 //     <o2.12>     PID12: Parallel I/O Controller C Clock Enable
00075 //     <o2.13>     PID13: USART 0 Clock Enable
00076 //     <o2.14>     PID14: USART 1 Clock Enable
00077 //     <o2.15>     PID15: USART 2 Clock Enable
00078 //     <o2.16>     PID16: USART 3 Clock Enable
00079 //     <o2.17>     PID17: High Speed Multimedia Card Interface Clock Enable
00080 //     <o2.18>     PID18: Two-wire Interface 0 Clock Enable
00081 //     <o2.19>     PID19: Two-wire Interface 1 Clock Enable
00082 //     <o2.20>     PID20: Synchronous Peripheral Interface Clock Enable
00083 //     <o2.21>     PID21: Synchronous Serial Controller Clock Enable
00084 //     <o2.22>     PID22: Timer Counter 0 Clock Enable
00085 //     <o2.23>     PID23: Timer Counter 1 Clock Enable
00086 //     <o2.24>     PID24: Timer Counter 2 Clock Enable
00087 //     <o2.25>     PID25: Pulse Width Modulation Controller Clock Enable
00088 //     <o2.26>     PID26: 12-bit ADC Controller Clock Enable
00089 //     <o2.27>     PID27: 10-bit ADC Controller Clock Enable
00090 //     <o2.28>     PID28: DMA Controller Clock Enable
00091 //     <o2.29>     PID29: USB Device High Speed Clock Enable
00092 //   </h>
00093 //
00094 //   <h> UTMI Clock Configuration Register (CKGR_UCKR)
00095 //     <o3.16>     UPLLEN: UTMI PLL Enable
00096 //     <o3.20..23> UPLLCOUNT: UTMI PLL Startup Time <0-15>
00097 //   </h>
00098 //
00099 //   <h> Main Oscillator Register (CKGR_MOR)
00100 //     <o4.0>      MOSCXTEN: Main Crystal Oscillator Enable
00101 //     <o4.1>      MOSCXTBY: Main Crystal Oscillator Bypass
00102 //     <o4.2>      WAITMODE: Wait Mode Command
00103 //     <o4.3>      MOSCRCEN: Main On-chip RC Oscillator Enable
00104 //     <o4.4..6>   MOSCRCF: Main On-chip RC Oscillator Frequency Selection
00105 //                   <0=> 4MHz <1=> 8 MHz <2=> 12 MHz <3=> Reserved
00106 //     <o4.8..15>  MOSCXTST: Main Crystal Oscillator Startup Time <0-255>
00107 //     <o4.24>     MOSCSEL: Main Oscillator Selection
00108 //                   <0=> Main On-chip RC Oscillator <1=> Main Crystal Oscillator
00109 //     <o4.25>     CFDEN: Clock Failure Detector Enable
00110 //   </h>
00111 //
00112 //   <h> Clock Generator Phase Locked Loop A Register (CKGR_PLLAR)
00113 //                   <i> PLL A Freq = (Main CLOCK Freq / DIVA) * (MULA + 1)
00114 //                   <i> Example: XTAL = 12 MHz, DIVA = 1, MULA = 14  =>  PLLA =  168 MHz
00115 //     <o5.0..7>   DIVA: PLL Divider A <0-255>
00116 //                   <i> 0        - Divider output is 0
00117 //                   <i> 1        - Divider is bypassed
00118 //                   <i> 2 .. 255 - Divider output is the Main Clock divided by DIVA
00119 //     <o5.8..13>  PLLACOUNT: PLL A Counter <0-63>
00120 //                   <i> Number of Slow Clocks before the LOCKA bit is set in
00121 //                   <i> PMC_SR after CKGR_PLLAR is written
00122 //     <o5.14..15> STMODE: Start Mode
00123 //                   <0=> Fast Startup <1=> Reserved <2=> Normal Startup <3=> Reserved
00124 //                   <i> Must be set to "Normal Startup" when PLL A is Off
00125 //     <o5.16..26> MULA: PLL A Multiplier <0-2047>
00126 //                   <i> 0         - The PLL A is deactivated
00127 //                   <i> 1 .. 2047 - The PLL A Clock frequency is the PLL a input
00128 //                   <i>             frequency multiplied by MULA + 1
00129 //   </h>
00130 //
00131 //   <h> Master Clock Register (CKGR_MCKR)
00132 //     <o6.0..1>   CSS: Master Clock Selection
00133 //                   <0=> Slow Clock
00134 //                   <1=> Main Clock
00135 //                   <2=> PLL A Clock
00136 //                   <3=> UPLL Clock
00137 //     <o6.4..6>   PRES: Master Clock Prescaler
00138 //                   <0=> Clock        <1=> Clock / 2
00139 //                   <2=> Clock / 4    <3=> Clock / 8
00140 //                   <4=> Clock / 16   <5=> Clock / 32
00141 //                   <6=> Clock / 64   <7=> Clock / 6
00142 //   </h>
00143 //
00144 //   <h> Programmable Clock Register 0 (PMC_PCK0)
00145 //     <o7.0..2>   CSS: Master Clock Selection
00146 //                   <0=> Slow Clock
00147 //                   <1=> Main Clock
00148 //                   <2=> PLL A Clock
00149 //                   <3=> UPLL Clock
00150 //                   <4=> Master Clock
00151 //                   <5=> Master Clock
00152 //                   <6=> Master Clock
00153 //                   <7=> Master Clock
00154 //     <o7.4..6>   PRES: Programmable Clock Prescaler
00155 //                   <0=> Clock        <1=> Clock / 2
00156 //                   <2=> Clock / 4    <3=> Clock / 8
00157 //                   <4=> Clock / 16   <5=> Clock / 32
00158 //                   <6=> Clock / 64   <7=> Reserved
00159 //   </h>
00160 //
00161 //   <h> Programmable Clock Register 1 (PMC_PCK1)
00162 //     <o8.0..2>   CSS: Master Clock Selection
00163 //                   <0=> Slow Clock
00164 //                   <1=> Main Clock
00165 //                   <2=> PLL A Clock
00166 //                   <3=> UPLL Clock
00167 //                   <4=> Master Clock
00168 //                   <5=> Master Clock
00169 //                   <6=> Master Clock
00170 //                   <7=> Master Clock
00171 //     <o8.4..6>   PRES: Programmable Clock Prescaler
00172 //                   <0=> None         <1=> Clock / 2
00173 //                   <2=> Clock / 4    <3=> Clock / 8
00174 //                   <4=> Clock / 16   <5=> Clock / 32
00175 //                   <6=> Clock / 64   <7=> Reserved
00176 //   </h>
00177 //
00178 //   <h> Programmable Clock Register 2 (PMC_PCK2)
00179 //     <o9.0..2>   CSS: Master Clock Selection
00180 //                   <0=> Slow Clock
00181 //                   <1=> Main Clock
00182 //                   <2=> PLL A Clock
00183 //                   <3=> UPLL Clock
00184 //                   <4=> Master Clock
00185 //                   <5=> Master Clock
00186 //                   <6=> Master Clock
00187 //                   <7=> Master Clock
00188 //     <o9.4..6>   PRES: Programmable Clock Prescaler
00189 //                   <0=> None         <1=> Clock / 2
00190 //                   <2=> Clock / 4    <3=> Clock / 8
00191 //                   <4=> Clock / 16   <5=> Clock / 32
00192 //                   <6=> Clock / 64   <7=> Reserved
00193 //   </h>
00194 // </e>
00195 */
00196 #define PMC_SETUP       1               // Reset values:
00197 #define PMC_SCER_Val    0x00000000      // WO register (0x00000001)
00198 #define PMC_PCER_Val    0x00001C00      // WO register (0x00000000)
00199 #define CKGR_UCKR_Val   0x10200000      // 0x10200800
00200 #define CKGR_MOR_Val    0x01370101      // 0x00000001
00201 #define CKGR_PLLAR_Val  0x200F8601 //0x200D8601      // 0x00003F00
00202 #define PMC_MCKR_Val    0x00000012      // 0x00000001
00203 #define PMC_PCK0_Val    0x00000000      // 0x00000000
00204 #define PMC_PCK1_Val    0x00000000      // 0x00000000
00205 #define PMC_PCK2_Val    0x00000000      // 0x00000000
00206 
00207 
00208 /*--------------------- Watchdog Configuration -------------------------------
00209 //
00210 // <e> Watchdog Disable
00211 // </e>
00212 */
00213 #define WDT_SETUP       1               // Reset values:
00214 
00215 
00216 /*
00217 //-------- <<< end of configuration section >>> ------------------------------
00218 */
00219 
00220 /*----------------------------------------------------------------------------
00221   Check the register settings
00222  *----------------------------------------------------------------------------*/
00223 #define CHECK_RANGE(val, min, max)                ((val < min) || (val > max))
00224 #define CHECK_RSVD(val, mask)                     (val & mask)
00225 
00226 /* Embedded Flash Controllers Configuration ----------------------------------*/
00227 #if (CHECK_RSVD((EEFC0_FMR_Val),  ~0x01000F01))
00228    #error "EEFC0_FMR: Invalid values of reserved bits!"
00229 #endif
00230 
00231 #if (CHECK_RSVD((EEFC1_FMR_Val),  ~0x01000F01))
00232    #error "EEFC1_FMR: Invalid values of reserved bits!"
00233 #endif
00234 
00235 /* Power Management Controller Configuration ---------------------------------*/
00236 #if (CHECK_RSVD((PMC_SCER_Val),   ~0x00000700))
00237    #error "PMC_SCER: Invalid values of reserved bits!"
00238 #endif
00239 
00240 #if (CHECK_RSVD((PMC_PCER_Val),   ~0xFFFFFFFC))
00241    #error "PMC_PCER: Invalid values of reserved bits!"
00242 #endif
00243 
00244 #if (CHECK_RSVD((CKGR_UCKR_Val),  ~0x10F10000))
00245    #error "CKGR_UCKR: Invalid values of reserved bits!"
00246 #endif
00247 
00248 #if (CHECK_RSVD((CKGR_MOR_Val),   ~0x03FFFF7F))
00249    #error "CKGR_MOR: Invalid values of reserved bits!"
00250 #endif
00251 
00252 #if (CHECK_RSVD((CKGR_PLLAR_Val), ~0x27FFFFFF))
00253    #error "CKGR_PLLAR: Invalid values of reserved bits!"
00254 #endif
00255 
00256 #if (CHECK_RSVD((PMC_MCKR_Val),   ~0x00000073))
00257    #error "PMC_MCKR: Invalid values of reserved bits!"
00258 #endif
00259 
00260 #if (CHECK_RSVD((PMC_PCK0_Val),   ~0x00000077))
00261    #error "PMC_PCK0: Invalid values of reserved bits!"
00262 #endif
00263 
00264 #if (CHECK_RSVD((PMC_PCK1_Val),   ~0x00000077))
00265    #error "PMC_PCK1: Invalid values of reserved bits!"
00266 #endif
00267 
00268 #if (CHECK_RSVD((PMC_PCK2_Val),   ~0x00000077))
00269    #error "PMC_PCK2: Invalid values of reserved bits!"
00270 #endif
00271 
00272 
00273 /*----------------------------------------------------------------------------
00274   DEFINES
00275  *----------------------------------------------------------------------------*/
00276 
00277 /*----------------------------------------------------------------------------
00278   Define clocks
00279  *----------------------------------------------------------------------------*/
00280 #define XTAL        (12000000UL)        /* Crystal frequency                  */
00281 #define XTAL32      (   32768UL)        /* 32k crystal frequency              */
00282 #define OSC_CLK     (      XTAL)        /* Main oscillator frequency          */
00283 #define OSC32_CLK   (    XTAL32)        /* 32k oscillator frequency           */
00284 #define ERC_OSC     (   32000UL)        /* Embedded RC oscillator freqquency  */
00285 #define EFRC_OSC    ( 4000000UL)        /* Embedded fast RC oscillator freq   */
00286 
00287 
00288 
00289 #if (PMC_SETUP)
00290   /* Determine clock frequency according to clock register values             */
00291   #if  ((PMC_MCKR_Val & 3) == 0)         /* Slow Clock is selected             */
00292       #if (1 /* PMC_SR & (1 << 7) */)   /* MUST be checked with correct register */
00293         #define __CORE_CLK_PRE     (OSC32_CLK)
00294       #else
00295         #define __CORE_CLK_PRE     (ERC_OSC)
00296       #endif
00297   #elif ((PMC_MCKR_Val & 3) == 1)        /* Main Clock is selected             */
00298       #if (CKGR_MOR_Val & (1 << 24))
00299         #if ((CKGR_MOR_Val & (1<< 0)) == 0)
00300           #error "CKGR_MOR: Main Crystal Oscillator selected but not enabled!"
00301         #endif
00302         #define __CORE_CLK_PRE     (OSC_CLK)
00303       #else
00304         #if ((CKGR_MOR_Val & (1<< 3)) == 0)
00305           #error "CKGR_MOR: Main On-Chip RC Oscillator selected but not enabled!"
00306         #endif
00307         #if   (((CKGR_MOR_Val >> 4) & 3) == 0)
00308           #define __CORE_CLK_PRE     (EFRC_OSC)
00309         #elif (((CKGR_MOR_Val >> 4) & 3) == 1)
00310           #define __CORE_CLK_PRE     (EFRC_OSC * 2)
00311         #elif (((CKGR_MOR_Val >> 4) & 3) == 2)
00312           #define __CORE_CLK_PRE     (EFRC_OSC * 3)
00313         #else
00314           #define __CORE_CLK_PRE     (EFRC_OSC)
00315         #endif
00316       #endif
00317   #elif ((PMC_MCKR_Val & 3) == 2)        /* PLLA Clock is selected             */
00318       #if (CKGR_MOR_Val & (1 << 24))
00319         #if ((CKGR_MOR_Val & (1<< 0)) == 0)
00320           #error "CKGR_MOR: Main Crystal Oscillator selected but not enabled!"
00321         #endif
00322         #define __PLLA_CLK       (OSC_CLK)
00323       #else
00324         #if ((CKGR_MOR_Val & (1<< 3)) == 0)
00325           #error "CKGR_MOR: Main On-Chip RC Oscillator selected but not enabled!"
00326         #endif
00327         #if   (((CKGR_MOR_Val >> 4) & 3) == 0)
00328           #define __PLLA_CLK      (EFRC_OSC)
00329         #elif (((CKGR_MOR_Val >> 4) & 3) == 1)
00330           #define __PLLA_CLK      (EFRC_OSC * 2)
00331         #elif (((CKGR_MOR_Val >> 4) & 3) == 2)
00332           #define __PLLA_CLK      (EFRC_OSC * 3)
00333         #else
00334           #define __PLLA_CLK      (EFRC_OSC)
00335         #endif
00336       #endif
00337 
00338       #define __PLLA_MUL       ((((CKGR_PLLAR_Val) >> 16) & 0x7FF) + 1)
00339       #define __PLLA_DIV       ((((CKGR_PLLAR_Val) >>  0) & 0x0FF))
00340       #define __CORE_CLK_PRE  (__PLLA_CLK * __PLLA_MUL / __PLLA_DIV)
00341   #else                                  /* UPLL Clock is selected             */
00342       #define __CORE_CLK_PRE  (OSC_CLK * 40)
00343   #endif
00344 
00345   #if (((PMC_MCKR_Val >> 4) & 7) == 7)
00346     #define __CORE_CLK   (__CORE_CLK_PRE / 6)
00347   #else
00348     #define __CORE_CLK    (__CORE_CLK_PRE >> ((PMC_MCKR_Val >> 4) & 7))
00349   #endif
00350 
00351 #else
00352     #define __CORE_CLK   (EFRC_OSC)
00353 #endif
00354 
00355 #if (__CORE_CLK > 96000000UL)
00356   #error "Core Clock > 96MHz!"
00357 #endif
00358 
00359 /*----------------------------------------------------------------------------
00360   Clock Variable definitions
00361  *----------------------------------------------------------------------------*/
00362 uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
00363 
00364 
00365 /*----------------------------------------------------------------------------
00366   Clock functions
00367  *----------------------------------------------------------------------------*/
00368 void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
00369 {
00370   /* Determine clock frequency according to clock register values             */
00371   switch (PMC->PMC_MCKR & 3) {
00372     case 0:                             /* Slow clock                         */
00373       if (SUPC->SUPC_SR & (1 << 7))
00374         SystemCoreClock = OSC32_CLK;
00375       else
00376         SystemCoreClock = ERC_OSC;
00377       break;
00378     case 1:                             /* Main clock                         */
00379       if (PMC->CKGR_MOR & (1 << 24))
00380         SystemCoreClock = OSC_CLK;
00381       else {
00382         SystemCoreClock = EFRC_OSC;
00383         switch ((PMC->CKGR_MOR >> 4) & 3) {
00384           case 0:
00385             break;
00386           case 1:
00387             SystemCoreClock *= 2;
00388             break;
00389           case 2:
00390             SystemCoreClock *= 3;
00391             break;
00392           case 3:
00393             break;
00394         }
00395       }
00396       break;
00397     case 2:                             /* PLLA clock                         */
00398       if (PMC->CKGR_MOR & (1 << 24))
00399         SystemCoreClock = OSC_CLK;
00400       else {
00401         SystemCoreClock = EFRC_OSC;
00402         switch ((PMC->CKGR_MOR >> 4) & 3) {
00403           case 0:
00404             break;
00405           case 1:
00406             SystemCoreClock *= 2;
00407             break;
00408           case 2:
00409             SystemCoreClock *= 3;
00410             break;
00411           case 3:
00412             break;
00413         }
00414       }
00415       SystemCoreClock *= ((((PMC->CKGR_PLLAR) >> 16) & 0x7FF) + 1);
00416       SystemCoreClock /= ((((PMC->CKGR_PLLAR) >>  0) & 0x0FF));
00417       break;
00418     case 3:                             /* UPLL clock                         */
00419       SystemCoreClock = OSC_CLK * 40;
00420       break;
00421   }
00422 
00423   if (((PMC->PMC_MCKR >> 4) & 7) == 7)
00424     SystemCoreClock /= 6;
00425   else
00426     SystemCoreClock >>= ((PMC->PMC_MCKR >> 4) & 7);
00427 
00428 }
00429 
00430 /**
00431  * Initialize the system
00432  *
00433  * @param  none
00434  * @return none
00435  *
00436  * @brief  Setup the microcontroller system.
00437  *         Initialize the System and update the SystemFrequency variable.
00438  */
00439 void SystemInit (void)
00440 {
00441 #if (EEFC0_SETUP == 1)                  /* Embedded Flash Controller 0 Setup  */
00442   EFC0->EEFC_FMR = EEFC0_FMR_Val;
00443 #endif
00444 
00445 #if (EEFC1_SETUP == 1)                  /* Embedded Flash Controller 1 Setup  */
00446   #ifdef EFC1                           /* some SAM3U devices do not have EFC1*/
00447   EFC1->EEFC_FMR = EEFC1_FMR_Val;
00448   #endif
00449 #endif
00450 
00451 #if (PMC_SETUP == 1)                    /* Power Management Controller Setup  */
00452 
00453 PMC->PMC_WPMR = 0x504D4300;             /* Disable write protect              */
00454 
00455 #if (CKGR_UCKR_Val & (1 << 16))         /* If UPLL Enabled                    */
00456   PMC->CKGR_UCKR = CKGR_UCKR_Val;
00457   while (!(PMC->PMC_SR & (1 << 6)));    /* Wait for LOCKU                     */
00458 #endif
00459 
00460 #if (CKGR_MOR_Val & ((1<<3)|(1<<0)))    /* If MOSCRCEN or MOSCXTEN set        */
00461   PMC->CKGR_MOR  =  (PMC->CKGR_MOR &  (1<<24)) | /* Keep the current MOSCSEL  */
00462                     (CKGR_MOR_Val  & ~(1<<24)) | /* Set value except MOSCSEL  */
00463                     ((1<<3)|(1<<0));             /* and enable bothe OSC      */
00464 #if (CKGR_MOR_Val & ((1 << 3)))
00465   while (!(PMC->PMC_SR & (1 << 17)));   /* Wait for MOSCRCS                   */
00466 #endif
00467 #if (CKGR_MOR_Val & ((1 << 0)))
00468   while (!(PMC->PMC_SR & (1 << 0)));    /* Wait for MOSCXTS                   */
00469 #endif
00470   PMC->CKGR_MOR  =  CKGR_MOR_Val;       /* set the desired selection          */
00471   while (!(PMC->PMC_SR & (1 << 16)));   /* Wait for MOSCSELS                  */
00472 #endif
00473 
00474 #if (CKGR_PLLAR_Val & ((0x7FF<<16)))    /* If MULA != 0                       */
00475   PMC->CKGR_PLLAR = CKGR_PLLAR_Val;
00476   while (!(PMC->PMC_SR & (1 << 1)));    /* Wait for LOCKA                     */
00477 #endif
00478 
00479   if ((PMC_MCKR_Val & 0x03) >= 2) {
00480     /* Write PRES field only                                                  */
00481     PMC->PMC_MCKR = (PMC->PMC_MCKR & ~0x70) | (PMC_MCKR_Val & 0x70);
00482   } else {
00483     /* Write CSS field only                                                   */
00484     PMC->PMC_MCKR = (PMC->PMC_MCKR & ~0x03) | (PMC_MCKR_Val & 0x03);
00485   }
00486   while (!(PMC->PMC_SR & (1 << 3)));    /* Wait for MCKRDY                    */
00487   PMC->PMC_MCKR   =  PMC_MCKR_Val;      /* Write all MCKR                     */
00488   while (!(PMC->PMC_SR & (1 << 3)));    /* Wait for MCKRDY                    */
00489 
00490 #if (PMC_PCK0_Val)
00491   PMC->PMC_PCKR[0] = PMC_PCK0_Val;      /* Write PCK0                         */
00492   while (!(PMC->PMC_SR & (1 << 8)));    /* Wait for PCKRDY0                   */
00493 #endif
00494 #if (PMC_PCK1_Val)
00495   PMC->PMC_PCKR[1] = PMC_PCK1_Val;      /* Write PCK1                         */
00496   while (!(PMC->PMC_SR & (1 << 9)));    /* Wait for PCKRDY1                   */
00497 #endif
00498 #if (PMC_PCK2_Val)
00499   PMC->PMC_PCKR[2] = PMC_PCK2_Val;      /* Write PCK2                         */
00500   while (!(PMC->PMC_SR & (1 << 10)));   /* Wait for PCKRDY2                   */
00501 #endif
00502 
00503   PMC->PMC_SCER  = PMC_SCER_Val;
00504   PMC->PMC_PCER0 = PMC_PCER_Val;
00505 
00506 PMC->PMC_WPMR = 0x504D4301;             /* Enable write protect               */
00507 #endif
00508 
00509 #if (WDT_SETUP == 1)                    /* Watchdog Setup                     */
00510   WDT->WDT_MR = WDT_MR_WDDIS;
00511 #endif
00512 }