system_MKL26Z4.c

00001 /*
00002 ** ###################################################################
00003 **     Processor:           MKL26Z128VLK4
00004 **     Compilers:           ARM Compiler
00005 **                          Freescale C/C++ for Embedded ARM
00006 **                          GNU C Compiler
00007 **                          IAR ANSI C/C++ Compiler for ARM
00008 **
00009 **     Reference manual:    KL26RM, Rev.1, Jun 2012
00010 **     Version:             rev. 1.1, 2012-06-21
00011 **
00012 **     Abstract:
00013 **         Provides a system configuration function and a global variable that
00014 **         contains the system frequency. It configures the device and initializes
00015 **         the oscillator (PLL) that is part of the microcontroller device.
00016 **
00017 **     Copyright: 2012 Freescale Semiconductor, Inc. All Rights Reserved.
00018 **
00019 **     http:                 www.freescale.com
00020 **     mail:                 support@freescale.com
00021 **
00022 **     Revisions:
00023 **     - rev. 1.0 (2012-06-13)
00024 **         Initial version.
00025 **     - rev. 1.1 (2012-06-21)
00026 **         Update according to reference manual rev. 1.
00027 **
00028 ** ###################################################################
00029 */
00030 
00031 /**
00032  * @file MKL25Z4
00033  * @version 1.1
00034  * @date 2012-06-21
00035  * @brief Device specific configuration file for MKL25Z4 (implementation file)
00036  *
00037  * Provides a system configuration function and a global variable that contains
00038  * the system frequency. It configures the device and initializes the oscillator
00039  * (PLL) that is part of the microcontroller device.
00040  */
00041 
00042 #include "stdint.h"
00043 #include "MKL26Z4.h"
00044 
00045 #define DISABLE_WDOG    1
00046 
00047 #define CLOCK_SETUP     1
00048 /* Predefined clock setups
00049    0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
00050          Reference clock source for MCG module is the slow internal clock source 32.768kHz
00051          Core clock = 41.94MHz, BusClock = 13.98MHz
00052    1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
00053          Reference clock source for MCG module is an external crystal 8MHz
00054          Core clock = 48MHz, BusClock = 24MHz
00055    2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
00056          Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication
00057          Core clock = 8MHz, BusClock = 8MHz
00058 */
00059 
00060 /*----------------------------------------------------------------------------
00061   Define clock source values
00062  *----------------------------------------------------------------------------*/
00063 #if (CLOCK_SETUP == 0)
00064     #define CPU_XTAL_CLK_HZ                 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
00065     #define CPU_INT_SLOW_CLK_HZ             32768u   /* Value of the slow internal oscillator clock frequency in Hz  */
00066     #define CPU_INT_FAST_CLK_HZ             4000000u /* Value of the fast internal oscillator clock frequency in Hz  */
00067     #define DEFAULT_SYSTEM_CLOCK            41943040u /* Default System clock value */
00068 #elif (CLOCK_SETUP == 1)
00069     #define CPU_XTAL_CLK_HZ                 16000000u/* Value of the external crystal or oscillator clock frequency in Hz */
00070     #define CPU_INT_SLOW_CLK_HZ             32768u   /* Value of the slow internal oscillator clock frequency in Hz  */
00071     #define CPU_INT_FAST_CLK_HZ             4000000u /* Value of the fast internal oscillator clock frequency in Hz  */
00072     #define DEFAULT_SYSTEM_CLOCK            48000000u /* Default System clock value */
00073 #elif (CLOCK_SETUP == 2)
00074     #define CPU_XTAL_CLK_HZ                 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
00075     #define CPU_INT_SLOW_CLK_HZ             32768u   /* Value of the slow internal oscillator clock frequency in Hz  */
00076     #define CPU_INT_FAST_CLK_HZ             4000000u /* Value of the fast internal oscillator clock frequency in Hz  */
00077     #define DEFAULT_SYSTEM_CLOCK            8000000u /* Default System clock value */
00078 #endif /* (CLOCK_SETUP == 2) */
00079 
00080 
00081 /* ----------------------------------------------------------------------------
00082    -- Core clock
00083    ---------------------------------------------------------------------------- */
00084 
00085 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
00086 
00087 /* ----------------------------------------------------------------------------
00088    -- SystemInit()
00089    ---------------------------------------------------------------------------- */
00090 
00091 void SystemInit (void) {
00092 #if (DISABLE_WDOG)
00093   /* Disable the WDOG module */
00094   /* SIM_COPC: COPT=0,COPCLKS=0,COPW=0 */
00095   SIM->COPC = (uint32_t)0x00u;
00096 #endif /* (DISABLE_WDOG) */
00097 #if (CLOCK_SETUP == 0)
00098   SIM->CLKDIV1 = (uint32_t)0x00020000UL; /* Update system prescalers */
00099   /* Switch to FEI Mode */
00100   /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
00101   MCG->C1 = (uint8_t)0x06U;
00102   MCG->C2 = (uint8_t)0x00U;
00103   /* MCG->C4: DMX32=0,DRST_DRS=1 */
00104   MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0U) | (uint8_t)0x20U);
00105   OSC0->CR = (uint8_t)0x80U;
00106   MCG->C5 = (uint8_t)0x00U;
00107   /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
00108   MCG->C6 = (uint8_t)0x00U;
00109   while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
00110   }
00111   while((MCG->S & 0x0CU) != 0x00U) {    /* Wait until output of the FLL is selected */
00112   }
00113 #elif (CLOCK_SETUP == 1)
00114   /* SIM->SCGC5: PORTA=1 */
00115   SIM->SCGC5 |= (uint32_t)0x0200UL;     /* Enable clock gate for ports to enable pin routing */
00116   SIM->CLKDIV1 = (uint32_t)0x10010000UL; /* Update system prescalers */
00117   /* PORTA->PCR18: ISF=0,MUX=0 */
00118   PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
00119   /* PORTA->PCR19: ISF=0,MUX=0 */
00120   PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
00121   /* Switch to FBE Mode */
00122   OSC0->CR = (uint8_t)0x80U; // was 0x89U for 8Mhz
00123   MCG->C2 = (uint8_t)0x24U;
00124   /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
00125   MCG->C1 = (uint8_t)0xA2U; //was 0x9AU; for 8Mhz
00126   /* MCG->C4: DMX32=0,DRST_DRS=0 */
00127   MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
00128   MCG->C5 = (uint8_t)0x03U; //was 0x01U; for 8Mhz 
00129   /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
00130   MCG->C6 = (uint8_t)0x00U;
00131   while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
00132   }
00133   while((MCG->S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */
00134   }
00135   /* Switch to PBE Mode */
00136   /* MCG->C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0 */
00137   MCG->C6 = (uint8_t)0x40U;
00138   while((MCG->S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */
00139   }
00140   while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until locked */
00141   }
00142   /* Switch to PEE Mode */
00143   /* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
00144   MCG->C1 = (uint8_t)0x1AU;
00145   while((MCG->S & 0x0CU) != 0x0CU) {    /* Wait until output of the PLL is selected */
00146   }
00147 #elif (CLOCK_SETUP == 2)
00148   /* SIM->SCGC5: PORTA=1 */
00149   SIM->SCGC5 |= (uint32_t)0x0200UL;     /* Enable clock gate for ports to enable pin routing */
00150   SIM->CLKDIV1 = (uint32_t)0x00000000UL; /* Update system prescalers */
00151   /* PORTA->PCR18: ISF=0,MUX=0 */
00152   PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
00153   /* PORTA->PCR19: ISF=0,MUX=0 */
00154   PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
00155   /* Switch to FBE Mode */
00156   OSC0->CR = (uint8_t)0x89U;
00157   MCG->C2 = (uint8_t)0x24U;
00158   /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
00159   MCG->C1 = (uint8_t)0x9AU;
00160   /* MCG->C4: DMX32=0,DRST_DRS=0 */
00161   MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
00162   MCG->C5 = (uint8_t)0x00U;
00163   /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
00164   MCG->C6 = (uint8_t)0x00U;
00165   while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
00166   }
00167   while((MCG->S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */
00168   }
00169   /* Switch to BLPE Mode */
00170   MCG->C2 = (uint8_t)0x26U;
00171   while((MCG->S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */
00172   }
00173 #endif /* (CLOCK_SETUP == 2) */
00174 }
00175 
00176 /* ----------------------------------------------------------------------------
00177    -- SystemCoreClockUpdate()
00178    ---------------------------------------------------------------------------- */
00179 
00180 void SystemCoreClockUpdate (void) {
00181   uint32_t MCGOUTClock;                                                        /* Variable to store output clock frequency of the MCG module */
00182   uint8_t Divider;
00183 
00184   if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
00185     /* Output of FLL or PLL is selected */
00186     if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {
00187       /* FLL is selected */
00188       if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
00189         /* External reference clock is selected */
00190         MCGOUTClock = CPU_XTAL_CLK_HZ;                                       /* System oscillator drives MCG clock */
00191         Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
00192         MCGOUTClock = (MCGOUTClock / Divider);  /* Calculate the divided FLL reference clock */
00193         if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) {
00194           MCGOUTClock /= 32u;                                                  /* If high range is enabled, additional 32 divider is active */
00195         } /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */
00196       } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
00197         MCGOUTClock = CPU_INT_SLOW_CLK_HZ;                                     /* The slow internal reference clock is selected */
00198       } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
00199       /* Select correct multiplier to calculate the MCG output clock  */
00200       switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
00201         case 0x0u:
00202           MCGOUTClock *= 640u;
00203           break;
00204         case 0x20u:
00205           MCGOUTClock *= 1280u;
00206           break;
00207         case 0x40u:
00208           MCGOUTClock *= 1920u;
00209           break;
00210         case 0x60u:
00211           MCGOUTClock *= 2560u;
00212           break;
00213         case 0x80u:
00214           MCGOUTClock *= 732u;
00215           break;
00216         case 0xA0u:
00217           MCGOUTClock *= 1464u;
00218           break;
00219         case 0xC0u:
00220           MCGOUTClock *= 2197u;
00221           break;
00222         case 0xE0u:
00223           MCGOUTClock *= 2929u;
00224           break;
00225         default:
00226           break;
00227       }
00228     } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
00229       /* PLL is selected */
00230       Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
00231       MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider);                     /* Calculate the PLL reference clock */
00232       Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
00233       MCGOUTClock *= Divider;                       /* Calculate the MCG output clock */
00234     } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
00235   } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
00236     /* Internal reference clock is selected */
00237     if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
00238       MCGOUTClock = CPU_INT_SLOW_CLK_HZ;                                       /* Slow internal reference clock selected */
00239     } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
00240       MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));  /* Fast internal reference clock selected */
00241     } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
00242   } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
00243     /* External reference clock is selected */
00244     MCGOUTClock = CPU_XTAL_CLK_HZ;                                           /* System oscillator drives MCG clock */
00245   } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
00246     /* Reserved value */
00247     return;
00248   } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
00249   SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
00250 }