system_MK26F18.c

00001 /*
00002 ** ###################################################################
00003 **     Processors:          MK26FN2M0CAC18
00004 **                          MK26FN2M0VLQ18
00005 **                          MK26FN2M0VMD18
00006 **                          MK26FN2M0VMI18
00007 **
00008 **     Compilers:           Keil ARM C/C++ Compiler
00009 **                          Freescale C/C++ for Embedded ARM
00010 **                          GNU C Compiler
00011 **                          IAR ANSI C/C++ Compiler for ARM
00012 **                          MCUXpresso Compiler
00013 **
00014 **     Reference manual:    MK26P169M180SF5RM, Rev. 1, Mar 2015
00015 **     Version:             rev. 2.0, 2015-03-25
00016 **     Build:               b180801
00017 **
00018 **     Abstract:
00019 **         Provides a system configuration function and a global variable that
00020 **         contains the system frequency. It configures the device and initializes
00021 **         the oscillator (PLL) that is part of the microcontroller device.
00022 **
00023 **     Copyright 2016 Freescale Semiconductor, Inc.
00024 **     Copyright 2016-2018 NXP
00025 **
00026 **     SPDX-License-Identifier: BSD-3-Clause
00027 **
00028 **     http:                 www.nxp.com
00029 **     mail:                 support@nxp.com
00030 **
00031 **     Revisions:
00032 **     - rev. 1.0 (2014-12-04)
00033 **         Initial version.
00034 **     - rev. 1.1 (2015-02-19)
00035 **         Renamed interrupt vector LLW to LLWU.
00036 **     - rev. 2.0 (2015-03-25)
00037 **         Registers updated according to the reference manual revision 1, March 2015
00038 **
00039 ** ###################################################################
00040 */
00041 
00042 /*!
00043  * @file MK26F18
00044  * @version 2.0
00045  * @date 2015-03-25
00046  * @brief Device specific configuration file for MK26F18 (implementation file)
00047  *
00048  * Provides a system configuration function and a global variable that contains
00049  * the system frequency. It configures the device and initializes the oscillator
00050  * (PLL) that is part of the microcontroller device.
00051  */
00052 
00053 #include <stdint.h>
00054 #include "fsl_device_registers.h"
00055 
00056 
00057 
00058 /* ----------------------------------------------------------------------------
00059    -- Core clock
00060    ---------------------------------------------------------------------------- */
00061 
00062 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
00063 
00064 /* ----------------------------------------------------------------------------
00065    -- SystemInit()
00066    ---------------------------------------------------------------------------- */
00067 
00068 void SystemInit (void) {
00069 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
00070   SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2));    /* set CP10, CP11 Full Access */
00071 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
00072   /* Watchdog disable */
00073 #if (DISABLE_WDOG)
00074   /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
00075   WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
00076   /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
00077   WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
00078   /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
00079   WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
00080                  WDOG_STCTRLH_WAITEN_MASK |
00081                  WDOG_STCTRLH_STOPEN_MASK |
00082                  WDOG_STCTRLH_ALLOWUPDATE_MASK |
00083                  WDOG_STCTRLH_CLKSRC_MASK |
00084                  0x0100U;
00085 #endif /* (DISABLE_WDOG) */
00086 
00087   SystemInitHook();
00088 }
00089 
00090 /* ----------------------------------------------------------------------------
00091    -- SystemCoreClockUpdate()
00092    ---------------------------------------------------------------------------- */
00093 
00094 void SystemCoreClockUpdate (void) {
00095   uint32_t MCGOUTClock;                                                        /* Variable to store output clock frequency of the MCG module */
00096   uint16_t Divider;
00097 
00098   if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
00099     /* Output of FLL or PLL is selected */
00100     if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
00101       /* FLL is selected */
00102       if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
00103         /* External reference clock is selected */
00104         switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
00105         case 0x00U:
00106           MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
00107           break;
00108         case 0x01U:
00109           MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
00110           break;
00111         case 0x02U:
00112         default:
00113           MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
00114           break;
00115         }
00116         if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
00117           switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
00118           case 0x38U:
00119             Divider = 1536U;
00120             break;
00121           case 0x30U:
00122             Divider = 1280U;
00123             break;
00124           default:
00125             Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
00126             break;
00127           }
00128         } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
00129           Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
00130         }
00131         MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
00132       } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
00133         MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
00134       } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
00135       /* Select correct multiplier to calculate the MCG output clock  */
00136       switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
00137         case 0x00U:
00138           MCGOUTClock *= 640U;
00139           break;
00140         case 0x20U:
00141           MCGOUTClock *= 1280U;
00142           break;
00143         case 0x40U:
00144           MCGOUTClock *= 1920U;
00145           break;
00146         case 0x60U:
00147           MCGOUTClock *= 2560U;
00148           break;
00149         case 0x80U:
00150           MCGOUTClock *= 732U;
00151           break;
00152         case 0xA0U:
00153           MCGOUTClock *= 1464U;
00154           break;
00155         case 0xC0U:
00156           MCGOUTClock *= 2197U;
00157           break;
00158         case 0xE0U:
00159           MCGOUTClock *= 2929U;
00160           break;
00161         default:
00162           break;
00163       }
00164     } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
00165       if ((MCG->C11 & MCG_C11_PLLCS_MASK) == 0x00U) {
00166         /* PLL is selected */
00167         Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV_MASK) + 0x01U);
00168         MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
00169         Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV_MASK) + 16U);
00170         MCGOUTClock *= Divider;        /* Calculate the VCO output clock */
00171         MCGOUTClock /= 2;              /* Calculate the MCG output clock */
00172       } else {
00173         /* External PLL is selected */
00174         if ((USBPHY->ANACTRL & USBPHY_ANACTRL_PFD_CLK_SEL_MASK) == 0x00U) {
00175           MCGOUTClock = CPU_XTAL_CLK_HZ;
00176         } else {
00177           Divider = (((uint16_t)USBPHY->ANACTRL & USBPHY_ANACTRL_PFD_FRAC_MASK) >> 4);
00178           if ((USBPHY->ANACTRL & USBPHY_ANACTRL_PFD_CLK_SEL_MASK) == USBPHY_ANACTRL_PFD_CLK_SEL(1)) {
00179             Divider *= 0x04U;
00180           } else if ((USBPHY->ANACTRL & USBPHY_ANACTRL_PFD_CLK_SEL_MASK) == USBPHY_ANACTRL_PFD_CLK_SEL(2)) {
00181             Divider *= 0x02U;
00182           }
00183           MCGOUTClock = (uint32_t)(480000000 / Divider);
00184           MCGOUTClock *= 18;
00185         }
00186       }
00187     } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
00188   } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
00189     /* Internal reference clock is selected */
00190     if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
00191       MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
00192     } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
00193       Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
00194       MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
00195     } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
00196   } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
00197     /* External reference clock is selected */
00198     switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
00199     case 0x00U:
00200       MCGOUTClock = CPU_XTAL_CLK_HZ;   /* System oscillator drives MCG clock */
00201       break;
00202     case 0x01U:
00203       MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
00204       break;
00205     case 0x02U:
00206     default:
00207       MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
00208       break;
00209     }
00210   } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
00211     /* Reserved value */
00212     return;
00213   } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
00214   SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
00215 }
00216 
00217 /* ----------------------------------------------------------------------------
00218    -- SystemInitHook()
00219    ---------------------------------------------------------------------------- */
00220 
00221 __attribute__ ((weak)) void SystemInitHook (void) {
00222   /* Void implementation of the weak function. */
00223 }