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stm32f1xx_hal_rcc_ex.h
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f1xx_hal_rcc_ex.h 00004 * @author MCD Application Team 00005 * @version V1.0.4 00006 * @date 29-April-2016 00007 * @brief Header file of RCC HAL Extension module. 00008 ****************************************************************************** 00009 * @attention 00010 * 00011 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> 00012 * 00013 * Redistribution and use in source and binary forms, with or without modification, 00014 * are permitted provided that the following conditions are met: 00015 * 1. Redistributions of source code must retain the above copyright notice, 00016 * this list of conditions and the following disclaimer. 00017 * 2. Redistributions in binary form must reproduce the above copyright notice, 00018 * this list of conditions and the following disclaimer in the documentation 00019 * and/or other materials provided with the distribution. 00020 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00021 * may be used to endorse or promote products derived from this software 00022 * without specific prior written permission. 00023 * 00024 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00025 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00026 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00027 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00028 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00029 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00030 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00031 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00032 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00033 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00034 * 00035 ****************************************************************************** 00036 */ 00037 00038 /* Define to prevent recursive inclusion -------------------------------------*/ 00039 #ifndef __STM32F1xx_HAL_RCC_EX_H 00040 #define __STM32F1xx_HAL_RCC_EX_H 00041 00042 #ifdef __cplusplus 00043 extern "C" { 00044 #endif 00045 00046 /* Includes ------------------------------------------------------------------*/ 00047 #include "stm32f1xx_hal_def.h" 00048 00049 /** @addtogroup STM32F1xx_HAL_Driver 00050 * @{ 00051 */ 00052 00053 /** @addtogroup RCCEx 00054 * @{ 00055 */ 00056 00057 /** @addtogroup RCCEx_Private_Constants 00058 * @{ 00059 */ 00060 00061 #if defined(STM32F105xC) || defined(STM32F107xC) 00062 00063 /* Alias word address of PLLI2SON bit */ 00064 #define PLLI2SON_BITNUMBER POSITION_VAL(RCC_CR_PLL3ON) 00065 #define RCC_CR_PLLI2SON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (PLLI2SON_BITNUMBER * 4))) 00066 /* Alias word address of PLL2ON bit */ 00067 #define PLL2ON_BITNUMBER POSITION_VAL(RCC_CR_PLL2ON) 00068 #define RCC_CR_PLL2ON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (PLL2ON_BITNUMBER * 4))) 00069 00070 #define PLLI2S_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ 00071 #define PLL2_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ 00072 00073 #endif /* STM32F105xC || STM32F107xC */ 00074 00075 00076 #define CR_REG_INDEX ((uint8_t)1) 00077 00078 /** 00079 * @} 00080 */ 00081 00082 /** @addtogroup RCCEx_Private_Macros 00083 * @{ 00084 */ 00085 00086 #if defined(STM32F105xC) || defined(STM32F107xC) 00087 #define IS_RCC_PREDIV1_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_PREDIV1_SOURCE_HSE) || \ 00088 ((__SOURCE__) == RCC_PREDIV1_SOURCE_PLL2)) 00089 #endif /* STM32F105xC || STM32F107xC */ 00090 00091 #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ 00092 || defined(STM32F100xE) 00093 #define IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1) || ((__DIV__) == RCC_HSE_PREDIV_DIV2) || \ 00094 ((__DIV__) == RCC_HSE_PREDIV_DIV3) || ((__DIV__) == RCC_HSE_PREDIV_DIV4) || \ 00095 ((__DIV__) == RCC_HSE_PREDIV_DIV5) || ((__DIV__) == RCC_HSE_PREDIV_DIV6) || \ 00096 ((__DIV__) == RCC_HSE_PREDIV_DIV7) || ((__DIV__) == RCC_HSE_PREDIV_DIV8) || \ 00097 ((__DIV__) == RCC_HSE_PREDIV_DIV9) || ((__DIV__) == RCC_HSE_PREDIV_DIV10) || \ 00098 ((__DIV__) == RCC_HSE_PREDIV_DIV11) || ((__DIV__) == RCC_HSE_PREDIV_DIV12) || \ 00099 ((__DIV__) == RCC_HSE_PREDIV_DIV13) || ((__DIV__) == RCC_HSE_PREDIV_DIV14) || \ 00100 ((__DIV__) == RCC_HSE_PREDIV_DIV15) || ((__DIV__) == RCC_HSE_PREDIV_DIV16)) 00101 00102 #else 00103 #define IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1) || ((__DIV__) == RCC_HSE_PREDIV_DIV2)) 00104 #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ 00105 00106 #if defined(STM32F105xC) || defined(STM32F107xC) 00107 #define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \ 00108 ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \ 00109 ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \ 00110 ((__MUL__) == RCC_PLL_MUL6_5)) 00111 00112 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \ 00113 || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \ 00114 || ((__SOURCE__) == RCC_MCO1SOURCE_PLL2CLK) || ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK) \ 00115 || ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK_DIV2) || ((__SOURCE__) == RCC_MCO1SOURCE_EXT_HSE) \ 00116 || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK)) 00117 00118 #else 00119 #define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2) || ((__MUL__) == RCC_PLL_MUL3) || \ 00120 ((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \ 00121 ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \ 00122 ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \ 00123 ((__MUL__) == RCC_PLL_MUL10) || ((__MUL__) == RCC_PLL_MUL11) || \ 00124 ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL13) || \ 00125 ((__MUL__) == RCC_PLL_MUL14) || ((__MUL__) == RCC_PLL_MUL15) || \ 00126 ((__MUL__) == RCC_PLL_MUL16)) 00127 00128 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \ 00129 || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \ 00130 || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK)) 00131 00132 #endif /* STM32F105xC || STM32F107xC*/ 00133 00134 #define IS_RCC_ADCPLLCLK_DIV(__ADCCLK__) (((__ADCCLK__) == RCC_ADCPCLK2_DIV2) || ((__ADCCLK__) == RCC_ADCPCLK2_DIV4) || \ 00135 ((__ADCCLK__) == RCC_ADCPCLK2_DIV6) || ((__ADCCLK__) == RCC_ADCPCLK2_DIV8)) 00136 00137 #if defined(STM32F105xC) || defined(STM32F107xC) 00138 #define IS_RCC_I2S2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK) || ((__SOURCE__) == RCC_I2S2CLKSOURCE_PLLI2S_VCO)) 00139 00140 #define IS_RCC_I2S3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK) || ((__SOURCE__) == RCC_I2S3CLKSOURCE_PLLI2S_VCO)) 00141 00142 #define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV2) || ((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV3)) 00143 00144 #define IS_RCC_PLLI2S_MUL(__MUL__) (((__MUL__) == RCC_PLLI2S_MUL8) || ((__MUL__) == RCC_PLLI2S_MUL9) || \ 00145 ((__MUL__) == RCC_PLLI2S_MUL10) || ((__MUL__) == RCC_PLLI2S_MUL11) || \ 00146 ((__MUL__) == RCC_PLLI2S_MUL12) || ((__MUL__) == RCC_PLLI2S_MUL13) || \ 00147 ((__MUL__) == RCC_PLLI2S_MUL14) || ((__MUL__) == RCC_PLLI2S_MUL16) || \ 00148 ((__MUL__) == RCC_PLLI2S_MUL20)) 00149 00150 #define IS_RCC_HSE_PREDIV2(__DIV__) (((__DIV__) == RCC_HSE_PREDIV2_DIV1) || ((__DIV__) == RCC_HSE_PREDIV2_DIV2) || \ 00151 ((__DIV__) == RCC_HSE_PREDIV2_DIV3) || ((__DIV__) == RCC_HSE_PREDIV2_DIV4) || \ 00152 ((__DIV__) == RCC_HSE_PREDIV2_DIV5) || ((__DIV__) == RCC_HSE_PREDIV2_DIV6) || \ 00153 ((__DIV__) == RCC_HSE_PREDIV2_DIV7) || ((__DIV__) == RCC_HSE_PREDIV2_DIV8) || \ 00154 ((__DIV__) == RCC_HSE_PREDIV2_DIV9) || ((__DIV__) == RCC_HSE_PREDIV2_DIV10) || \ 00155 ((__DIV__) == RCC_HSE_PREDIV2_DIV11) || ((__DIV__) == RCC_HSE_PREDIV2_DIV12) || \ 00156 ((__DIV__) == RCC_HSE_PREDIV2_DIV13) || ((__DIV__) == RCC_HSE_PREDIV2_DIV14) || \ 00157 ((__DIV__) == RCC_HSE_PREDIV2_DIV15) || ((__DIV__) == RCC_HSE_PREDIV2_DIV16)) 00158 00159 #define IS_RCC_PLL2(__PLL__) (((__PLL__) == RCC_PLL2_NONE) || ((__PLL__) == RCC_PLL2_OFF) || \ 00160 ((__PLL__) == RCC_PLL2_ON)) 00161 00162 #define IS_RCC_PLL2_MUL(__MUL__) (((__MUL__) == RCC_PLL2_MUL8) || ((__MUL__) == RCC_PLL2_MUL9) || \ 00163 ((__MUL__) == RCC_PLL2_MUL10) || ((__MUL__) == RCC_PLL2_MUL11) || \ 00164 ((__MUL__) == RCC_PLL2_MUL12) || ((__MUL__) == RCC_PLL2_MUL13) || \ 00165 ((__MUL__) == RCC_PLL2_MUL14) || ((__MUL__) == RCC_PLL2_MUL16) || \ 00166 ((__MUL__) == RCC_PLL2_MUL20)) 00167 00168 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 00169 ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 00170 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 00171 (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \ 00172 (((__SELECTION__) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) || \ 00173 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)) 00174 00175 #elif defined(STM32F103xE) || defined(STM32F103xG) 00176 00177 #define IS_RCC_I2S2CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK) 00178 00179 #define IS_RCC_I2S3CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK) 00180 00181 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 00182 ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 00183 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 00184 (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \ 00185 (((__SELECTION__) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) || \ 00186 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)) 00187 00188 00189 #elif defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ 00190 || defined(STM32F103xB) 00191 00192 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 00193 ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 00194 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 00195 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)) 00196 00197 #else 00198 00199 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 00200 ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 00201 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)) 00202 00203 #endif /* STM32F105xC || STM32F107xC */ 00204 00205 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ 00206 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) 00207 00208 #define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBCLKSOURCE_PLL) || ((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV1_5)) 00209 00210 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ 00211 00212 /** 00213 * @} 00214 */ 00215 00216 /* Exported types ------------------------------------------------------------*/ 00217 00218 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types 00219 * @{ 00220 */ 00221 00222 #if defined(STM32F105xC) || defined(STM32F107xC) 00223 /** 00224 * @brief RCC PLL2 configuration structure definition 00225 */ 00226 typedef struct 00227 { 00228 uint32_t PLL2State; /*!< The new state of the PLL2. 00229 This parameter can be a value of @ref RCCEx_PLL2_Config */ 00230 00231 uint32_t PLL2MUL; /*!< PLL2MUL: Multiplication factor for PLL2 VCO input clock 00232 This parameter must be a value of @ref RCCEx_PLL2_Multiplication_Factor*/ 00233 00234 #if defined(STM32F105xC) || defined(STM32F107xC) 00235 uint32_t HSEPrediv2Value; /*!< The Prediv2 factor value. 00236 This parameter can be a value of @ref RCCEx_Prediv2_Factor */ 00237 00238 #endif /* STM32F105xC || STM32F107xC */ 00239 } RCC_PLL2InitTypeDef; 00240 00241 #endif /* STM32F105xC || STM32F107xC */ 00242 00243 /** 00244 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition 00245 */ 00246 typedef struct 00247 { 00248 uint32_t OscillatorType; /*!< The oscillators to be configured. 00249 This parameter can be a value of @ref RCC_Oscillator_Type */ 00250 00251 #if defined(STM32F105xC) || defined(STM32F107xC) 00252 uint32_t Prediv1Source; /*!< The Prediv1 source value. 00253 This parameter can be a value of @ref RCCEx_Prediv1_Source */ 00254 #endif /* STM32F105xC || STM32F107xC */ 00255 00256 uint32_t HSEState; /*!< The new state of the HSE. 00257 This parameter can be a value of @ref RCC_HSE_Config */ 00258 00259 uint32_t HSEPredivValue; /*!< The Prediv1 factor value (named PREDIV1 or PLLXTPRE in RM) 00260 This parameter can be a value of @ref RCCEx_Prediv1_Factor */ 00261 00262 uint32_t LSEState; /*!< The new state of the LSE. 00263 This parameter can be a value of @ref RCC_LSE_Config */ 00264 00265 uint32_t HSIState; /*!< The new state of the HSI. 00266 This parameter can be a value of @ref RCC_HSI_Config */ 00267 00268 uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). 00269 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ 00270 00271 uint32_t LSIState; /*!< The new state of the LSI. 00272 This parameter can be a value of @ref RCC_LSI_Config */ 00273 00274 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ 00275 00276 #if defined(STM32F105xC) || defined(STM32F107xC) 00277 RCC_PLL2InitTypeDef PLL2; /*!< PLL2 structure parameters */ 00278 #endif /* STM32F105xC || STM32F107xC */ 00279 } RCC_OscInitTypeDef; 00280 00281 #if defined(STM32F105xC) || defined(STM32F107xC) 00282 /** 00283 * @brief RCC PLLI2S configuration structure definition 00284 */ 00285 typedef struct 00286 { 00287 uint32_t PLLI2SMUL; /*!< PLLI2SMUL: Multiplication factor for PLLI2S VCO input clock 00288 This parameter must be a value of @ref RCCEx_PLLI2S_Multiplication_Factor*/ 00289 00290 #if defined(STM32F105xC) || defined(STM32F107xC) 00291 uint32_t HSEPrediv2Value; /*!< The Prediv2 factor value. 00292 This parameter can be a value of @ref RCCEx_Prediv2_Factor */ 00293 00294 #endif /* STM32F105xC || STM32F107xC */ 00295 } RCC_PLLI2SInitTypeDef; 00296 #endif /* STM32F105xC || STM32F107xC */ 00297 00298 /** 00299 * @brief RCC extended clocks structure definition 00300 */ 00301 typedef struct 00302 { 00303 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 00304 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 00305 00306 uint32_t RTCClockSelection; /*!< specifies the RTC clock source. 00307 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 00308 00309 uint32_t AdcClockSelection; /*!< ADC clock source 00310 This parameter can be a value of @ref RCCEx_ADC_Prescaler */ 00311 00312 #if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ 00313 || defined(STM32F107xC) 00314 uint32_t I2s2ClockSelection; /*!< I2S2 clock source 00315 This parameter can be a value of @ref RCCEx_I2S2_Clock_Source */ 00316 00317 uint32_t I2s3ClockSelection; /*!< I2S3 clock source 00318 This parameter can be a value of @ref RCCEx_I2S3_Clock_Source */ 00319 00320 #if defined(STM32F105xC) || defined(STM32F107xC) 00321 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters 00322 This parameter will be used only when PLLI2S is selected as Clock Source I2S2 or I2S3 */ 00323 00324 #endif /* STM32F105xC || STM32F107xC */ 00325 #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ 00326 00327 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ 00328 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ 00329 || defined(STM32F105xC) || defined(STM32F107xC) 00330 uint32_t UsbClockSelection; /*!< USB clock source 00331 This parameter can be a value of @ref RCCEx_USB_Prescaler */ 00332 00333 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ 00334 } RCC_PeriphCLKInitTypeDef; 00335 00336 /** 00337 * @} 00338 */ 00339 00340 /* Exported constants --------------------------------------------------------*/ 00341 00342 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants 00343 * @{ 00344 */ 00345 00346 /** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection 00347 * @{ 00348 */ 00349 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000001) 00350 #define RCC_PERIPHCLK_ADC ((uint32_t)0x00000002) 00351 #if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ 00352 || defined(STM32F107xC) 00353 #define RCC_PERIPHCLK_I2S2 ((uint32_t)0x00000004) 00354 #define RCC_PERIPHCLK_I2S3 ((uint32_t)0x00000008) 00355 #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ 00356 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ 00357 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ 00358 || defined(STM32F105xC) || defined(STM32F107xC) 00359 #define RCC_PERIPHCLK_USB ((uint32_t)0x00000010) 00360 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ 00361 00362 /** 00363 * @} 00364 */ 00365 00366 /** @defgroup RCCEx_ADC_Prescaler ADC Prescaler 00367 * @{ 00368 */ 00369 #define RCC_ADCPCLK2_DIV2 RCC_CFGR_ADCPRE_DIV2 00370 #define RCC_ADCPCLK2_DIV4 RCC_CFGR_ADCPRE_DIV4 00371 #define RCC_ADCPCLK2_DIV6 RCC_CFGR_ADCPRE_DIV6 00372 #define RCC_ADCPCLK2_DIV8 RCC_CFGR_ADCPRE_DIV8 00373 00374 /** 00375 * @} 00376 */ 00377 00378 #if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ 00379 || defined(STM32F107xC) 00380 /** @defgroup RCCEx_I2S2_Clock_Source I2S2 Clock Source 00381 * @{ 00382 */ 00383 #define RCC_I2S2CLKSOURCE_SYSCLK ((uint32_t)0x00000000) 00384 #if defined(STM32F105xC) || defined(STM32F107xC) 00385 #define RCC_I2S2CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S2SRC 00386 #endif /* STM32F105xC || STM32F107xC */ 00387 00388 /** 00389 * @} 00390 */ 00391 00392 /** @defgroup RCCEx_I2S3_Clock_Source I2S3 Clock Source 00393 * @{ 00394 */ 00395 #define RCC_I2S3CLKSOURCE_SYSCLK ((uint32_t)0x00000000) 00396 #if defined(STM32F105xC) || defined(STM32F107xC) 00397 #define RCC_I2S3CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S3SRC 00398 #endif /* STM32F105xC || STM32F107xC */ 00399 00400 /** 00401 * @} 00402 */ 00403 00404 #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ 00405 00406 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ 00407 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) 00408 00409 /** @defgroup RCCEx_USB_Prescaler USB Prescaler 00410 * @{ 00411 */ 00412 #define RCC_USBCLKSOURCE_PLL RCC_CFGR_USBPRE 00413 #define RCC_USBCLKSOURCE_PLL_DIV1_5 ((uint32_t)0x00000000) 00414 00415 /** 00416 * @} 00417 */ 00418 00419 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ 00420 00421 00422 #if defined(STM32F105xC) || defined(STM32F107xC) 00423 /** @defgroup RCCEx_USB_Prescaler USB Prescaler 00424 * @{ 00425 */ 00426 #define RCC_USBCLKSOURCE_PLL_DIV2 RCC_CFGR_OTGFSPRE 00427 #define RCC_USBCLKSOURCE_PLL_DIV3 ((uint32_t)0x00000000) 00428 00429 /** 00430 * @} 00431 */ 00432 00433 /** @defgroup RCCEx_PLLI2S_Multiplication_Factor PLLI2S Multiplication Factor 00434 * @{ 00435 */ 00436 00437 #define RCC_PLLI2S_MUL8 RCC_CFGR2_PLL3MUL8 /*!< PLLI2S input clock * 8 */ 00438 #define RCC_PLLI2S_MUL9 RCC_CFGR2_PLL3MUL9 /*!< PLLI2S input clock * 9 */ 00439 #define RCC_PLLI2S_MUL10 RCC_CFGR2_PLL3MUL10 /*!< PLLI2S input clock * 10 */ 00440 #define RCC_PLLI2S_MUL11 RCC_CFGR2_PLL3MUL11 /*!< PLLI2S input clock * 11 */ 00441 #define RCC_PLLI2S_MUL12 RCC_CFGR2_PLL3MUL12 /*!< PLLI2S input clock * 12 */ 00442 #define RCC_PLLI2S_MUL13 RCC_CFGR2_PLL3MUL13 /*!< PLLI2S input clock * 13 */ 00443 #define RCC_PLLI2S_MUL14 RCC_CFGR2_PLL3MUL14 /*!< PLLI2S input clock * 14 */ 00444 #define RCC_PLLI2S_MUL16 RCC_CFGR2_PLL3MUL16 /*!< PLLI2S input clock * 16 */ 00445 #define RCC_PLLI2S_MUL20 RCC_CFGR2_PLL3MUL20 /*!< PLLI2S input clock * 20 */ 00446 00447 /** 00448 * @} 00449 */ 00450 #endif /* STM32F105xC || STM32F107xC */ 00451 00452 #if defined(STM32F105xC) || defined(STM32F107xC) 00453 /** @defgroup RCCEx_Prediv1_Source Prediv1 Source 00454 * @{ 00455 */ 00456 00457 #define RCC_PREDIV1_SOURCE_HSE RCC_CFGR2_PREDIV1SRC_HSE 00458 #define RCC_PREDIV1_SOURCE_PLL2 RCC_CFGR2_PREDIV1SRC_PLL2 00459 00460 /** 00461 * @} 00462 */ 00463 #endif /* STM32F105xC || STM32F107xC */ 00464 00465 /** @defgroup RCCEx_Prediv1_Factor HSE Prediv1 Factor 00466 * @{ 00467 */ 00468 00469 #define RCC_HSE_PREDIV_DIV1 ((uint32_t)0x00000000) 00470 00471 #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ 00472 || defined(STM32F100xE) 00473 #define RCC_HSE_PREDIV_DIV2 RCC_CFGR2_PREDIV1_DIV2 00474 #define RCC_HSE_PREDIV_DIV3 RCC_CFGR2_PREDIV1_DIV3 00475 #define RCC_HSE_PREDIV_DIV4 RCC_CFGR2_PREDIV1_DIV4 00476 #define RCC_HSE_PREDIV_DIV5 RCC_CFGR2_PREDIV1_DIV5 00477 #define RCC_HSE_PREDIV_DIV6 RCC_CFGR2_PREDIV1_DIV6 00478 #define RCC_HSE_PREDIV_DIV7 RCC_CFGR2_PREDIV1_DIV7 00479 #define RCC_HSE_PREDIV_DIV8 RCC_CFGR2_PREDIV1_DIV8 00480 #define RCC_HSE_PREDIV_DIV9 RCC_CFGR2_PREDIV1_DIV9 00481 #define RCC_HSE_PREDIV_DIV10 RCC_CFGR2_PREDIV1_DIV10 00482 #define RCC_HSE_PREDIV_DIV11 RCC_CFGR2_PREDIV1_DIV11 00483 #define RCC_HSE_PREDIV_DIV12 RCC_CFGR2_PREDIV1_DIV12 00484 #define RCC_HSE_PREDIV_DIV13 RCC_CFGR2_PREDIV1_DIV13 00485 #define RCC_HSE_PREDIV_DIV14 RCC_CFGR2_PREDIV1_DIV14 00486 #define RCC_HSE_PREDIV_DIV15 RCC_CFGR2_PREDIV1_DIV15 00487 #define RCC_HSE_PREDIV_DIV16 RCC_CFGR2_PREDIV1_DIV16 00488 #else 00489 #define RCC_HSE_PREDIV_DIV2 RCC_CFGR_PLLXTPRE 00490 #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ 00491 00492 /** 00493 * @} 00494 */ 00495 00496 #if defined(STM32F105xC) || defined(STM32F107xC) 00497 /** @defgroup RCCEx_Prediv2_Factor HSE Prediv2 Factor 00498 * @{ 00499 */ 00500 00501 #define RCC_HSE_PREDIV2_DIV1 RCC_CFGR2_PREDIV2_DIV1 /*!< PREDIV2 input clock not divided */ 00502 #define RCC_HSE_PREDIV2_DIV2 RCC_CFGR2_PREDIV2_DIV2 /*!< PREDIV2 input clock divided by 2 */ 00503 #define RCC_HSE_PREDIV2_DIV3 RCC_CFGR2_PREDIV2_DIV3 /*!< PREDIV2 input clock divided by 3 */ 00504 #define RCC_HSE_PREDIV2_DIV4 RCC_CFGR2_PREDIV2_DIV4 /*!< PREDIV2 input clock divided by 4 */ 00505 #define RCC_HSE_PREDIV2_DIV5 RCC_CFGR2_PREDIV2_DIV5 /*!< PREDIV2 input clock divided by 5 */ 00506 #define RCC_HSE_PREDIV2_DIV6 RCC_CFGR2_PREDIV2_DIV6 /*!< PREDIV2 input clock divided by 6 */ 00507 #define RCC_HSE_PREDIV2_DIV7 RCC_CFGR2_PREDIV2_DIV7 /*!< PREDIV2 input clock divided by 7 */ 00508 #define RCC_HSE_PREDIV2_DIV8 RCC_CFGR2_PREDIV2_DIV8 /*!< PREDIV2 input clock divided by 8 */ 00509 #define RCC_HSE_PREDIV2_DIV9 RCC_CFGR2_PREDIV2_DIV9 /*!< PREDIV2 input clock divided by 9 */ 00510 #define RCC_HSE_PREDIV2_DIV10 RCC_CFGR2_PREDIV2_DIV10 /*!< PREDIV2 input clock divided by 10 */ 00511 #define RCC_HSE_PREDIV2_DIV11 RCC_CFGR2_PREDIV2_DIV11 /*!< PREDIV2 input clock divided by 11 */ 00512 #define RCC_HSE_PREDIV2_DIV12 RCC_CFGR2_PREDIV2_DIV12 /*!< PREDIV2 input clock divided by 12 */ 00513 #define RCC_HSE_PREDIV2_DIV13 RCC_CFGR2_PREDIV2_DIV13 /*!< PREDIV2 input clock divided by 13 */ 00514 #define RCC_HSE_PREDIV2_DIV14 RCC_CFGR2_PREDIV2_DIV14 /*!< PREDIV2 input clock divided by 14 */ 00515 #define RCC_HSE_PREDIV2_DIV15 RCC_CFGR2_PREDIV2_DIV15 /*!< PREDIV2 input clock divided by 15 */ 00516 #define RCC_HSE_PREDIV2_DIV16 RCC_CFGR2_PREDIV2_DIV16 /*!< PREDIV2 input clock divided by 16 */ 00517 00518 /** 00519 * @} 00520 */ 00521 00522 /** @defgroup RCCEx_PLL2_Config PLL Config 00523 * @{ 00524 */ 00525 #define RCC_PLL2_NONE ((uint32_t)0x00000000) 00526 #define RCC_PLL2_OFF ((uint32_t)0x00000001) 00527 #define RCC_PLL2_ON ((uint32_t)0x00000002) 00528 00529 /** 00530 * @} 00531 */ 00532 00533 /** @defgroup RCCEx_PLL2_Multiplication_Factor PLL2 Multiplication Factor 00534 * @{ 00535 */ 00536 00537 #define RCC_PLL2_MUL8 RCC_CFGR2_PLL2MUL8 /*!< PLL2 input clock * 8 */ 00538 #define RCC_PLL2_MUL9 RCC_CFGR2_PLL2MUL9 /*!< PLL2 input clock * 9 */ 00539 #define RCC_PLL2_MUL10 RCC_CFGR2_PLL2MUL10 /*!< PLL2 input clock * 10 */ 00540 #define RCC_PLL2_MUL11 RCC_CFGR2_PLL2MUL11 /*!< PLL2 input clock * 11 */ 00541 #define RCC_PLL2_MUL12 RCC_CFGR2_PLL2MUL12 /*!< PLL2 input clock * 12 */ 00542 #define RCC_PLL2_MUL13 RCC_CFGR2_PLL2MUL13 /*!< PLL2 input clock * 13 */ 00543 #define RCC_PLL2_MUL14 RCC_CFGR2_PLL2MUL14 /*!< PLL2 input clock * 14 */ 00544 #define RCC_PLL2_MUL16 RCC_CFGR2_PLL2MUL16 /*!< PLL2 input clock * 16 */ 00545 #define RCC_PLL2_MUL20 RCC_CFGR2_PLL2MUL20 /*!< PLL2 input clock * 20 */ 00546 00547 /** 00548 * @} 00549 */ 00550 00551 #endif /* STM32F105xC || STM32F107xC */ 00552 00553 /** @defgroup RCCEx_PLL_Multiplication_Factor PLL Multiplication Factor 00554 * @{ 00555 */ 00556 00557 #if defined(STM32F105xC) || defined(STM32F107xC) 00558 #else 00559 #define RCC_PLL_MUL2 RCC_CFGR_PLLMULL2 00560 #define RCC_PLL_MUL3 RCC_CFGR_PLLMULL3 00561 #endif /* STM32F105xC || STM32F107xC */ 00562 #define RCC_PLL_MUL4 RCC_CFGR_PLLMULL4 00563 #define RCC_PLL_MUL5 RCC_CFGR_PLLMULL5 00564 #define RCC_PLL_MUL6 RCC_CFGR_PLLMULL6 00565 #define RCC_PLL_MUL7 RCC_CFGR_PLLMULL7 00566 #define RCC_PLL_MUL8 RCC_CFGR_PLLMULL8 00567 #define RCC_PLL_MUL9 RCC_CFGR_PLLMULL9 00568 #if defined(STM32F105xC) || defined(STM32F107xC) 00569 #define RCC_PLL_MUL6_5 RCC_CFGR_PLLMULL6_5 00570 #else 00571 #define RCC_PLL_MUL10 RCC_CFGR_PLLMULL10 00572 #define RCC_PLL_MUL11 RCC_CFGR_PLLMULL11 00573 #define RCC_PLL_MUL12 RCC_CFGR_PLLMULL12 00574 #define RCC_PLL_MUL13 RCC_CFGR_PLLMULL13 00575 #define RCC_PLL_MUL14 RCC_CFGR_PLLMULL14 00576 #define RCC_PLL_MUL15 RCC_CFGR_PLLMULL15 00577 #define RCC_PLL_MUL16 RCC_CFGR_PLLMULL16 00578 #endif /* STM32F105xC || STM32F107xC */ 00579 00580 /** 00581 * @} 00582 */ 00583 00584 /** @defgroup RCCEx_MCO1_Clock_Source MCO1 Clock Source 00585 * @{ 00586 */ 00587 #define RCC_MCO1SOURCE_NOCLOCK ((uint32_t)RCC_CFGR_MCO_NOCLOCK) 00588 #define RCC_MCO1SOURCE_SYSCLK ((uint32_t)RCC_CFGR_MCO_SYSCLK) 00589 #define RCC_MCO1SOURCE_HSI ((uint32_t)RCC_CFGR_MCO_HSI) 00590 #define RCC_MCO1SOURCE_HSE ((uint32_t)RCC_CFGR_MCO_HSE) 00591 #define RCC_MCO1SOURCE_PLLCLK ((uint32_t)RCC_CFGR_MCO_PLLCLK_DIV2) 00592 #if defined(STM32F105xC) || defined(STM32F107xC) 00593 #define RCC_MCO1SOURCE_PLL2CLK ((uint32_t)RCC_CFGR_MCO_PLL2CLK) 00594 #define RCC_MCO1SOURCE_PLL3CLK_DIV2 ((uint32_t)RCC_CFGR_MCO_PLL3CLK_DIV2) 00595 #define RCC_MCO1SOURCE_EXT_HSE ((uint32_t)RCC_CFGR_MCO_EXT_HSE) 00596 #define RCC_MCO1SOURCE_PLL3CLK ((uint32_t)RCC_CFGR_MCO_PLL3CLK) 00597 #endif /* STM32F105xC || STM32F107xC*/ 00598 /** 00599 * @} 00600 */ 00601 00602 #if defined(STM32F105xC) || defined(STM32F107xC) 00603 /** @defgroup RCCEx_Interrupt RCCEx Interrupt 00604 * @{ 00605 */ 00606 #define RCC_IT_PLL2RDY ((uint8_t)RCC_CIR_PLL2RDYF) 00607 #define RCC_IT_PLLI2SRDY ((uint8_t)RCC_CIR_PLL3RDYF) 00608 /** 00609 * @} 00610 */ 00611 00612 /** @defgroup RCCEx_Flag RCCEx Flag 00613 * Elements values convention: 0XXYYYYYb 00614 * - YYYYY : Flag position in the register 00615 * - XX : Register index 00616 * - 01: CR register 00617 * @{ 00618 */ 00619 /* Flags in the CR register */ 00620 #define RCC_FLAG_PLL2RDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_PLL2RDY))) 00621 #define RCC_FLAG_PLLI2SRDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_PLL3RDY))) 00622 /** 00623 * @} 00624 */ 00625 #endif /* STM32F105xC || STM32F107xC*/ 00626 00627 /** 00628 * @} 00629 */ 00630 00631 /* Exported macro ------------------------------------------------------------*/ 00632 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros 00633 * @{ 00634 */ 00635 00636 /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable 00637 * @brief Enable or disable the AHB1 peripheral clock. 00638 * @note After reset, the peripheral clock (used for registers read/write access) 00639 * is disabled and the application software has to enable this clock before 00640 * using it. 00641 * @{ 00642 */ 00643 00644 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ 00645 || defined(STM32F103xG) || defined(STM32F105xC) || defined (STM32F107xC)\ 00646 || defined (STM32F100xE) 00647 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \ 00648 __IO uint32_t tmpreg; \ 00649 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ 00650 /* Delay after an RCC peripheral clock enabling */ \ 00651 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ 00652 UNUSED(tmpreg); \ 00653 } while(0) 00654 00655 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN)) 00656 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F105xC || STM32F107xC || STM32F100xE */ 00657 00658 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ 00659 || defined(STM32F103xG) || defined (STM32F100xE) 00660 #define __HAL_RCC_FSMC_CLK_ENABLE() do { \ 00661 __IO uint32_t tmpreg; \ 00662 SET_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\ 00663 /* Delay after an RCC peripheral clock enabling */ \ 00664 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\ 00665 UNUSED(tmpreg); \ 00666 } while(0) 00667 00668 #define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN)) 00669 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */ 00670 00671 #if defined(STM32F103xE) || defined(STM32F103xG) 00672 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \ 00673 __IO uint32_t tmpreg; \ 00674 SET_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\ 00675 /* Delay after an RCC peripheral clock enabling */ \ 00676 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\ 00677 UNUSED(tmpreg); \ 00678 } while(0) 00679 00680 00681 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SDIOEN)) 00682 #endif /* STM32F103xE || STM32F103xG */ 00683 00684 #if defined(STM32F105xC) || defined(STM32F107xC) 00685 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \ 00686 __IO uint32_t tmpreg; \ 00687 SET_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\ 00688 /* Delay after an RCC peripheral clock enabling */ \ 00689 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\ 00690 UNUSED(tmpreg); \ 00691 } while(0) 00692 00693 00694 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_OTGFSEN)) 00695 #endif /* STM32F105xC || STM32F107xC*/ 00696 00697 #if defined(STM32F107xC) 00698 #define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \ 00699 __IO uint32_t tmpreg; \ 00700 SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN);\ 00701 /* Delay after an RCC peripheral clock enabling */ \ 00702 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN);\ 00703 UNUSED(tmpreg); \ 00704 } while(0) 00705 00706 #define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \ 00707 __IO uint32_t tmpreg; \ 00708 SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN);\ 00709 /* Delay after an RCC peripheral clock enabling */ \ 00710 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN);\ 00711 UNUSED(tmpreg); \ 00712 } while(0) 00713 00714 #define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \ 00715 __IO uint32_t tmpreg; \ 00716 SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN);\ 00717 /* Delay after an RCC peripheral clock enabling */ \ 00718 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN);\ 00719 UNUSED(tmpreg); \ 00720 } while(0) 00721 00722 #define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACEN)) 00723 #define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACTXEN)) 00724 #define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACRXEN)) 00725 00726 /** 00727 * @brief Enable ETHERNET clock. 00728 */ 00729 #define __HAL_RCC_ETH_CLK_ENABLE() do { \ 00730 __HAL_RCC_ETHMAC_CLK_ENABLE(); \ 00731 __HAL_RCC_ETHMACTX_CLK_ENABLE(); \ 00732 __HAL_RCC_ETHMACRX_CLK_ENABLE(); \ 00733 } while(0) 00734 /** 00735 * @brief Disable ETHERNET clock. 00736 */ 00737 #define __HAL_RCC_ETH_CLK_DISABLE() do { \ 00738 __HAL_RCC_ETHMACTX_CLK_DISABLE(); \ 00739 __HAL_RCC_ETHMACRX_CLK_DISABLE(); \ 00740 __HAL_RCC_ETHMAC_CLK_DISABLE(); \ 00741 } while(0) 00742 00743 #endif /* STM32F107xC*/ 00744 00745 /** 00746 * @} 00747 */ 00748 00749 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status 00750 * @brief Get the enable or disable status of the AHB1 peripheral clock. 00751 * @note After reset, the peripheral clock (used for registers read/write access) 00752 * is disabled and the application software has to enable this clock before 00753 * using it. 00754 * @{ 00755 */ 00756 00757 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ 00758 || defined(STM32F103xG) || defined(STM32F105xC) || defined (STM32F107xC)\ 00759 || defined (STM32F100xE) 00760 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET) 00761 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET) 00762 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F105xC || STM32F107xC || STM32F100xE */ 00763 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ 00764 || defined(STM32F103xG) || defined (STM32F100xE) 00765 #define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) != RESET) 00766 #define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) == RESET) 00767 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */ 00768 #if defined(STM32F103xE) || defined(STM32F103xG) 00769 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) != RESET) 00770 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) == RESET) 00771 #endif /* STM32F103xE || STM32F103xG */ 00772 #if defined(STM32F105xC) || defined(STM32F107xC) 00773 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) != RESET) 00774 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) == RESET) 00775 #endif /* STM32F105xC || STM32F107xC*/ 00776 #if defined(STM32F107xC) 00777 #define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) != RESET) 00778 #define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) == RESET) 00779 #define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) != RESET) 00780 #define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) == RESET) 00781 #define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) != RESET) 00782 #define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) == RESET) 00783 #endif /* STM32F107xC*/ 00784 00785 /** 00786 * @} 00787 */ 00788 00789 /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Clock Enable Disable 00790 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. 00791 * @note After reset, the peripheral clock (used for registers read/write access) 00792 * is disabled and the application software has to enable this clock before 00793 * using it. 00794 * @{ 00795 */ 00796 00797 #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\ 00798 || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC) 00799 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \ 00800 __IO uint32_t tmpreg; \ 00801 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ 00802 /* Delay after an RCC peripheral clock enabling */ \ 00803 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ 00804 UNUSED(tmpreg); \ 00805 } while(0) 00806 00807 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) 00808 #endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ 00809 00810 #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\ 00811 || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\ 00812 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ 00813 || defined(STM32F105xC) || defined(STM32F107xC) 00814 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 00815 __IO uint32_t tmpreg; \ 00816 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 00817 /* Delay after an RCC peripheral clock enabling */ \ 00818 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 00819 UNUSED(tmpreg); \ 00820 } while(0) 00821 00822 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ 00823 __IO uint32_t tmpreg; \ 00824 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ 00825 /* Delay after an RCC peripheral clock enabling */ \ 00826 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ 00827 UNUSED(tmpreg); \ 00828 } while(0) 00829 00830 #define __HAL_RCC_USART3_CLK_ENABLE() do { \ 00831 __IO uint32_t tmpreg; \ 00832 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 00833 /* Delay after an RCC peripheral clock enabling */ \ 00834 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 00835 UNUSED(tmpreg); \ 00836 } while(0) 00837 00838 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ 00839 __IO uint32_t tmpreg; \ 00840 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ 00841 /* Delay after an RCC peripheral clock enabling */ \ 00842 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ 00843 UNUSED(tmpreg); \ 00844 } while(0) 00845 00846 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) 00847 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) 00848 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) 00849 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) 00850 #endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ 00851 00852 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ 00853 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) 00854 #define __HAL_RCC_USB_CLK_ENABLE() do { \ 00855 __IO uint32_t tmpreg; \ 00856 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ 00857 /* Delay after an RCC peripheral clock enabling */ \ 00858 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ 00859 UNUSED(tmpreg); \ 00860 } while(0) 00861 00862 #define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN)) 00863 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ 00864 00865 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ 00866 || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) 00867 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \ 00868 __IO uint32_t tmpreg; \ 00869 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ 00870 /* Delay after an RCC peripheral clock enabling */ \ 00871 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ 00872 UNUSED(tmpreg); \ 00873 } while(0) 00874 00875 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 00876 __IO uint32_t tmpreg; \ 00877 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 00878 /* Delay after an RCC peripheral clock enabling */ \ 00879 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 00880 UNUSED(tmpreg); \ 00881 } while(0) 00882 00883 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ 00884 __IO uint32_t tmpreg; \ 00885 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 00886 /* Delay after an RCC peripheral clock enabling */ \ 00887 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 00888 UNUSED(tmpreg); \ 00889 } while(0) 00890 00891 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 00892 __IO uint32_t tmpreg; \ 00893 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 00894 /* Delay after an RCC peripheral clock enabling */ \ 00895 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 00896 UNUSED(tmpreg); \ 00897 } while(0) 00898 00899 #define __HAL_RCC_UART4_CLK_ENABLE() do { \ 00900 __IO uint32_t tmpreg; \ 00901 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 00902 /* Delay after an RCC peripheral clock enabling */ \ 00903 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 00904 UNUSED(tmpreg); \ 00905 } while(0) 00906 00907 #define __HAL_RCC_UART5_CLK_ENABLE() do { \ 00908 __IO uint32_t tmpreg; \ 00909 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 00910 /* Delay after an RCC peripheral clock enabling */ \ 00911 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 00912 UNUSED(tmpreg); \ 00913 } while(0) 00914 00915 #define __HAL_RCC_DAC_CLK_ENABLE() do { \ 00916 __IO uint32_t tmpreg; \ 00917 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 00918 /* Delay after an RCC peripheral clock enabling */ \ 00919 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 00920 UNUSED(tmpreg); \ 00921 } while(0) 00922 00923 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) 00924 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) 00925 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) 00926 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) 00927 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) 00928 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) 00929 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) 00930 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */ 00931 00932 #if defined(STM32F100xB) || defined (STM32F100xE) 00933 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 00934 __IO uint32_t tmpreg; \ 00935 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 00936 /* Delay after an RCC peripheral clock enabling */ \ 00937 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 00938 UNUSED(tmpreg); \ 00939 } while(0) 00940 00941 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ 00942 __IO uint32_t tmpreg; \ 00943 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 00944 /* Delay after an RCC peripheral clock enabling */ \ 00945 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 00946 UNUSED(tmpreg); \ 00947 } while(0) 00948 00949 #define __HAL_RCC_DAC_CLK_ENABLE() do { \ 00950 __IO uint32_t tmpreg; \ 00951 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 00952 /* Delay after an RCC peripheral clock enabling */ \ 00953 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 00954 UNUSED(tmpreg); \ 00955 } while(0) 00956 00957 #define __HAL_RCC_CEC_CLK_ENABLE() do { \ 00958 __IO uint32_t tmpreg; \ 00959 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ 00960 /* Delay after an RCC peripheral clock enabling */ \ 00961 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ 00962 UNUSED(tmpreg); \ 00963 } while(0) 00964 00965 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) 00966 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) 00967 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) 00968 #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) 00969 #endif /* STM32F100xB || STM32F100xE */ 00970 00971 #ifdef STM32F100xE 00972 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \ 00973 __IO uint32_t tmpreg; \ 00974 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ 00975 /* Delay after an RCC peripheral clock enabling */ \ 00976 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ 00977 UNUSED(tmpreg); \ 00978 } while(0) 00979 00980 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \ 00981 __IO uint32_t tmpreg; \ 00982 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 00983 /* Delay after an RCC peripheral clock enabling */ \ 00984 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 00985 UNUSED(tmpreg); \ 00986 } while(0) 00987 00988 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \ 00989 __IO uint32_t tmpreg; \ 00990 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 00991 /* Delay after an RCC peripheral clock enabling */ \ 00992 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 00993 UNUSED(tmpreg); \ 00994 } while(0) 00995 00996 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ 00997 __IO uint32_t tmpreg; \ 00998 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 00999 /* Delay after an RCC peripheral clock enabling */ \ 01000 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 01001 UNUSED(tmpreg); \ 01002 } while(0) 01003 01004 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 01005 __IO uint32_t tmpreg; \ 01006 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 01007 /* Delay after an RCC peripheral clock enabling */ \ 01008 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 01009 UNUSED(tmpreg); \ 01010 } while(0) 01011 01012 #define __HAL_RCC_UART4_CLK_ENABLE() do { \ 01013 __IO uint32_t tmpreg; \ 01014 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 01015 /* Delay after an RCC peripheral clock enabling */ \ 01016 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 01017 UNUSED(tmpreg); \ 01018 } while(0) 01019 01020 #define __HAL_RCC_UART5_CLK_ENABLE() do { \ 01021 __IO uint32_t tmpreg; \ 01022 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 01023 /* Delay after an RCC peripheral clock enabling */ \ 01024 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 01025 UNUSED(tmpreg); \ 01026 } while(0) 01027 01028 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) 01029 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) 01030 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) 01031 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) 01032 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) 01033 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) 01034 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) 01035 #endif /* STM32F100xE */ 01036 01037 #if defined(STM32F105xC) || defined(STM32F107xC) 01038 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \ 01039 __IO uint32_t tmpreg; \ 01040 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ 01041 /* Delay after an RCC peripheral clock enabling */ \ 01042 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ 01043 UNUSED(tmpreg); \ 01044 } while(0) 01045 01046 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) 01047 #endif /* STM32F105xC || STM32F107xC */ 01048 01049 #if defined(STM32F101xG) || defined(STM32F103xG) 01050 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \ 01051 __IO uint32_t tmpreg; \ 01052 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 01053 /* Delay after an RCC peripheral clock enabling */ \ 01054 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 01055 UNUSED(tmpreg); \ 01056 } while(0) 01057 01058 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \ 01059 __IO uint32_t tmpreg; \ 01060 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 01061 /* Delay after an RCC peripheral clock enabling */ \ 01062 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 01063 UNUSED(tmpreg); \ 01064 } while(0) 01065 01066 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ 01067 __IO uint32_t tmpreg; \ 01068 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 01069 /* Delay after an RCC peripheral clock enabling */ \ 01070 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 01071 UNUSED(tmpreg); \ 01072 } while(0) 01073 01074 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) 01075 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) 01076 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) 01077 #endif /* STM32F101xG || STM32F103xG*/ 01078 01079 /** 01080 * @} 01081 */ 01082 01083 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status 01084 * @brief Get the enable or disable status of the APB1 peripheral clock. 01085 * @note After reset, the peripheral clock (used for registers read/write access) 01086 * is disabled and the application software has to enable this clock before 01087 * using it. 01088 * @{ 01089 */ 01090 01091 #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\ 01092 || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC) 01093 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) 01094 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) 01095 #endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ 01096 #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\ 01097 || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\ 01098 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ 01099 || defined(STM32F105xC) || defined(STM32F107xC) 01100 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) 01101 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) 01102 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET) 01103 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET) 01104 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) 01105 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) 01106 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET) 01107 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET) 01108 #endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ 01109 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ 01110 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) 01111 #define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET) 01112 #define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET) 01113 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ 01114 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ 01115 || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) 01116 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET) 01117 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET) 01118 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) 01119 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) 01120 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) 01121 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) 01122 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 01123 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 01124 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) 01125 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) 01126 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) 01127 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) 01128 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) 01129 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) 01130 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */ 01131 #if defined(STM32F100xB) || defined (STM32F100xE) 01132 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) 01133 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) 01134 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) 01135 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) 01136 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) 01137 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) 01138 #define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET) 01139 #define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET) 01140 #endif /* STM32F100xB || STM32F100xE */ 01141 #ifdef STM32F100xE 01142 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET) 01143 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET) 01144 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) 01145 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) 01146 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) 01147 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) 01148 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) 01149 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) 01150 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 01151 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 01152 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) 01153 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) 01154 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) 01155 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) 01156 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) 01157 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) 01158 #endif /* STM32F100xE */ 01159 #if defined(STM32F105xC) || defined(STM32F107xC) 01160 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) 01161 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) 01162 #endif /* STM32F105xC || STM32F107xC */ 01163 #if defined(STM32F101xG) || defined(STM32F103xG) 01164 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) 01165 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) 01166 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) 01167 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) 01168 #endif /* STM32F101xG || STM32F103xG*/ 01169 01170 /** 01171 * @} 01172 */ 01173 01174 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Clock Enable Disable 01175 * @brief Enable or disable the High Speed APB (APB2) peripheral clock. 01176 * @note After reset, the peripheral clock (used for registers read/write access) 01177 * is disabled and the application software has to enable this clock before 01178 * using it. 01179 * @{ 01180 */ 01181 01182 #if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\ 01183 || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\ 01184 || defined(STM32F103xG) 01185 #define __HAL_RCC_ADC2_CLK_ENABLE() do { \ 01186 __IO uint32_t tmpreg; \ 01187 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ 01188 /* Delay after an RCC peripheral clock enabling */ \ 01189 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ 01190 UNUSED(tmpreg); \ 01191 } while(0) 01192 01193 #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) 01194 #endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */ 01195 01196 #if defined(STM32F100xB) || defined(STM32F100xE) 01197 #define __HAL_RCC_TIM15_CLK_ENABLE() do { \ 01198 __IO uint32_t tmpreg; \ 01199 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ 01200 /* Delay after an RCC peripheral clock enabling */ \ 01201 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ 01202 UNUSED(tmpreg); \ 01203 } while(0) 01204 01205 #define __HAL_RCC_TIM16_CLK_ENABLE() do { \ 01206 __IO uint32_t tmpreg; \ 01207 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ 01208 /* Delay after an RCC peripheral clock enabling */ \ 01209 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ 01210 UNUSED(tmpreg); \ 01211 } while(0) 01212 01213 #define __HAL_RCC_TIM17_CLK_ENABLE() do { \ 01214 __IO uint32_t tmpreg; \ 01215 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ 01216 /* Delay after an RCC peripheral clock enabling */ \ 01217 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ 01218 UNUSED(tmpreg); \ 01219 } while(0) 01220 01221 #define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN)) 01222 #define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN)) 01223 #define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN)) 01224 #endif /* STM32F100xB || STM32F100xE */ 01225 01226 #if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\ 01227 || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\ 01228 || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ 01229 || defined(STM32F107xC) 01230 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 01231 __IO uint32_t tmpreg; \ 01232 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\ 01233 /* Delay after an RCC peripheral clock enabling */ \ 01234 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\ 01235 UNUSED(tmpreg); \ 01236 } while(0) 01237 01238 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPEEN)) 01239 #endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ 01240 01241 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ 01242 || defined(STM32F103xG) 01243 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 01244 __IO uint32_t tmpreg; \ 01245 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\ 01246 /* Delay after an RCC peripheral clock enabling */ \ 01247 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\ 01248 UNUSED(tmpreg); \ 01249 } while(0) 01250 01251 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ 01252 __IO uint32_t tmpreg; \ 01253 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\ 01254 /* Delay after an RCC peripheral clock enabling */ \ 01255 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\ 01256 UNUSED(tmpreg); \ 01257 } while(0) 01258 01259 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN)) 01260 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN)) 01261 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/ 01262 01263 #if defined(STM32F103xE) || defined(STM32F103xG) 01264 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ 01265 __IO uint32_t tmpreg; \ 01266 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 01267 /* Delay after an RCC peripheral clock enabling */ \ 01268 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 01269 UNUSED(tmpreg); \ 01270 } while(0) 01271 01272 #define __HAL_RCC_ADC3_CLK_ENABLE() do { \ 01273 __IO uint32_t tmpreg; \ 01274 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ 01275 /* Delay after an RCC peripheral clock enabling */ \ 01276 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ 01277 UNUSED(tmpreg); \ 01278 } while(0) 01279 01280 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) 01281 #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) 01282 #endif /* STM32F103xE || STM32F103xG */ 01283 01284 #if defined(STM32F100xE) 01285 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 01286 __IO uint32_t tmpreg; \ 01287 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\ 01288 /* Delay after an RCC peripheral clock enabling */ \ 01289 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\ 01290 UNUSED(tmpreg); \ 01291 } while(0) 01292 01293 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ 01294 __IO uint32_t tmpreg; \ 01295 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\ 01296 /* Delay after an RCC peripheral clock enabling */ \ 01297 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\ 01298 UNUSED(tmpreg); \ 01299 } while(0) 01300 01301 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN)) 01302 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN)) 01303 #endif /* STM32F100xE */ 01304 01305 #if defined(STM32F101xG) || defined(STM32F103xG) 01306 #define __HAL_RCC_TIM9_CLK_ENABLE() do { \ 01307 __IO uint32_t tmpreg; \ 01308 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ 01309 /* Delay after an RCC peripheral clock enabling */ \ 01310 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ 01311 UNUSED(tmpreg); \ 01312 } while(0) 01313 01314 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \ 01315 __IO uint32_t tmpreg; \ 01316 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 01317 /* Delay after an RCC peripheral clock enabling */ \ 01318 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 01319 UNUSED(tmpreg); \ 01320 } while(0) 01321 01322 #define __HAL_RCC_TIM11_CLK_ENABLE() do { \ 01323 __IO uint32_t tmpreg; \ 01324 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ 01325 /* Delay after an RCC peripheral clock enabling */ \ 01326 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ 01327 UNUSED(tmpreg); \ 01328 } while(0) 01329 01330 #define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN)) 01331 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) 01332 #define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN)) 01333 #endif /* STM32F101xG || STM32F103xG */ 01334 01335 /** 01336 * @} 01337 */ 01338 01339 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status 01340 * @brief Get the enable or disable status of the APB2 peripheral clock. 01341 * @note After reset, the peripheral clock (used for registers read/write access) 01342 * is disabled and the application software has to enable this clock before 01343 * using it. 01344 * @{ 01345 */ 01346 01347 #if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\ 01348 || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\ 01349 || defined(STM32F103xG) 01350 #define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) 01351 #define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) 01352 #endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */ 01353 #if defined(STM32F100xB) || defined(STM32F100xE) 01354 #define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET) 01355 #define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET) 01356 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET) 01357 #define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET) 01358 #define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET) 01359 #define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET) 01360 #endif /* STM32F100xB || STM32F100xE */ 01361 #if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\ 01362 || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\ 01363 || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ 01364 || defined(STM32F107xC) 01365 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) != RESET) 01366 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) == RESET) 01367 #endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ 01368 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ 01369 || defined(STM32F103xG) 01370 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET) 01371 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET) 01372 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET) 01373 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET) 01374 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/ 01375 #if defined(STM32F103xE) || defined(STM32F103xG) 01376 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) 01377 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) 01378 #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) 01379 #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET) 01380 #endif /* STM32F103xE || STM32F103xG */ 01381 #if defined(STM32F100xE) 01382 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET) 01383 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET) 01384 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET) 01385 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET) 01386 #endif /* STM32F100xE */ 01387 #if defined(STM32F101xG) || defined(STM32F103xG) 01388 #define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET) 01389 #define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET) 01390 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) 01391 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) 01392 #define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET) 01393 #define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET) 01394 #endif /* STM32F101xG || STM32F103xG */ 01395 01396 /** 01397 * @} 01398 */ 01399 01400 #if defined(STM32F105xC) || defined(STM32F107xC) 01401 /** @defgroup RCCEx_Peripheral_Clock_Force_Release Peripheral Clock Force Release 01402 * @brief Force or release AHB peripheral reset. 01403 * @{ 01404 */ 01405 #define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU) 01406 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_OTGFSRST)) 01407 #if defined(STM32F107xC) 01408 #define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ETHMACRST)) 01409 #endif /* STM32F107xC */ 01410 01411 #define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00) 01412 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_OTGFSRST)) 01413 #if defined(STM32F107xC) 01414 #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ETHMACRST)) 01415 #endif /* STM32F107xC */ 01416 01417 /** 01418 * @} 01419 */ 01420 #endif /* STM32F105xC || STM32F107xC */ 01421 01422 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 01423 * @brief Force or release APB1 peripheral reset. 01424 * @{ 01425 */ 01426 01427 #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\ 01428 || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC) 01429 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) 01430 01431 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) 01432 #endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ 01433 01434 #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\ 01435 || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\ 01436 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ 01437 || defined(STM32F105xC) || defined(STM32F107xC) 01438 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) 01439 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) 01440 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) 01441 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) 01442 01443 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) 01444 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) 01445 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) 01446 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) 01447 #endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ 01448 01449 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ 01450 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) 01451 #define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST)) 01452 #define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST)) 01453 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ 01454 01455 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ 01456 || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) 01457 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) 01458 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) 01459 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) 01460 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) 01461 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) 01462 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) 01463 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) 01464 01465 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) 01466 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) 01467 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) 01468 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) 01469 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) 01470 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) 01471 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) 01472 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */ 01473 01474 #if defined(STM32F100xB) || defined (STM32F100xE) 01475 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) 01476 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) 01477 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) 01478 #define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST)) 01479 01480 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) 01481 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) 01482 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) 01483 #define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST)) 01484 #endif /* STM32F100xB || STM32F100xE */ 01485 01486 #if defined (STM32F100xE) 01487 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) 01488 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) 01489 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) 01490 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) 01491 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) 01492 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) 01493 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) 01494 01495 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) 01496 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) 01497 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) 01498 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) 01499 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) 01500 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) 01501 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) 01502 #endif /* STM32F100xE */ 01503 01504 #if defined(STM32F105xC) || defined(STM32F107xC) 01505 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) 01506 01507 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) 01508 #endif /* STM32F105xC || STM32F107xC */ 01509 01510 #if defined(STM32F101xG) || defined(STM32F103xG) 01511 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) 01512 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) 01513 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) 01514 01515 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) 01516 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) 01517 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) 01518 #endif /* STM32F101xG || STM32F103xG */ 01519 01520 /** 01521 * @} 01522 */ 01523 01524 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 01525 * @brief Force or release APB2 peripheral reset. 01526 * @{ 01527 */ 01528 01529 #if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\ 01530 || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\ 01531 || defined(STM32F103xG) 01532 #define __HAL_RCC_ADC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC2RST)) 01533 01534 #define __HAL_RCC_ADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC2RST)) 01535 #endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */ 01536 01537 #if defined(STM32F100xB) || defined(STM32F100xE) 01538 #define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST)) 01539 #define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST)) 01540 #define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST)) 01541 01542 #define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST)) 01543 #define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST)) 01544 #define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST)) 01545 #endif /* STM32F100xB || STM32F100xE */ 01546 01547 #if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\ 01548 || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\ 01549 || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ 01550 || defined(STM32F107xC) 01551 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPERST)) 01552 01553 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPERST)) 01554 #endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ 01555 01556 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ 01557 || defined(STM32F103xG) 01558 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPFRST)) 01559 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPGRST)) 01560 01561 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST)) 01562 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST)) 01563 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/ 01564 01565 #if defined(STM32F103xE) || defined(STM32F103xG) 01566 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) 01567 #define __HAL_RCC_ADC3_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC3RST)) 01568 01569 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) 01570 #define __HAL_RCC_ADC3_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC3RST)) 01571 #endif /* STM32F103xE || STM32F103xG */ 01572 01573 #if defined(STM32F100xE) 01574 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPFRST)) 01575 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPGRST)) 01576 01577 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST)) 01578 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST)) 01579 #endif /* STM32F100xE */ 01580 01581 #if defined(STM32F101xG) || defined(STM32F103xG) 01582 #define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST)) 01583 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) 01584 #define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST)) 01585 01586 #define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST)) 01587 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) 01588 #define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST)) 01589 #endif /* STM32F101xG || STM32F103xG*/ 01590 01591 /** 01592 * @} 01593 */ 01594 01595 /** @defgroup RCCEx_HSE_Configuration HSE Configuration 01596 * @{ 01597 */ 01598 01599 #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ 01600 || defined(STM32F100xE) 01601 /** 01602 * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL. 01603 * @note Predivision factor can not be changed if PLL is used as system clock 01604 * In this case, you have to select another source of the system clock, disable the PLL and 01605 * then change the HSE predivision factor. 01606 * @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE. 01607 * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16. 01608 */ 01609 #define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1, (uint32_t)(__HSE_PREDIV_VALUE__)) 01610 #else 01611 /** 01612 * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL. 01613 * @note Predivision factor can not be changed if PLL is used as system clock 01614 * In this case, you have to select another source of the system clock, disable the PLL and 01615 * then change the HSE predivision factor. 01616 * @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE. 01617 * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV2. 01618 */ 01619 #define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) \ 01620 MODIFY_REG(RCC->CFGR,RCC_CFGR_PLLXTPRE, (uint32_t)(__HSE_PREDIV_VALUE__)) 01621 01622 #endif /* STM32F105xC || STM32F107xC */ 01623 01624 #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ 01625 || defined(STM32F100xE) 01626 /** 01627 * @brief Macro to get prediv1 factor for PLL. 01628 */ 01629 #define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1) 01630 01631 #else 01632 /** 01633 * @brief Macro to get prediv1 factor for PLL. 01634 */ 01635 #define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE) 01636 01637 #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ 01638 01639 /** 01640 * @} 01641 */ 01642 01643 #if defined(STM32F105xC) || defined(STM32F107xC) 01644 /** @defgroup RCCEx_PLLI2S_Configuration PLLI2S Configuration 01645 * @{ 01646 */ 01647 01648 /** @brief Macros to enable the main PLLI2S. 01649 * @note After enabling the main PLLI2S, the application software should wait on 01650 * PLLI2SRDY flag to be set indicating that PLLI2S clock is stable and can 01651 * be used as system clock source. 01652 * @note The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes. 01653 */ 01654 #define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE) 01655 01656 /** @brief Macros to disable the main PLLI2S. 01657 * @note The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes. 01658 */ 01659 #define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE) 01660 01661 /** @brief macros to configure the main PLLI2S multiplication factor. 01662 * @note This function must be used only when the main PLLI2S is disabled. 01663 * 01664 * @param __PLLI2SMUL__ specifies the multiplication factor for PLLI2S VCO output clock 01665 * This parameter can be one of the following values: 01666 * @arg @ref RCC_PLLI2S_MUL8 PLLI2SVCO = PLLI2S clock entry x 8 01667 * @arg @ref RCC_PLLI2S_MUL9 PLLI2SVCO = PLLI2S clock entry x 9 01668 * @arg @ref RCC_PLLI2S_MUL10 PLLI2SVCO = PLLI2S clock entry x 10 01669 * @arg @ref RCC_PLLI2S_MUL11 PLLI2SVCO = PLLI2S clock entry x 11 01670 * @arg @ref RCC_PLLI2S_MUL12 PLLI2SVCO = PLLI2S clock entry x 12 01671 * @arg @ref RCC_PLLI2S_MUL13 PLLI2SVCO = PLLI2S clock entry x 13 01672 * @arg @ref RCC_PLLI2S_MUL14 PLLI2SVCO = PLLI2S clock entry x 14 01673 * @arg @ref RCC_PLLI2S_MUL16 PLLI2SVCO = PLLI2S clock entry x 16 01674 * @arg @ref RCC_PLLI2S_MUL20 PLLI2SVCO = PLLI2S clock entry x 20 01675 * 01676 */ 01677 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SMUL__)\ 01678 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL3MUL,(__PLLI2SMUL__)) 01679 01680 /** 01681 * @} 01682 */ 01683 01684 #endif /* STM32F105xC || STM32F107xC */ 01685 01686 /** @defgroup RCCEx_Peripheral_Configuration Peripheral Configuration 01687 * @brief Macros to configure clock source of different peripherals. 01688 * @{ 01689 */ 01690 01691 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ 01692 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) 01693 /** @brief Macro to configure the USB clock. 01694 * @param __USBCLKSOURCE__ specifies the USB clock source. 01695 * This parameter can be one of the following values: 01696 * @arg @ref RCC_USBCLKSOURCE_PLL PLL clock divided by 1 selected as USB clock 01697 * @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL clock divided by 1.5 selected as USB clock 01698 */ 01699 #define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \ 01700 MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSOURCE__)) 01701 01702 /** @brief Macro to get the USB clock (USBCLK). 01703 * @retval The clock source can be one of the following values: 01704 * @arg @ref RCC_USBCLKSOURCE_PLL PLL clock divided by 1 selected as USB clock 01705 * @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL clock divided by 1.5 selected as USB clock 01706 */ 01707 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE))) 01708 01709 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ 01710 01711 #if defined(STM32F105xC) || defined(STM32F107xC) 01712 01713 /** @brief Macro to configure the USB OTSclock. 01714 * @param __USBCLKSOURCE__ specifies the USB clock source. 01715 * This parameter can be one of the following values: 01716 * @arg @ref RCC_USBCLKSOURCE_PLL_DIV2 PLL clock divided by 2 selected as USB OTG FS clock 01717 * @arg @ref RCC_USBCLKSOURCE_PLL_DIV3 PLL clock divided by 3 selected as USB OTG FS clock 01718 */ 01719 #define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \ 01720 MODIFY_REG(RCC->CFGR, RCC_CFGR_OTGFSPRE, (uint32_t)(__USBCLKSOURCE__)) 01721 01722 /** @brief Macro to get the USB clock (USBCLK). 01723 * @retval The clock source can be one of the following values: 01724 * @arg @ref RCC_USBCLKSOURCE_PLL_DIV2 PLL clock divided by 2 selected as USB OTG FS clock 01725 * @arg @ref RCC_USBCLKSOURCE_PLL_DIV3 PLL clock divided by 3 selected as USB OTG FS clock 01726 */ 01727 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_OTGFSPRE))) 01728 01729 #endif /* STM32F105xC || STM32F107xC */ 01730 01731 /** @brief Macro to configure the ADCx clock (x=1 to 3 depending on devices). 01732 * @param __ADCCLKSOURCE__ specifies the ADC clock source. 01733 * This parameter can be one of the following values: 01734 * @arg @ref RCC_ADCPCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC clock 01735 * @arg @ref RCC_ADCPCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC clock 01736 * @arg @ref RCC_ADCPCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC clock 01737 * @arg @ref RCC_ADCPCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC clock 01738 */ 01739 #define __HAL_RCC_ADC_CONFIG(__ADCCLKSOURCE__) \ 01740 MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADCCLKSOURCE__)) 01741 01742 /** @brief Macro to get the ADC clock (ADCxCLK, x=1 to 3 depending on devices). 01743 * @retval The clock source can be one of the following values: 01744 * @arg @ref RCC_ADCPCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC clock 01745 * @arg @ref RCC_ADCPCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC clock 01746 * @arg @ref RCC_ADCPCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC clock 01747 * @arg @ref RCC_ADCPCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC clock 01748 */ 01749 #define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE))) 01750 01751 /** 01752 * @} 01753 */ 01754 01755 #if defined(STM32F105xC) || defined(STM32F107xC) 01756 01757 /** @addtogroup RCCEx_HSE_Configuration 01758 * @{ 01759 */ 01760 01761 /** 01762 * @brief Macro to configure the PLL2 & PLLI2S Predivision factor. 01763 * @note Predivision factor can not be changed if PLL2 is used indirectly as system clock 01764 * In this case, you have to select another source of the system clock, disable the PLL2 and PLLI2S and 01765 * then change the PREDIV2 factor. 01766 * @param __HSE_PREDIV2_VALUE__ specifies the PREDIV2 value applied to PLL2 & PLLI2S. 01767 * This parameter must be a number between RCC_HSE_PREDIV2_DIV1 and RCC_HSE_PREDIV2_DIV16. 01768 */ 01769 #define __HAL_RCC_HSE_PREDIV2_CONFIG(__HSE_PREDIV2_VALUE__) \ 01770 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2, (uint32_t)(__HSE_PREDIV2_VALUE__)) 01771 01772 /** 01773 * @brief Macro to get prediv2 factor for PLL2 & PLL3. 01774 */ 01775 #define __HAL_RCC_HSE_GET_PREDIV2() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV2) 01776 01777 /** 01778 * @} 01779 */ 01780 01781 /** @addtogroup RCCEx_PLLI2S_Configuration 01782 * @{ 01783 */ 01784 01785 /** @brief Macros to enable the main PLL2. 01786 * @note After enabling the main PLL2, the application software should wait on 01787 * PLL2RDY flag to be set indicating that PLL2 clock is stable and can 01788 * be used as system clock source. 01789 * @note The main PLL2 is disabled by hardware when entering STOP and STANDBY modes. 01790 */ 01791 #define __HAL_RCC_PLL2_ENABLE() (*(__IO uint32_t *) RCC_CR_PLL2ON_BB = ENABLE) 01792 01793 /** @brief Macros to disable the main PLL2. 01794 * @note The main PLL2 can not be disabled if it is used indirectly as system clock source 01795 * @note The main PLL2 is disabled by hardware when entering STOP and STANDBY modes. 01796 */ 01797 #define __HAL_RCC_PLL2_DISABLE() (*(__IO uint32_t *) RCC_CR_PLL2ON_BB = DISABLE) 01798 01799 /** @brief macros to configure the main PLL2 multiplication factor. 01800 * @note This function must be used only when the main PLL2 is disabled. 01801 * 01802 * @param __PLL2MUL__ specifies the multiplication factor for PLL2 VCO output clock 01803 * This parameter can be one of the following values: 01804 * @arg @ref RCC_PLL2_MUL8 PLL2VCO = PLL2 clock entry x 8 01805 * @arg @ref RCC_PLL2_MUL9 PLL2VCO = PLL2 clock entry x 9 01806 * @arg @ref RCC_PLL2_MUL10 PLL2VCO = PLL2 clock entry x 10 01807 * @arg @ref RCC_PLL2_MUL11 PLL2VCO = PLL2 clock entry x 11 01808 * @arg @ref RCC_PLL2_MUL12 PLL2VCO = PLL2 clock entry x 12 01809 * @arg @ref RCC_PLL2_MUL13 PLL2VCO = PLL2 clock entry x 13 01810 * @arg @ref RCC_PLL2_MUL14 PLL2VCO = PLL2 clock entry x 14 01811 * @arg @ref RCC_PLL2_MUL16 PLL2VCO = PLL2 clock entry x 16 01812 * @arg @ref RCC_PLL2_MUL20 PLL2VCO = PLL2 clock entry x 20 01813 * 01814 */ 01815 #define __HAL_RCC_PLL2_CONFIG(__PLL2MUL__)\ 01816 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL2MUL,(__PLL2MUL__)) 01817 01818 /** 01819 * @} 01820 */ 01821 01822 /** @defgroup RCCEx_I2S_Configuration I2S Configuration 01823 * @brief Macros to configure clock source of I2S peripherals. 01824 * @{ 01825 */ 01826 01827 /** @brief Macro to configure the I2S2 clock. 01828 * @param __I2S2CLKSOURCE__ specifies the I2S2 clock source. 01829 * This parameter can be one of the following values: 01830 * @arg @ref RCC_I2S2CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry 01831 * @arg @ref RCC_I2S2CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry 01832 */ 01833 #define __HAL_RCC_I2S2_CONFIG(__I2S2CLKSOURCE__) \ 01834 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S2SRC, (uint32_t)(__I2S2CLKSOURCE__)) 01835 01836 /** @brief Macro to get the I2S2 clock (I2S2CLK). 01837 * @retval The clock source can be one of the following values: 01838 * @arg @ref RCC_I2S2CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry 01839 * @arg @ref RCC_I2S2CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry 01840 */ 01841 #define __HAL_RCC_GET_I2S2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S2SRC))) 01842 01843 /** @brief Macro to configure the I2S3 clock. 01844 * @param __I2S2CLKSOURCE__ specifies the I2S3 clock source. 01845 * This parameter can be one of the following values: 01846 * @arg @ref RCC_I2S3CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry 01847 * @arg @ref RCC_I2S3CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry 01848 */ 01849 #define __HAL_RCC_I2S3_CONFIG(__I2S2CLKSOURCE__) \ 01850 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S3SRC, (uint32_t)(__I2S2CLKSOURCE__)) 01851 01852 /** @brief Macro to get the I2S3 clock (I2S3CLK). 01853 * @retval The clock source can be one of the following values: 01854 * @arg @ref RCC_I2S3CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry 01855 * @arg @ref RCC_I2S3CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry 01856 */ 01857 #define __HAL_RCC_GET_I2S3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S3SRC))) 01858 01859 /** 01860 * @} 01861 */ 01862 01863 #endif /* STM32F105xC || STM32F107xC */ 01864 /** 01865 * @} 01866 */ 01867 01868 /* Exported functions --------------------------------------------------------*/ 01869 /** @addtogroup RCCEx_Exported_Functions 01870 * @{ 01871 */ 01872 01873 /** @addtogroup RCCEx_Exported_Functions_Group1 01874 * @{ 01875 */ 01876 01877 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 01878 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 01879 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); 01880 01881 /** 01882 * @} 01883 */ 01884 01885 #if defined(STM32F105xC) || defined(STM32F107xC) 01886 /** @addtogroup RCCEx_Exported_Functions_Group2 01887 * @{ 01888 */ 01889 HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit); 01890 HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void); 01891 01892 /** 01893 * @} 01894 */ 01895 01896 /** @addtogroup RCCEx_Exported_Functions_Group3 01897 * @{ 01898 */ 01899 HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init); 01900 HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void); 01901 01902 /** 01903 * @} 01904 */ 01905 #endif /* STM32F105xC || STM32F107xC */ 01906 01907 /** 01908 * @} 01909 */ 01910 01911 /** 01912 * @} 01913 */ 01914 01915 /** 01916 * @} 01917 */ 01918 01919 #ifdef __cplusplus 01920 } 01921 #endif 01922 01923 #endif /* __STM32F1xx_HAL_RCC_EX_H */ 01924 01925 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 01926
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