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stm32f1xx_hal_rcc.h
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f1xx_hal_rcc.h 00004 * @author MCD Application Team 00005 * @version V1.0.4 00006 * @date 29-April-2016 00007 * @brief Header file of RCC HAL module. 00008 ****************************************************************************** 00009 * @attention 00010 * 00011 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> 00012 * 00013 * Redistribution and use in source and binary forms, with or without modification, 00014 * are permitted provided that the following conditions are met: 00015 * 1. Redistributions of source code must retain the above copyright notice, 00016 * this list of conditions and the following disclaimer. 00017 * 2. Redistributions in binary form must reproduce the above copyright notice, 00018 * this list of conditions and the following disclaimer in the documentation 00019 * and/or other materials provided with the distribution. 00020 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00021 * may be used to endorse or promote products derived from this software 00022 * without specific prior written permission. 00023 * 00024 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00025 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00026 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00027 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00028 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00029 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00030 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00031 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00032 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00033 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00034 * 00035 ****************************************************************************** 00036 */ 00037 00038 /* Define to prevent recursive inclusion -------------------------------------*/ 00039 #ifndef __STM32F1xx_HAL_RCC_H 00040 #define __STM32F1xx_HAL_RCC_H 00041 00042 #ifdef __cplusplus 00043 extern "C" { 00044 #endif 00045 00046 /* Includes ------------------------------------------------------------------*/ 00047 #include "stm32f1xx_hal_def.h" 00048 00049 /** @addtogroup STM32F1xx_HAL_Driver 00050 * @{ 00051 */ 00052 00053 /** @addtogroup RCC 00054 * @{ 00055 */ 00056 00057 /** @addtogroup RCC_Private_Constants 00058 * @{ 00059 */ 00060 00061 /** @defgroup RCC_Timeout RCC Timeout 00062 * @{ 00063 */ 00064 00065 /* Disable Backup domain write protection state change timeout */ 00066 #define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ 00067 /* LSE state change timeout */ 00068 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT 00069 #define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */ 00070 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT 00071 #define HSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms (minimum Tick + 1) */ 00072 #define LSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms (minimum Tick + 1) */ 00073 #define PLL_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms (minimum Tick + 1) */ 00074 #define LSI_VALUE ((uint32_t)40000) /* 40kHz */ 00075 /** 00076 * @} 00077 */ 00078 00079 /** @defgroup RCC_Register_Offset Register offsets 00080 * @{ 00081 */ 00082 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE) 00083 #define RCC_CR_OFFSET 0x00 00084 #define RCC_CFGR_OFFSET 0x04 00085 #define RCC_CIR_OFFSET 0x08 00086 #define RCC_BDCR_OFFSET 0x20 00087 #define RCC_CSR_OFFSET 0x24 00088 00089 /** 00090 * @} 00091 */ 00092 00093 /** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion 00094 * @brief RCC registers bit address in the alias region 00095 * @{ 00096 */ 00097 #define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET) 00098 #define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET) 00099 #define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET) 00100 #define RCC_BDCR_OFFSET_BB (RCC_OFFSET + RCC_BDCR_OFFSET) 00101 #define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET) 00102 00103 /* --- CR Register ---*/ 00104 /* Alias word address of HSION bit */ 00105 #define RCC_HSION_BIT_NUMBER POSITION_VAL(RCC_CR_HSION) 00106 #define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_HSION_BIT_NUMBER * 4))) 00107 /* Alias word address of HSEON bit */ 00108 #define RCC_HSEON_BIT_NUMBER POSITION_VAL(RCC_CR_HSEON) 00109 #define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_HSEON_BIT_NUMBER * 4))) 00110 /* Alias word address of CSSON bit */ 00111 #define RCC_CSSON_BIT_NUMBER POSITION_VAL(RCC_CR_CSSON) 00112 #define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_CSSON_BIT_NUMBER * 4))) 00113 /* Alias word address of PLLON bit */ 00114 #define RCC_PLLON_BIT_NUMBER POSITION_VAL(RCC_CR_PLLON) 00115 #define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_PLLON_BIT_NUMBER * 4))) 00116 00117 /* --- CSR Register ---*/ 00118 /* Alias word address of LSION bit */ 00119 #define RCC_LSION_BIT_NUMBER POSITION_VAL(RCC_CSR_LSION) 00120 #define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_LSION_BIT_NUMBER * 4))) 00121 00122 /* Alias word address of RMVF bit */ 00123 #define RCC_RMVF_BIT_NUMBER POSITION_VAL(RCC_CSR_RMVF) 00124 #define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_RMVF_BIT_NUMBER * 4))) 00125 00126 /* --- BDCR Registers ---*/ 00127 /* Alias word address of LSEON bit */ 00128 #define RCC_LSEON_BIT_NUMBER POSITION_VAL(RCC_BDCR_LSEON) 00129 #define RCC_BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RCC_LSEON_BIT_NUMBER * 4))) 00130 00131 /* Alias word address of LSEON bit */ 00132 #define RCC_LSEBYP_BIT_NUMBER POSITION_VAL(RCC_BDCR_LSEBYP) 00133 #define RCC_BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RCC_LSEBYP_BIT_NUMBER * 4))) 00134 00135 /* Alias word address of RTCEN bit */ 00136 #define RCC_RTCEN_BIT_NUMBER POSITION_VAL(RCC_BDCR_RTCEN) 00137 #define RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RCC_RTCEN_BIT_NUMBER * 4))) 00138 00139 /* Alias word address of BDRST bit */ 00140 #define RCC_BDRST_BIT_NUMBER POSITION_VAL(RCC_BDCR_BDRST) 00141 #define RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RCC_BDRST_BIT_NUMBER * 4))) 00142 00143 /** 00144 * @} 00145 */ 00146 00147 /* CR register byte 2 (Bits[23:16]) base address */ 00148 #define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02)) 00149 00150 /* CIR register byte 1 (Bits[15:8]) base address */ 00151 #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01)) 00152 00153 /* CIR register byte 2 (Bits[23:16]) base address */ 00154 #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02)) 00155 00156 /* Defines used for Flags */ 00157 #define CR_REG_INDEX ((uint8_t)1) 00158 #define BDCR_REG_INDEX ((uint8_t)2) 00159 #define CSR_REG_INDEX ((uint8_t)3) 00160 00161 #define RCC_FLAG_MASK ((uint8_t)0x1F) 00162 00163 /** 00164 * @} 00165 */ 00166 00167 /** @addtogroup RCC_Private_Macros 00168 * @{ 00169 */ 00170 /** @defgroup RCC_Alias_For_Legacy Alias define maintained for legacy 00171 * @{ 00172 */ 00173 #define __HAL_RCC_SYSCFG_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE 00174 #define __HAL_RCC_SYSCFG_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE 00175 #define __HAL_RCC_SYSCFG_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET 00176 #define __HAL_RCC_SYSCFG_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET 00177 /** 00178 * @} 00179 */ 00180 00181 #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI_DIV2) || \ 00182 ((__SOURCE__) == RCC_PLLSOURCE_HSE)) 00183 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ 00184 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ 00185 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ 00186 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ 00187 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) 00188 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ 00189 ((__HSE__) == RCC_HSE_BYPASS)) 00190 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ 00191 ((__LSE__) == RCC_LSE_BYPASS)) 00192 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) 00193 #define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F) 00194 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) 00195 #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \ 00196 ((__PLL__) == RCC_PLL_ON)) 00197 00198 #define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \ 00199 (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \ 00200 (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || \ 00201 (((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)) 00202 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ 00203 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ 00204 ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) 00205 #define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \ 00206 ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \ 00207 ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK)) 00208 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ 00209 ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ 00210 ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ 00211 ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ 00212 ((__HCLK__) == RCC_SYSCLK_DIV512)) 00213 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ 00214 ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ 00215 ((__PCLK__) == RCC_HCLK_DIV16)) 00216 #define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO) 00217 #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1)) 00218 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \ 00219 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ 00220 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ 00221 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV128)) 00222 00223 /** 00224 * @} 00225 */ 00226 00227 /* Exported types ------------------------------------------------------------*/ 00228 00229 /** @defgroup RCC_Exported_Types RCC Exported Types 00230 * @{ 00231 */ 00232 00233 /** 00234 * @brief RCC PLL configuration structure definition 00235 */ 00236 typedef struct 00237 { 00238 uint32_t PLLState; /*!< PLLState: The new state of the PLL. 00239 This parameter can be a value of @ref RCC_PLL_Config */ 00240 00241 uint32_t PLLSource; /*!< PLLSource: PLL entry clock source. 00242 This parameter must be a value of @ref RCC_PLL_Clock_Source */ 00243 00244 uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock 00245 This parameter must be a value of @ref RCCEx_PLL_Multiplication_Factor */ 00246 } RCC_PLLInitTypeDef; 00247 00248 /** 00249 * @brief RCC System, AHB and APB busses clock configuration structure definition 00250 */ 00251 typedef struct 00252 { 00253 uint32_t ClockType; /*!< The clock to be configured. 00254 This parameter can be a value of @ref RCC_System_Clock_Type */ 00255 00256 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. 00257 This parameter can be a value of @ref RCC_System_Clock_Source */ 00258 00259 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). 00260 This parameter can be a value of @ref RCC_AHB_Clock_Source */ 00261 00262 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). 00263 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ 00264 00265 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). 00266 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ 00267 } RCC_ClkInitTypeDef; 00268 00269 /** 00270 * @} 00271 */ 00272 00273 /* Exported constants --------------------------------------------------------*/ 00274 /** @defgroup RCC_Exported_Constants RCC Exported Constants 00275 * @{ 00276 */ 00277 00278 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source 00279 * @{ 00280 */ 00281 00282 #define RCC_PLLSOURCE_HSI_DIV2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ 00283 #define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC /*!< HSE clock selected as PLL entry clock source */ 00284 00285 /** 00286 * @} 00287 */ 00288 00289 /** @defgroup RCC_Oscillator_Type Oscillator Type 00290 * @{ 00291 */ 00292 #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000) 00293 #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001) 00294 #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002) 00295 #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004) 00296 #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008) 00297 /** 00298 * @} 00299 */ 00300 00301 /** @defgroup RCC_HSE_Config HSE Config 00302 * @{ 00303 */ 00304 #define RCC_HSE_OFF ((uint32_t)0x00000000) /*!< HSE clock deactivation */ 00305 #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ 00306 #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */ 00307 /** 00308 * @} 00309 */ 00310 00311 /** @defgroup RCC_LSE_Config LSE Config 00312 * @{ 00313 */ 00314 #define RCC_LSE_OFF ((uint32_t)0x00000000) /*!< LSE clock deactivation */ 00315 #define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ 00316 #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */ 00317 00318 /** 00319 * @} 00320 */ 00321 00322 /** @defgroup RCC_HSI_Config HSI Config 00323 * @{ 00324 */ 00325 #define RCC_HSI_OFF ((uint32_t)0x00000000) /*!< HSI clock deactivation */ 00326 #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ 00327 00328 #define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */ 00329 00330 /** 00331 * @} 00332 */ 00333 00334 /** @defgroup RCC_LSI_Config LSI Config 00335 * @{ 00336 */ 00337 #define RCC_LSI_OFF ((uint32_t)0x00000000) /*!< LSI clock deactivation */ 00338 #define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ 00339 00340 /** 00341 * @} 00342 */ 00343 00344 /** @defgroup RCC_PLL_Config PLL Config 00345 * @{ 00346 */ 00347 #define RCC_PLL_NONE ((uint32_t)0x00000000) /*!< PLL is not configured */ 00348 #define RCC_PLL_OFF ((uint32_t)0x00000001) /*!< PLL deactivation */ 00349 #define RCC_PLL_ON ((uint32_t)0x00000002) /*!< PLL activation */ 00350 00351 /** 00352 * @} 00353 */ 00354 00355 /** @defgroup RCC_System_Clock_Type System Clock Type 00356 * @{ 00357 */ 00358 #define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001) /*!< SYSCLK to configure */ 00359 #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002) /*!< HCLK to configure */ 00360 #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004) /*!< PCLK1 to configure */ 00361 #define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008) /*!< PCLK2 to configure */ 00362 00363 /** 00364 * @} 00365 */ 00366 00367 /** @defgroup RCC_System_Clock_Source System Clock Source 00368 * @{ 00369 */ 00370 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selected as system clock */ 00371 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selected as system clock */ 00372 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selected as system clock */ 00373 00374 /** 00375 * @} 00376 */ 00377 00378 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status 00379 * @{ 00380 */ 00381 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ 00382 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ 00383 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ 00384 00385 /** 00386 * @} 00387 */ 00388 00389 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source 00390 * @{ 00391 */ 00392 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ 00393 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ 00394 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ 00395 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ 00396 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ 00397 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ 00398 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ 00399 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ 00400 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ 00401 00402 /** 00403 * @} 00404 */ 00405 00406 /** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source 00407 * @{ 00408 */ 00409 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ 00410 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ 00411 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ 00412 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ 00413 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ 00414 00415 /** 00416 * @} 00417 */ 00418 00419 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source 00420 * @{ 00421 */ 00422 #define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000) /*!< No clock */ 00423 #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */ 00424 #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */ 00425 #define RCC_RTCCLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL_HSE /*!< HSE oscillator clock divided by 128 used as RTC clock */ 00426 /** 00427 * @} 00428 */ 00429 00430 00431 /** @defgroup RCC_MCO_Index MCO Index 00432 * @{ 00433 */ 00434 #define RCC_MCO1 ((uint32_t)0x00000000) 00435 #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ 00436 00437 /** 00438 * @} 00439 */ 00440 00441 /** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler 00442 * @{ 00443 */ 00444 #define RCC_MCODIV_1 ((uint32_t)0x00000000) 00445 00446 /** 00447 * @} 00448 */ 00449 00450 /** @defgroup RCC_Interrupt Interrupts 00451 * @{ 00452 */ 00453 #define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /*!< LSI Ready Interrupt flag */ 00454 #define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /*!< LSE Ready Interrupt flag */ 00455 #define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /*!< HSI Ready Interrupt flag */ 00456 #define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /*!< HSE Ready Interrupt flag */ 00457 #define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /*!< PLL Ready Interrupt flag */ 00458 #define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /*!< Clock Security System Interrupt flag */ 00459 /** 00460 * @} 00461 */ 00462 00463 /** @defgroup RCC_Flag Flags 00464 * Elements values convention: XXXYYYYYb 00465 * - YYYYY : Flag position in the register 00466 * - XXX : Register index 00467 * - 001: CR register 00468 * - 010: BDCR register 00469 * - 011: CSR register 00470 * @{ 00471 */ 00472 /* Flags in the CR register */ 00473 #define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_HSIRDY))) /*!< Internal High Speed clock ready flag */ 00474 #define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_HSERDY))) /*!< External High Speed clock ready flag */ 00475 #define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_PLLRDY))) /*!< PLL clock ready flag */ 00476 00477 /* Flags in the CSR register */ 00478 #define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LSIRDY))) /*!< Internal Low Speed oscillator Ready */ 00479 #define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_PINRSTF))) /*!< PIN reset flag */ 00480 #define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_PORRSTF))) /*!< POR/PDR reset flag */ 00481 #define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_SFTRSTF))) /*!< Software Reset flag */ 00482 #define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_IWDGRSTF))) /*!< Independent Watchdog reset flag */ 00483 #define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_WWDGRSTF))) /*!< Window watchdog reset flag */ 00484 #define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LPWRRSTF))) /*!< Low-Power reset flag */ 00485 00486 /* Flags in the BDCR register */ 00487 #define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5) | POSITION_VAL(RCC_BDCR_LSERDY))) /*!< External Low Speed oscillator Ready */ 00488 00489 /** 00490 * @} 00491 */ 00492 00493 /** 00494 * @} 00495 */ 00496 00497 /* Exported macro ------------------------------------------------------------*/ 00498 00499 /** @defgroup RCC_Exported_Macros RCC Exported Macros 00500 * @{ 00501 */ 00502 00503 /** @defgroup RCC_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable 00504 * @brief Enable or disable the AHB1 peripheral clock. 00505 * @note After reset, the peripheral clock (used for registers read/write access) 00506 * is disabled and the application software has to enable this clock before 00507 * using it. 00508 * @{ 00509 */ 00510 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \ 00511 __IO uint32_t tmpreg; \ 00512 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ 00513 /* Delay after an RCC peripheral clock enabling */\ 00514 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ 00515 UNUSED(tmpreg); \ 00516 } while(0) 00517 00518 #define __HAL_RCC_SRAM_CLK_ENABLE() do { \ 00519 __IO uint32_t tmpreg; \ 00520 SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\ 00521 /* Delay after an RCC peripheral clock enabling */\ 00522 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\ 00523 UNUSED(tmpreg); \ 00524 } while(0) 00525 00526 #define __HAL_RCC_FLITF_CLK_ENABLE() do { \ 00527 __IO uint32_t tmpreg; \ 00528 SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ 00529 /* Delay after an RCC peripheral clock enabling */\ 00530 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ 00531 UNUSED(tmpreg); \ 00532 } while(0) 00533 00534 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 00535 __IO uint32_t tmpreg; \ 00536 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ 00537 /* Delay after an RCC peripheral clock enabling */\ 00538 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ 00539 UNUSED(tmpreg); \ 00540 } while(0) 00541 00542 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN)) 00543 #define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN)) 00544 #define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN)) 00545 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN)) 00546 00547 /** 00548 * @} 00549 */ 00550 00551 /** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status 00552 * @brief Get the enable or disable status of the AHB peripheral clock. 00553 * @note After reset, the peripheral clock (used for registers read/write access) 00554 * is disabled and the application software has to enable this clock before 00555 * using it. 00556 * @{ 00557 */ 00558 00559 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET) 00560 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET) 00561 #define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET) 00562 #define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET) 00563 #define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET) 00564 #define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET) 00565 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET) 00566 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET) 00567 00568 /** 00569 * @} 00570 */ 00571 00572 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Clock Enable Disable 00573 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. 00574 * @note After reset, the peripheral clock (used for registers read/write access) 00575 * is disabled and the application software has to enable this clock before 00576 * using it. 00577 * @{ 00578 */ 00579 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 00580 __IO uint32_t tmpreg; \ 00581 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 00582 /* Delay after an RCC peripheral clock enabling */\ 00583 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 00584 UNUSED(tmpreg); \ 00585 } while(0) 00586 00587 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 00588 __IO uint32_t tmpreg; \ 00589 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 00590 /* Delay after an RCC peripheral clock enabling */\ 00591 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 00592 UNUSED(tmpreg); \ 00593 } while(0) 00594 00595 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ 00596 __IO uint32_t tmpreg; \ 00597 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ 00598 /* Delay after an RCC peripheral clock enabling */\ 00599 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ 00600 UNUSED(tmpreg); \ 00601 } while(0) 00602 00603 #define __HAL_RCC_USART2_CLK_ENABLE() do { \ 00604 __IO uint32_t tmpreg; \ 00605 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ 00606 /* Delay after an RCC peripheral clock enabling */\ 00607 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ 00608 UNUSED(tmpreg); \ 00609 } while(0) 00610 00611 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ 00612 __IO uint32_t tmpreg; \ 00613 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ 00614 /* Delay after an RCC peripheral clock enabling */\ 00615 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ 00616 UNUSED(tmpreg); \ 00617 } while(0) 00618 00619 #define __HAL_RCC_BKP_CLK_ENABLE() do { \ 00620 __IO uint32_t tmpreg; \ 00621 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\ 00622 /* Delay after an RCC peripheral clock enabling */\ 00623 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\ 00624 UNUSED(tmpreg); \ 00625 } while(0) 00626 00627 #define __HAL_RCC_PWR_CLK_ENABLE() do { \ 00628 __IO uint32_t tmpreg; \ 00629 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ 00630 /* Delay after an RCC peripheral clock enabling */\ 00631 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ 00632 UNUSED(tmpreg); \ 00633 } while(0) 00634 00635 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) 00636 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) 00637 #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) 00638 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) 00639 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) 00640 00641 #define __HAL_RCC_BKP_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_BKPEN)) 00642 #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) 00643 00644 /** 00645 * @} 00646 */ 00647 00648 /** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status 00649 * @brief Get the enable or disable status of the APB1 peripheral clock. 00650 * @note After reset, the peripheral clock (used for registers read/write access) 00651 * is disabled and the application software has to enable this clock before 00652 * using it. 00653 * @{ 00654 */ 00655 00656 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) 00657 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) 00658 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 00659 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 00660 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET) 00661 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET) 00662 #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET) 00663 #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET) 00664 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET) 00665 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET) 00666 #define __HAL_RCC_BKP_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) != RESET) 00667 #define __HAL_RCC_BKP_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) == RESET) 00668 #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET) 00669 #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET) 00670 00671 /** 00672 * @} 00673 */ 00674 00675 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Clock Enable Disable 00676 * @brief Enable or disable the High Speed APB (APB2) peripheral clock. 00677 * @note After reset, the peripheral clock (used for registers read/write access) 00678 * is disabled and the application software has to enable this clock before 00679 * using it. 00680 * @{ 00681 */ 00682 #define __HAL_RCC_AFIO_CLK_ENABLE() do { \ 00683 __IO uint32_t tmpreg; \ 00684 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\ 00685 /* Delay after an RCC peripheral clock enabling */\ 00686 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\ 00687 UNUSED(tmpreg); \ 00688 } while(0) 00689 00690 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ 00691 __IO uint32_t tmpreg; \ 00692 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\ 00693 /* Delay after an RCC peripheral clock enabling */\ 00694 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\ 00695 UNUSED(tmpreg); \ 00696 } while(0) 00697 00698 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ 00699 __IO uint32_t tmpreg; \ 00700 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\ 00701 /* Delay after an RCC peripheral clock enabling */\ 00702 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\ 00703 UNUSED(tmpreg); \ 00704 } while(0) 00705 00706 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ 00707 __IO uint32_t tmpreg; \ 00708 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\ 00709 /* Delay after an RCC peripheral clock enabling */\ 00710 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\ 00711 UNUSED(tmpreg); \ 00712 } while(0) 00713 00714 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 00715 __IO uint32_t tmpreg; \ 00716 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\ 00717 /* Delay after an RCC peripheral clock enabling */\ 00718 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\ 00719 UNUSED(tmpreg); \ 00720 } while(0) 00721 00722 #define __HAL_RCC_ADC1_CLK_ENABLE() do { \ 00723 __IO uint32_t tmpreg; \ 00724 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ 00725 /* Delay after an RCC peripheral clock enabling */\ 00726 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ 00727 UNUSED(tmpreg); \ 00728 } while(0) 00729 00730 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ 00731 __IO uint32_t tmpreg; \ 00732 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ 00733 /* Delay after an RCC peripheral clock enabling */\ 00734 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ 00735 UNUSED(tmpreg); \ 00736 } while(0) 00737 00738 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ 00739 __IO uint32_t tmpreg; \ 00740 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ 00741 /* Delay after an RCC peripheral clock enabling */\ 00742 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ 00743 UNUSED(tmpreg); \ 00744 } while(0) 00745 00746 #define __HAL_RCC_USART1_CLK_ENABLE() do { \ 00747 __IO uint32_t tmpreg; \ 00748 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ 00749 /* Delay after an RCC peripheral clock enabling */\ 00750 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ 00751 UNUSED(tmpreg); \ 00752 } while(0) 00753 00754 #define __HAL_RCC_AFIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_AFIOEN)) 00755 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPAEN)) 00756 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPBEN)) 00757 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPCEN)) 00758 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPDEN)) 00759 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) 00760 00761 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) 00762 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) 00763 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) 00764 00765 /** 00766 * @} 00767 */ 00768 00769 /** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status 00770 * @brief Get the enable or disable status of the APB2 peripheral clock. 00771 * @note After reset, the peripheral clock (used for registers read/write access) 00772 * is disabled and the application software has to enable this clock before 00773 * using it. 00774 * @{ 00775 */ 00776 00777 #define __HAL_RCC_AFIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) != RESET) 00778 #define __HAL_RCC_AFIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) == RESET) 00779 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) != RESET) 00780 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) == RESET) 00781 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) != RESET) 00782 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) == RESET) 00783 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) != RESET) 00784 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) == RESET) 00785 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) != RESET) 00786 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) == RESET) 00787 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET) 00788 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET) 00789 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET) 00790 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET) 00791 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET) 00792 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET) 00793 #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET) 00794 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET) 00795 00796 /** 00797 * @} 00798 */ 00799 00800 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset 00801 * @brief Force or release APB1 peripheral reset. 00802 * @{ 00803 */ 00804 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) 00805 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) 00806 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) 00807 #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) 00808 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) 00809 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) 00810 00811 #define __HAL_RCC_BKP_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_BKPRST)) 00812 #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) 00813 00814 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00) 00815 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) 00816 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) 00817 #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) 00818 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) 00819 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) 00820 00821 #define __HAL_RCC_BKP_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_BKPRST)) 00822 #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) 00823 00824 /** 00825 * @} 00826 */ 00827 00828 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset 00829 * @brief Force or release APB2 peripheral reset. 00830 * @{ 00831 */ 00832 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) 00833 #define __HAL_RCC_AFIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_AFIORST)) 00834 #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPARST)) 00835 #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPBRST)) 00836 #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPCRST)) 00837 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPDRST)) 00838 #define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST)) 00839 00840 #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST)) 00841 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) 00842 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) 00843 00844 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00) 00845 #define __HAL_RCC_AFIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_AFIORST)) 00846 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPARST)) 00847 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPBRST)) 00848 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPCRST)) 00849 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPDRST)) 00850 #define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST)) 00851 00852 #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST)) 00853 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) 00854 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) 00855 00856 /** 00857 * @} 00858 */ 00859 00860 /** @defgroup RCC_HSI_Configuration HSI Configuration 00861 * @{ 00862 */ 00863 00864 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). 00865 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. 00866 * @note HSI can not be stopped if it is used as system clock source. In this case, 00867 * you have to select another source of the system clock then stop the HSI. 00868 * @note After enabling the HSI, the application software should wait on HSIRDY 00869 * flag to be set indicating that HSI clock is stable and can be used as 00870 * system clock source. 00871 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator 00872 * clock cycles. 00873 */ 00874 #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE) 00875 #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE) 00876 00877 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. 00878 * @note The calibration is used to compensate for the variations in voltage 00879 * and temperature that influence the frequency of the internal HSI RC. 00880 * @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value. 00881 * (default is RCC_HSICALIBRATION_DEFAULT). 00882 * This parameter must be a number between 0 and 0x1F. 00883 */ 00884 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \ 00885 (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << POSITION_VAL(RCC_CR_HSITRIM))) 00886 00887 /** 00888 * @} 00889 */ 00890 00891 /** @defgroup RCC_LSI_Configuration LSI Configuration 00892 * @{ 00893 */ 00894 00895 /** @brief Macro to enable the Internal Low Speed oscillator (LSI). 00896 * @note After enabling the LSI, the application software should wait on 00897 * LSIRDY flag to be set indicating that LSI clock is stable and can 00898 * be used to clock the IWDG and/or the RTC. 00899 */ 00900 #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE) 00901 00902 /** @brief Macro to disable the Internal Low Speed oscillator (LSI). 00903 * @note LSI can not be disabled if the IWDG is running. 00904 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator 00905 * clock cycles. 00906 */ 00907 #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE) 00908 00909 /** 00910 * @} 00911 */ 00912 00913 /** @defgroup RCC_HSE_Configuration HSE Configuration 00914 * @{ 00915 */ 00916 00917 /** 00918 * @brief Macro to configure the External High Speed oscillator (HSE). 00919 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not 00920 * supported by this macro. User should request a transition to HSE Off 00921 * first and then HSE On or HSE Bypass. 00922 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application 00923 * software should wait on HSERDY flag to be set indicating that HSE clock 00924 * is stable and can be used to clock the PLL and/or system clock. 00925 * @note HSE state can not be changed if it is used directly or through the 00926 * PLL as system clock. In this case, you have to select another source 00927 * of the system clock then change the HSE state (ex. disable it). 00928 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. 00929 * @note This function reset the CSSON bit, so if the clock security system(CSS) 00930 * was previously enabled you have to enable it again after calling this 00931 * function. 00932 * @param __STATE__ specifies the new state of the HSE. 00933 * This parameter can be one of the following values: 00934 * @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after 00935 * 6 HSE oscillator clock cycles. 00936 * @arg @ref RCC_HSE_ON turn ON the HSE oscillator 00937 * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock 00938 */ 00939 #define __HAL_RCC_HSE_CONFIG(__STATE__) \ 00940 do{ \ 00941 if ((__STATE__) == RCC_HSE_ON) \ 00942 { \ 00943 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 00944 } \ 00945 else if ((__STATE__) == RCC_HSE_OFF) \ 00946 { \ 00947 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ 00948 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ 00949 } \ 00950 else if ((__STATE__) == RCC_HSE_BYPASS) \ 00951 { \ 00952 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ 00953 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 00954 } \ 00955 else \ 00956 { \ 00957 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ 00958 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ 00959 } \ 00960 }while(0) 00961 00962 /** 00963 * @} 00964 */ 00965 00966 /** @defgroup RCC_LSE_Configuration LSE Configuration 00967 * @{ 00968 */ 00969 00970 /** 00971 * @brief Macro to configure the External Low Speed oscillator (LSE). 00972 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. 00973 * @note As the LSE is in the Backup domain and write access is denied to 00974 * this domain after reset, you have to enable write access using 00975 * @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE 00976 * (to be done once after reset). 00977 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application 00978 * software should wait on LSERDY flag to be set indicating that LSE clock 00979 * is stable and can be used to clock the RTC. 00980 * @param __STATE__ specifies the new state of the LSE. 00981 * This parameter can be one of the following values: 00982 * @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after 00983 * 6 LSE oscillator clock cycles. 00984 * @arg @ref RCC_LSE_ON turn ON the LSE oscillator. 00985 * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. 00986 */ 00987 #define __HAL_RCC_LSE_CONFIG(__STATE__) \ 00988 do{ \ 00989 if ((__STATE__) == RCC_LSE_ON) \ 00990 { \ 00991 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 00992 } \ 00993 else if ((__STATE__) == RCC_LSE_OFF) \ 00994 { \ 00995 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 00996 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 00997 } \ 00998 else if ((__STATE__) == RCC_LSE_BYPASS) \ 00999 { \ 01000 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 01001 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 01002 } \ 01003 else \ 01004 { \ 01005 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 01006 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 01007 } \ 01008 }while(0) 01009 01010 /** 01011 * @} 01012 */ 01013 01014 /** @defgroup RCC_PLL_Configuration PLL Configuration 01015 * @{ 01016 */ 01017 01018 /** @brief Macro to enable the main PLL. 01019 * @note After enabling the main PLL, the application software should wait on 01020 * PLLRDY flag to be set indicating that PLL clock is stable and can 01021 * be used as system clock source. 01022 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. 01023 */ 01024 #define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE) 01025 01026 /** @brief Macro to disable the main PLL. 01027 * @note The main PLL can not be disabled if it is used as system clock source 01028 */ 01029 #define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE) 01030 01031 /** @brief Macro to configure the main PLL clock source and multiplication factors. 01032 * @note This function must be used only when the main PLL is disabled. 01033 * 01034 * @param __RCC_PLLSOURCE__ specifies the PLL entry clock source. 01035 * This parameter can be one of the following values: 01036 * @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL clock entry 01037 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry 01038 * @param __PLLMUL__ specifies the multiplication factor for PLL VCO output clock 01039 * This parameter can be one of the following values: 01040 * @arg @ref RCC_PLL_MUL4 PLLVCO = PLL clock entry x 4 01041 * @arg @ref RCC_PLL_MUL6 PLLVCO = PLL clock entry x 6 01042 @if STM32F105xC 01043 * @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5 01044 @elseif STM32F107xC 01045 * @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5 01046 @else 01047 * @arg @ref RCC_PLL_MUL2 PLLVCO = PLL clock entry x 2 01048 * @arg @ref RCC_PLL_MUL3 PLLVCO = PLL clock entry x 3 01049 * @arg @ref RCC_PLL_MUL10 PLLVCO = PLL clock entry x 10 01050 * @arg @ref RCC_PLL_MUL11 PLLVCO = PLL clock entry x 11 01051 * @arg @ref RCC_PLL_MUL12 PLLVCO = PLL clock entry x 12 01052 * @arg @ref RCC_PLL_MUL13 PLLVCO = PLL clock entry x 13 01053 * @arg @ref RCC_PLL_MUL14 PLLVCO = PLL clock entry x 14 01054 * @arg @ref RCC_PLL_MUL15 PLLVCO = PLL clock entry x 15 01055 * @arg @ref RCC_PLL_MUL16 PLLVCO = PLL clock entry x 16 01056 @endif 01057 * @arg @ref RCC_PLL_MUL8 PLLVCO = PLL clock entry x 8 01058 * @arg @ref RCC_PLL_MUL9 PLLVCO = PLL clock entry x 9 01059 * 01060 */ 01061 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__)\ 01062 MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL),((__RCC_PLLSOURCE__) | (__PLLMUL__) )) 01063 01064 /** @brief Get oscillator clock selected as PLL input clock 01065 * @retval The clock source used for PLL entry. The returned value can be one 01066 * of the following: 01067 * @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL input clock 01068 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock 01069 */ 01070 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC))) 01071 01072 /** 01073 * @} 01074 */ 01075 01076 /** @defgroup RCC_Get_Clock_source Get Clock source 01077 * @{ 01078 */ 01079 01080 /** 01081 * @brief Macro to configure the system clock source. 01082 * @param __SYSCLKSOURCE__ specifies the system clock source. 01083 * This parameter can be one of the following values: 01084 * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source. 01085 * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source. 01086 * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source. 01087 */ 01088 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ 01089 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__)) 01090 01091 /** @brief Macro to get the clock source used as system clock. 01092 * @retval The clock source used as system clock. The returned value can be one 01093 * of the following: 01094 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock 01095 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock 01096 * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock 01097 */ 01098 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS))) 01099 01100 /** 01101 * @} 01102 */ 01103 01104 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config 01105 * @{ 01106 */ 01107 01108 #if defined(RCC_CFGR_MCO_3) 01109 /** @brief Macro to configure the MCO clock. 01110 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 01111 * This parameter can be one of the following values: 01112 * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock 01113 * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock (SYSCLK) selected as MCO clock 01114 * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock 01115 * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock 01116 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO clock 01117 * @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected by 2 selected as MCO clock 01118 * @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO clock 01119 * @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected (for Ethernet) as MCO clock 01120 * @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected (for Ethernet) as MCO clock 01121 * @param __MCODIV__ specifies the MCO clock prescaler. 01122 * This parameter can be one of the following values: 01123 * @arg @ref RCC_MCODIV_1 No division applied on MCO clock source 01124 */ 01125 #else 01126 /** @brief Macro to configure the MCO clock. 01127 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 01128 * This parameter can be one of the following values: 01129 * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock 01130 * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock (SYSCLK) selected as MCO clock 01131 * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock 01132 * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock 01133 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO clock 01134 * @param __MCODIV__ specifies the MCO clock prescaler. 01135 * This parameter can be one of the following values: 01136 * @arg @ref RCC_MCODIV_1 No division applied on MCO clock source 01137 */ 01138 #endif 01139 01140 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ 01141 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__)) 01142 01143 01144 /** 01145 * @} 01146 */ 01147 01148 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration 01149 * @{ 01150 */ 01151 01152 /** @brief Macro to configure the RTC clock (RTCCLK). 01153 * @note As the RTC clock configuration bits are in the Backup domain and write 01154 * access is denied to this domain after reset, you have to enable write 01155 * access using the Power Backup Access macro before to configure 01156 * the RTC clock source (to be done once after reset). 01157 * @note Once the RTC clock is configured it can't be changed unless the 01158 * Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by 01159 * a Power On Reset (POR). 01160 * 01161 * @param __RTC_CLKSOURCE__ specifies the RTC clock source. 01162 * This parameter can be one of the following values: 01163 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock 01164 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock 01165 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock 01166 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock 01167 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to 01168 * work in STOP and STANDBY modes, and can be used as wakeup source. 01169 * However, when the HSE clock is used as RTC clock source, the RTC 01170 * cannot be used in STOP and STANDBY modes. 01171 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as 01172 * RTC clock source). 01173 */ 01174 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__)) 01175 01176 /** @brief Macro to get the RTC clock source. 01177 * @retval The clock source can be one of the following values: 01178 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock 01179 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock 01180 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock 01181 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock 01182 */ 01183 #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) 01184 01185 /** @brief Macro to enable the the RTC clock. 01186 * @note These macros must be used only after the RTC clock source was selected. 01187 */ 01188 #define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE) 01189 01190 /** @brief Macro to disable the the RTC clock. 01191 * @note These macros must be used only after the RTC clock source was selected. 01192 */ 01193 #define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE) 01194 01195 /** @brief Macro to force the Backup domain reset. 01196 * @note This function resets the RTC peripheral (including the backup registers) 01197 * and the RTC clock source selection in RCC_BDCR register. 01198 */ 01199 #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE) 01200 01201 /** @brief Macros to release the Backup domain reset. 01202 */ 01203 #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE) 01204 01205 /** 01206 * @} 01207 */ 01208 01209 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management 01210 * @brief macros to manage the specified RCC Flags and interrupts. 01211 * @{ 01212 */ 01213 01214 /** @brief Enable RCC interrupt. 01215 * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. 01216 * This parameter can be any combination of the following values: 01217 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 01218 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 01219 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 01220 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 01221 * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt 01222 @if STM32F105xx 01223 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. 01224 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. 01225 @elsif STM32F107xx 01226 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. 01227 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. 01228 @endif 01229 */ 01230 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) 01231 01232 /** @brief Disable RCC interrupt. 01233 * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. 01234 * This parameter can be any combination of the following values: 01235 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 01236 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 01237 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 01238 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 01239 * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt 01240 @if STM32F105xx 01241 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. 01242 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. 01243 @elsif STM32F107xx 01244 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. 01245 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. 01246 @endif 01247 */ 01248 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__))) 01249 01250 /** @brief Clear the RCC's interrupt pending bits. 01251 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 01252 * This parameter can be any combination of the following values: 01253 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt. 01254 * @arg @ref RCC_IT_LSERDY LSE ready interrupt. 01255 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt. 01256 * @arg @ref RCC_IT_HSERDY HSE ready interrupt. 01257 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt. 01258 @if STM32F105xx 01259 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. 01260 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. 01261 @elsif STM32F107xx 01262 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. 01263 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. 01264 @endif 01265 * @arg @ref RCC_IT_CSS Clock Security System interrupt 01266 */ 01267 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__)) 01268 01269 /** @brief Check the RCC's interrupt has occurred or not. 01270 * @param __INTERRUPT__ specifies the RCC interrupt source to check. 01271 * This parameter can be one of the following values: 01272 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt. 01273 * @arg @ref RCC_IT_LSERDY LSE ready interrupt. 01274 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt. 01275 * @arg @ref RCC_IT_HSERDY HSE ready interrupt. 01276 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt. 01277 @if STM32F105xx 01278 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. 01279 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. 01280 @elsif STM32F107xx 01281 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. 01282 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. 01283 @endif 01284 * @arg @ref RCC_IT_CSS Clock Security System interrupt 01285 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 01286 */ 01287 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__)) 01288 01289 /** @brief Set RMVF bit to clear the reset flags. 01290 * The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, 01291 * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST 01292 */ 01293 #define __HAL_RCC_CLEAR_RESET_FLAGS() (*(__IO uint32_t *)RCC_CSR_RMVF_BB = ENABLE) 01294 01295 /** @brief Check RCC flag is set or not. 01296 * @param __FLAG__ specifies the flag to check. 01297 * This parameter can be one of the following values: 01298 * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready. 01299 * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready. 01300 * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready. 01301 @if STM32F105xx 01302 * @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready. 01303 * @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready. 01304 @elsif STM32F107xx 01305 * @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready. 01306 * @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready. 01307 @endif 01308 * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready. 01309 * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready. 01310 * @arg @ref RCC_FLAG_PINRST Pin reset. 01311 * @arg @ref RCC_FLAG_PORRST POR/PDR reset. 01312 * @arg @ref RCC_FLAG_SFTRST Software reset. 01313 * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset. 01314 * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset. 01315 * @arg @ref RCC_FLAG_LPWRRST Low Power reset. 01316 * @retval The new state of __FLAG__ (TRUE or FALSE). 01317 */ 01318 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR : \ 01319 ((((__FLAG__) >> 5) == BDCR_REG_INDEX)? RCC->BDCR : \ 01320 RCC->CSR)) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) 01321 01322 /** 01323 * @} 01324 */ 01325 01326 /** 01327 * @} 01328 */ 01329 01330 /* Include RCC HAL Extension module */ 01331 #include "stm32f1xx_hal_rcc_ex.h" 01332 01333 /* Exported functions --------------------------------------------------------*/ 01334 /** @addtogroup RCC_Exported_Functions 01335 * @{ 01336 */ 01337 01338 /** @addtogroup RCC_Exported_Functions_Group1 01339 * @{ 01340 */ 01341 01342 /* Initialization and de-initialization functions ******************************/ 01343 void HAL_RCC_DeInit(void); 01344 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 01345 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); 01346 01347 /** 01348 * @} 01349 */ 01350 01351 /** @addtogroup RCC_Exported_Functions_Group2 01352 * @{ 01353 */ 01354 01355 /* Peripheral Control functions ************************************************/ 01356 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); 01357 void HAL_RCC_EnableCSS(void); 01358 void HAL_RCC_DisableCSS(void); 01359 uint32_t HAL_RCC_GetSysClockFreq(void); 01360 uint32_t HAL_RCC_GetHCLKFreq(void); 01361 uint32_t HAL_RCC_GetPCLK1Freq(void); 01362 uint32_t HAL_RCC_GetPCLK2Freq(void); 01363 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 01364 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); 01365 01366 /* CSS NMI IRQ handler */ 01367 void HAL_RCC_NMI_IRQHandler(void); 01368 01369 /* User Callbacks in non blocking mode (IT mode) */ 01370 void HAL_RCC_CSSCallback(void); 01371 01372 /** 01373 * @} 01374 */ 01375 01376 /** 01377 * @} 01378 */ 01379 01380 /** 01381 * @} 01382 */ 01383 01384 /** 01385 * @} 01386 */ 01387 01388 #ifdef __cplusplus 01389 } 01390 #endif 01391 01392 #endif /* __STM32F1xx_HAL_RCC_H */ 01393 01394 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 01395
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