stm32f1xx_hal_gpio_ex.h

00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_gpio_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.4
00006   * @date    29-April-2016
00007   * @brief   Header file of GPIO HAL Extension module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */ 
00037 
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_HAL_GPIO_EX_H
00040 #define __STM32F1xx_HAL_GPIO_EX_H
00041 
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045 
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f1xx_hal_def.h"
00048 
00049 /** @addtogroup STM32F1xx_HAL_Driver
00050   * @{
00051   */
00052 
00053 /** @defgroup GPIOEx GPIOEx
00054   * @{
00055   */ 
00056 
00057 /* Exported types ------------------------------------------------------------*/
00058 
00059 /* Exported constants --------------------------------------------------------*/
00060 
00061 /** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
00062   * @{
00063   */ 
00064   
00065 /** @defgroup GPIOEx_EVENTOUT EVENTOUT Cortex Configuration
00066   * @brief This section propose definition to use the Cortex EVENTOUT signal.
00067   * @{
00068   */
00069   
00070 /** @defgroup GPIOEx_EVENTOUT_PIN EVENTOUT Pin 
00071   * @{
00072   */
00073   
00074 #define AFIO_EVENTOUT_PIN_0  AFIO_EVCR_PIN_PX0 /*!< EVENTOUT on pin 0 */
00075 #define AFIO_EVENTOUT_PIN_1  AFIO_EVCR_PIN_PX1 /*!< EVENTOUT on pin 1 */
00076 #define AFIO_EVENTOUT_PIN_2  AFIO_EVCR_PIN_PX2 /*!< EVENTOUT on pin 2 */
00077 #define AFIO_EVENTOUT_PIN_3  AFIO_EVCR_PIN_PX3 /*!< EVENTOUT on pin 3 */
00078 #define AFIO_EVENTOUT_PIN_4  AFIO_EVCR_PIN_PX4 /*!< EVENTOUT on pin 4 */
00079 #define AFIO_EVENTOUT_PIN_5  AFIO_EVCR_PIN_PX5 /*!< EVENTOUT on pin 5 */
00080 #define AFIO_EVENTOUT_PIN_6  AFIO_EVCR_PIN_PX6 /*!< EVENTOUT on pin 6 */
00081 #define AFIO_EVENTOUT_PIN_7  AFIO_EVCR_PIN_PX7 /*!< EVENTOUT on pin 7 */
00082 #define AFIO_EVENTOUT_PIN_8  AFIO_EVCR_PIN_PX8 /*!< EVENTOUT on pin 8 */
00083 #define AFIO_EVENTOUT_PIN_9  AFIO_EVCR_PIN_PX9 /*!< EVENTOUT on pin 9 */
00084 #define AFIO_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10 /*!< EVENTOUT on pin 10 */
00085 #define AFIO_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11 /*!< EVENTOUT on pin 11 */
00086 #define AFIO_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12 /*!< EVENTOUT on pin 12 */
00087 #define AFIO_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13 /*!< EVENTOUT on pin 13 */
00088 #define AFIO_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14 /*!< EVENTOUT on pin 14 */
00089 #define AFIO_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15 /*!< EVENTOUT on pin 15 */
00090 
00091 #define IS_AFIO_EVENTOUT_PIN(__PIN__) (((__PIN__) == AFIO_EVENTOUT_PIN_0) || \
00092                                        ((__PIN__) == AFIO_EVENTOUT_PIN_1) || \
00093                                        ((__PIN__) == AFIO_EVENTOUT_PIN_2) || \
00094                                        ((__PIN__) == AFIO_EVENTOUT_PIN_3) || \
00095                                        ((__PIN__) == AFIO_EVENTOUT_PIN_4) || \
00096                                        ((__PIN__) == AFIO_EVENTOUT_PIN_5) || \
00097                                        ((__PIN__) == AFIO_EVENTOUT_PIN_6) || \
00098                                        ((__PIN__) == AFIO_EVENTOUT_PIN_7) || \
00099                                        ((__PIN__) == AFIO_EVENTOUT_PIN_8) || \
00100                                        ((__PIN__) == AFIO_EVENTOUT_PIN_9) || \
00101                                        ((__PIN__) == AFIO_EVENTOUT_PIN_10) || \
00102                                        ((__PIN__) == AFIO_EVENTOUT_PIN_11) || \
00103                                        ((__PIN__) == AFIO_EVENTOUT_PIN_12) || \
00104                                        ((__PIN__) == AFIO_EVENTOUT_PIN_13) || \
00105                                        ((__PIN__) == AFIO_EVENTOUT_PIN_14) || \
00106                                        ((__PIN__) == AFIO_EVENTOUT_PIN_15))
00107 /**
00108   * @}
00109   */ 
00110   
00111 /** @defgroup GPIOEx_EVENTOUT_PORT EVENTOUT Port
00112   * @{
00113   */
00114   
00115 #define AFIO_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA /*!< EVENTOUT on port A */
00116 #define AFIO_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB /*!< EVENTOUT on port B */
00117 #define AFIO_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC /*!< EVENTOUT on port C */
00118 #define AFIO_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD /*!< EVENTOUT on port D */
00119 #define AFIO_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE /*!< EVENTOUT on port E */
00120 
00121 #define IS_AFIO_EVENTOUT_PORT(__PORT__) (((__PORT__) == AFIO_EVENTOUT_PORT_A) || \
00122                                          ((__PORT__) == AFIO_EVENTOUT_PORT_B) || \
00123                                          ((__PORT__) == AFIO_EVENTOUT_PORT_C) || \
00124                                          ((__PORT__) == AFIO_EVENTOUT_PORT_D) || \
00125                                          ((__PORT__) == AFIO_EVENTOUT_PORT_E))
00126 /**
00127   * @}
00128   */
00129   
00130 /**
00131   * @}
00132   */
00133 
00134 /** @defgroup GPIOEx_AFIO_AF_REMAPPING Alternate Function Remapping
00135   * @brief This section propose definition to remap the alternate function to some other port/pins.
00136   * @{
00137   */
00138   
00139 /**
00140   * @brief Enable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
00141   * @note  ENABLE: Remap     (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5)
00142   * @retval None
00143   */
00144 #define __HAL_AFIO_REMAP_SPI1_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP)
00145 
00146 /**
00147   * @brief Disable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
00148   * @note  DISABLE: No remap (NSS/PA4,  SCK/PA5, MISO/PA6, MOSI/PA7)
00149   * @retval None
00150   */
00151 #define __HAL_AFIO_REMAP_SPI1_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP)
00152 
00153 /**
00154   * @brief Enable the remapping of I2C1 alternate function SCL and SDA.
00155   * @note  ENABLE: Remap     (SCL/PB8, SDA/PB9)
00156   * @retval None
00157   */
00158 #define __HAL_AFIO_REMAP_I2C1_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP)
00159 
00160 /**
00161   * @brief Disable the remapping of I2C1 alternate function SCL and SDA.
00162   * @note  DISABLE: No remap (SCL/PB6, SDA/PB7)
00163   * @retval None
00164   */
00165 #define __HAL_AFIO_REMAP_I2C1_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP)
00166 
00167 /**
00168   * @brief Enable the remapping of USART1 alternate function TX and RX.
00169   * @note  ENABLE: Remap     (TX/PB6, RX/PB7)
00170   * @retval None
00171   */
00172 #define __HAL_AFIO_REMAP_USART1_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP)
00173 
00174 /**
00175   * @brief Disable the remapping of USART1 alternate function TX and RX.
00176   * @note  DISABLE: No remap (TX/PA9, RX/PA10)
00177   * @retval None
00178   */
00179 #define __HAL_AFIO_REMAP_USART1_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP)
00180 
00181 /**
00182   * @brief Enable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
00183   * @note  ENABLE: Remap     (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7)
00184   * @retval None
00185   */
00186 #define __HAL_AFIO_REMAP_USART2_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP)
00187 
00188 /**
00189   * @brief Disable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
00190   * @note  DISABLE: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4)
00191   * @retval None
00192   */
00193 #define __HAL_AFIO_REMAP_USART2_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP)
00194 
00195 /**
00196   * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
00197   * @note  ENABLE: Full remap     (TX/PD8,  RX/PD9,  CK/PD10, CTS/PD11, RTS/PD12)
00198   * @retval None
00199   */
00200 #define __HAL_AFIO_REMAP_USART3_ENABLE()  MODIFY_REG(AFIO->MAPR, AFIO_MAPR_USART3_REMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP)
00201 
00202 /**
00203   * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
00204   * @note  PARTIAL: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)
00205   * @retval None
00206   */
00207 #define __HAL_AFIO_REMAP_USART3_PARTIAL() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_USART3_REMAP, AFIO_MAPR_USART3_REMAP_PARTIALREMAP)
00208 
00209 /**
00210   * @brief Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
00211   * @note  DISABLE: No remap      (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)
00212   * @retval None
00213   */
00214 #define __HAL_AFIO_REMAP_USART3_DISABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_USART3_REMAP, AFIO_MAPR_USART3_REMAP_NOREMAP)
00215 
00216 /**
00217   * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
00218   * @note  ENABLE: Full remap     (ETR/PE7,  CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8,  CH2N/PE10, CH3N/PE12)
00219   * @retval None
00220   */
00221 #define __HAL_AFIO_REMAP_TIM1_ENABLE()  MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP)
00222 
00223 /**
00224   * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
00225   * @note  PARTIAL: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9,  CH3/PA10, CH4/PA11, BKIN/PA6,  CH1N/PA7,  CH2N/PB0,  CH3N/PB1)
00226   * @retval None
00227   */
00228 #define __HAL_AFIO_REMAP_TIM1_PARTIAL() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP, AFIO_MAPR_TIM1_REMAP_PARTIALREMAP)
00229 
00230 /**
00231   * @brief Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
00232   * @note  DISABLE: No remap      (ETR/PA12, CH1/PA8, CH2/PA9,  CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15)
00233   * @retval None
00234   */
00235 #define __HAL_AFIO_REMAP_TIM1_DISABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP, AFIO_MAPR_TIM1_REMAP_NOREMAP)
00236 
00237 /**
00238   * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
00239   * @note  ENABLE: Full remap       (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
00240   * @retval None
00241   */
00242 #define __HAL_AFIO_REMAP_TIM2_ENABLE()    MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP)
00243 
00244 /**
00245   * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
00246   * @note  PARTIAL_2: Partial remap (CH1/ETR/PA0,  CH2/PA1, CH3/PB10, CH4/PB11)
00247   * @retval None
00248   */
00249 #define __HAL_AFIO_REMAP_TIM2_PARTIAL_2() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP, AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2)
00250 
00251 /**
00252   * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
00253   * @note  PARTIAL_1: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2,  CH4/PA3)
00254   * @retval None
00255   */
00256 #define __HAL_AFIO_REMAP_TIM2_PARTIAL_1() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP, AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1)
00257 
00258 /**
00259   * @brief Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
00260   * @note  DISABLE: No remap        (CH1/ETR/PA0,  CH2/PA1, CH3/PA2,  CH4/PA3)
00261   * @retval None
00262   */
00263 #define __HAL_AFIO_REMAP_TIM2_DISABLE()   MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP, AFIO_MAPR_TIM2_REMAP_NOREMAP)
00264 
00265 /**
00266   * @brief Enable the remapping of TIM3 alternate function channels 1 to 4
00267   * @note  ENABLE: Full remap     (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)
00268   * @note  TIM3_ETR on PE0 is not re-mapped.
00269   * @retval None
00270   */
00271 #define __HAL_AFIO_REMAP_TIM3_ENABLE()  MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP)
00272 
00273 /**
00274   * @brief Enable the remapping of TIM3 alternate function channels 1 to 4
00275   * @note  PARTIAL: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)
00276   * @note  TIM3_ETR on PE0 is not re-mapped.
00277   * @retval None
00278   */
00279 #define __HAL_AFIO_REMAP_TIM3_PARTIAL() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP, AFIO_MAPR_TIM3_REMAP_PARTIALREMAP)
00280 
00281 /**
00282   * @brief Disable the remapping of TIM3 alternate function channels 1 to 4
00283   * @note  DISABLE: No remap      (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)
00284   * @note  TIM3_ETR on PE0 is not re-mapped.
00285   * @retval None
00286   */
00287 #define __HAL_AFIO_REMAP_TIM3_DISABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP, AFIO_MAPR_TIM3_REMAP_NOREMAP)
00288 
00289 /**
00290   * @brief Enable the remapping of TIM4 alternate function channels 1 to 4.
00291   * @note  ENABLE: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15)
00292   * @note  TIM4_ETR on PE0 is not re-mapped.
00293   * @retval None
00294   */
00295 #define __HAL_AFIO_REMAP_TIM4_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP)
00296 
00297 /**
00298   * @brief Disable the remapping of TIM4 alternate function channels 1 to 4.
00299   * @note  DISABLE: No remap  (TIM4_CH1/PB6,  TIM4_CH2/PB7,  TIM4_CH3/PB8,  TIM4_CH4/PB9)
00300   * @note  TIM4_ETR on PE0 is not re-mapped.
00301   * @retval None
00302   */
00303 #define __HAL_AFIO_REMAP_TIM4_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP)
00304 
00305 #if defined(AFIO_MAPR_CAN_REMAP_REMAP1)
00306 
00307 /**
00308   * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
00309   * @note  CASE 1: CAN_RX mapped to PA11, CAN_TX mapped to PA12
00310   * @retval None
00311   */
00312 #define __HAL_AFIO_REMAP_CAN1_1() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_CAN_REMAP, AFIO_MAPR_CAN_REMAP_REMAP1)
00313 
00314 /**
00315   * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
00316   * @note  CASE 2: CAN_RX mapped to PB8,  CAN_TX mapped to PB9 (not available on 36-pin package)
00317   * @retval None
00318   */
00319 #define __HAL_AFIO_REMAP_CAN1_2() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_CAN_REMAP, AFIO_MAPR_CAN_REMAP_REMAP2)
00320 
00321 /**
00322   * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
00323   * @note  CASE 3: CAN_RX mapped to PD0,  CAN_TX mapped to PD1
00324   * @retval None
00325   */
00326 #define __HAL_AFIO_REMAP_CAN1_3() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_CAN_REMAP, AFIO_MAPR_CAN_REMAP_REMAP3)
00327 #endif
00328 
00329 /**
00330   * @brief Enable the remapping of PD0 and PD1. When the HSE oscillator is not used 
00331   *        (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and 
00332   *        OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available 
00333   *        on 100-pin and 144-pin packages, no need for remapping).
00334   * @note  ENABLE: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT.
00335   * @retval None
00336   */
00337 #define __HAL_AFIO_REMAP_PD01_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP)
00338 
00339 /**
00340   * @brief Disable the remapping of PD0 and PD1. When the HSE oscillator is not used 
00341   *        (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and 
00342   *        OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available 
00343   *        on 100-pin and 144-pin packages, no need for remapping).
00344   * @note  DISABLE: No remapping of PD0 and PD1
00345   * @retval None
00346   */
00347 #define __HAL_AFIO_REMAP_PD01_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP)
00348 
00349 #if defined(AFIO_MAPR_TIM5CH4_IREMAP)
00350 /**
00351   * @brief Enable the remapping of TIM5CH4.
00352   * @note  ENABLE: LSI internal clock is connected to TIM5_CH4 input for calibration purpose.
00353   * @note  This function is available only in high density value line devices.
00354   * @retval None
00355   */
00356 #define __HAL_AFIO_REMAP_TIM5CH4_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP)
00357 
00358 /**
00359   * @brief Disable the remapping of TIM5CH4.
00360   * @note  DISABLE: TIM5_CH4 is connected to PA3
00361   * @note  This function is available only in high density value line devices.
00362   * @retval None
00363   */
00364 #define __HAL_AFIO_REMAP_TIM5CH4_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP)
00365 #endif
00366 
00367 #if defined(AFIO_MAPR_ETH_REMAP)
00368 /**
00369   * @brief Enable the remapping of Ethernet MAC connections with the PHY.
00370   * @note  ENABLE: Remap     (RX_DV-CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PD11, RXD3/PD12)
00371   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
00372   * @retval None
00373   */
00374 #define __HAL_AFIO_REMAP_ETH_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP)
00375 
00376 /**
00377   * @brief Disable the remapping of Ethernet MAC connections with the PHY.
00378   * @note  DISABLE: No remap (RX_DV-CRS_DV/PA7, RXD0/PC4, RXD1/PC5,  RXD2/PB0,  RXD3/PB1)
00379   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
00380   * @retval None
00381   */
00382 #define __HAL_AFIO_REMAP_ETH_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP)
00383 #endif
00384 
00385 #if defined(AFIO_MAPR_CAN2_REMAP)
00386 
00387 /**
00388   * @brief Enable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
00389   * @note  ENABLE: Remap     (CAN2_RX/PB5,  CAN2_TX/PB6)
00390   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
00391   * @retval None
00392   */
00393 #define __HAL_AFIO_REMAP_CAN2_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP)
00394 
00395 /**
00396   * @brief Disable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
00397   * @note  DISABLE: No remap (CAN2_RX/PB12, CAN2_TX/PB13)
00398   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
00399   * @retval None
00400   */
00401 #define __HAL_AFIO_REMAP_CAN2_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP)
00402 #endif
00403 
00404 #if defined(AFIO_MAPR_MII_RMII_SEL)
00405 /**
00406   * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
00407   * @note  ETH_RMII: Configure Ethernet MAC for connection with an RMII PHY
00408   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
00409   * @retval None
00410   */
00411 #define __HAL_AFIO_ETH_RMII() SET_BIT(AFIO->MAPR, AFIO_MAPR_MII_RMII_SEL)
00412 
00413 /**
00414   * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
00415   * @note  ETH_MII: Configure Ethernet MAC for connection with an MII PHY
00416   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
00417   * @retval None
00418   */
00419 #define __HAL_AFIO_ETH_MII()  CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_MII_RMII_SEL)
00420 #endif
00421 
00422 /**
00423   * @brief Enable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
00424   * @note  ENABLE: ADC1 External Event injected conversion is connected to TIM8 Channel4.
00425   * @retval None
00426   */
00427 #define __HAL_AFIO_REMAP_ADC1_ETRGINJ_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP)
00428 
00429 /**
00430   * @brief Disable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
00431   * @note  DISABLE: ADC1 External trigger injected conversion is connected to EXTI15
00432   * @retval None
00433   */
00434 #define __HAL_AFIO_REMAP_ADC1_ETRGINJ_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP)
00435 
00436 /**
00437   * @brief Enable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
00438   * @note  ENABLE: ADC1 External Event regular conversion is connected to TIM8 TRG0.
00439   * @retval None
00440   */
00441 #define __HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP)
00442 
00443 /**
00444   * @brief Disable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
00445   * @note  DISABLE: ADC1 External trigger regular conversion is connected to EXTI11
00446   * @retval None
00447   */
00448 #define __HAL_AFIO_REMAP_ADC1_ETRGREG_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP)
00449 
00450 #if defined(AFIO_MAPR_ADC2_ETRGINJ_REMAP)
00451 
00452 /**
00453   * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
00454   * @note  ENABLE: ADC2 External Event injected conversion is connected to TIM8 Channel4.
00455   * @retval None
00456   */
00457 #define __HAL_AFIO_REMAP_ADC2_ETRGINJ_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP)
00458 
00459 /**
00460   * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
00461   * @note  DISABLE: ADC2 External trigger injected conversion is connected to EXTI15
00462   * @retval None
00463   */
00464 #define __HAL_AFIO_REMAP_ADC2_ETRGINJ_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP)
00465 #endif
00466 
00467 #if defined (AFIO_MAPR_ADC2_ETRGREG_REMAP)
00468 
00469 /**
00470   * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
00471   * @note  ENABLE: ADC2 External Event regular conversion is connected to TIM8 TRG0.
00472   * @retval None
00473   */
00474 #define __HAL_AFIO_REMAP_ADC2_ETRGREG_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP)
00475 
00476 /**
00477   * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
00478   * @note  DISABLE: ADC2 External trigger regular conversion is connected to EXTI11
00479   * @retval None
00480   */
00481 #define __HAL_AFIO_REMAP_ADC2_ETRGREG_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP)
00482 #endif
00483 
00484 /**
00485   * @brief Enable the Serial wire JTAG configuration
00486   * @note  ENABLE: Full SWJ (JTAG-DP + SW-DP): Reset State
00487   * @retval None
00488   */
00489 #define __HAL_AFIO_REMAP_SWJ_ENABLE()   MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_RESET)
00490 
00491 /**
00492   * @brief Enable the Serial wire JTAG configuration
00493   * @note  NONJTRST: Full SWJ (JTAG-DP + SW-DP) but without NJTRST
00494   * @retval None
00495   */
00496 #define __HAL_AFIO_REMAP_SWJ_NONJTRST() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_NOJNTRST)
00497 
00498 /**
00499   * @brief Enable the Serial wire JTAG configuration
00500   * @note  NOJTAG: JTAG-DP Disabled and SW-DP Enabled
00501   * @retval None
00502   */
00503 #define __HAL_AFIO_REMAP_SWJ_NOJTAG()   MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_JTAGDISABLE)
00504 
00505 /**
00506   * @brief Disable the Serial wire JTAG configuration
00507   * @note  DISABLE: JTAG-DP Disabled and SW-DP Disabled
00508   * @retval None
00509   */
00510 #define __HAL_AFIO_REMAP_SWJ_DISABLE()  MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_DISABLE)
00511 
00512 #if defined(AFIO_MAPR_SPI3_REMAP)
00513 
00514 /**
00515   * @brief Enable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
00516   * @note  ENABLE: Remap     (SPI3_NSS-I2S3_WS/PA4,  SPI3_SCK-I2S3_CK/PC10, SPI3_MISO/PC11, SPI3_MOSI-I2S3_SD/PC12)
00517   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
00518   * @retval None
00519   */
00520 #define __HAL_AFIO_REMAP_SPI3_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP)
00521 
00522 /**
00523   * @brief Disable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
00524   * @note  DISABLE: No remap (SPI3_NSS-I2S3_WS/PA15, SPI3_SCK-I2S3_CK/PB3,  SPI3_MISO/PB4,  SPI3_MOSI-I2S3_SD/PB5).
00525   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
00526   * @retval None
00527   */
00528 #define __HAL_AFIO_REMAP_SPI3_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP)
00529 #endif
00530 
00531 #if defined(AFIO_MAPR_TIM2ITR1_IREMAP)
00532 
00533 /**
00534   * @brief Control of TIM2_ITR1 internal mapping.
00535   * @note  TO_USB: Connect USB OTG SOF (Start of Frame) output to TIM2_ITR1 for calibration purposes.
00536   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
00537   * @retval None
00538   */
00539 #define __HAL_AFIO_TIM2ITR1_TO_USB() SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2ITR1_IREMAP)
00540 
00541 /**
00542   * @brief Control of TIM2_ITR1 internal mapping.
00543   * @note  TO_ETH: Connect TIM2_ITR1 internally to the Ethernet PTP output for calibration purposes.
00544   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
00545   * @retval None
00546   */
00547 #define __HAL_AFIO_TIM2ITR1_TO_ETH() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2ITR1_IREMAP)
00548 #endif
00549 
00550 #if defined(AFIO_MAPR_PTP_PPS_REMAP)
00551 
00552 /**
00553   * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
00554   * @note  ENABLE: PTP_PPS is output on PB5 pin.
00555   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
00556   * @retval None
00557   */
00558 #define __HAL_AFIO_ETH_PTP_PPS_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_PTP_PPS_REMAP)
00559 
00560 /**
00561   * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
00562   * @note  DISABLE: PTP_PPS not output on PB5 pin.
00563   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
00564   * @retval None
00565   */
00566 #define __HAL_AFIO_ETH_PTP_PPS_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_PTP_PPS_REMAP)
00567 #endif
00568 
00569 #if defined(AFIO_MAPR2_TIM9_REMAP)
00570 
00571 /**
00572   * @brief Enable the remapping of TIM9_CH1 and TIM9_CH2.
00573   * @note  ENABLE: Remap     (TIM9_CH1 on PE5 and TIM9_CH2 on PE6).
00574   * @retval None
00575   */
00576 #define __HAL_AFIO_REMAP_TIM9_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP)
00577 
00578 /**
00579   * @brief Disable the remapping of TIM9_CH1 and TIM9_CH2.
00580   * @note  DISABLE: No remap (TIM9_CH1 on PA2 and TIM9_CH2 on PA3).
00581   * @retval None
00582   */
00583 #define __HAL_AFIO_REMAP_TIM9_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP)
00584 #endif
00585 
00586 #if defined(AFIO_MAPR2_TIM10_REMAP)
00587 
00588 /**
00589   * @brief Enable the remapping of TIM10_CH1.
00590   * @note  ENABLE: Remap     (TIM10_CH1 on PF6).
00591   * @retval None
00592   */
00593 #define __HAL_AFIO_REMAP_TIM10_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP)
00594 
00595 /**
00596   * @brief Disable the remapping of TIM10_CH1.
00597   * @note  DISABLE: No remap (TIM10_CH1 on PB8).
00598   * @retval None
00599   */
00600 #define __HAL_AFIO_REMAP_TIM10_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP)
00601 #endif
00602 
00603 #if defined(AFIO_MAPR2_TIM11_REMAP)
00604 /**
00605   * @brief Enable the remapping of TIM11_CH1.
00606   * @note  ENABLE: Remap     (TIM11_CH1 on PF7).
00607   * @retval None
00608   */
00609 #define __HAL_AFIO_REMAP_TIM11_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP)
00610 
00611 /**
00612   * @brief Disable the remapping of TIM11_CH1.
00613   * @note  DISABLE: No remap (TIM11_CH1 on PB9).
00614   * @retval None
00615   */
00616 #define __HAL_AFIO_REMAP_TIM11_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP)
00617 #endif
00618 
00619 #if defined(AFIO_MAPR2_TIM13_REMAP)
00620 
00621 /**
00622   * @brief Enable the remapping of TIM13_CH1.
00623   * @note  ENABLE: Remap     STM32F100:(TIM13_CH1 on PF8). Others:(TIM13_CH1 on PB0).
00624   * @retval None
00625   */
00626 #define __HAL_AFIO_REMAP_TIM13_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP)
00627 
00628 /**
00629   * @brief Disable the remapping of TIM13_CH1.
00630   * @note  DISABLE: No remap STM32F100:(TIM13_CH1 on PA6). Others:(TIM13_CH1 on PC8).
00631   * @retval None
00632   */
00633 #define __HAL_AFIO_REMAP_TIM13_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP)
00634 #endif
00635 
00636 #if defined(AFIO_MAPR2_TIM14_REMAP)
00637 
00638 /**
00639   * @brief Enable the remapping of TIM14_CH1.
00640   * @note  ENABLE: Remap     STM32F100:(TIM14_CH1 on PB1). Others:(TIM14_CH1 on PF9).
00641   * @retval None
00642   */
00643 #define __HAL_AFIO_REMAP_TIM14_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP)
00644 
00645 /**
00646   * @brief Disable the remapping of TIM14_CH1.
00647   * @note  DISABLE: No remap STM32F100:(TIM14_CH1 on PC9). Others:(TIM14_CH1 on PA7).
00648   * @retval None
00649   */
00650 #define __HAL_AFIO_REMAP_TIM14_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP)
00651 #endif
00652 
00653 #if defined(AFIO_MAPR2_FSMC_NADV_REMAP)
00654 
00655 /**
00656   * @brief Controls the use of the optional FSMC_NADV signal.
00657   * @note  DISCONNECTED: The NADV signal is not connected. The I/O pin can be used by another peripheral.
00658   * @retval None
00659   */
00660 #define __HAL_AFIO_FSMCNADV_DISCONNECTED() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP)
00661 
00662 /**
00663   * @brief Controls the use of the optional FSMC_NADV signal.
00664   * @note  CONNECTED: The NADV signal is connected to the output (default).
00665   * @retval None
00666   */
00667 #define __HAL_AFIO_FSMCNADV_CONNECTED()    CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP)
00668 #endif
00669 
00670 #if defined(AFIO_MAPR2_TIM15_REMAP)
00671 
00672 /**
00673   * @brief Enable the remapping of TIM15_CH1 and TIM15_CH2.
00674   * @note  ENABLE: Remap     (TIM15_CH1 on PB14 and TIM15_CH2 on PB15).
00675   * @retval None
00676   */
00677 #define __HAL_AFIO_REMAP_TIM15_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP)
00678 
00679 /**
00680   * @brief Disable the remapping of TIM15_CH1 and TIM15_CH2.
00681   * @note  DISABLE: No remap (TIM15_CH1 on PA2  and TIM15_CH2 on PA3).
00682   * @retval None
00683   */
00684 #define __HAL_AFIO_REMAP_TIM15_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP)
00685 #endif
00686 
00687 #if defined(AFIO_MAPR2_TIM16_REMAP)
00688 
00689 /**
00690   * @brief Enable the remapping of TIM16_CH1.
00691   * @note  ENABLE: Remap     (TIM16_CH1 on PA6).
00692   * @retval None
00693   */
00694 #define __HAL_AFIO_REMAP_TIM16_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP)
00695 
00696 /**
00697   * @brief Disable the remapping of TIM16_CH1.
00698   * @note  DISABLE: No remap (TIM16_CH1 on PB8).
00699   * @retval None
00700   */
00701 #define __HAL_AFIO_REMAP_TIM16_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP)
00702 #endif
00703 
00704 #if defined(AFIO_MAPR2_TIM17_REMAP)
00705 
00706 /**
00707   * @brief Enable the remapping of TIM17_CH1.
00708   * @note  ENABLE: Remap     (TIM17_CH1 on PA7).
00709   * @retval None
00710   */
00711 #define __HAL_AFIO_REMAP_TIM17_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP)
00712 
00713 /**
00714   * @brief Disable the remapping of TIM17_CH1.
00715   * @note  DISABLE: No remap (TIM17_CH1 on PB9).
00716   * @retval None
00717   */
00718 #define __HAL_AFIO_REMAP_TIM17_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP)
00719 #endif
00720 
00721 #if defined(AFIO_MAPR2_CEC_REMAP)
00722 
00723 /**
00724   * @brief Enable the remapping of CEC.
00725   * @note  ENABLE: Remap     (CEC on PB10).
00726   * @retval None
00727   */
00728 #define __HAL_AFIO_REMAP_CEC_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP)
00729 
00730 /**
00731   * @brief Disable the remapping of CEC.
00732   * @note  DISABLE: No remap (CEC on PB8).
00733   * @retval None
00734   */
00735 #define __HAL_AFIO_REMAP_CEC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP)
00736 #endif
00737 
00738 #if defined(AFIO_MAPR2_TIM1_DMA_REMAP)
00739 
00740 /**
00741   * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.
00742   * @note  ENABLE: Remap (TIM1_CH1 DMA request/DMA1 Channel6, TIM1_CH2 DMA request/DMA1 Channel6)
00743   * @retval None
00744   */
00745 #define __HAL_AFIO_REMAP_TIM1DMA_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP)
00746 
00747 /**
00748   * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.
00749   * @note  DISABLE: No remap (TIM1_CH1 DMA request/DMA1 Channel2, TIM1_CH2 DMA request/DMA1 Channel3).
00750   * @retval None
00751   */
00752 #define __HAL_AFIO_REMAP_TIM1DMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP)
00753 #endif
00754 
00755 #if defined(AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
00756 
00757 /**
00758   * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.
00759   * @note  ENABLE: Remap (TIM6_DAC1 DMA request/DMA1 Channel3, TIM7_DAC2 DMA request/DMA1 Channel4)
00760   * @retval None
00761   */
00762 #define __HAL_AFIO_REMAP_TIM67DACDMA_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
00763 
00764 /**
00765   * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.
00766   * @note  DISABLE: No remap (TIM6_DAC1 DMA request/DMA2 Channel3, TIM7_DAC2 DMA request/DMA2 Channel4)
00767   * @retval None
00768   */
00769 #define __HAL_AFIO_REMAP_TIM67DACDMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
00770 #endif
00771 
00772 #if defined(AFIO_MAPR2_TIM12_REMAP)
00773 
00774 /**
00775   * @brief Enable the remapping of TIM12_CH1 and TIM12_CH2.
00776   * @note  ENABLE: Remap     (TIM12_CH1 on PB12 and TIM12_CH2 on PB13).
00777   * @note  This bit is available only in high density value line devices.
00778   * @retval None
00779   */
00780 #define __HAL_AFIO_REMAP_TIM12_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP)
00781 
00782 /**
00783   * @brief Disable the remapping of TIM12_CH1 and TIM12_CH2.
00784   * @note  DISABLE: No remap (TIM12_CH1 on PC4  and TIM12_CH2 on PC5).
00785   * @note  This bit is available only in high density value line devices.
00786   * @retval None
00787   */
00788 #define __HAL_AFIO_REMAP_TIM12_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP)
00789 #endif
00790 
00791 #if defined(AFIO_MAPR2_MISC_REMAP)
00792 
00793 /**
00794   * @brief Miscellaneous features remapping.
00795   *        This bit is set and cleared by software. It controls miscellaneous features.
00796   *        The DMA2 channel 5 interrupt position in the vector table.
00797   *        The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).
00798   * @note  ENABLE: DMA2 channel 5 interrupt is mapped separately at position 60 and TIM15 TRGO event is
00799   *        selected as DAC Trigger 3, TIM15 triggers TIM1/3.
00800   * @note  This bit is available only in high density value line devices.
00801   * @retval None
00802   */
00803 #define __HAL_AFIO_REMAP_MISC_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP)
00804 
00805 /**
00806   * @brief Miscellaneous features remapping.
00807   *        This bit is set and cleared by software. It controls miscellaneous features.
00808   *        The DMA2 channel 5 interrupt position in the vector table.
00809   *        The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).
00810   * @note  DISABLE: DMA2 channel 5 interrupt is mapped with DMA2 channel 4 at position 59, TIM5 TRGO
00811   *        event is selected as DAC Trigger 3, TIM5 triggers TIM1/3.
00812   * @note  This bit is available only in high density value line devices.
00813   * @retval None
00814   */
00815 #define __HAL_AFIO_REMAP_MISC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP)
00816 #endif
00817 
00818 /**
00819   * @}
00820   */ 
00821   
00822 /**
00823   * @}
00824   */
00825   
00826 /** @defgroup GPIOEx_Private_Macros GPIOEx Private Macros
00827   * @{
00828   */
00829 #if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)
00830 #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
00831                                    ((__GPIOx__) == (GPIOB))? 1U :\
00832                                    ((__GPIOx__) == (GPIOC))? 2U :3U)
00833 #elif defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC)
00834 #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
00835                                    ((__GPIOx__) == (GPIOB))? 1U :\
00836                                    ((__GPIOx__) == (GPIOC))? 2U :\
00837                                    ((__GPIOx__) == (GPIOD))? 3U :4U)
00838 #elif defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
00839 #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
00840                                    ((__GPIOx__) == (GPIOB))? 1U :\
00841                                    ((__GPIOx__) == (GPIOC))? 2U :\
00842                                    ((__GPIOx__) == (GPIOD))? 3U :\
00843                                    ((__GPIOx__) == (GPIOE))? 4U :\
00844                                    ((__GPIOx__) == (GPIOF))? 5U :6U)
00845 #endif
00846 
00847 /**
00848   * @}
00849   */
00850 
00851 /* Exported macro ------------------------------------------------------------*/
00852 /* Exported functions --------------------------------------------------------*/
00853 
00854 /** @addtogroup GPIOEx_Exported_Functions
00855   * @{
00856   */
00857 
00858 /** @addtogroup GPIOEx_Exported_Functions_Group1
00859   * @{
00860   */
00861 void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource);
00862 void HAL_GPIOEx_EnableEventout(void);
00863 void HAL_GPIOEx_DisableEventout(void);
00864 
00865 /**
00866   * @}
00867   */ 
00868 
00869 /**
00870   * @}
00871   */ 
00872 
00873 /**
00874   * @}
00875   */ 
00876 
00877 /**
00878   * @}
00879   */ 
00880   
00881 #ifdef __cplusplus
00882 }
00883 #endif
00884 
00885 #endif /* __STM32F1xx_HAL_GPIO_EX_H */
00886 
00887 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/