stm32f1xx_hal_gpio.c

00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_gpio.c
00004   * @author  MCD Application Team
00005   * @version V1.0.4
00006   * @date    29-April-2016
00007   * @brief   GPIO HAL module driver.
00008   *         This file provides firmware functions to manage the following 
00009   *          functionalities of the General Purpose Input/Output (GPIO) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *         
00013   @verbatim
00014   ==============================================================================
00015                     ##### GPIO Peripheral features #####
00016   ==============================================================================         
00017   [..] 
00018   Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
00019   port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software
00020   in several modes:
00021   (+) Input mode 
00022   (+) Analog mode
00023   (+) Output mode
00024   (+) Alternate function mode
00025   (+) External interrupt/event lines
00026 
00027   [..]  
00028   During and just after reset, the alternate functions and external interrupt  
00029   lines are not active and the I/O ports are configured in input floating mode.
00030   
00031   [..]   
00032   All GPIO pins have weak internal pull-up and pull-down resistors, which can be 
00033   activated or not.
00034 
00035   [..]
00036   In Output or Alternate mode, each IO can be configured on open-drain or push-pull
00037   type and the IO speed can be selected depending on the VDD value.
00038 
00039   [..]  
00040   All ports have external interrupt/event capability. To use external interrupt 
00041   lines, the port must be configured in input mode. All available GPIO pins are 
00042   connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
00043   
00044   [..]  
00045   The external interrupt/event controller consists of up to 20 edge detectors in connectivity
00046   line devices, or 19 edge detectors in other devices for generating event/interrupt requests.
00047   Each input line can be independently configured to select the type (event or interrupt) and
00048   the corresponding trigger event (rising or falling or both). Each line can also masked
00049   independently. A pending register maintains the status line of the interrupt requests
00050  
00051                      ##### How to use this driver #####
00052   ==============================================================================  
00053  [..]             
00054    (#) Enable the GPIO APB2 clock using the following function : __HAL_RCC_GPIOx_CLK_ENABLE(). 
00055    
00056    (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
00057        (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
00058        (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef 
00059             structure.
00060        (++) In case of Output or alternate function mode selection: the speed is 
00061             configured through "Speed" member from GPIO_InitTypeDef structure
00062        (++) Analog mode is required when a pin is to be used as ADC channel 
00063             or DAC output.
00064        (++) In case of external interrupt/event selection the "Mode" member from 
00065             GPIO_InitTypeDef structure select the type (interrupt or event) and 
00066             the corresponding trigger event (rising or falling or both).
00067    
00068    (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority 
00069        mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
00070        HAL_NVIC_EnableIRQ().
00071          
00072    (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
00073             
00074    (#) To set/reset the level of a pin configured in output mode use 
00075        HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
00076   
00077    (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
00078                  
00079    (#) During and just after reset, the alternate functions are not 
00080        active and the GPIO pins are configured in input floating mode (except JTAG
00081        pins).
00082   
00083    (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose 
00084        (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has 
00085        priority over the GPIO function.
00086   
00087    (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as 
00088        general purpose PD0 and PD1, respectively, when the HSE oscillator is off. 
00089        The HSE has priority over the GPIO function.
00090   
00091   @endverbatim
00092   ******************************************************************************
00093   * @attention
00094   *
00095   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00096   *
00097   * Redistribution and use in source and binary forms, with or without modification,
00098   * are permitted provided that the following conditions are met:
00099   *   1. Redistributions of source code must retain the above copyright notice,
00100   *      this list of conditions and the following disclaimer.
00101   *   2. Redistributions in binary form must reproduce the above copyright notice,
00102   *      this list of conditions and the following disclaimer in the documentation
00103   *      and/or other materials provided with the distribution.
00104   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00105   *      may be used to endorse or promote products derived from this software
00106   *      without specific prior written permission.
00107   *
00108   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00109   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00110   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00111   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00112   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00113   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00114   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00115   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00116   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00117   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00118   *
00119   ******************************************************************************  
00120   */ 
00121 
00122 /* Includes ------------------------------------------------------------------*/
00123 #include "stm32f1xx_hal.h"
00124 
00125 /** @addtogroup STM32F1xx_HAL_Driver
00126   * @{
00127   */
00128 
00129 /** @defgroup GPIO GPIO
00130   * @brief GPIO HAL module driver
00131   * @{
00132   */
00133 
00134 #ifdef HAL_GPIO_MODULE_ENABLED
00135 
00136 /* Private typedef -----------------------------------------------------------*/
00137 /* Private define ------------------------------------------------------------*/
00138 /** @defgroup GPIO_Private_Constants GPIO Private Constants
00139   * @{
00140   */
00141   
00142 #define GPIO_MODE             ((uint32_t)0x00000003)
00143 #define EXTI_MODE             ((uint32_t)0x10000000)
00144 #define GPIO_MODE_IT          ((uint32_t)0x00010000)
00145 #define GPIO_MODE_EVT         ((uint32_t)0x00020000)
00146 #define RISING_EDGE           ((uint32_t)0x00100000) 
00147 #define FALLING_EDGE          ((uint32_t)0x00200000) 
00148 #define GPIO_OUTPUT_TYPE      ((uint32_t)0x00000010) 
00149 #define GPIO_NUMBER           ((uint32_t)16)
00150 
00151 /* Definitions for bit manipulation of CRL and CRH register */
00152 #define  GPIO_CR_MODE_INPUT         ((uint32_t)0x00000000) /*!< 00: Input mode (reset state)  */
00153 #define  GPIO_CR_CNF_ANALOG         ((uint32_t)0x00000000) /*!< 00: Analog mode  */
00154 #define  GPIO_CR_CNF_INPUT_FLOATING ((uint32_t)0x00000004) /*!< 01: Floating input (reset state)  */
00155 #define  GPIO_CR_CNF_INPUT_PU_PD    ((uint32_t)0x00000008) /*!< 10: Input with pull-up / pull-down  */
00156 #define  GPIO_CR_CNF_GP_OUTPUT_PP   ((uint32_t)0x00000000) /*!< 00: General purpose output push-pull  */
00157 #define  GPIO_CR_CNF_GP_OUTPUT_OD   ((uint32_t)0x00000004) /*!< 01: General purpose output Open-drain  */
00158 #define  GPIO_CR_CNF_AF_OUTPUT_PP   ((uint32_t)0x00000008) /*!< 10: Alternate function output Push-pull  */
00159 #define  GPIO_CR_CNF_AF_OUTPUT_OD   ((uint32_t)0x0000000C) /*!< 11: Alternate function output Open-drain  */
00160  
00161 /**
00162   * @}
00163   */
00164 
00165 /* Private macro -------------------------------------------------------------*/
00166 /* Private variables ---------------------------------------------------------*/
00167 /* Private function prototypes -----------------------------------------------*/
00168 /* Private functions ---------------------------------------------------------*/
00169 
00170 /** @defgroup GPIO_Exported_Functions GPIO Exported Functions
00171   * @{
00172   */
00173 
00174 /** @defgroup GPIO_Exported_Functions_Group1 Initialization and deinitialization functions
00175  *  @brief    Initialization and Configuration functions
00176  *
00177 @verbatim    
00178  ===============================================================================
00179               ##### Initialization and deinitialization functions #####
00180  ===============================================================================
00181   [..]
00182     This section provides functions allowing to initialize and de-initialize the GPIOs
00183     to be ready for use.
00184  
00185 @endverbatim
00186   * @{
00187   */
00188 
00189 /**
00190   * @brief  Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
00191   * @param  GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
00192   * @param  GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
00193   *         the configuration information for the specified GPIO peripheral.
00194   * @retval None
00195   */
00196 void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
00197 {
00198   uint32_t position;
00199   uint32_t ioposition = 0x00;
00200   uint32_t iocurrent = 0x00;
00201   uint32_t temp = 0x00;
00202   uint32_t config = 0x00;
00203   __IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */
00204   uint32_t registeroffset = 0; /* offset used during computation of CNF and MODE bits placement inside CRL or CRH register */
00205   
00206   /* Check the parameters */
00207   assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
00208   assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
00209   assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
00210 
00211   /* Configure the port pins */
00212   for (position = 0; position < GPIO_NUMBER; position++)
00213   {
00214     /* Get the IO position */
00215     ioposition = ((uint32_t)0x01) << position;
00216     
00217     /* Get the current IO position */
00218     iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
00219 
00220     if (iocurrent == ioposition)
00221     {
00222       /* Check the Alternate function parameters */
00223       assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
00224 
00225       /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */
00226       switch (GPIO_Init->Mode)
00227       {
00228         /* If we are configuring the pin in OUTPUT push-pull mode */
00229         case GPIO_MODE_OUTPUT_PP:
00230           /* Check the GPIO speed parameter */
00231           assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
00232           config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP;
00233           break;
00234           
00235         /* If we are configuring the pin in OUTPUT open-drain mode */
00236         case GPIO_MODE_OUTPUT_OD:
00237           /* Check the GPIO speed parameter */
00238           assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
00239           config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD;
00240           break;
00241           
00242         /* If we are configuring the pin in ALTERNATE FUNCTION push-pull mode */
00243         case GPIO_MODE_AF_PP:
00244           /* Check the GPIO speed parameter */
00245           assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
00246           config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP;
00247           break;
00248           
00249         /* If we are configuring the pin in ALTERNATE FUNCTION open-drain mode */
00250         case GPIO_MODE_AF_OD:
00251           /* Check the GPIO speed parameter */
00252           assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
00253           config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD;
00254           break;
00255           
00256         /* If we are configuring the pin in INPUT (also applicable to EVENT and IT mode) */
00257         case GPIO_MODE_INPUT:
00258         case GPIO_MODE_IT_RISING:
00259         case GPIO_MODE_IT_FALLING:
00260         case GPIO_MODE_IT_RISING_FALLING:
00261         case GPIO_MODE_EVT_RISING:
00262         case GPIO_MODE_EVT_FALLING:
00263         case GPIO_MODE_EVT_RISING_FALLING:
00264           /* Check the GPIO pull parameter */
00265           assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
00266           if(GPIO_Init->Pull == GPIO_NOPULL)
00267           {  
00268             config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING;
00269           }
00270           else if(GPIO_Init->Pull == GPIO_PULLUP)
00271           {
00272             config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
00273             
00274             /* Set the corresponding ODR bit */
00275             GPIOx->BSRR = ioposition;
00276           }
00277           else /* GPIO_PULLDOWN */
00278           {
00279             config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
00280             
00281             /* Reset the corresponding ODR bit */
00282             GPIOx->BRR = ioposition;
00283           }
00284           break; 
00285           
00286         /* If we are configuring the pin in INPUT analog mode */
00287         case GPIO_MODE_ANALOG:
00288             config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
00289           break;
00290         
00291         /* Parameters are checked with assert_param */
00292         default:
00293           break;
00294       }
00295       
00296       /* Check if the current bit belongs to first half or last half of the pin count number
00297        in order to address CRH or CRL register*/
00298       configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL     : &GPIOx->CRH;
00299       registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2) : ((position - 8) << 2);
00300       
00301       /* Apply the new configuration of the pin to the register */
00302       MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset ), (config << registeroffset));
00303       
00304       /*--------------------- EXTI Mode Configuration ------------------------*/
00305       /* Configure the External Interrupt or event for the current IO */
00306       if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) 
00307       {
00308         /* Enable AFIO Clock */
00309         __HAL_RCC_AFIO_CLK_ENABLE();
00310         temp = AFIO->EXTICR[position >> 2];
00311         CLEAR_BIT(temp, ((uint32_t)0x0F) << (4 * (position & 0x03)));
00312         SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
00313         AFIO->EXTICR[position >> 2] = temp;
00314         
00315 
00316         /* Configure the interrupt mask */
00317         if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
00318         {
00319           SET_BIT(EXTI->IMR, iocurrent); 
00320         } 
00321         else
00322         {
00323           CLEAR_BIT(EXTI->IMR, iocurrent); 
00324         } 
00325         
00326         /* Configure the event mask */
00327         if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
00328         {
00329           SET_BIT(EXTI->EMR, iocurrent); 
00330         } 
00331         else
00332         {
00333           CLEAR_BIT(EXTI->EMR, iocurrent); 
00334         }
00335         
00336         /* Enable or disable the rising trigger */
00337         if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
00338         {
00339           SET_BIT(EXTI->RTSR, iocurrent); 
00340         } 
00341         else
00342         {
00343           CLEAR_BIT(EXTI->RTSR, iocurrent); 
00344         }
00345         
00346         /* Enable or disable the falling trigger */
00347         if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
00348         {
00349           SET_BIT(EXTI->FTSR, iocurrent); 
00350         } 
00351         else
00352         {
00353           CLEAR_BIT(EXTI->FTSR, iocurrent); 
00354         }
00355       }
00356     }
00357   }
00358 }
00359 
00360 /**
00361   * @brief  De-initializes the GPIOx peripheral registers to their default reset values.
00362   * @param  GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
00363   * @param  GPIO_Pin: specifies the port bit to be written.
00364   *         This parameter can be one of GPIO_PIN_x where x can be (0..15).
00365   * @retval None
00366   */
00367 void HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)
00368 { 
00369   uint32_t position = 0x00;
00370   uint32_t iocurrent = 0x00;
00371   uint32_t tmp = 0x00;
00372   __IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */
00373   uint32_t registeroffset = 0;
00374  
00375   /* Check the parameters */
00376   assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
00377   assert_param(IS_GPIO_PIN(GPIO_Pin));
00378 
00379   /* Configure the port pins */
00380   while ((GPIO_Pin >> position) != 0)
00381   {
00382     /* Get current io position */
00383     iocurrent = (GPIO_Pin) & ((uint32_t)1 << position);
00384 
00385     if (iocurrent)
00386     {
00387       /*------------------------- GPIO Mode Configuration --------------------*/
00388       /* Check if the current bit belongs to first half or last half of the pin count number
00389        in order to address CRH or CRL register */
00390       configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL     : &GPIOx->CRH;
00391       registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2) : ((position - 8) << 2);
00392       
00393       /* CRL/CRH default value is floating input(0x04) shifted to correct position */
00394       MODIFY_REG(*configregister, ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset ), GPIO_CRL_CNF0_0 << registeroffset);
00395       
00396       /* ODR default value is 0 */
00397       CLEAR_BIT(GPIOx->ODR, iocurrent);
00398       
00399       /*------------------------- EXTI Mode Configuration --------------------*/
00400       /* Clear the External Interrupt or Event for the current IO */
00401       
00402       tmp = AFIO->EXTICR[position >> 2];
00403       tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03)));
00404       if(tmp == (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03))))
00405       {
00406         tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));
00407         CLEAR_BIT(AFIO->EXTICR[position >> 2], tmp);
00408           
00409         /* Clear EXTI line configuration */
00410         CLEAR_BIT(EXTI->IMR, (uint32_t)iocurrent);
00411         CLEAR_BIT(EXTI->EMR, (uint32_t)iocurrent);
00412         
00413         /* Clear Rising Falling edge configuration */
00414         CLEAR_BIT(EXTI->RTSR, (uint32_t)iocurrent);
00415         CLEAR_BIT(EXTI->FTSR, (uint32_t)iocurrent);
00416       }
00417     }
00418     
00419     position++;
00420   }
00421 }
00422 
00423 /**
00424   * @}
00425   */
00426 
00427 /** @defgroup GPIO_Exported_Functions_Group2 IO operation functions 
00428  *  @brief   GPIO Read and Write 
00429  *
00430 @verbatim   
00431  ===============================================================================
00432                        ##### IO operation functions #####
00433  ===============================================================================
00434   [..]
00435     This subsection provides a set of functions allowing to manage the GPIOs.
00436 
00437 @endverbatim
00438   * @{
00439   */
00440 /**
00441   * @brief  Reads the specified input port pin.
00442   * @param  GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
00443   * @param  GPIO_Pin: specifies the port bit to read.
00444   *         This parameter can be GPIO_PIN_x where x can be (0..15).
00445   * @retval The input port pin value.
00446   */
00447 GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
00448 {
00449   GPIO_PinState bitstatus;
00450 
00451   /* Check the parameters */
00452   assert_param(IS_GPIO_PIN(GPIO_Pin));
00453 
00454   if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
00455   {
00456     bitstatus = GPIO_PIN_SET;
00457   }
00458   else
00459   {
00460     bitstatus = GPIO_PIN_RESET;
00461   }
00462   return bitstatus;
00463 }
00464 
00465 /**
00466   * @brief  Sets or clears the selected data port bit.
00467   * 
00468   * @note   This function uses GPIOx_BSRR register to allow atomic read/modify 
00469   *         accesses. In this way, there is no risk of an IRQ occurring between
00470   *         the read and the modify access.
00471   *               
00472   * @param  GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
00473   * @param  GPIO_Pin: specifies the port bit to be written.
00474   *          This parameter can be one of GPIO_PIN_x where x can be (0..15).
00475   * @param  PinState: specifies the value to be written to the selected bit.
00476   *          This parameter can be one of the GPIO_PinState enum values:
00477   *            @arg GPIO_BIT_RESET: to clear the port pin
00478   *            @arg GPIO_BIT_SET: to set the port pin
00479   * @retval None
00480   */
00481 void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
00482 {
00483   /* Check the parameters */
00484   assert_param(IS_GPIO_PIN(GPIO_Pin));
00485   assert_param(IS_GPIO_PIN_ACTION(PinState));
00486 
00487   if(PinState != GPIO_PIN_RESET)
00488   {
00489     GPIOx->BSRR = GPIO_Pin;
00490   }
00491   else
00492   {
00493     GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;
00494   }
00495 }
00496 
00497 /**
00498   * @brief  Toggles the specified GPIO pin
00499   * @param  GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral 
00500   * @param  GPIO_Pin: Specifies the pins to be toggled.
00501   * @retval None
00502   */
00503 void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
00504 {
00505   /* Check the parameters */
00506   assert_param(IS_GPIO_PIN(GPIO_Pin));
00507 
00508   GPIOx->ODR ^= GPIO_Pin;
00509 }
00510 
00511 /**
00512 * @brief  Locks GPIO Pins configuration registers.
00513 * @note   The locking mechanism allows the IO configuration to be frozen. When the LOCK sequence
00514 *         has been applied on a port bit, it is no longer possible to modify the value of the port bit until
00515 *         the next reset.
00516 * @param  GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
00517 * @param  GPIO_Pin: specifies the port bit to be locked.
00518 *         This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
00519 * @retval None
00520 */
00521 HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
00522 {
00523   __IO uint32_t tmp = GPIO_LCKR_LCKK;
00524 
00525   /* Check the parameters */
00526   assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
00527   assert_param(IS_GPIO_PIN(GPIO_Pin));
00528 
00529   /* Apply lock key write sequence */
00530   SET_BIT(tmp, GPIO_Pin);
00531   /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
00532   GPIOx->LCKR = tmp;
00533   /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
00534   GPIOx->LCKR = GPIO_Pin;
00535   /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
00536   GPIOx->LCKR = tmp;
00537   /* Read LCKK bit*/
00538   tmp = GPIOx->LCKR;
00539 
00540   if((uint32_t)(GPIOx->LCKR & GPIO_LCKR_LCKK))
00541   {
00542     return HAL_OK;
00543   }
00544   else
00545   {
00546     return HAL_ERROR;
00547   }
00548 }
00549 
00550 /**
00551   * @brief This function handles EXTI interrupt request.
00552   * @param GPIO_Pin: Specifies the pins connected EXTI line
00553   * @retval None
00554   */
00555 void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
00556 {
00557   /* EXTI line interrupt detected */
00558   if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET) 
00559   { 
00560     __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
00561     HAL_GPIO_EXTI_Callback(GPIO_Pin);
00562   }
00563 }
00564 
00565 /**
00566   * @brief  EXTI line detection callback
00567   * @param GPIO_Pin: Specifies the pins connected EXTI line
00568   * @retval None
00569   */
00570 __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
00571 {
00572   /* Prevent unused argument(s) compilation warning */
00573   UNUSED(GPIO_Pin);
00574   /* NOTE : This function Should not be modified, when the callback is needed,
00575             the HAL_GPIO_EXTI_Callback could be implemented in the user file
00576    */ 
00577 }
00578 
00579 /**
00580   * @}
00581   */
00582 
00583 
00584 /**
00585   * @}
00586   */
00587 
00588 #endif /* HAL_GPIO_MODULE_ENABLED */
00589 /**
00590   * @}
00591   */
00592 
00593 /**
00594   * @}
00595   */
00596 
00597 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/